TPS61177A [TI]
适用于笔记本和平板电脑显示屏的 WLED 驱动器;
| 型号： | TPS61177A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于笔记本和平板电脑显示屏的 WLED 驱动器 驱动 电脑 驱动器 |
| 文件： | 总40页 (文件大小：2674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
具有 PWM 接口和混合调光模式的笔记本电脑用 TPS61177A WLED 驱动
器
1 特性
3 说明
1
•
•
•
2.5V 至 24V 输入电压范围
TPS61177A 器件可为笔记本 LCD 背光提供高度集成
的白色 LED (WLED) 驱动器解决方案。该器件内置高
效升压稳压器，稳压器集成有 1.8A、40V 功率
MOSFET。六个灌电流稳压器提供了高精度的电流调
节和匹配。该器件总共可支持 72 个 WLED。此外，升
压输出还可自动地将其电压调节至 WLED 正向电压以
优化效率。
39V 最大输出电压
集成 1.8A、40V 金属氧化物半导体场效应晶体管
(MOSFET)
•
•
450kHz 至 1.2MHz 可编程开关频率
为白色发光二极管 (WLED) 提供电压的自适应升压
输出
•
100Hz 至 25kHz 宽输入脉宽调制 (PWM) 调光频率
范围
TPS61177A 支持模拟调光、模拟和 PWM 混合调光以
及直接 PWM 调光三种方法。在模拟调光模式下，各
CS 电流将根据 PWMB 引脚上的占空比信息线性变
化。在模拟和 PWM 混合调光模式下，输入 PWM 占
空比信息将转换成模拟信号，以在 25% 至 100% 的亮
度区域线性控制 WLED 电流。该器件还可在模拟电流
低至 25% 时增加 PWM 调光。电流低于 25% 后，模
拟信号会转换成 PWM 占空比信息以控制 WLED 电流
的导通或关断并求取低至 1% 的 WLED 电流的平均
值。增加 PWM 调光的频率与 PWMB 引脚上的输入
PWM 频率相同。TPS61177A 还支持直接 PWM 调光
方法，在直接 PWM 调光模式下，将根据 PWM 输入
信号同步导通或关断 WLED 电流。
•
•
•
•
•
•
•
•
1% 最小调光占空比
小型外部组件
集成环路补偿
六路最高 30mA 的灌电流
1% 电流匹配（典型值）
输入 PWM 毛刺脉冲滤波器
PWM 亮度接口控制
三种调光方法可供选择，包括直接 PWM 调光、模
拟调光以及模拟和 PWM 混合调光
•
•
内置 WLED 开路保护
热关断
2 应用范围
器件信息(1)
•
•
•
•
•
笔记本和平板电脑显示屏背光
患者监测仪
器件型号
TPS61177A
封装
VQFN (20)
封装尺寸（标称值）
3.50mm x 3.50mm
医疗显示屏
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
HMI
测试和测量设备
典型应用 - 模拟和 PWM 混合模式
L1
10 μH
VIN 2.5 V – 24 V
VOUT
D1
C2
4.7 μF
C1
4.7 μF
LXB
VINB
VCC
C4
1 μF
PGND
VLED
R1
10 kΩ
ENB
R2 10 kΩ
100 Hz – 25 KHz
PWMB
SDA
SCL
CS1
CS2
CS3
CS4
CS5
CS6
REF
C5
470 nF
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSA76
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 16
7.5 Programming........................................................... 18
7.6 Register Maps......................................................... 18
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application ................................................. 28
Power Supply Recommendations...................... 30
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 I2C Timing Requirements.......................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 器件支持................................................................ 32
11.2 社区资源................................................................ 32
11.3 商标....................................................................... 32
11.4 静电放电警告......................................................... 32
11.5 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2016) to Revision B
Page
•
Changed layout example picture to show Vout connected to pin 14 of the device, not pin 13............................................ 31
Changes from Original (March 2015) to Revision A
Page
•
已添加 将几项添加至第 1 页的“应用” ..................................................................................................................................... 1
2
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
5 Pin Configuration and Functions
RGR Package
20-Pin VQFN
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NUMBER
AGND
5, 9
—
I
Signal ground of the device.
Current sink regulation inputs. They are connected to the cathode of
WLEDs. The PWM loop regulates the lowest VCS to 500 mV. Each
channel is limited to 30-mA current. Connect any unused CS pin to
AGND or leave it open.
CS1, CS2, CS3, CS4,
CS5, CS6
6, 7, 8, 10, 11, 12
ENB
LXB
19
I
I
Enable pin
Drain connection of the internal PWM switch MOSFET and external
Schottky diode.
16, 17
The reference pin for internal error amplifier. Connect a 470-nF
ceramic capacitor to REF.
REF
4
O
—
I
Power ground of the IC. Internally, it connects to the source of the
PWM switch. Tie the ground of power stage components to this
ground.
PGND
15
Dimming control logic input. The dimming frequency range is from 100
Hz to 25 kHz.
PWMB
20
SCL
SDA
2
1
I
Clock input for I2C interface
Data input for I2C interface
I/O
Internal pre-regulator and supply rail for the internal logic. Do not
connect any capacitor to VCC pin.
VCC
3
I
VINB
18
14
I
I
Power supply to the IC
VLED
The voltage detect pin for VOUT.
Copyright © 2015–2017, Texas Instruments Incorporated
3
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
26.4
40
UNIT
VINB
LXB, VLED, CS1, CS2, CS3, CS4, CS5, CS6
Voltage(2)
V
ENB, PWMB
30
SDA, SCL, VCC
Continuous power dissipation
Operating junction temperature
Storage temperature, Tstg
3.6
See Thermal Information
–40
–65
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
24
UNIT
V
VIN
Input voltage
2.5
VIN + 2
0.1
VOUT
FPWM_I
DMIN_I
FBOOST
TA
Output voltage
39
PWM input signal frequency
PWM input signal minimum duty cycle
Boost regulator switching frequency
Operating free-air temperature
Operating junction temperature
25
kHz
1%
450
1200
85
kHz
°C
–40
TJ
–40
125
6.4 Thermal Information
TPS61177A
RGR (VQFN)
20 PINS
34.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
46.8
12.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
12.3
RθJC(bot)
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
6.5 Electrical Characteristics
VINB = 12 V, PWMB/ENB = logic high, CS current = 20 mA, CS voltage = 500 mV, TA = –40°C to +85°C, typical values are
at TA = 25°C (unless otherwise noted).
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
VINB
Input voltage range
2.5
24
V
Device enable, no switching and no load,
VINB = 12 V
3.5
Operating quiescent current into
VIN
Iq_VINB
mA
VINB = 12 V, EN = low
VINB = 24 V, EN = low
UVLO = 000
10
15
ISD
Shutdown current
µA
2.1
2.4
2.8
3.3
3.8
2.25
2.55
3
2.4
2.7
3.2
3.7
4.2
UVLO = 001
VINB undervoltage lockout
threshold,
voltage ramp up
VINB_UVLO
UVLO = 010
V
UVLO = 011
3.5
4
Other case
VIN undervoltage lockout
hysteresis
200
VIN_Hys
mV
BOOST OUTPUT REGULATION
VCS
CS voltage regulation
500
0.20
0.30
2.2
600
0.35
0.40
2.6
mV
VIN = 12 V
VIN = 3.3 V
D = Dmax
RDS(ON)
Switch FET on-resistance
Ω
ILIM
Switching MOSFET current limit
Switch FET leakage current
1.8
A
ILEAK_LX
VSW = 40 V
FREQ = 00
FREQ = 01
FREQ = 10
FREQ = 11
FLX = 0.8 MHz
SR = 00
5
µA
0.36
0.48
0.64
0.96
90%
0.45
0.6
0.8
1.2
95%
4.6
3.5
2.5
1.3
0.54
0.72
0.96
1.44
FLX
DMAX
TF
Switching frequency
MHz
V/ns
mA
Maximum duty cycle
SR = 01
Slew rate of switching FET ON
SR = 10
SR = 11
CS CURRENT REGULATION
ICS = 0000
ICS = 0001
…
15
16
…
30
CSn current
ICS
(See Figure 23)
ICS = 1111
ICS = 20 mA, MODE = 00 and 01
DPWM_I = 100%, TA = 25°C
–3%
–3%
–3%
–5%
–8%
3%
3%
3%
5%
8%
ICS = 20 mA, MODE = 01
DPWM_I = 255/1023, TA = 25°C
CSn current accuracy
ICS = 20 mA, MODE = 10,
DPWM_I = 255/1023, TA = 25°C
ICSA
(ICSn – 20 mA × DPWM_I)/20 mA x
DPWM_I
ICS = 20 mA, MODE = 10,
DPWM_I = 51/1023, TA = 25°C
ICS = 20 mA, MODE = 10,
DPWM_I = 10/1023, TA = 25°C
Copyright © 2015–2017, Texas Instruments Incorporated
5
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
Electrical Characteristics (continued)
VINB = 12 V, PWMB/ENB = logic high, CS current = 20 mA, CS voltage = 500 mV, TA = –40°C to +85°C, typical values are
at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICS = 20 mA, MODE = 00 and 01,
DPWM_I = 100%, TA = 25°C
–2%
2%
ICS = 20 mA, MODE = 01,
DPWM_I = 255/1023, TA = 25°C
–2%
–2%
–5%
–5%
2%
2%
ICS = 20 mA, MODE = 10,
DPWM_I = 255/1023, TA = 25°C
Current matching (ICSn
IAVG)/IAVG
–
ICSM
ICS = 20 mA, MODE = 10,
DPWM_I = 51/1023, TA = 25°C
-5%
5%
ICS = 20 mA, MODE = 10,
DPWM_I = 10/1023, TA = 25°C
MODE = 01 and 10, FPWM_I = 0.1 to 5 kHz
MODE = 01 and 10, FPWM_I = 5 to 10 kHz
MODE = 01 and 10, FPWM_I = 10 to 25 kHz
1024
512
256
400
DC dimming resolution steps
Brightness response time
DPWM_I 10% to 90% MODE = mixed and DC,
FPWM_I = 25 kHz
μs
DPWM_I 10% to 90% MODE = mixed and DC,
FPWM_I = 100 Hz
10.4
ms
ICSLK
ICSIR
tMP
CSn leakage current
CSn current inrush
VCS = 40 V
5
μA
10%
125
Minimum dimming pulse
Deglitch pulse width
MODE = 00
400
ns
ns
tDEG
CONTROL AND PROTECTION
VH
VL
VH
VL
ENB logic high threshold
VINB = 2.7 V and 3.3 V
VINB = 2.7 V and 3.3 V
VINB = 2.7 V and 3.3 V
VINB = 2.7 V and 3.3 V
ENB = 3.3 V
1.8
1.8
ENB logic low threshold
0.5
V
PWMB logic high threshold
PWMB logic low threshold
Pulldown resistor on ENB
Pulldown resistor on PWMB
Output overvoltage threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
0.5
1200
1200
40
300
300
39
600
600
39.5
150
15
RPD
kΩ
PWMB = 3.3 V
VOVP
V
Tshutdown
°C
Input sampling oscillator
frequency
22
25
29
FSAMPLE
MHz
6
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
6.6 I2C Timing Requirements
MIN
NOM
58h
MAX
UNIT
Write
Read
ADDR
Configuration parameters slave address
59h
Supply = 2.5 V, VIN falling,
standard and fast modes
VIL
Low level input voltage
High level input voltage
Hysteresis
0.75
V
V
Supply = 2.5 V, VIN rising,
standard and fast modes
VIH
1.75
125
Supply = 2.5 V,
applicable to fast mode only
VHYS
mV
VOL
CI
Low level output voltage
Input capacitance
Sinking 3 mA
500
10
mV
pF
Standard mode
Fast mode
100
400
ƒSCL
tLOW
tHIGH
tBUF
Clock frequency
Clock low period
Clock high period
kHz
µs
µs
µs
µs
µs
ns
µs
ns
ns
ns
ns
ns
µs
pF
Standard mode
Fast mode
4.7
1.3
Standard mode
Fast mode
4
0.6
Standard mode
Fast mode
4.7
Bus free time between a STOP and a
START condition
1.3
Standard mode
Fast mode
4
Hold time for a repeated START
condition
thd:STA
tsu:STA
tsu:DAT
thd:DAT
tRCL1
tRCL
0.6
Standard mode
Fast mode
4
Set-up time for a repeated START
condition
0.6
Standard mode
Fast mode
250
Data set-up time
Data hold time
100
Standard mode
Fast mode
0.05
3.45
0.9
0.05
Standard mode
Fast mode
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
4
1000
1000
1000
300
Rise time of SCL after a repeated START
condition and after an ACK bit
Standard mode
Fast mode
Rise time of SCL
Standard mode
Fast mode
300
tFCL
Fall time of SCL
300
Standard mode
Fast mode
1000
300
tRDA
Rise time of SDA
Standard mode
Fast mode
300
tFDA
Fall time of SDA
300
Standard mode
Fast mode
tsu:STO
Set-up time for STOP condition
Capacitive load on SDA and SCL
0.6
Standard mode
Fast mode
400
400
CB
NWRITE
tWRITE
Number of write cycles
Write time
1000
100
ms
hrs
Data retention
Storage temperature = 150°C
100,000
Copyright © 2015–2017, Texas Instruments Incorporated
7
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
6.7 Typical Characteristics
Table 1. Table of Graphs
TITLE
DESCRIPTION
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Efficiency vs PWM Duty in PWM Mode VIN = 12 V, VOUT = 6S6P, 8S6P, 10S6P, ICS = 20 mA, L = 10 µH
Efficiency vs PWM Duty in PWM Mode VIN = 3 V, 12 V, 21 V, VOUT = 6S6P, 8S6P, 10S6P, L = 10 µH
Efficiency vs PWM duty in Mixed Mode VIN = 12 V, VOUT = 6S6P, 8S6P, 10S6P, ICS = 20 mA, L = 10 µH
Efficiency vs PWM duty in Mixed Mode VIN = 3 V, 12 V, 21 V, VOUT = 6S6P, 8S6P, 10S6P, L = 10 µH
Efficiency vs PWM duty in Analog
VIN = 12 V, VOUT = 6S6P, 8S6P, 10S6P, ICS = 20 mA, L = 10 µH
Mode
Figure 5
Figure 6
Efficiency vs PWM duty in Analog
VIN = 3 V, 12 V, 21 V, VOUT = 6S6P, 8S6P, 10S6P, L = 10 µH
Mode
Dimming Linearity in PWM Mode
Dimming Linearity in Mixed Mode
Dimming linearity in Analog Mode
Switch Waveform
VIN = 12 V, VOUT = 10S6P , FDIM = 200 Hz and 20 kHz, L = 10 µH
VIN = 12 V, VOUT = 10S6P , FDIM = 200 Hz and 20 kHz, L = 10 µH
VIN = 12 V, VOUT = 10S6P , FDIM = 200 Hz and 20 kHz, L = 10 µH
VIN = 3 V, VOUT = 6S6P, Duty = 100%, L = 10 µH
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Switch Waveform
VIN = 12 V, VOUT = 10S6P, Duty = 100%, L = 10 µH
Mixed-Mode Dimming Ripple
Mixed-Mode Dimming Ripple
Mixed-Mode Dimming Ripple
PWM-Mode Dimming Ripple
PWM-Mode Dimming Ripple
VIN = 12 V, VOUT = 10S6P, FDIM = 200 Hz, Duty = 50%, L = 10 µH
VIN = 12 V, VOUT = 10S6P, FDIM = 200 Hz, Duty = 12.5%, L = 10 µH
VIN = 12 V, VOUT = 10S6P, FDIM = 20 kHz, Duty = 12.5%, L = 10 µH
VIN = 12 V, VOUT = 10S6P, FDIM = 200 Hz, Duty = 50%, L = 10 µH
VIN = 12 V, VOUT = 10S6P, FDIM = 20 kHz, Duty = 50%, L = 10 µH
100
90
80
70
60
50
40
100
90
80
70
60
Vin = 3 V 6S6P
6S6P
50
Vin=12V8S6P
8S6P
V
= 21 V 10S6P
10S6P
in
40
0
20
40
60
80
100
0
20
40
60
80
100
C001
C002
PWM Duty Cycle (%)
PWM Duty Cycle (%)
Figure 1. Efficiency vs PWM Duty in PWM Mode
Figure 2. Efficiency vs PWM Duty in PWM Mode
8
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
100
100
90
80
70
60
50
40
90
80
70
60
50
Vin = 3 V 6S6P
6S6P
8S6P
10S6P
Vin=12V8S6P
V
= 21 V 10S6P
in
40
0
20
40
60
80
100
0
20
40
60
80
100
C003
C004
PWM Duty Cycle (%)
PWM Duty Cycle (%)
Figure 3. Efficiency vs PWM Duty in Mixed Mode
Figure 4. Efficiency vs PWM Duty in Mixed Mode
100
90
80
70
60
50
40
100
90
80
70
60
50
40
Vin = 3 V 6S6P
6S6P
8S6P
10S6P
Vin=12V8S6P
V
= 21 V 10S6P
in
0
20
40
60
80
100
0
20
40
60
80
100
C005
C006
PWM Duty Cycle (%)
PWM Duty Cycle (%)
Figure 5. Efficiency vs PWM Duty in Analog Mode
Figure 6. Efficiency vs PWM Duty in Analog Mode
120
120
100
80
60
40
20
0
100
80
60
40
20
0
200 Hz
20 kHz
200 Hz
20 kHz
0
20
40
60
80
100
0
20
40
60
80
100
C007
C008
PWM Duty Cycle (%)
PWM Duty Cycle (%)
Figure 7. Dimming Linearity in PWM Mode
Figure 8. Dimming Linearity in Mixed Mode
Copyright © 2015–2017, Texas Instruments Incorporated
9
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
120
100
80
60
40
20
0
VLED Voltage 100mV/div
LXB Voltage 10V/div
200 Hz
20 kHz
Inductor Current 300mA/div
0
20
40
60
80
100
C009
PWM Duty Cycle (%)
Time (1µs/div)
Figure 9. Dimming Linearity in Analog Mode
Figure 10. Switch Waveform
VLED Voltage 100mV/div
VLED Voltage 100mV/div
PWMB Voltage 3V/div
CS1 Voltage 1V/div
CS Current 50mA/div
LXB Voltage 10V/div
Inductor Current 300mA/div
Time (1µs/div)
Time (5 ms/div)
FDIM = 200 Hz
Duty = 50%
Figure 11. Switch Waveform
VLED Voltage 100mV/div
Figure 12. Mixed-Mode PWM Dimming
VLED Voltage 100mV/div
PWMB Voltage 3V/div
PWMB Voltage 3V/div
CS1 Voltage 4V/div
CS1 Voltage 4V/div
IOUT Current 50mA/div
IOUT Current 50mA/div
Time (5 ms/div)
Time (50 µs/div)
FDIM = 200 Hz
Duty = 12.5%
FDIM = 20 kHz
Duty = 12.5%
Figure 13. Mixed-Mode PWM Dimming
Figure 14. Mixed-Mode PWM Dimming
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VLED Voltage 200mV/div
PWMB Voltage 3V/div
VLED Voltage 200mV/div
PWMB Voltage 3V/div
CS1 Voltage 5V/div
CS1 Voltage 5V/div
IOUT Current 100mA/div
IOUT Current 100mA/div
Time (5 ms/div)
Time (50 µs/div)
FDIM = 200 Hz
Duty = 50%
FDIM = 20 kHz
Duty = 50%
Figure 15. PWM Mode Dimming
Figure 16. PWM Mode Dimming
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7 Detailed Description
7.1 Overview
The TPS61177A is a high-efficiency, high output voltage white-LED (WLED) driver for notebook panel
backlighting applications. Due to the large number of white LEDs required to provide backlighting for medium-to-
large display panels, the LEDs must be arranged in parallel strings of several LEDs in series. Therefore, the
backlight driver for battery-powered systems is almost always a boost regulator with multiple current-sink
regulators. Having more WLEDs in series reduces the number of parallel strings, thus improving overall current
matching. However, the efficiency of the boost regulator declines due to the need for high output voltage. Also,
there must be enough white LEDs in series to ensure the output voltage stays above the input voltage range.
The TPS61177A device has integrated all of the key function blocks to power and control up to 72 WLEDs. The
device includes a 1.8-A, 40-V boost regulator, six 30-mA current sink regulators, and a protection circuit for
overcurrent, overvoltage, open LED, short LED, and overtemperature failures. The TPS61177A integrates mixed
mode dimming methods with the PWM interface to reduce the output ripple voltage and audible noise. Optional
direct PWM and pure analog dimming modes are user selectable through the I2C programming.
7.2 Functional Block Diagram
L
D
VIN
VOUT
C1
C2
4.7μF
4.7μF
LXB
VLED
VIN
Linear
Regulator
VCC
Q
R
S
PGND
Slope
Compensation
Σ
Oscillator
CS1
CS2
CS3
M
U
X
EA
CS4
CS5
CS6
GM
Vref
500mV
REF
PWM
C3
470nF
CS1
25MHz
ENB
PWMB
Dimming
Mode
Decoder
EA
A0h
A1h
A2h
A3h
A4h
A5h
MODE
Current
Reference
CS
UVLO
FREQ
SR
AGND
CS2
CS3
CS4
CS5
CS6
Current Sink
Current Sink
Current Sink
Current Sink
Current Sink
ILIM
SDA
SCL
I2C
Interface
7.3 Feature Description
7.3.1 Supply Voltage
The TPS61177A device has a built-in linear regulator to supply the device analog and logic circuit. The VCC pin
is recommended to be open without any capacitance load. VCC does not have high current sourcing capability
for external use and typically is regulated at 3.3 V.
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Feature Description (continued)
7.3.2 Boost Regulator
The fixed-frequency PWM boost converter uses current-mode control and has integrated loop compensation.
The internal compensation ensures stable output over the full input and output voltage ranges assuming the
recommended inductance and output capacitance values shown in Figure 36. The output voltage of the boost
regulator is automatically set by the device to minimize voltage drop across the CS pins. The device regulates
the lowest CS pin to 500 mV at 20-mA current and consistently adjusts the boost output voltage to account for
any changes in LED forward voltages. If the input voltage is higher than the sum of the WLED forward voltage
drops (at low duty cycles), the boost converter is not able to regulate the output due to its minimum duty cycle
limitation. In this case, increase the number of WLEDs in series or include series ballast resistors in order to
provide enough headroom for the converter to boost the output voltage. Since the TPS61177A integrates a 1.8-
A, 40-V power MOSFET, the boost converter can provide up to a 39-V output voltage.
7.3.3 Programmable Switch Frequency and Slew Rate
Both switching frequency and slew rate of TPS61177A can be programmable by a E2PROM register value which
is pre-set before device power up. The switching frequency has four options adjustable to 450 kHz, 600 kHz, 800
kHz, or 1200 kHz. The slew rate of switching FET from off to on also has four selections: 1.3 V/ns, 2.5 V/ns, 3.5
V/ns to 4.6 V/ns.
See FREQ (A3h) and SR (A4h) for E2PROM address and data table of boost switching frequency programming
and boost switching slew rate selection.
The adjustable switching frequency feature provides the user with the flexibility of choosing either a faster
switching frequency by using an inductor with smaller inductance and footprint or a slower switching frequency to
get potentially higher efficiency due to lower switching losses. In additional, the selectable slew rate for switching
gives flexibility to trade off between switching loss and electronic-magnetic interference (EMI) effects to the
application system.
7.3.4 LED Current Sinks
The six current sink regulators embedded in the TPS61177A can be collectively configured to provide up to a
maximum of 30 mA each. These six specialized current sinks are accurate to within ±3% max for currents at 20
mA, with a string-to-string difference of ±2%.
Each CS channel current must be programmed to the highest WLED current expected; each CS channel current
is programmable from 15 mA to 30 mA by an E2PROM register through the I2C interface. See CS (A1h) for the
E2PROM register table of CS current programming.
7.3.5 Enable and Start-Up Timing
The internal regulator which provides VCC wakes up as soon as ENB is applied. VCC does not come to full
regulation until VINB voltage is above UVLO. Before boost convert start-up, the TPS61177A checks the status of
all current feedback channels and shuts down any unused feedback channels. It is recommended to short the
unused channels to ground for faster start-up.
After the device is enabled, if the PWM pin is left floating or grounded, the output voltage of the TPS61177A
regulates to the minimum output voltage. Once the device detects a voltage on the PWM pin, the TPS61177A
begins to regulate the CS pin current, as a pre-set per the E2PROM register data, according to the duty cycle of
the signal on the PWMB pin. The boost converter output voltage rises to the appropriate level to accommodate
the sum of the white LED string with the highest forward voltage drops plus the headroom of the current sink at
that current.
Pulling the ENB pin low shuts down the device, resulting in consumption of less than 10 µA in shutdown mode.
The TPS61177A also integrates power-up sequence control for start-up. There is no specified power or control
signal sequence requirement for VINB, ENB, and PWMB. Figure 17 provides the detail timing diagram for
TPS61177A start-up and shutdown.
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Feature Description (continued)
VINB
ENB
PWMB
VLED
PWMB decoder delay
4 ms
No use detection
VCSn
ICSn
Figure 17. Start-up and Shutdown Timing Diagram
The PWMB decoder delay time period is determined by different dimming mode, input duty cycle, and frequency
on the PWMB pin. In PWM mode, the decoder delay time is zero. Once the rising edge is detected on the PWMB
pin, the output voltage starts ramping up immediately. While in mixed dimming mode or analogdimming mode,
the decoder delay time is equal to twice input PWM signal cycle time and 400 µs minimally. If PWM signal input
keeps at high level after first rising edge, the decoder delay is about 20 ms.
Figure 18 provides the detail timing diagram for TPS61177A start-up and shutdown when one of CS channel is
open. The VLED voltage always ramps up to the overvoltage protection threshold which is 39.5 V typically, if one
of CS pin is floating. The device then detects the zero current string, and removes it from the feedback loop.
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Feature Description (continued)
VINB
ENB
PWMB
39.5 V
VLED
PWMB decoder delay
4 ms
No use detection
VCSn
ICSn
Figure 18. Start-Up and Shutdown Timing Diagram (Mixed Mode and DC Mode)
7.3.6 Input Undervoltage Protection (UVLO)
The TPS61177A will not start up until the VINB voltage is higher than the UVLO threshold which is preset by
E2PROM register data. During normal operation, if the VINB drops below UVLO with 200-mV hysteresis, the
TPS61177A immediately shuts down. See UVLO (A2h) for E2PROM address and data table of UVLO threshold.
7.3.7 Overvoltage Protection (OVP)
The TPS61177A integrates output OVP which is fixed at 39.5 V typically. Once the VLED pin detects the voltage
higher than 39.5 V, the boost switching regulator stops switching until the voltage of VLED pin drop below 39.5 V
with 500-mV hysteresis.
7.3.8 Current-Sink Open Protection
If one of the device WLED strings is open, the device automatically detects and disables that string. The open
WLED string is detected by sensing no current in the corresponding CS pin. As a result, the TPS61177A
deactivates the open current sink and removes it from the voltage feedback loop. Subsequently, the output
voltage drops and is regulated to the minimum voltage required for the connected WLED strings. The CS
currents of the connected WLED strings remain in regulation.
The device turns off if it detects that all of the WLED strings are open. If an open string is reconnected again, a
power-on reset (POR) or ENB pin toggling is required to reactivate a previously deactivated string.
7.3.9 Overcurrent Protection
The TPS61177A has a pulse-by-pulse overcurrent limit of 1.8 A (minimum). The PWM switch turns off when the
inductor current reaches this current threshold. The PWM switch remains off until the beginning of the next
switching cycle. This protects the device and external components during an overload condition. When there is a
sustained overcurrent condition more than 2 ms, the device shuts down and requires a POR or EN pin toggling
to restart. The overcurrent shutdown protection can be disabled by E2PROM register through I2C interface. See
ILIM (A5h) for E2PROM register table of ILIM shutdown protection programming.
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Feature Description (continued)
7.3.10 Thermal Protection
When the junction temperature of the TPS61177A is over 150°C, the thermal protection circuit is triggered and
shuts down the device immediately. The device automatically restarts when the junction temperature is back to
less than 150°C with about 15°C hysteresis.
7.4 Device Functional Modes
7.4.1 Mode Selection
The mixed-mode dimming method, analog dimming method, or direct PWM dimming method can be selected
through the E2PROM register. See MODE (A0h) for E2PROM register table of dimming mode programming.
7.4.2 Analog and PWM Mixed Dimming Mode
In analog and PWM mixed mode, the TPS61177A features both analog dimming and PWM digital dimming.
Analog dimming can provide potentially a lower power requirement for the same WLED brightness output
because of a low voltage drop across each WLED when the current is low. Digital PWM dimming provides less
WLED color distortion since the WLED current is held at 25% of full scale when the WLED is on.
The brightness control signal on the PWM pin is translated to a 10-bit digital signal and sent to control the six
current regulators. Each current regulator outputs is DC, and PWM (25% < DPWM < 100%) modulates the
amplitude of the currents from 25% to 100% of preset full-scale current. For DPWM < 25%, each CS turns on/off
at translated duty cycle and same frequency to the input PWM, and in the WLED on duty current is regulated at
25% of full scale. Mixed-mode dimming provides the benefits of both the analog and PWM dimming. For 25% <
DPWM < 100%, analog dimming benefits the low power requirement and increases the power to brightness
transform efficiency. At light load conditions, DPWM < 25%, the PWM dimming provides both high accuracy
brightness and low color distortion. Figure 19 provides the detailed timing diagram of the analog and PWM mixed
dimming mode.
D=100%
D=80%
D=60%
D=50%
D=25%
D=12.5%
D=6.25%
PWM
Input
TON
TPWM
ILEDMAX
80%
CSn
60%
50%
D=50%
D=25%
25%
0A
Analog and PWM Mixed Dimming Mode
Figure 19. Analog and PWM Mixed-Mode Dimming Diagram
7.4.3 Analog Dimming Mode
In analog dimming mode, TPS61177A features pure analog dimming all over the brightness range of full-scale
LED current. Analog dimming can provide potentially low power requirement for same WLED brightness output
because of low voltage drop across each WLED when the current is low. In additional, the brightness control
signal on the PWMB pin is translated to an up to 10-bits digital signal and sent to control the six current
regulators. Each current regulator output DC modulates the amplitude of the currents from 1% to 100% of preset
full-scale current. Figure 20 provides the detailed timing diagram of the analog dimming mode.
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Device Functional Modes (continued)
D=100%
D=80%
D=60%
D=50%
D=25%
D=12.5%
D=6.25%
PWM
Input
TON
TPWM
ILEDMAX
80%
60%
50%
CSn
0A
25%
12.5%
Analog Dimming Mode
Figure 20. Analog-Mode Dimming Diagram
7.4.4 Direct PWM Dimming
In direct PWM mode, all current feedback channels are turned on and off and are synchronized with the input
PWM signal. Figure 21 provides the detailed timing diagram of the direct PWM dimming mode.
D=100%
D=80%
D=60%
D=50%
D=25%
D=12.5%
D=6.25%
PWM
Input
TON
TPWM
ILEDMAX
CSn
0A
Direct PWM Dimming Mode
Figure 21. Direct PWM-Mode Dimming Diagram
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7.5 Programming
7.5.1 Configuration Parameters
Table 2 shows the memory map of the configuration parameters.
Table 2. Configuration Memory Map
REGISTER
ADDRESS
REGISTER
NAME
FACTORY
DEFAULT
DESCRIPTION
A0h
A1h
A2h
A3h
A4h
A5h
FFh
MODE
CS
01h
Sets brightness dimming mode
05h
Sets the current sinks full scale current
Sets the input voltage UVLO threshold
Sets the boost switching frequency
UVLO
FREQ
SR
03h
01h
00h
Sets the boost switching slew rate
ILIM
00h
Enables/disables the shutdown protection for current limit
Controls whether read and write operations access RAM or E2PROM registers.
Control
00h
7.6 Register Maps
7.6.1 MODE (A0h)
The MODE register can be written to and read from.
Figure 22. MODE Register Bit Allocation
7
6
5
4
3
2
1
0
RESERVED
R/W-0
MODE
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3. MODE Register Bit Field Descriptions
Bit
Field
Type
Reset
Description
These bits are reserved for future use. During write operations, data intended for
these bits are ignored, and during read operations 0 is returned.
7:2
RESERVED
R/W
0
These bits configure the current sink dimming method for brightness control.
00 = Direct PWM dimming mode
01 = Analog and PWM mixed dimming mode
10 = Analog dimming mode
1:0
MODE
R/W
1
7.6.2 CS (A1h)
The CS register can be written to and read from.
Figure 23. CS Register Bit Allocation
7
6
5
4
3
2
1
0
RESERVED
R/W-0
CS
R/W-5
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. CS Register Bit Descriptions
Bit
Field
Type
Reset
Description
These bits are reserved for future use. During write operations, data intended for these
bits are ignored, and during read operations 0 is returned.
7:4
RESERVED
R/W
0
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Table 4. CS Register Bit Descriptions (continued)
Bit
Field
Type
Reset
Description
These bits select the full scale current for all six current sinks.
0000: ICS = 15 mA
0001: ICS = 16 mA
0010: ICS = 17 mA
0011: ICS = 18 mA
0100: ICS = 19 mA
0101: ICS = 20 mA
0110: ICS = 21 mA
0111: ICS = 22 mA
1000: ICS = 23 mA
1001: ICS = 24 mA
1010: ICS = 25 mA
1011: ICS = 26 mA
1100: ICS = 27 mA
1101: ICS = 28 mA
1110: ICS = 29 mA
1111: ICS = 30 mA
3:0
CS
R/W
5
7.6.3 UVLO (A2h)
The UVLO register can be written to and read from.
Figure 24. UVLO Register Bit Allocation
7
6
5
4
3
2
1
0
RESERVED
R/W-0
UVLO
R/W-3
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. UVLO Register Bit Field Descriptions
Bit
Field
Type
Reset
Description
These bits are reserved for future use. During write operations data intended for these
bits is ignored, and during read operations 0 is returned.
7:3
RESERVED
R/W
0
These bits select the UVLO threshold.
000: VUVLO = 2.25 V
001: VUVLO = 2.55 V
010: VUVLO = 3 V
2:0
UVLO
R/W
3
011: VUVLO = 3.5 V
100: VUVLO = 4 V
Others: VUVLO = 4 V
7.6.4 FREQ (A3h)
The FREQ register can be written to and read from.
Figure 25. FREQ Register Bit Allocation
7
6
5
4
3
2
1
0
RESERVED
R/W-0
FREQ
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. FREQ Register Bit Field Descriptions
Bit
Field
Type
Reset
Description
These bits are reserved for future use. During write operations, data intended for
these bits are ignored, and during read operations 0 is returned.
7:2
RESERVED
R/W
0
These bits configure the switching frequency.
00: FLX = 450 kHz
1:0
FREQ
R/W
1
01: FLX = 600 kHz
10: FLX = 800 kHz
11: FLX = 1200 kHz
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7.6.5 SR (A4h)
The SR register can be written to and read from.
Figure 26. SR Register Bit Allocation
7
6
5
4
3
2
1
0
RESERVED
R/W-0
SR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. SR Register Bit Field Descriptions
Bit
Field
Type
Reset
Description
These bits are reserved for future use. During write operations, data intended for
these bits are ignored, and during read operations 0 is returned.
7:2
RESERVED
R/W
0
These bits configure the falling slew rate of switching voltage from OFF to ON.
00: SR = 4.6 V/ns
01: SR = 3.5 V/ns
10: SR = 2.5 V/ns
11: SR = 1.3 V/ns
1:0
SR
R/W
0
7.6.6 ILIM (A5h)
The ILIM register can be written to and read from.
Figure 27. ILIM Register Bit Allocation
7
6
5
4
3
2
1
0
RESERVED
R/W-0
ILIM
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. ILIM Register Bit Field Descriptions
Bit
Field
Type
Reset Description
These bits are reserved for future use. During write operations, data intended for these
bits are ignored, and during read operations 0 is returned.
7:1
RESERVED
R/W
0
This bit configures the current limit shutdown protection.
0 = Disable current limit shutdown protection
1 = Enable current limit shutdown protection
0
ILIM
R/W
0
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7.6.7 Control (FFh)
Figure 28. Control Register Bit Allocation
7
6
5
4
3
2
1
0
WED
RESERVED
R/W-0
RED
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Control Register Bit Field Descriptions
Bit
Field
Type
Reset
Description
Setting this bit forces the contents of all registers to be copied into E2PROM,
thereby making them the default values during power up.
7
WED
When the contents of all the registers have been written to E2PROM, the
TPS61177A device automatically resets this bit.
These bits are reserved for future use. During write operations, data intended for
these bits are ignored, and during read operations 0 is returned.
6:1
0
RESERVED
RED
R/W
R/W
0
0
The state of this bit determines whether read operations return the contents of the
registers or the contents of the E2PROM.
0 = Read operations return the contents of the registers.
1 = Read operations return the contents of the E2PROM.
7.6.8 Example – Writing to a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of RAM register (A0h)
5. TPS61177A acknowledges
6. Bus master sends data to be written
7. TPS61177A acknowledges
8. Bus master sends STOP condition
58h
A0h
DATA
RAM Register Address
RAM Register Data
S
7-Bit Slave Address
0
A
A
A
P
Figure 29. Writing To A Single Ram Register
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7.6.9 Example – Writing to Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h).
3. TPS61177A acknowledges
4. Bus master sends address of first RAM register to be written to (A0h)
5. TPS61177A acknowledges
6. Bus master sends data to be written to first RAM register
7. TPS61177A acknowledges
8. Bus master sends data to be written to RAM register at next higher address (auto-increment)
9. TPS61177A acknowledges
10. Steps (8) and (9) repeated until data for final RAM register has been sent
11. TPS61177A acknowledges
12. Bus master sends STOP condition
58h
A0h
DATA
DATA
RAM Register Address (n)
RAM Register Data (n)
RAM Register Data (n+1)
7-Bit Slave Address
S
0
A
A
A
A
DATA
RAM Register Data (Last)
A
P
Figure 30. Writing To Multiple Ram Registers
7.6.10 Example – Saving Contents of all RAM Registers to E2PROM
1. Pull high the Enable pin of TPS61177A
2. Pull the PWM pin of TPS61177A to low
3. Bus master sends START condition
4. Bus master sends 7-bit slave address plus low R/W bit (58h)
5. TPS61177A acknowledges
6. Bus master sends address of Control Register (FFh)
7. TPS61177A acknowledges
8. Bus master sends data to be written to the Control Register (80h)
9. TPS61177A acknowledges
10. Bus master sends STOP condition
58h
FFh
80h
Control Register Data
Control Register Address
S
7-Bit Slave Address
0
A
A
A
P
Figure 31. Saving Contents Of All Ram Registers To E2PROM
The TPS61177A needs a 50-ms time period after receiving STOP condition for saving all RAM registers data to
E2PROM. If bus master send 7-bit slave address to call TPS61177A again within 50-ms period, the TPS61177A
pulls down the SCL line to LOW until the all RAM registers data saving to E2PROM is completed.
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7.6.11 Example – Reading from a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of RAM register (A0h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends RAM register data
18. Bus master not acknowledges
19. Bus master sends STOP condition
58h
FFh
00h
Control Register Address
Control Register Data
S
7-Bit Slave Address
0
A
A
A
P
58h
A0h
59h
DATA
RAM Register Address
RAM Register Data
S
7-Bit Slave Address
0
A
A
Sr
7-Bit Slave Address
1
A
A
P
Figure 32. Reading From A Single Ram Register
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TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
7.6.12 Example – Reading from a Single E2PROM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of RAM register (A0h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends E2PROM register data
18. Bus master not acknowledges
19. Bus master sends STOP condition
58h
FFh
01h
Control Register Address
Control Register Data
S
7-Bit Slave Address
0
A
A
A
P
58h
A0h
59h
DATA
E2PROM Register Address
E2PROM Register Address
S
7-Bit Slave Address
0
A
A
Sr
7-Bit Slave Address
1
A
A
P
Figure 33. Reading From A Single E2PROM Register
24
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
7.6.13 Example – Reading from Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of RAM register (A0h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends contents of first RAM register to be read
18. Bus master acknowledges
19. TPS61177A sends contents of second RAM register to be read
20. Bus master acknowledges
21. TPS61177A sends contents of third (last) RAM register to be read
22. Bus master not acknowledges
23. Bus master sends STOP condition
58h
FFh
00h
Control Register Address
Control Register Data
S
7-Bit Slave Address
0
A
A
A
P
58h
A0h
59h
DATA
RAM Register Address (n)
RAM Register Data (n)
S
7-Bit Slave Address
0
A
A
Sr
7-Bit Slave Address
1
A
A
DATA
DATA
RAM Register Data (n+1)
RAM Register Data (Last)
A
A
P
Figure 34. Reading From A Multiple Ram Register
Copyright © 2015–2017, Texas Instruments Incorporated
25
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
7.6.14 Example – Reading from Multiple E2PROM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of E2PROM register (00h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends contents of first E2PROM register to be read
18. Bus master acknowledges
19. TPS61177A sends contents of second E2PROM register to be read
20. Bus master acknowledges
21. TPS61177A sends contents of third (last) E2PROM register to be read
22. Bus master not acknowledges
23. Bus master sends STOP condition
58h
FFh
01h
Control Register Address
S
7-Bit Slave Address
0
A
A
A
P
Control Register Data
58h
A0h
59h
DATA
E2PROM Register Data (n)
E2PROM Register Address (n)
S
7-Bit Slave Address
0
A
A
Sr
7-Bit Slave Address
1
A
A
DATA
DATA
E2PROM Register Data (n+1)
E2PROM Register Data (Last)
A
A
P
Figure 35. Reading From Multiple E2PROM Registers
26
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 CS Pin Unused
The TPS61177A has open/short string detection. For an unused CS string, simply short it to ground or leave it
open. If the CS pin is open, the boost output voltage ramps up to overvoltage threshold during start-up. The
device then detects the zero current string and removes it from the feedback loop. If the CS pin is shorted to
ground, the device detects the short and immediately removes it (or them) out of feedback loop within 4 ms after
device enable, and the boost output voltage does not go up to overvoltage threshold. Instead, it ramps to the
regulation voltage after soft start.
Shorting unused CS pins to ground for faster start-up is recommended.
8.1.2 Brightness Dimming Control
The TPS61177A has three dimming methods. See Mode Selection section for dimming mode selection. With
analog and PWM mixed dimming or pure analog dimming through the PWM control interface, the internal
decoder block detects duty information from the input PWM signal, saves it in an up to 10-bits register and
delivers to either a mixed mode dimming control circuit or pure analog dimming control circuit. In mixed dimming
mode, the output dimming control circuit sets the DC current of six current sinks linearly between 25% and 100%
at same scale to the value in up to a 10-bits register. When the brightness level is below 25% to full-scale value,
the dimming control circuit turns on/off six output current sinks at same frequency with PWMB and duty cycle out
of shift register. See Analog and PWM Mixed Dimming Mode section for more explanation. While in pure analog
dimming mode, the output dimming control circuit sets the DC current of six current sinks linearly between 1%
and 100% at same scale to the value in up to a 10-bits register. See Analog Dimming Mode section for more
detail explanation.
The TPS61177A also has direct PWM dimming control through the PWM control interface. In direct PWM mode,
each current sink turns on/off at the same frequency and duty cycle as the input PWM signal. See Direct PWM
Dimming section for more explanation.
When in analog and PWM mixed mode, insertion of a series 10-kΩ to 20-kΩ resistor close to PWMB pin is
recommended. This resistor, together with an internal capacitor, forms a low pass R-C filter with a 30-ns to 60-ns
time constant. This prevents possible high frequency noise being coupled into the input PWM signal and causing
interference to the internal duty cycle decoding circuit. However, it is not necessary for direct PWM mode since
the duty cycle decoding circuit is disabled during direct PWM mode.
Copyright © 2015–2017, Texas Instruments Incorporated
27
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
8.2 Typical Application
L1
10 μH
VIN 2.5 V – 24 V
VOUT
D1
C2
4.7 μF
C1
4.7 μF
LXB
VINB
C4
1 μF
PGND
VLED
VCC
R1
R2
10 kΩ
10 kΩ
ENB
PWMB
100 Hz – 25 KHz
SDA
SCL
CS1
CS2
CS3
CS4
CS5
CS6
REF
C5
470 nF
AGND
Figure 36. TPS61177A Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Inductor
10 µH
2.5 V
12
Minimum input voltage
Number of series LED
LED maximum forward voltage (Vf)
Schottky diode forward voltage (Vf)
Efficiency (η)
3.3 V
0.2 V
85%
Switching frequency
600 kHz
1 kHz
30 mA
PWM input frequency
Maximum LED string current
28
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
The TPS61177A is designed to support up to 2.2 A (typical) SW current. Thus, SW current must be carefully
calculated with factors such as inductor, target efficiency, output voltage, load current, and so forth. In most
cases, the voltage ratio between input and boost output must be < 10.
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor Selection
Because selection of the inductor affects power supply steady-state operation, transient behavior, and loop
stability, the inductor is the most important component in switching power regulator design. There are three
specifications most important to the performance of the inductor: inductor value, DC resistance, and saturation
current. The TPS61177A is designed to work with inductor values between 4.7 µH and 22 µH. A 10-µH inductor
is typically available in a smaller or lower profile package, while a 22-µH inductor may produce higher efficiency
due to a slower switching frequency and/or lower inductor ripple. If the boost output current is limited by the
overcurrent protection of the device, using a 10-µH inductor and the highest switching frequency maximizes
controller output current capability.
Internal loop compensation for PWM control is optimized for the external component values, including typical
tolerances, recommended in Table 10. Inductor values can have ±20% tolerance with no current bias. When the
inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0-A value
depending on how the inductor vendor defines saturation. In a boost regulator, the inductor DC current can be
calculated with Equation 1.
V
OUT ´IOUT
IL(DC)
=
V ´ h
IN
where
•
•
•
•
VOUT = boost output voltage
IOUT = boost output current
VIN = boost input voltage
η = power conversion efficiency, use 90% for TPS61177A applications
(1)
The inductor current peak-to-peak ripple can be calculated with Equation 2.
1
DIL(P-P)
=
æ
ç
è
ö
÷
ø
1
1
L ´
+
´F
S
VOUT - V
V
IN
IN
where
•
•
•
•
•
ΔIL(P-P) = inductor peak-to-peak ripple
L = inductor value
FS = Switching frequency
VOUT = boost output voltage
VIN = boost input voltage
(2)
(3)
Therefore, the peak current seen by the inductor is calculated with Equation 3.
DI
L(P -P)
I
= I
+
L(P) L(DC)
2
Select an inductor with a saturation current over the calculated peak current. To calculate the worst-case inductor
peak current, use the minimum input voltage, maximum output voltage, and maximum load current.
Regulator efficiency is dependent on the resistance of its high current path and switching losses associated with
the power FET switch and power diode. Although the TPS61177A device has optimized the internal switch
resistances, the overall efficiency is affected by the inductor DC resistance (DCR). Lower DCR improves
efficiency. However, there is a trade off between DCR and inductor footprint; furthermore, shielded inductors
typically have higher DCR than unshielded ones. Table 10 lists the recommended inductors.
Copyright © 2015–2017, Texas Instruments Incorporated
29
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
Table 10. Recommended Inductor
L (µH)
DCR (mΩ)
ISAT (A)
Size (L × W × H mm)
5.4 × 5.2 × 1.6
6 × 6 × 1.2
Cyntec
PCMB051H-100MS
Taiyo
10
10
140
335
3
NRA6012T 100ME
1.45
8.2.2.2 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirement for output ripple and loop stability. This ripple
voltage is related to the capacitance of the capacitor and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated with Equation 4:
V
- V ´I
IN OUT
(
)
OUT ´FS ´ V
OUT
COUT
=
V
ripple
where
•
Vripple = peak-to-peak output ripple.
(4)
The additional part of the ripple caused by ESR is calculated using: Vripple_ESR = IOUT × RESR
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used. The controller output voltage also ripples due to the load transient that occurs
during PWM dimming. The TPS61177A adopts a patented technology to limit this type of output ripple even with
the minimum recommended output capacitance. In a typical application, the output ripple is less than 250 mV
during PWM dimming with a 4.7-µF output capacitor. However, the output ripple decreases with higher output
capacitances.
8.2.3 Application Curves
VLED Voltage 10V/div
VLED Voltage 10V/div
PWMB Voltage 3V/div
CS1 Voltage 4V/div
PWMB Voltage 3V/div
CS1 Voltage 4V/div
Inductor Current 500mA/div
Inductor Current 500mA/div
Time (20 ms/div)
Time (5 ms/div)
Figure 38. Start-Up Waveform
Figure 37. Start-Up Waveform
9 Power Supply Recommendations
The power supply for applications using the TPS61177A device must be big enough considering output power
and efficiency at a given input voltage condition. Minimum current requirement condition is (VOUT × IOUT)/(VIN
efficiency), and TI recommends a minimum current that is approximately 20% to 30% higher than this value.
×
30
Copyright © 2015–2017, Texas Instruments Incorporated
TPS61177A
www.ti.com.cn
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C1 in the Typical
Application , must not only to be close to the VIN pin, but also to the GND pin in order to reduce the input ripple
seen by the device. The input capacitor, C4 in the Typical Application , must also be placed close to the inductor.
C5 is the reference capacitor for the internal integration circuit. It must be placed as close between the REF and
AGND pins as possible to prevent any noise insertion to the digital circuits. The LX pin carries high current with
fast rising and falling edges. Therefore, the connection between the pin to the inductor and Schottky diode must
be kept as short and wide as possible. It is also beneficial to have the ground of the output capacitor C2 close to
the PGND pin because there is a large ground return current flowing between them. When laying out signal
grounds, TI recommends using short traces separated from power ground traces, and connecting them together
at a single point, for example on the DAP. The DAP must be soldered on to the PCB and connected to the GND
pin of the device. An additional thermal via can significantly improve power dissipation of the device.
10.2 Layout Example
VIN
PGND
VOUT
ENB
PWMB
PGND
2019181716
15
SDA
SCL
1
2
3
4
5
14
13
12
11
PGND
CS1
CS2
AGND
6 7
8 9 10
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31
TPS61177A
ZHCSDK2B –MARCH 2015–REVISED MARCH 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
32
版权 © 2015–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61177ARGRR
ACTIVE
VQFN
RGR
20
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
77AS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61177ARGRR
VQFN
RGR
20
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGR 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPS61177ARGRR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGR 20
3.5 x 3.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228482/A
www.ti.com
PACKAGE OUTLINE
RGR0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
3.65
3.35
SIDE WALL
METAL THICKNESS
DIM A
1.0
0.8
OPTION 1
0.1
OPTION 2
0.2
C
SEATING PLANE
0.08 C
0.05
0.00
2X 2
(DIM A) TYP
SYMM
6
10
EXPOSED
THERMAL PAD
11
5
SYMM
21
2X 2
2.05 0.1
16X 0.5
1
15
0.30
20X
PIN 1 ID
20
16
0.18
0.5
0.3
0.1
C A B
20X
0.05
4219031/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGR0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
16
SEE SOLDER MASK
DETAIL
20
20X (0.6)
15
20X (0.24)
16X (0.5)
1
(2.05)
SYMM
21
(3.3)
(0.775)
5
11
(R0.05) TYP
(
0.2) TYP
VIA
6
10
(0.775)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219031/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGR0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
16
20
20X (0.6)
1
20X (0.24)
16X (0.5)
15
(0.56) TYP
(3.3)
21
SYMM
4X (0.92)
11
(R0.05) TYP
5
6
10
4X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 21
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219031/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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