TPS61194PWPRQ1 [TI]
适用于汽车照明的低 EMI、高性能 4 通道 LED 驱动器 | PWP | 20 | -40 to 125;
| 型号： | TPS61194PWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于汽车照明的低 EMI、高性能 4 通道 LED 驱动器 | PWP | 20 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总35页 (文件大小：1117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61194-Q1
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
TPS61194-Q1 具有四条 100mA 通道的低 EMI 汽车 LED 驱动器
1 特性
2 应用
1
•
符合汽车应用 要求
•
为以下应用提供背光：
•
具有符合 AEC-Q100 标准的下列结果：
–
–
–
–
–
–
汽车信息娱乐系统
汽车仪表盘
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
智能车镜
•
•
输入工作电压范围：4.5V 至 40V
抬头显示屏 (HUD)
中央信息显示屏 (CID)
音视频导航 (AVN)
四路高精度电流阱
–
–
–
电流匹配率为 1%（典型值）
发光二极管 (LED) 灯串电流高达 100mA/通道
输出可在外部合并，从而提高每条灯串的电流
3 说明
•
•
100Hz 频率下的调光比率高达 10000:1
TPS61194-Q1 是一款集成 DC-DC 转换器的低电磁干
扰 (EMI) 且易于使用的汽车类高效 LED 驱动器。DC-
DC 转换器支持升压和 SEPIC 工作模式。该器件具备
的四路高精度电流阱可进行组合，以提高电流能力。
适用于 LED 灯串电源的集成升压/SEPIC 转换器
–
–
–
–
输出电压高达 45V
开关频率：300kHz 至 2.2MHz
开关同步输入
DC-DC 转换器可基于 LED 电流阱余量电压提供自适
应输出电压控制。该特性可在所有条件下将电压调节到
能够满足需要的最低水平，从而最大限度降低功耗。为
了降低 EMI，DC-DC 转换器支持针对开关频率进行扩
频以及使用专用引脚实现外部同步。凭借较大的可调节
频率范围，TPS61194-Q1 能够避免调幅无线电频带干
扰。
扩展频谱，用于降低电磁干扰 (EMI)
•
丰富的故障检测功能 特性
–
–
–
–
故障输出
输入过压保护 (OVP) 和欠压锁定 (UVLO)
开路和短路 LED 故障检测
热关断
•
最大限度减少外部组件数
TPS61194-Q1 的输入电压范围为 4.5V 至 40V，支持
汽车启动/停止以及负载突降情况。TPS61194-Q1 集成
了丰富的故障检测 功能的反馈。
简化电路原理图
L1
D1
VOUT up to 45 V
VIN 4.5...40 V
C
IN
器件信息(1)
C
OUT
器件型号
封装
封装尺寸（标称值）
R2
R1
SW
TPS61194-Q1
HTSSOP (20)
6.50mm x 4.40mm
FB
C
FB
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
VIN
Up to 100 mA/string
LDO
CLDO
RFSET
TPS61194-Q1OUT1
系统效率
OUT2
100
95
FSET
OUT3
OUT4
SYNC
PWM
90
BRIGHTNESS
EN
85
VDDIO/EN
FAULT
80
ISET
VIN=5V
75
70
65
VIN=8V
PGND
GND PAD
VIN=12V
VIN=16V
RISET
0
20
40
60
80
100
Brightness (%)
C012
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAE9
TPS61194-Q1
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
www.ti.com.cn
目录
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Applications ................................................ 21
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics .......................................... 6
7.6 Internal LDO Electrical Characteristics ..................... 6
7.7 Protection Electrical Characteristics ......................... 6
7.8 Current Sinks Electrical Characteristics.................... 7
7.9 PWM Brightness Control Electrical Characteristics .. 7
7.10 Boost and SEPIC Converter Characteristics .......... 7
7.11 Logic Interface Characteristics................................ 7
7.12 Typical Characteristics............................................ 9
Detailed Description ............................................ 11
9
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 器件和文档支持 ..................................................... 29
12.1 器件支持................................................................ 29
12.2 文档支持................................................................ 29
12.3 接收文档更新通知 ................................................. 29
12.4 社区资源................................................................ 29
12.5 商标....................................................................... 29
12.6 静电放电警告......................................................... 29
12.7 Glossary................................................................ 29
13 机械、封装和可订购信息....................................... 29
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (April 2017) to Revision D
Page
•
•
Enhanced pin descriptions for pins 3, 10 and 16 in Pin Functions ....................................................................................... 4
Deleted "Dimming ratio is calculated as ratio between the input PWM period and minimum on/off time (0.5 µs). "
from Brightness Control........................................................................................................................................................ 15
Changes from Revision B (October 2016) to Revision C
Page
•
•
•
•
Deleted "IOUT = 100 mA" from tON/OFF row of Table 7.9 .......................................................................................................... 7
Changed "0.5" from MAX to TYP column in tON/OFF row of Table 7.9 ................................................................................... 7
Added table note 1 for Tables 7.9 and 7.10........................................................................................................................... 7
Deleted "Initial DC-DC voltage is about 88% of VMAX BOOST." from Integrated DC-DC Converter; change wording in
last sentence before equation 1. .......................................................................................................................................... 13
•
•
Changed eq. 1; added "K" eq definitions for eq. 1 and paragraph after Fig. 9 ................................................................... 13
Added new paragraph before Internal LDO ......................................................................................................................... 15
Changes from Revision A (January 2016) to Revision B
Page
•
•
已删除 特性中多个条目的措辞 ............................................................................................................................................... 1
已更改 “输出电流”至“LED 灯串电流”以及“200Hz 频率下的调光比率高达 10000:1”至“100Hz 频率下的调光比率高达
10000:1”.................................................................................................................................................................................. 1
•
•
•
•
•
已添加 其他应用 .................................................................................................................................................................... 1
已更改 说明中的多处措辞 - 为了清晰起见 .............................................................................................................................. 1
已更改 “高开关频率”更改为“宽范围可调频率” ......................................................................................................................... 1
已添加 器件比较表.................................................................................................................................................................. 3
Added 2 new LED Current graphs ....................................................................................................................................... 10
2
版权 © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
Changes from Original (December 2015) to Revision A
Page
•
已更改 将“预览”更改为“生产数据” ........................................................................................................................................... 1
5 器件比较表
LP8860-Q1
LP8862-Q1
LP8861-Q1
TPS61193-Q1
TPS61194-Q1
TPS61196-Q1
VIN 范围
3V 至 48V
4.5V 至 40V
4.5V 至 45V
4.5V 至 40V
4.5V 至 40V
8V 至 30V
LED 通道的数量
LED 电流/通道
I2C/SPI 支持
SEPIC 支持
4
150mA
有
2
160mA
無
4
100mA
無
3
100mA
無
4
100mA
無
6
200mA
無
否
有
是
是
是
无
Copyright © 2016–2017, Texas Instruments Incorporated
3
TPS61194-Q1
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
www.ti.com.cn
6 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
VIN
LDO
1
2
3
4
5
6
7
8
9
20
19
VIN
NC
FSET
18 SW
PGND
VDDIO/EN
FAULT
17
16 FB
SYNC
PWM
15
14
13
12
11
OUT1
OUT2
OUT3
OUT4
NC
GND
EP*
ISET 10
GND
*EXPOSED PAD
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
VIN
A
A
Input power pin
2
LDO
Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free GND.
DC-DC (boost or SEPIC) switching frequency setting resistor; for normal operation, resistor value
from 24 kΩ to 219 kΩ must be connected between this pin and ground.
3
FSET
A
4
5
VDDIO/EN
FAULT
I
Enable input for the device as well as supply input (VDDIO) for digital pins
Fault signal output. If unused, the pin may be left floating.
OD
Input for synchronizing boost. If synchronization is not used, connect this pin to GND to disable
spread spectrum or to VDDIO/EN to enable spread spectrum.
6
SYNC
I
7
8
9
PWM
NC
I
PWM dimming input.
No connect
—
G
GND
Ground.
LED current setting resistor; for normal operation, resistor value from 24 kΩ to 129 kΩ must be
connected between this pin and ground.
10
11
12
ISET
GND
A
G
A
Ground
Current sink output
This pin must be connected to GND if not used.
OUT4
Current sink output
This pin must be connected to GND if not used.
13
14
15
OUT3
OUT2
OUT1
A
A
A
Current sink output
This pin must be connected to GND if not used.
Current sink output
This pin must be connected to GND if not used.
DC-DC (boost or SEPIC) feedback input; for normal operation this pin must be connected to the
middle of a resistor divider between VOUT and ground using feedback resistor values from 5 kΩ to
150 kΩ.
16
FB
A
17
18
19
20
PGND
SW
G
A
A
A
DC-DC (boost or SEPIC) power ground
DC-DC (boost or SEPIC) switch pin
No connect
NC
VIN
Input power pin
(1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin
4
Copyright © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
MAX
50
UNIT
VIN, SW, FB
Voltage on pins
OUT1, OUT2, OUT3, OUT4
45
V
LDO, SYNC, FSET, ISET, PWM, VDDIO/EN, FAULT
5.5
Continuous power dissipation(3)
Internally Limited
(4)
Ambient temperature range TA
Junction temperature range TJ
–40
–40
125
°C
°C
(4)
150
Maximum lead temperature (soldering)
Storage temperature, Tstg
See(5)
–65
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and
disengages at TJ = 145°C (typical).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
(5) For detailed soldering specifications and information, refer to the PowerPAD™ Thermally Enhanced Package .
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All other pins
V
Charged-device model (CDM), per AEC Q100-
011
Corner pins (1,10,11,20)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VIN
4.5
0
45
45
SW
Voltage on pins
OUT1, OUT2, OUT3, OUT4
FB, FSET, LDO, ISET, VDDIO/EN, FAULT
SYNC, PWM
0
40
V
0
5.25
0
VDDIO/EN
(1) All voltages are with respect to the potential at the GND pins.
Copyright © 2016–2017, Texas Instruments Incorporated
5
TPS61194-Q1
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
www.ti.com.cn
7.4 Thermal Information
TPS61194-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
20 PINS
44.2
26.5
22.4
0.9
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
22.2
2.5
RθJCbot
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
7.5 Electrical Characteristics(1)(2)
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device disabled, VVDDIO/EN = 0 V,
VIN = 12 V
Standby supply current
4.5
20
μA
IQ
VIN = 12 V, VOUT = 26 V, output
current 80 mA/channel, converter
ƒSW = 300 kHz
Active supply current
5
12
mA
VPOR_R
VPOR_F
TTSD
Power-on reset rising threshold
Power-on reset falling threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
LDO pin voltage
LDO pin voltage
2.7
V
V
1.5
150
165
20
175
°C
°C
TTSD_HYST
(1) All voltages are with respect to the potential at the GND pins.
(2) Minimum and maximum limits are specified by design, test, or statistical analysis.
7.6 Internal LDO Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
Output voltage
TEST CONDITIONS
VIN = 12 V
MIN
4.15
120
TYP
4.3
MAX
4.55
430
UNIT
V
VLDO
VDR
Dropout voltage
300
50
mV
mA
ISHORT
Short circuit current
7.7 Protection Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
42
4
MAX
UNIT
V
VOVP
VIN OVP threshold voltage
VIN UVLO
41
44
VUVLO
V
VUVLO_HYST
VIN UVLO hysteresis
LED short detection threshold
100
6
mV
V
5.6
7
6
Copyright © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
7.8 Current Sinks Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
0.1
MAX UNIT
ILEAKAGE
IMAX
Leakage current
Outputs OUT1 to OUT4 , VOUTx = 45 V
OUT1, OUT2, OUT3, OUT4
IOUT = 100 mA
5
µA
Maximum current
100
mA
IOUT
Output current accuracy
Output current matching(1)
Saturation voltage(2)
−5%
5%
5%
0.7
IMATCH
VSAT
IOUT = 100 mA, PWM duty =100%
IOUT = 100 mA
1%
0.4
V
(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (OUTx), the following are determined:
the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching
number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED
current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.
7.9 PWM Brightness Control Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Hz
ƒPWM
PWM input frequency
Minimum on/off time(1)
100
20 000
tON/OFF
0.5
µs
(1) This specification is not ensured by ATE.
7.10 Boost and SEPIC Converter Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
Unless otherwise specified: VIN = 12 V, VEN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10-μF ceramic and 33-μF electrolytic,
COUT = 2 × 10-μF ceramic and 33-μF electrolytic, D = NRVB460MFS, ƒSW = 300 kHz.
PARAMETER
Input voltage
TEST CONDITIONS
MIN
4.5
6
TYP
MAX
40
UNIT
VIN
V
VOUT
Output voltage
45
Minimum switching frequency
(central frequency if spread
spectrum is enabled)
ƒSW_MIN
300
kHz
kHz
Defined by RFSET resistor
Maximum switching frequency
(central frequency if spread
spectrum is enabled)
ƒSW_MAX
2 200
VOUT/VIN
TOFF
Conversion ratio
Minimum switch OFF time(1)
10
55
ƒ
SW ≥ 1.15 MHz
ns
A
ISW_MAX
RDSON
SW current limit
1.8
2
2.2
FET RDSON
Pin-to-pin
240
400
mΩ
kHz
ns
fSYNC
External SYNC frequency
External SYNC minimum on time(1)
External SYNC minimum off time(1)
300
2 200
tSYNC_ON_MIN
tSYNC_OFF_MIN
150
150
ns
(1) This specification is not ensured by ATE.
7.11 Logic Interface Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT VDDIO/EN
VIL
VIH
II
Input low level
Input high level
Input current
0.4
30
V
1.65
−1
5
µA
LOGIC INPUT SYNC/FSET, PWM
Copyright © 2016–2017, Texas Instruments Incorporated
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ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
www.ti.com.cn
Logic Interface Characteristics (continued)
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
Input low level
Input high level
Input current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIL
VIH
II
0.2 × VDDIO/EN
0.8 × VDDIO/EN
−1
1
μA
LOGIC OUTPUT FAULT
VOL
Output low level
Pullup current 3 mA
V = 5.5 V
0.3
0.5
1
V
ILEAKAGE
Output leakage current
μA
8
Copyright © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
7.12 Typical Characteristics
Unless otherwise specified: D = NRVB460MFS, T = 25°C
1000
900
800
700
600
500
1000
900
800
700
600
500
400
300
200
Vboost = 22 V
Vboost = 30 V
Vboost = 37 V
Vboost = 22 V
Vboost = 30V
Vboost = 37 V
400
300
200
5
10
15
20
25
30
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
C001
C002
ƒSW = 300 kHz
L = 33 μH
DC Load (PWM = 100%)
ƒSW = 800 kHz
L = 15 μH
DC Load (PWM = 100%)
CIN and COUT = 33 µF + 2 × 10 µF (ceramic)
CIN and COUT = 2 ×10 µF (ceramic)
Figure 1. Maximum Boost Current
Figure 2. Maximum Boost Current
1000
900
800
700
600
500
400
300
200
1000
900
800
700
600
500
400
300
200
Vboost = 22 V
Vboost = 30 V
Vboost = 37 V
Vboost = 22 V
Vboost = 30 V
Vboost = 37 V
5
10
15
20
25
30
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
C003
C004
ƒSW = 1.5 MHz
L = 8.2 μH
DC Load (PWM = 100%)
ƒSW = 2.2 MHz
L = 4.7 μH
DC Load (PWM = 100%)
CIN and COUT = 2 × 10 µF (ceramic)
CIN and COUT = 2 × 10 µF (ceramic)
Figure 3. Maximum Boost Current
Figure 4. Maximum Boost Current
100
80
60
40
20
0
2200
1800
1400
1000
600
200
20
60
100
140
180
220
20
40
60
80
100
120
140
160
RFSET (kꢀ)
C009
RISET (kꢀ)
C005
Figure 6. Boost Switching Frequency ƒSW vs RFSET
Figure 5. LED Current vs RISET
Copyright © 2016–2017, Texas Instruments Incorporated
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ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
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Typical Characteristics (continued)
Unless otherwise specified: D = NRVB460MFS, T = 25°C
120
100
80
60
40
20
0
6
5
4
3
2
1
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
40
50
60
70
80
90
100
Voltage (V)
C014
Output current (mA)
C013
RISET = 24 kΩ
Figure 8. LED Current Sink Saturation Voltage
Figure 7. LED Current Sink Matching
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8 Detailed Description
8.1 Overview
The TPS61194-Q1 is a highly integrated LED driver for automotive infotainment, lighting system and medium-
sized LCD backlight applications. It includes a DC-DC with an integrated FET, supporting both boost and SEPIC
modes, an internal LDO enabling direct connection to battery without need for a pre-regulated supply and four
LED current sinks. The VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs) and at
the same time enables the device.
The switching frequency on the DC-DC converter is set by a resistor connected to the FSET pin. The maximum
voltage of the DC-DC is set by a resistive divider connected to the FB pin. For the best efficiency the output
voltage is adapted automatically to the minimum necessary level needed to drive the LED strings. This is done
by monitoring LED output voltage drop in real time. For EMI reduction and control two optional features are
available:
•
•
Spread spectrum, which reduces EMI noise around the switching frequency and its harmonic frequencies
DC-DC can be synchronized to an external frequency connected to SYNC pin
The four constant current outputs OUT1, OUT2, OUT3, and OUT4 provide LED current up to 100 mA.Value for
the current per OUT pin is set with a resistor connected to ISET pin. Current sinks that are not used must be
connected to ground. Grounded current sink is disabled and excluded from adaptive voltage detection loop.
Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED
output PWM follows the input PWM so the output frequency is equal to the input frequency.
TPS61194-Q1 has extensive fault detection features :
•
•
•
•
Open-string and shorted LED detections
LED fault detection prevents system overheating in case of open or short in some of the LED strings
VIN input overvoltage protection
Threshold sensing from VIN pin
VIN input undervoltage protection
Threshold sensing from VIN pin
Thermal shutdown in case of die overtemperature
–
–
–
Fault condition is indicated through the FAULT output pin.
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8.2 Functional Block Diagram
L
D
VOUT
VIN
CIN
COUT
VIN
LDO
LDO
CLDO
SW
SYNC
PGND
FB
BOOST
CONTROLLER
RFSET
FSET
ISET
R1
RISET
R2
LED
CURRENT
SINKS
CURRENT
SETTING
OUT1
OUT2
OUT3
PWM
VDDIO/EN
FAULT
DIGITAL BLOCKS
(FSM, ADAPTIVE VOLTAGE
CONTROL, SAFETY LOGIC
etc.)
OUT4
GND
ANALOG BLOCKS
(CLOCK GENERATOR,
VREF, TSD etc.)
VDDIO
EXPOSED PAD
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8.3 Feature Description
8.3.1 Integrated DC-DC Converter
The TPS61194-Q1 DC-DC converter generates supply voltage for the LEDs and can operate in boost mode or in
SEPIC mode. The maximum output voltage VOUT_MAX is defined by an external resistive divider (R1, R2).
VOUT_MAX voltage should be chosen based on the maximum voltage required for LED strings. Recommended
maximum voltage is about 30% higher than maximum LED string voltage. DC-DC output voltage is adjusted
automatically based on LED current sink headroom voltage. Maximum, minimum, and initial boost voltages can
be calculated with Equation 1:
V
≈
’
BG
VBOOST
=
+K ì 0.0387 ì R1+ VBG
∆
«
÷
R2
◊
where
•
•
•
•
•
•
VBG = 1.2 V
R2 recommended value is 130 kΩ
Resistor values are in kΩ
K = 1 for maximum adaptive boost voltage (typical)
K = 0 for minimum adaptive boost voltage (typical)
K = 0.88 for initial boost voltage (typical)
(1)
45
40
35
30
25
20
15
10
200
300
400
500
600
700
800
900
1000
R1 (kꢀ)
C008
Figure 9. Maximum Converter Output Voltage vs R1 Resistance
Alternatively, a T-divider can be used if resistance less than 100 kΩ is required for the external resistive divider.
Refer to Using the TPS61194xEVM Evaluation Module for details.
The converter is a current mode DC-DC converter, where the inductor current is measured and controlled with
the feedback. Switching frequency is adjustable between 250 kHz and 2.2 MHz with RFSET resistor as
Equation 2:
ƒSW = 67600 / (RFSET + 6.4)
where
•
•
ƒSW is switching frequency, kHz
RFSET is frequency setting resistor, kΩ
(2)
In most cases lower frequency has higher system efficiency. DC-DC internal parameters are chosen
automatically according to the selected switching frequency (see Table 2) to ensure stability. In boost mode a 15-
pF capacitor CFB must be placed across resistor R1 when operating in 300-kHz to 500-kHz range (see Typical
Application for 4 LED Strings). When operating in the 1.8-MHz to 2.2-MHz range CFB = 4.7 pF.
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Feature Description (continued)
D
VIN
VOUT
CIN
COUT
R1
SW
OCP
ADAPTIVE
VOLTAGE
CONTROL
RC
R2
LIGHT
LOAD
CURRENT
SENSE
OVP
R
S
R
R
filter
FB
-
GM
PGND
R
+
SYNC
GM
ꢀ
FSET
FSET
CTRL
BLANK
TIME
BOOST
OSCILLATOR
OFF/BLANK
TIME
CURRENT
RAMP
PULSE
GENERATOR
GENERATOR
RFSET
Figure 10. Boost Block Diagram
DC-DC can be driven by an external SYNC signal between 300 kHz and 2.2 MHz. If the external synchronization
input disappears, DC-DC continues operation at the frequency defined by RFSET resistor. When external
frequency disappears and SYNC pin level is low, converter continues operation without spread spectrum
immediately. If SYNC remains high, converter continues switching with spread spectrum enabled after 256 µs.
External SYNC frequency must be 1.2 to 1.5 times higher than the frequency defined by RFSET resistor. Minimum
frequency setting with RFSET is 250 kHz to support 300-kHz switching with external clock.
The optional spread spectrum feature (±3% from central frequency, 1-kHz modulation frequency) reduces EMI
noise at the switching frequency and its harmonic frequencies. When external synchronization is used, spread
spectrum is not available.
Table 1. DC-DC Synchronization Mode
SYNC PIN INPUT
MODE
Low
High
Spread spectrum disabled
Spread spectrum enabled
300 to 2200 kHz frequency
Spread spectrum disabled, external synchronization mode
Table 2. DC-DC Parameters(1)
TYPICAL BOOST INPUT
AND OUTPUT
CAPACITORS (µF)
FREQUENCY
(kHz)
TYPICAL
INDUCTANCE (µH)
MINIMUM SWITCH
OFF TIME (ns)(2)
BLANK
TIME (ns)
CURRENT
RAMP (A/s)
CURRENT RAMP
DELAY (ns)
RANGE
1
2
3
4
300 to 480
480 to 1150
1150 to 1650
1650 to 2200
33
15
10
4.7
2 ×10 (cer.) + 33 (electr.)
10 (cer.) + 33 (electr.)
3 × 10 (cer.)
150
60
95
95
95
70
24
43
550
300
0
40
79
3 × 10 (cer.)
40
145
0
(1) Parameters are for reference only
(2) Due to current sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.
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The converter SW pin DC current is limited to 2 A (typical). To support warm-start transient condition the current
limit is automatically increased to 2.5 A for a short period of 1.5 seconds when a 2-A limit is reached.
NOTE
Application condition where the 2-A limit is exceeded continuously is not allowed. In this
case the current limit would be 2 A for 1.5 seconds followed by 2.5-A limit for 1.5 seconds,
and this 3-second period repeats.
To keep switching voltage within safe levels there is a 48-V limit comparator in the event that FB loop is broken.
8.3.2 Internal LDO
The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage for internal use. Connect a
minimum of 1-µF ceramic capacitor from LDO pin to ground, as close to the LDO pin as possible.
8.3.3 LED Current Sinks
8.3.3.1 Output Configuration
TPS61194-Q1 detects LED output configuration during start-up. Any current sink output connected to ground is
disabled and excluded from the adaptive voltage control of the DC-DC and fault detections.
8.3.3.2 Current Setting
Maximum current for the LED outputs is controlled with external RISET resistor. RISET value for target maximum
current can be calculated using Equation 3:
RISET = 2342 / (IOUT œ 2.5)
where
•
•
RISET is current setting resistor, kΩ
ILED is output current per output, mA
(3)
8.3.3.3 Brightness Control
TPS61194-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the
input PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.
8.3.4 Protection and Fault Detections
The TPS61194-Q1 has fault detection for LED open and short, VIN input overvoltage protection (VIN_OVP) , VIN
undervoltage lockout (VIN_UVLO), and thermal shutdown (TSD).
8.3.4.1 Adaptive DC-DC Voltage Control and Functionality of LED Fault Comparators
Adaptive voltage control function adjusts the DC-DC output voltage to the minimum sufficient voltage for proper
LED current sink operation. The current sink with highest VF LED string is detected and DC-DC output voltage
adjusted accordingly. DC-DC adaptive control voltage step size is defined by maximum voltage setting, VSTEP
=
(VOUT_MAX – VOUT_MIN) / 256. Periodic down pressure is applied to the target voltage to achieve better system
efficiency.
Every LED current sink has 3 comparators for the adaptive DC-DC control and LED fault detections. Comparator
outputs are filtered, filtering time is 1 µs.
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OUT#
SHORT STRING
DETECTION LEVEL
HIGH_COMP
VOLTAGE THRESHOLD
MID_COMP
LOW_COMP
LOWEST VOLTAGE
CURRENT/PWM
CONTROL
Figure 11. Comparators for Adaptive Voltage Control and LED Fault Detection
Figure 12 shows different cases which cause DC-DC voltage increase, decrease, or generate faults. In normal
operation voltage at all the OUT# pins is between LOW_COMP and MID_COMP levels, and boost voltage stays
constant. LOW_COMP level is the minimum for proper LED current sink operation, 1.1 × VSAT + 0.2 V (typical).
MID_COMP level is 1.1 × VSAT + 1.2 V (typical) so typical headroom window is 1 V.
When voltage at all the OUT# pins increases above MID_COMP level, DC-DC voltage adapts downwards.
When voltage at any of the OUT# pins falls below LOW_COMP threshold, DC-DC voltage adapts upwards. In
the condition where DC-DC voltage reaches the maximum and there are one or more outputs still below
LOW_COMP level, an open LED fault is detected.
HIGH_COMP level, 6 V typical, is the threshold for shorted LED detection. When the voltage of one or more of
the OUT# pins increases above HIGH_COMP level and at least one of the other outputs is within the normal
headroom window, shorted LED fault is detected.
Shorted LED fault (at
DCDC
decreases
voltage
DCDC
increases
voltage
least one output should
be between LOW_COMP
and MID_COMP)
Open LED fault when
VOUT = VOUT_MAX
No actions
No actions
Shorted
LED fault
Minimum
headroom
level reached
All outputs are
above headroom
window
Open LED
fault
HIGH_COMP
MID_COMP
HEADROOM
WINDOW
LOW_COMP
Figure 12. Protection and DC-DC Voltage Adaptation Algorithms
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8.3.4.2 Overview of the Fault/Protection Schemes
A summary of the TPS61194-Q1fault detection behavior is shown in Table 3. Detected faults (excluding LED
open or short) cause device to enter FAULT_RECOVERY state. In FAULT_RECOVERY the DC-DC and LED
current sinks of the device are disabled, and the FAULT pin is pulled low. The device recovers automatically and
enters normal operating mode (ACTIVE) after a recovery time of 100 ms if the fault condition has disappeared.
When recovery is succesful, FAULT pin is released.
If a LED fault is detected, the device continues normal operation and only the faulty string is disabled. The fault is
indicated via the FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2 µs to 20
µs. LEDs are turned off for this period but the device stays in ACTIVE mode. If VDDIO/EN is low longer, the
device goes to STANDBY and restarts when EN goes high again.
Table 3. Fault Detections
FAULT_
RECOVERY
STATE
FAULT/
PROTECTION
FAULT
PIN
FAULT NAME
VIN_OVP
THRESHOLD
ACTION
1. Overvoltage is monitored from the beginning of soft
start. Fault is detected if the duration of overvoltage
condition is 100 µs minimum.
2. Overvoltage is monitored from the beginning of
normal operation (ACTIVE mode). Fault is detected if
over-voltage condition duration is 560 ms minimum
(tfilter). After the first fault, detection filter time is reduced
to 50 ms for following recovery cycles. When the device
recovers and has been in ACTIVE mode for 160 ms,
filter time is increased back to 560 ms .
1. VIN > 42 V
2. VOUT
>
VSET_DCDC + 6..10
V.
VSET_DCDC is
voltage value
defined by logic
during adaptation
VIN
overvoltage
protection
Yes
Yes
Yes
Yes
Yes
No
VIN
undervoltage
lockout
Detects undervoltage condition at VIN pin. Sensed in all
operating modes. Fault is detected if undervoltage
condition duration is 100 µs minimum.
Falling 3.9 V
Rising 4 V
VIN_UVLO
OPEN_LED
Detected if the voltage of one or more current sinks is
below threshold level, and DC-DC adaptive control has
reached maximum voltage. Open string is removed from
the DC-DC voltage control loop and current sink is
disabled.
Fault pin is released by toggling VDDIO/EN pin. If
VDDIO/EN is low for a period of 2 µs to 20 µs, LEDs are
turned off for this period but device stays ACTIVE. If
VDDIO/EN is low longer, device goes to STANDBY and
restarts when EN goes high again.
LOW_COMP
threshold
Open LED fault
Detected if the voltage of one or more current sinks is
above shorted string detection level and at least one
OUTx voltage is within headroom window. Shorted string
is removed from the DC-DC voltage control loop and
current sink is disabled.
Fault pin is released by toggling VDDIO/EN pin. If
VDDIO/EN is low for a period of 2…20 µs, LEDs are
turned off for this period but device stays ACTIVE. If
VDDIO/EN is low longer, device goes to STANDBY and
restarts when EN goes high again..
Shorted LED
fault
Shorted string
detection level 6 V
SHORT_LED
Yes
Yes
No
165ºC
Thermal shutdown
hysteresis 20ºC
Thermal shutdown is monitored from the beginning of
soft start. Die temperature must decrease by 20ºC for
device to recover.
Thermal
protection
TSD
Yes
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Time is not enough to
discharge COUT
VIN OVERVOLTAGE
VIN OK
VIN
VOUT
VSET_DCDC + 6...10 V
IOUT
FAULT
tFILTER = 560 ms
tRECOVERY
100 ms
=
tSOFTSTART
tBOOST START
+
tFILTER
50 ms
=
tRECOVERY
100 ms
=
tSOFTSTART
tBOOST START 40 - 50 ms
+
tFILTER
=
tRECOVERY
100 ms
=
tSOFTSTART + tFILTER =
tBOOST START 50 ms
Figure 13. VIN Overvoltage Protection (DC-DC OVP)
VIN OVP threshold
VIN
DCDC OVP threshold
FB
ttSOFTSTART +t
ttBOOST STARTUP
FAULT
ttRECOVERY = 100 mst
ttRECOVERY = 100 mst
t
Figure 14. VIN Overvoltage Protection (VIN OVP)
UVLO rising threshold
UVLO falling threshold
VIN
FB
ttSOFTSTART +t
ttBOOST STARTUP
FAULT
ttRECOVERY = 100 mst
ttRECOVERY = 100 mst
t
Figure 15. VIN Undervoltage Lockout
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VOUT_MAX
VOUT
OUT# pin
Other LEDs
OUT# pin
Open LED
LOW_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 16. LED Open Fault
MID_COMP level
LOW_COMP level
OUT# pin
Other LEDs
OUTT# pin
Shorted LED
HIGH_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 17. LED Short Fault
8.4 Device Functional Modes
8.4.1 Device States
The TPS61194-Q1 enters STANDBY mode when the internal LDO output rises above the power-on reset level,
VLDO > VPOR. In STANDBY mode the device is able to detect VDDIO/EN signal. When VDDIO/EN is pulled high,
the device powers up. After start LED outputs are sensed to detect grounded outputs. Grounded outputs are
disabled and excluded from the adaptive voltage control loop of the DC-DC.
If a fault condition is detected, the device enters FAULT_RECOVERY state. Faults that cause the device to enter
FAULT_RECOVERY are listed in Table 3. When LED open or short is detected, the faulty string is disabled, but
device stays in ACTIVE mode.
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Device Functional Modes (continued)
POR=1
STANDBY
VDDIO/EN=1
VIN_OVP
VIN_UVLO
TSD
100 ms
SOFT START
65 ms
50 ms
FAULT RECOVERY
BOOST START
FAULTS
VDDIO/EN=0
NO
FAULT
RECOVERY?
FAULTS
FAULTS:
- VIN_OVP
- VIN_UVLO
- TSD
LED OUTPUT
CONFIGURATION
DETECTION
YES
ACTIVE
VDDIO/EN=0
DC-DC AND LED CURRENT
SINKS ARE DISABLED IN
FAULT RECOVERY STATE
SHUTDOWN
Figure 18. State Diagram
T=50ꢀs
t>500ꢀs
VIN
LDO
VDDIO/EN
SYNC
Headroom adaptation
VOUT=VIN level œ diode drop
VOUT
PWM OUT
IQ
Active mode
SOFT
START
BOOST
START
Figure 19. Timing Diagram for the Typical Start-Up and Shutdown
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS61194-Q1 is designed for automotive applications, and an input voltage (VIN), intended to be connected
to the automotive battery, supports input voltage range from 4.5 V to 40 V. Device internal circuitry is powered
from the integrated LDO.
The TPS61194-Q1 uses a simple four-wire control:
•
•
•
•
VDDIO/EN for enable
PWM input for brightness control
SYNC pin for boost synchronisation (optional)
FAULT output to indicate fault condition (optional)
9.2 Typical Applications
9.2.1 Typical Application for 4 LED Strings
Figure 20 shows the typical application for TPS61194-Q1 which supports 4 LED strings, 80 mA per string, , with
a boost switching frequency of 300 kHz.
VIN
5...28 V
L1
D1
Up to 37 V
CIN BOOST
C
OUT
R2
R1
SW
FB
C
FB
VIN
C
IN
Up to 100 mA/string
LDO
CLDO
RFSET
TPS61194-Q1OUT1
OUT2
OUT3
OUT4
FSET
SYNC
PWM
BRIGHTNESS
EN
VDDIO/EN
FAULT
FAULT
ISET
R3
PGND GND PAD
RISET
VDDIO
Figure 20. Four Strings 80 mA per String Configuration
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Typical Applications (continued)
9.2.1.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5 V – 28 V
LED string
4P8S LEDs (30 V)
LED string current
100 mA
Maximum boost voltage
37 V
Boost switching frequency
300 kHz
External boost sync
not used
Boost spread spectrum
enabled
L1
CIN
33 μH
100 µF, 50 V
CIN BOOST
COUT
CFB
2 × (10-µF, 50-V ceramic) + 33-µF, 50-V electrolytic
2 × (10-µF, 50-V ceramic) + 33-µF, 50-V electrolytic
15 pF
1 µF, 10 V
24 kΩ
CLDO
RISET
RFSET
R1
210 kΩ
750 kΩ
130 kΩ
10 kΩ
R2
R3
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.
The saturation current must be greater than the sum of the maximum load current, and the worst case average-
to-peak inductor current. Equation 4 shows the worst case conditions
IOUTMAX
ISAT
>
+ IRIPPLE
For Boost
D‘
VIN
x
(VOUT - VIN)
(2 x L x f)
Where IRIPPLE
=
VOUT
(VOUT œ VIN)
and D‘ = (1 - D)
Where D =
(VOUT
)
•
•
•
•
•
•
•
IRIPPLE - peak inductor current
IOUTMAX - maximum load current
VIN - minimum input voltage in application
L - min inductor value including worst case tolerances
f - minimum switching frequency
VOUT - output voltage
D - Duty Cycle for CCM Operation
(4)
As a result, the inductor should be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A
saturation current rating of at least 2.5 A is recommended for most applications. See Table 2 for recommended
inductance value for the different switching frequency ranges. The inductor’s resistance should be less than
300 mΩ for good efficiency.
22
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See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies. Power Stage
Designer™ Tool can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer.
9.2.1.2.2 Output Capacitor Selection
A ceramic capacitor with 2 × VMAX BOOST or more voltage rating is recommended for the output capacitor. The
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendations for different switching frequencies are shown in Table 2. To
minimize audible noise of ceramic capacitors their physical size should typically be minimized.
9.2.1.2.3 Input Capacitor Selection
A ceramic capacitor with 2 × VIN MAX or more voltage rating is recommended for the input capacitor. The DC-bias
effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value
selection. Capacitance recommendations for different boost switching frequencies are shown in Table 2.
9.2.1.2.4 LDO Output Capacitor
A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Typically a 1-µF capacitor is sufficient.
9.2.1.2.5 Diode
A Schottky diode should be used for the boost output diode. Do not use ordinary rectifier diodes because slow
switching speeds and long recovery times degrade the efficiency and the load regulation. Diode rating for peak
repetitive current should be greater than inductor peak current (up to 3 A) to ensure reliable operation in boost
mode. Average current rating should be greater than the maximum output current. Schottky diodes with a low
forward drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage
of the Schottky diode significantly larger than the output voltage.
9.2.1.3 Application Curves
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
VIN=5V
VIN=8V
VIN=12V
VIN=16V
VIN=5V
VIN=8V
VIN=12V
VIN=16V
0
20
40
60
80
100
0
20
40
60
80
100
Brightness (%)
Brightness (%)
C011
C012
Load 4 strings, 8 LEDs per string
100 mA/string for VIN = 12 V and VIN = 16 V
60 mA/string for VIN = 8 V
ƒsw=300 kHz, 33 μH
Load 4 strings, 8 LEDs per string
100 mA/string for VIN = 12 V and VIN = 16 V
60 mA/string for VIN = 8 V
ƒsw=300 kHz, 33 μH
50 mA/string for VIN = 5 V
50 mA/string for VIN = 5 V
Figure 21. Boost Efficiency
Figure 22. System Efficiency
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20ms/div
OUT1/OUT2/BOOST 10V/div
FAULT 2V/div
Figure 24. Open LED Fault
Figure 23. Typical Start-Up
9.2.2 SEPIC Mode Application
When LED string voltage can be above or below VIN voltage, SEPIC configuration can be used. In this example,
two separate coils are used for SEPIC. This can enable lower height external components to be used, compared
to a coupled coil solution. On the other hand, coupled coil typically maximizes the efficiency. Also, in this
example, an external clock is used to synchronize SEPIC switching frequency. External clock input can be
modulated to spread switching frequency spectrum.
D1
VIN
L1
C1
C
OUT
CIN SEPIC
R2
R1
SW
FB
VIN
Up to 100 mA/string
CLDO
C
IN
LDO
TPS61194-Q1OUT1
RFSET
OUT2
FSET
OUT3
OUT4
BOOST SYNC
BRIGHTNESS
SYNC
PWM
EN
VDDIO/EN
FAULT
FAULT
ISET
R3
GND
PGND
PAD
VDDIO
RISET
Figure 25. SEPIC Mode, 4 Strings, 100 mA per String Configuration
24
Copyright © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
9.2.2.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5 V – 30 V
LED string
4P2S LEDs (7.2 V)
LED string current
100 mA
Maxmum output voltage
10 V
SEPIC switching frequency
2.2 MHz
External sync for SEPIC
used
Spread spectrum
Internal spread spectrum disabled (external sync used)
L1, L2
CIN
10 µH
10 µF 50 V
CIN SEPIC
C1
2 × 10-µF, 50-V ceramic + 33 µF 50-V electrolytic
10-µF 50-V ceramic
COUT
CLDO
RISET
RFSET
R1
2 × 10-µF, 50-V ceramic + 33 µF 50-V electrolytic
1 µF, 10 V
24 kΩ
24 kΩ
184 kΩ
130 kΩ
10 kΩ
R2
R3
9.2.2.2 Detailed Design Procedure
In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output
voltage. Because of this, the maximum sum of input and output voltage must be limited below 50 V. See Detailed
Design Procedure for general external component guidelines. Main differences of SEPIC compared to boost are
described below.
Power Stage Designer™ Tool can be used for modeling SEPIC behavior: http://www.ti.com/tool/powerstage-
designer. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing
DC/DC Converters Based on SEPIC Topology (SLYT309).
9.2.2.2.1 Inductor
In SEPIC mode, currents flowing through the coupled inductors or the two separate inductors L1 and L2 are the
input current and output current, respectively. Values can be calculated using Power Stage Designer™ Tool or
using equations in SLYT309.
9.2.2.2.2 Diode
In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak
repetitive current should be greater than SW pin current limit (up to 3 A for transients) to ensure reliable
operation in boost mode. Average current rating should be greater than the maximum output current. Diode
voltage rating must be higher than sum of input and output voltages.
9.2.2.2.3 Capacitor C1
Ti recommends a ceramic capacitor with low ESR. Diode voltage rating must be higher than maximum input
voltage.
Copyright © 2016–2017, Texas Instruments Incorporated
25
TPS61194-Q1
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
www.ti.com.cn
9.2.2.3 Application Curves
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
VIN = 5V
VIN = 8V
VIN = 12V
VIN = 15V
VIN=5V
VIN=5V
VIN=12V
VIN=15V
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Brightness (%)
Brightness (%)
D001
D001
Load 100mA per string, 4 strings, 2 LEDs per string
fsw = 2.2 MHz
Load 100mA per string, 3 strings, 2 LEDs per string
ƒsw = 2.2 MHz
2 × 10 μH, IHLP2525BDER100M
2 × 10 μH, IHLP2525BDER100M
Figure 27. SEPIC Efficiency
Figure 26. SEPIC Efficiency
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VIN = 5V
VIN = 8V
VIN = 12V
VIN = 15V
0
10
20
30
40
50
60
70
80
90 100
Brightness (%)
D001
Load 100mA/string, 4 strings, 2 LEDs per string
fsw = 2.2 MHz
2 x 10 μH, IHLP2525BDER100M
Figure 28. System Efficiency
10 Power Supply Recommendations
The device is designed to operate from an automotive battery. Device should be protected from reversal voltage
and voltage dump over 50 V. The resistance of the input supply rail must be low enough so that the input current
transient does not cause too high drop at TPS61194-Q1 VIN pin. If the input supply is connected by using long
wires additional bulk capacitance may be required in addition to the ceramic bypass capacitors in the VIN line.
26
Copyright © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
11 Layout
11.1 Layout Guidelines
Figure 29 is a layout recommendation for TPS61194-Q1 used to demonstrate the principles of a good layout.
This layout can be adapted to the actual application layout if or where possible. It is important that all boost
components are close to the chip, and the high current traces must be wide enough. By placing boost
components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This
way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must be
placed as close as possible to the device.
Here are some main points to help the PCB layout work:
•
Current loops need to be minimized:
–
For low frequency the minimal current loop can be achieved by placing the boost components as close as
possible to the SW and PGND pins. Input and output capacitor grounds must be close to each other to
minimize current loop size.
–
Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High-frequency return currents find a route with minimum impedance, which is
the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the positivecurrent route in the ground plane, if the ground plane is intact
under the route.
•
•
•
•
The GND plane must be intact under the high current boost traces to provide shortest possible return path
and smallest possible current loops for high frequencies.
Current loops when the boost switch is conducting and not conducting must be on the same direction in
optimal case.
Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating
inductor 180° changes current direction.
Use separate power and noise-free grounds. Power ground is used for boost converter return current and
noise-free ground for more sensitive signals, such as LDO bypass capacitor grounding as well as grounding
the GND pin of the device.
•
Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the
diode cathode.
•
•
•
•
Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
Input and output capacitors require strong grounding (wide traces, many vias to GND plane).
If two output capacitors are used they must have symmetrical layout to get both capacitors working ideally.
Output ceramic capacitors have a DC-bias effect. If the output capacitance is too low, it can cause boost to
become unstable on some loads, and this increases EMI. DC-bias characteristics should be obtained from
the component manufacturer; they are not taken into account on component tolerance. TI recommends
X5R/X7R capacitors.
Copyright © 2016–2017, Texas Instruments Incorporated
27
TPS61194-Q1
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
www.ti.com.cn
11.2 Layout Example
VIN
VIN
VIN
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
LDO
LDO
NC
RFSET
SW
FSET
VDDIO/EN
FAULT
PGND
FB
OUT1
SYNC
PWM
VBOOST
OUT2
OUT3
OUT4
GND
13
12
NC
GND
RISET
11
10
ISET
Figure 29. TPS61194-Q1 Boost Layout
28
版权 © 2016–2017, Texas Instruments Incorporated
TPS61194-Q1
www.ti.com.cn
ZHCSEO9D –JANUARY 2016–REVISED MAY 2017
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
Power Stage Designer™工具可用于升压和 SEPIC 模式：http://www.ti.com.cn/tool/cn/powerstage-designer
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
•
《PowerPAD™ 耐热增强型封装》
《了解开关模式电源中的升压功率级》
《基于 SEPIC 拓扑设计 DC/DC 转换器》
12.3 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
Power Stage Designer, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
版权 © 2016–2017, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61194PWPRQ1
ACTIVE
HTSSOP
PWP
20
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
61194Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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