TPS612564CYFFT [TI]
采用 1.2mm x 1.3mm WCSP 封装且具有直通模式的 3.5MHz、5V、900mA 负载升压转换器 | YFF | 9 | -40 to 85;
| 型号： | TPS612564CYFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1.2mm x 1.3mm WCSP 封装且具有直通模式的 3.5MHz、5V、900mA 负载升压转换器 | YFF | 9 | -40 to 85 升压转换器 开关 |
| 文件： | 总29页 (文件大小：3260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
采用芯片级封装的 TPS61256xC 3.5 MHz 高效升压转换器
1 特性
借助 2.3V-5.5V 的宽输入电压范围，该器件支持由各
1
种电压的锂离子电池进行供电的 应用 。可提供 3.15V
到 5.0V 之间的不同固定电压输出版本。
•
•
•
•
•
•
•
•
•
•
•
频率为 3.5MHz 时，工作效率达 93%
正常运行时的静态电流为 37µA
2.3V 至 5.5V 的宽输入电压范围
支持 VIN ≥ VOUT 的工作模式
DC 电压输出总精度为 ±2%
轻负载频率脉冲调制 (PFM) 模式
通过拉低 EN 支持直通模式
热关断和过载保护
TPS61256xC 在 3.5MHz 的调节开关频率下运行，在
轻负载电流情况下会进入省电模式，以便在整个负载电
流范围内保持高效率。PFM 模式可在轻负载工作时将
静态电流降至 37μA（典型值），从而可延长电池使用
寿命。
此外，TPS61256xC 器件还可通过将 EN 拉至低电平
来支持直通模式。在这种模式下，输出电压跟随输入电
压变化，由电感器和高侧 FET 的电阻来降低电压。
只需三个表面贴装外部组件
总解决方案尺寸 < 25mm2
9 引脚 NanoFree™(CSP) 封装内
TPS61256xC 最大限度地减少了外部组件的数量，因
此拥有非常小巧的解决方案尺寸。为了实现小解决方案
尺寸，它允许使用小型电感器和输入电容器。
2 应用
•
•
•
•
NFC PA 电源
手机、智能电话
器件信息(1)
单声道和立体声 APA 应用
USB 充电端口
器件型号
封装
封装尺寸（标称值）
TPS61256xC
DSBGA (9)
1.206mm x 1.306mm
3 说明
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
TPS61256xC 器件为电池供电类便携式 优化提供了一
个电源解决方案。适用于低功耗 应用的 TPS61256xC
支持来自一节电池（放电电压低至 2.65V）的高达
800mA 的负载电流，并且允许使用低成本芯片电感器
和电容器。
效率与负载电流间的关系
VO = 5.0 V
100
90
80
70
60
50
40
30
20
.
10
0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDQ1
TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
www.ti.com.cn
目录
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ................................................ 12
11 Power Supply Recommendations ..................... 18
12 Layout................................................................... 18
12.1 Layout Guidelines ................................................. 18
12.2 Layout Example .................................................... 18
12.3 Thermal Considerations........................................ 19
13 器件和文档支持 ..................................................... 20
13.1 器件支持................................................................ 20
13.2 接收文档更新通知 ................................................. 20
13.3 社区资源................................................................ 20
13.4 商标....................................................................... 20
13.5 静电放电警告......................................................... 20
13.6 Glossary................................................................ 20
14 机械、封装和可订购信息....................................... 21
14.1 封装概要................................................................ 21
14.2 Package Option Addendum .................................. 22
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Options....................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 8
9.3 Feature Description................................................... 9
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (February 2017) to Revision A
Page
•
Added device numbers TPS612562C and TPS612564C ..................................................................................................... 3
2
Copyright © 2017, Texas Instruments Incorporated
TPS61256C
www.ti.com.cn
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
5 Device Options
OUTPUT
VOLTAGE
DEVICE
SPECIFIC FEATURES
TA
PART NUMBER(1)
TPS61256C
Supports 5 V / 900 mA loading
down to 3.3 V input voltage
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
5.0 V
5.2 V
5.4 V
Supports 5.2 V / 900 mA loading
down to 3.3 V input voltage
TPS612562C
TPS612564C
Supports 5.4 V / 900 mA loading
down to 3.3 V input voltage
(1) For all available packages, see the orderable addendum at the end of the datasheet.
6 Pin Configuration and Functions
YFF Package
9-Bump DSBGA
Top and Bottom Views
A1 A2 A3
B1 B2 B3
C1 C2 C3
A3 A2 A1
B3 B2 B1
C3 C2 C1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
EN = high, the device works in the boost mode. EN = low, the device is in pass-through mode. This
pin must not be left floating and must be terminated.
EN
B3
I
GND
SW
C1, C2, C3
B1, B2
A3
Ground pin.
I/O
I
This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs.
VIN
Power supply input.
VOUT
A1, A2
O
Boost converter output.
Copyright © 2017, Texas Instruments Incorporated
3
TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
Input voltage
Voltage at VIN(2), VOUT(2), SW(2), EN(2)
–0.3
V
(3)
Continuous average current into SW
1.8
3.5
Input current
A
(4)
Peak current into SW
Power dissipation
Internally limited
(5)
Operating, TA
–40
–40
–65
85
Temperature
Operating virtual junction, TJ
Storage, Tstg
150
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Limit the junction temperature to 105°C for continuous operation at maximum output power.
(4) Limit the junction temperature to 125°C for 5% duty cycle operation.
(5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
V(ESD)
Electrostatic discharge
V
Machine model (MM)
±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
MIN
2.5
10
NOM
MAX UNIT
VI
Input voltage range
TPS61256xC
TPS61256xC
4.85
V
Ω
RL
L
Minimum resistive load for start-up
Inductance
0.7
3.5
–40
–40
1.0
5
2.9
50
µH
µF
°C
°C
CO
TA
TJ
Output capacitance
Ambient temperature
Operating junction temperature
85
125
7.4 Thermal Information
TPS61256xC
YFF
THERMAL METRIC(1)
UNIT
9 PINS
108.3
1.0
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
18
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.2
ψJB
17.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
4
Copyright © 2017, Texas Instruments Incorporated
TPS61256C
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ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
7.5 Electrical Characteristics
Minimum and maximum values are at VIN = 2.3V to 5.5V, EN = 1.8V, TA = –40°C to 85°C; Circuit of Parameter Measurement
Information section (unless otherwise noted). Typical values are at VIN = 3.6V, EN = 1.8V, TA = 25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
IOUT = 0 mA, VIN = 3.6 V
EN = VIN
Device not switching
30
7
45
15
20
15
2.1
µA
µA
µA
µA
Operating quiescent current
into VIN Operating quiescent current
into VOUT pass-through mode quiescent current
into VIN pass-through mode quiescent current
into VOUT
IQ
IOUT = 0 mA, VIN = VOUT = 3.6 V
EN = GND,
Device not switching
11
9.5
Falling
2.0
0.1
V
V
VUVLO
Under-voltage lockout threshold
Hysteresis
ENABLE
VIL_EN
Low-level input voltage
High-level input voltage
Input leakage current
0.4
0.5
V
V
VIH_EN
1.0
Ilkg_EN
Input connected to GND or VIN
µA
OUTPUT
2.3 V ≤ VIN ≤ 4.85 V, IOUT = 0 mA
PWM operation. Open Loop
VOUT
VOUT
Regulated DC output voltage-TPS61256C
Regulated DC output voltage-TPS612562C
4.92
5.12
5.31
5
5.08
V
V
2.3 V ≤ VIN ≤ 4.85 V, IOUT = 0 mA
PWM operation. Open Loop
5.2 5.28
2.3 V ≤ VIN ≤ 4.85 V, IOUT = 0 mA
PWM operation. Open Loop
VOUT
Regulated DC output voltage-TPS612564C
Power-save mode output ripple voltage
5.4 5.49
50
V
ΔVOUT
PFM operation, IOUT = 1 mA
mVpk
POWER SWITCH
High-side MOSFET on resistance
170
rDS(on)
mΩ
Low-side MOSFET on resistance
Switch valley current limit
100
EN = VIN, Open Loop
TPS61256xC
1900
500
2150 2400
ILIM
mA
Pre-charge / pass-through mode current limit
(linear mode)
Overtemperature protection
Overtemperature hysteresis
140
20
°C
°C
OSCILLATOR
fOSC
Oscillator frequency
VIN = 3.6 V, VOUT = 4.5 V
3.5
MHz
TIMING
IOUT = 0 mA.
Time from active EN to start switching
70
µs
µs
Start-up time
IOUT = 0 mA.
Time from active EN to VOUT
400
Copyright © 2017, Texas Instruments Incorporated
5
TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
www.ti.com.cn
7.6 Typical Characteristics
100
98
5.15
5.1
96
I
= 300 mA
O
94
92
90
88
86
84
82
80
78
76
74
V = 5 V
I
V = 4.5 V
I
I
= 10 mA
O
I
= 100 mA
O
5.05
I
= 800 mA
O
V = 2.5 V
I
V = 3.6 V
I
5
72
70
4.95
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V - Input Voltage - V
I
0.1
1
10
100
1000
I
- Output Current - mA
O
VO = 5 V
PFM/PWM Operation
VO = 5 V
PFM/PWM Operation
Figure 1. Efficiency vs Input Voltage
Figure 2. DC Output Voltage vs Output Current
60
55
50
5.55
5.5
5.45
5.4
V
= 2.7 V
I
45
40
35
30
25
20
15
10
I
= 800 mA
O
V
= 3.3 V
5.35
5.3
I
I
= 500 mA
O
V
= 3.6 V
I
5.25
5.2
V
= 4.5 V
I
5.15
5.1
I
= 100 mA
O
I
= 10 mA
O
5.05
5
0
5
4.95
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
- Input Voltage - V
0
100 200 300 400 500 600 700 800 900 1000
- Output Current - mA
V
I
I
O
VO = 5 V
PFM/PWM
Operation
VO = 5 V
PFM/PWM Operation
CO = 22 µF 10 V (1210) X5R, muRata GRM32ER71A226K
Figure 3. DC Output Voltage vs Input Voltage
Figure 4. Peak-to-Peak Output Ripple Voltage vs Output
Current
80
75
70
65
200
180
160
Rectifier MOSFET
T
= 85°C
A
60
55
50
45
40
35
30
25
140
120
T
= 25°C
A
100
Switch MOSFET
80
60
40
T
= -40°C
A
20
15
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
V - Input Voltage - V
I
20
0
EN = High
No Switching
-30
-10
10
30
50
70
90
110 130
T
- Junction Temperature - °C
J
Figure 5. Supply Current vs Input Voltage
VO = 5 V
Figure 6. MOSFET rDS(on) vs Temperature
6
Copyright © 2017, Texas Instruments Incorporated
TPS61256C
www.ti.com.cn
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
8 Parameter Measurement Information
TPS61256xC
L
SW
VOUT
VOUT
1 μH
VIN
EN
VIN
CO
CI
4.7 μF
10 μF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Parameter Measurement Schematic
Copyright © 2017, Texas Instruments Incorporated
7
TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
www.ti.com.cn
9 Detailed Description
9.1 Overview
The TPS61256xC synchronous step-up converter typically operates at a quasi-constant 3.5-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS61256xC converter
operates in power-save mode with pulse frequency modulation (PFM).
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to
achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time.
At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps
up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer
has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally,
the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.
In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain
amount above the input voltage. The TPS61256xC device operates differently as it can smoothly transition in and
out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits
even though the converter is subject to an input voltage that tends to be excessive. In this operation mode, the
output current capability of the regulator is limited to 500 mA (min.). Refer to Figure 3 for further details.
The current mode architecture with adaptive slope compensation provides excellent transient load response,
requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while
minimizing the number of external components.
9.2 Functional Block Diagram
SW
VOUT
PMOS
NMOS
VIN
Valley
Current
Sense
Modulator
Softstart
VREF
Thermal
Shutdown
Control
Logic
EN
Undervoltage
Lockout
GND
Copyright © 2016, Texas Instruments Incorporated
8
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TPS61256C
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ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
9.3 Feature Description
9.3.1 Current Limit Operation
The TPS61256xC device employs a valley current limit sensing scheme. Current limit detection occurs during the
off-time by sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by
Equation 1.
1
IOUT(CL) = (1- D) g (IVALLEY
+
DIL )
2
(1)
The duty cycle (D) can be estimated by Equation 2
g h
D = 1-
V
IN
VOUT
(2)
(3)
and the peak-to-peak current ripple (ΔIL) is calculated by Equation 3
V
D
f
IN
DIL =
g
L
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the
current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism).
When the current limit is reached the output voltage decreases during further load increase.
Figure 8 illustrates the inductor and rectifier current waveforms during current limit operation.
I
PEAK
I
L
Current Limit
Threshold
I
= I
LIM
VALLEY
Rectifier
Current
I
DI
OUT(CL)
L
I
OUT(DC)
Increased
Load Current
I
IN(DC)
f
Inductorr
Current
I
IN(DC)
DI
L
V
D
f
IN
×
ΔI
=
L
L
Figure 8. Inductor/Rectifier Currents in Current Limit Operation
9.3.2 Enable
The TPS61256xC device starts operation when EN is set high and starts up with the soft-start sequence. For
proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN low and Vin above UVLO, the device is in the forced pass-through mode and the output voltage
follows the input voltage (with a voltage drop of the inductor DCR and Rdson of HS FET).
9.3.3 Softstart
The TPS61256xC device has an internal softstart circuit that limits the inrush current during start-up. The first
step in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the
output capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (500 mA
min.) during this phase. This mechanism is used to limit the output current under short-circuit condition.
Copyright © 2017, Texas Instruments Incorporated
9
TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
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Feature Description (continued)
Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start
system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the
output voltage is reached, the regulation loop takes control and full current operation is permitted.
The TPS61256xC works in the pass-through mode when EN is low and Vin above UVLO, the device enters into
the boost switching phase directly when EN becomes high.
9.3.4 Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage
lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO
threshold plus its hysteresis of 100 mV at typically 2.1 V.
9.3.5 Thermal Regulation
The TPS61256xC device contains a thermal regulation loop that monitors the die temperature during the pre-
charge phase. If the die temperature rises to high values of about 110 °C, the device automatically reduces the
current to prevent the die temperature from increasing further. Once the die temperature drops about 10 °C
below the threshold, the device automatically increases the current to the target value. This function also reduces
the current during a short-circuit condition.
9.3.6 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typ.) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the
thermal shutdown minus its hysteresis, the device continuous the operation.
9.4 Device Functional Modes
9.4.1 Power Save Mode
The TPS61256xC integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage.
The TPS61256xC ramps up the output voltage with several pulses and goes into power save mode once the
output voltage exceeds the set threshold voltage.
The PFM mode is exited and PWM mode entered when the output current can no longer be supported in PFM
mode.
Figure 9. Power Save
10
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TPS61256C
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ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
Device Functional Modes (continued)
9.4.2 Pass-Through Mode
When EN is pulled to low and Vin above UVLO, the device works in the pass-through mode and the output
voltage of TPS61256xC follows the input voltage level. In so called pass-through mode, the synchronous rectifier
is current limited to 500 mA (min.). The output voltage is slightly reduced due to voltage drop across the rectifier
MOSFET and the inductor DC resistance.
Copyright © 2017, Texas Instruments Incorporated
11
TPS61256C
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
With a wide input voltage range of 2.3 V to 5.5 V, the TPS61256xC supports applications powered by Li-Ion
batteries with extended voltage range. Intended for low-power applications, it supports up to 800-mA load current
from a battery discharged as low as 2.65 V and allows the use of low cost chip inductor and capacitors. Different
fixed voltage output versions are available from 3.15 V to 5.0 V. The TPS61256xC offers a very small solution
size due to minimum amount of external components. The TPS6125xC allows the use of small inductors and
input capacitors to achieve a small solution size. During the pass-through mode, the output voltage is biased to
the input voltage.
10.2 Typical Application
This section details an application with TPS61256xC to output fixed 5.0 V.
TPS61256xC
L
SW
VIN
EN
VOUT
VOUT
1 μH
VIN
CO
10 μF
CI
4.7 μF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 10. Smallest Solution Size Application
10.2.1 Design Requirements
In this example, TPS61256xC is used to design a 5-V power supply with up to 800-mA output current capability.
The TPS61256xC can be powered by one-cell Li-ion battery, and in this example the input voltage range is from
2.65 V to 4.85 V.
10.2.2 Detailed Design Procedure
Table 1. List of Components
REFERENCE
L(2)
DESCRIPTION
PART NUMBER, MANUFACTURER(1)
LQM32PN1R0MG0, muRata
1.0 μH, 1.8 A, 48 mΩ, 3.2 x 2.5 x 1.0mm max. height
4.7 μF, 6.3 V, 0402, X5R ceramic
10 μF, 6.3 V, 0603, X5R ceramic
CI
GRM155R60J475M, muRata
CO
GRM188R60J106ME84, muRata
(1) See Third-Party Products Discalimer
(2) Inductor used to characterize TPS61256xCYFF device.
10.2.2.1 Inductor Selection
A boost converter normally requires two main passive components for storing energy during the conversion, an
inductor and an output capacitor. TI advises selecting an inductor with a saturation current rating higher than the
possible peak current flowing through the power switches.
The inductor peak current varies as a function of the load, the input and output voltages and can be estimated
using Equation 4.
V gD
IOUT
V g h
IN
IN
IL(PEAK)
=
+
with D = 1-
2 g f g L
(1- D) g h
VOUT
(4)
12
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Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce its reliability.
When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating,
series resistance, and operating temperature. The inductor DC current rating should be greater (by some margin)
than the maximum input average current, refer to Equation 5 and Current Limit Operation section for more
details.
VOUT
1
IL(DC)
=
g
g IOUT
V
h
IN
(5)
The TPS61256xC series of step-up converters have been optimized to operate with a effective inductance in the
range of 0.7 µH to 2.9 µH and with output capacitors in the range of 10 µF to 47 µF. The internal compensation
is optimized for an output filter of L = 1 µH and CO = 10 µF. Larger or smaller inductor values can be used to
optimize the performance of the device for specific operating conditions. For more details, see the Checking
Loop Stability section.
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following frequency-
dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS61256xC converters.
Table 2. List of Inductors
MANUFACTURER(1)
SERIES
DIMENSIONS (in mm)
3.2 x 2.5 x 1.2 max. height
3.2 x 2.5 x 1.0 max. height
2.5 x 2.0 x 1.0 max. height
2.0 x 1.2 x 0.55 max height
3.2 x 2.5 x 1.2 max. height
2.0 x 1.2 x 0.58 max height
HITACHI METALS
KSLI-322512BL1-1R0
LQM32PN1R0MG0
LQM2HPN1R0MG0
LQM21PN1R5MC0
DFE322512C-1R0
MDT2012-CLR1R0AM
MURATA
TOKO
(1) See Third-Party Products Disclaimer
10.2.2.2 Output Capacitor
For the output capacitor, TI recommends using small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly
recommended. This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC.
To get an estimate of the recommended minimum output capacitance, Equation 6 can be used.
IOUT
g
V
- V
(
f g DV g VOUT
)
OUT IN
CMIN
=
(6)
Where f is the switching frequency which is 3.5 MHz (typ.) and ΔV is the maximum allowed output ripple.
With a chosen ripple voltage of 20mV, a minimum effective capacitance of 9 μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
Equation 7
VESR = IOUT g RESR
(7)
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An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This
is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V
and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive
at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause
lower output voltage ripple as well as lower output voltage drop during load transients but the total output
capacitance value should not exceed ca. 50µF.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 10-µF X5R 6.3-V 0603 MLCC capacitor would typically show an
effective capacitance of less than 4 µF (under 5 V bias condition, high temperature).
In applications featuring high pulsed load currents, it is recommended to run the converter with a reasonable
amount of effective output capacitance, for instance x2 10-µF X5R 6.3-V 0603 MLCC capacitors connected in
parallel.
10.2.2.3 Input Capacitor
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible
to the device. While a 4.7-μF input capacitor is sufficient for most applications, larger values may be used to
reduce input current ripple without limitations.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CI.
10.2.2.4 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted
when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
14
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10.2.3 Application Curves
FIGURE
Figure 11
PFM operation
PWM operation
Figure 12
Combined line/load transient response
Load transient response
AC load transient response
Start-up
Figure 13
Figure 14, Figure 16
Figure 15, Figure 17
Figure 18, Figure 19
spacing
VI = 3.6 V
VO = 5 V
IO = 40 mA
VI = 3.6 V
VO = 5 V
IO = 200 mA
Figure 11. Power-Save Mode Operation
Figure 12. PWM Operation
VO = 5 V
50 to 500 mA Load
Step
3.3 V to 3.9 V Line
Step
VI = 3.6 V
VO = 5 V
50 to 500 mA Load Step
CO = 10 µF 6.3 V (0603) X5R, muRata
Figure 13. Combined Line/Load Transient Response
Figure 14. Load Transient Response in PFM/PWM
Operation
Copyright © 2017, Texas Instruments Incorporated
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www.ti.com.cn
VI = 3.6 V
VO = 5 V
50 to 500 mA Load Step
VI = 3.6 V
VO = 5 V
0 to 400 mA Load
CO = 22 µF 10 V (1210) X5R, muRata
CO = 10 µF 6.3 V (0603) X5R, muRata
Figure 16. Load Transient Response in PFM/PWM
Operation
Figure 15. AC Load Transient Response
VI = 3.6 V
VO = 5 V
IO = 0 mA
VI = 3.6 V
VO = 5 V
0 to 400 mA Load
CO = 22 µF 10 V (1210) X5R, muRata
Figure 18. Pass-through to Boost by EN toggling
Figure 17. AC Load Transient Response
16
Copyright © 2017, Texas Instruments Incorporated
TPS61256C
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ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
VO = 5 V
IO = 0 mA
EN Connect to VIN
Figure 19. Start-Up by VIN
Copyright © 2017, Texas Instruments Incorporated
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11 Power Supply Recommendations
The power supply can be three-cell alkaline, NiCd or NiMH, or one-cell Li-Ion or Li-Polymer battery. The input
supply should be well regulated with the rating of TPS61256xC. If the input supply is located more than a few
inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
An electrolytic or tantalum capacitor with a value of 47 µF is a typical choice.
12 Layout
12.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to the ground pins of the IC.
12.2 Layout Example
GND
GND
C3
U1
EN
VIN
VOUT
L1
Figure 20. Suggested Layout (Top View)
18
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12.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
As power demand in portable designs is more and more important, designers must figure the best trade-off
between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction
temperature can increase significantly which could lead to bad application behaviors (i.e. premature thermal
shutdown or worst case reduce device reliability).
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
the high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board
design. The device operating junction temperature (TJ) should be kept below 125°C.
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13 器件和文档支持
13.1 器件支持
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
13.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.4 商标
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
14.1 封装概要
芯片尺寸封装
（底视图）
芯片尺寸封装
（顶视图）
A3
B3
C3
A2
A1
B1
C1
YMS
CC
D
B2
LLLL
A1
C2
E
代码：
•
•
•
•
YM - 2 位数日期代码
S - 组装地点代码
CC - 芯片代码（请参阅订购表）
LLLL - 批次追踪代码
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14.2 Package Option Addendum
14.2.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Lead/Ball
Finish(3)
(1)
(2)
(4)
Orderable Device
TPS612562CYFFR
TPS612562CYFFT
TPS612564CYFFR
TPS612564CYFFT
Status
Pins
Eco Plan
MSL Peak Temp
Op Temp (°C)
–40 to 85
Device Marking(5)(6)
Green (RoHS
and no Sb/Br)
PREVIEW
PREVIEW
PREVIEW
PREVIEW
DSBGA
YFF
YFF
YFF
YFF
9
9
9
9
3000
250
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
16H
16H
16I
Green (RoHS
and no Sb/Br)
DSBGA
DSBGA
DSBGA
–40 to 85
Green (RoHS
and no Sb/Br)
3000
250
–40 to 85
Green (RoHS
and no Sb/Br)
–40 to 85
16I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
22
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TPS61256C
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ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
Package
Type
Package
Drawing
Package
Qty
Lead/Ball
Finish(3)
(1)
(2)
(4)
Orderable Device
Status
Pins
Eco Plan
MSL Peak Temp
Op Temp (°C)
–40 to 85
Device Marking(5)(6)
Green (RoHS
and no Sb/Br)
TPS61256CYFFR
TPS61256CYFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
9
9
3000
250
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
15U
15U
Green (RoHS
and no Sb/Br)
–40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
版权 © 2017, Texas Instruments Incorporated
23
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14.2.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPS612562CYFFR
TPS612562CYFFT
TPS612564CYFFR
TPS612564CYFFT
TPS61256CYFFR
TPS61256CYFFT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
9
9
9
9
9
9
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
1.41
1.41
1.41
1.41
1.41
1.41
1.31
1.31
1.31
1.31
1.31
1.31
0.69
0.69
0.69
0.69
0.69
0.69
2.0
2.0
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
24
版权 © 2017, Texas Instruments Incorporated
TPS61256C
www.ti.com.cn
ZHCSG06A –FEBRUARY 2017–REVISED JUNE 2017
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
3000
250
Length (mm) Width (mm)
Height (mm)
20.0
TPS612562CYFFR
TPS612562CYFFT
TPS612564CYFFR
TPS612564CYFFT
TPS61256CYFFR
TPS61256CYFFT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
9
9
9
9
9
9
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
3000
250
20.0
20.0
3000
250
20.0
20.0
版权 © 2017, Texas Instruments Incorporated
25
PACKAGE OUTLINE
YFF0009
DSBGA - 0.625 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.625 MAX
C
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
0.8 TYP
C
B
SYMM
0.8
D: Max = 1.336 mm, Min =1.276 mm
E: Max = 1.236 mm, Min =1.176 mm
TYP
0.4 TYP
A
0.3
0.2
3
1
2
9X
SYMM
0.015
C A B
0.4 TYP
4219552/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
9X ( 0.23)
(0.4) TYP
1
2
A
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219552/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
9X ( 0.25)
1
3
2
A
(0.4) TYP
B
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219552/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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