TPS61256AYFFR [TI]
采用 1.2mm x 1.3mm WCSP 封装的 3.5MHz、5V、1A 负载升压转换器 | YFF | 9 | -40 to 85;
| 型号： | TPS61256AYFFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1.2mm x 1.3mm WCSP 封装的 3.5MHz、5V、1A 负载升压转换器 | YFF | 9 | -40 to 85 升压转换器 |
| 文件： | 总30页 (文件大小：4139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61256A
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
采用芯片级封装并具有 2.3A 电流限制的 TPS61256A 3.5MHz 高效升压转
换器
1 特性
借助 2.5V-5.5V 的宽输入电压范围，该器件支持由各
种电压的锂离子电池进行供电的 应用 并提供 5.0V 的
固定输出电压。
1
•
•
•
•
•
•
•
•
•
•
•
运行频率为 3.5MHz 时，效率 93%
36µA 静态电流
2.5V 至 5.5V 的宽输入电压范围
VOUT = 5.0V, VIN ≥3.3V 时，IOUT ≥1000mA
DC 电压输出总精度为 ±2%
轻负载频率脉冲调制 (PFM) 模式
关断期间的真正负载断开
TPS61256A 在 3.5MHz 的调节开关频率下运行，在轻
负载电流情况下会进入省电模式，以便在整个负载电流
范围内保持高效率。PFM 模式可在轻负载工作时将静
态电流降至 36μA（典型值），从而可延长电池使用寿
命。关断模式下的输入电流低于 5µA，从而最大程度
地延长电池寿命。
热关断和过载保护
只需三个表面贴装外部组件
总解决方案尺寸 < 35mm2
9 引脚 NanoFreeTM(CSP) 封装
TPS61256A 能够最大限度地减少外部组件的数量，因
此具有很小的解决方案尺寸。为了实现小解决方案尺
寸，允许使用小型电感器和输入电容器。在关断期间，
负载从电池上完全断开。
2 应用范围
•
•
•
手机、智能电话
这些器件具有有限的内置 ESD 保护功能。存储或装卸
时，应将导线短接在一起或将器件放置于导电泡棉中，
以防止 MOS 门极遭受静电损伤。
平板电脑
单声道和立体声 APA “应用”列表的
器件信息(1)
3 说明
器件型号
TPS61256A
封装
封装尺寸（标称值）
TPS61256A 器件为电池供电的便携式 应用提供了一个
电源解决方案。旨在面向低功耗 应用的 TPS61256A
支持来自一节电池（放电电压低至 2.7V）的高达
800mA 的负载电流，并且允许使用低成本芯片电感器
和电容器。
1.206mm x
1.306mm
YFF
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
效率与负载电流间的关系
最小解决方案尺寸应用
VOUT
5.0V @ 800mA
VO = 5.0 V
TPS61256A
100
L
L
VOUT
90
80
70
VIN
2.7 V .. 4.8 V
1 μH
VIN
EN
CO
22 uF
CI
10 μF
GND
60
50
40
30
20
10
0
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSB07
TPS61256A
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
www.ti.com.cn
目录
8.7 Feature Description................................................. 10
8.8 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Softstart..................................................................... 9
8.3 Undervoltage Lockout ............................................... 9
8.4 Thermal Regulation................................................... 9
8.5 Thermal Shutdown.................................................... 9
8.6 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
11.3 Thermal Information.............................................. 19
12 Package Summary .............................................. 20
12.1 Package Dimensions ............................................ 20
13 器件和文档支持 ..................................................... 21
13.1 器件支持 ............................................................... 21
13.2 接收文档更新通知 ................................................. 21
13.3 社区资源................................................................ 21
13.4 商标....................................................................... 21
13.5 静电放电警告......................................................... 21
13.6 Glossary................................................................ 21
14 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
Changes from Original (July 2011) to Revision A
Page
•
•
首次公开发布数据表。
...................................................................................................................................................................................... 1
如需了解新数据表格式和添加的部分，请参阅“目录”。
...................................................................................................................................................................................... 2
2
Copyright © 2011–2018, Texas Instruments Incorporated
TPS61256A
www.ti.com.cn
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
5 Pin Configuration and Functions
YFF Package
9-Bump DSBGA
Top View
A1 A2 A3
A3 A2 A1
B1 B2 B3
C1 C2 C3
B3 B2 B1
C3 C2 C1
Pin Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
mode. Pulling this pin high enables the device. This pin must not be left floating and must be
terminated.
EN
B3
I
GND
SW
C1, C2, C3
B1, B2
A3
Ground pin.
I/O
I
This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs.
VIN
Power supply input.
VOUT
A1, A2
O
Boost converter output.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
V
Input voltage
Voltage at VIN(2), VOUT(2), SW(2), EN(2)
Steady state DC current into SW
–0.3 to 7
2.3
Input current
A
Power dissipation
Internally limited
(3)
Operationg temperature range, TA
–40 to 85
–40 to 150
–65 to 150
°C
°C
°C
Temperature range
Operating virtual junction, TJ
Storage temperature range, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
Copyright © 2011–2018, Texas Instruments Incorporated
3
TPS61256A
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
www.ti.com.cn
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
±2000
V
Electrostatic
discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101(3)
(1)
V(ESD)
±1000
±200
V
V
Machine Model - (MM)
(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
MIN
2.5
55
NOM
MAX UNIT
VI
Input voltage range
4.85
V
Ω
RL
L
Minimum resistive load for start-up
Inductance
0.7
10
1.0
20
2.9
50
µH
µF
°C
°C
CO
TA
TJ
Output capacitance
Ambient temperature
Operating junction temperature
–40
–40
85
125
6.4 Thermal Information
TPS61256A
YFF
THERMAL METRIC
UNIT
9 PINS
108.3
1.0
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
18
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.2
ψJB
17.9
6.5 Electrical Characteristics
Minimum and maximum values are at VIN = 2.5V to 5.5V, VOUT = 5.0V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to
85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT
= 5.0V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
Operating quiescent current
into VIN
33
7
45
15
µA
µA
IOUT = 0mA, VOUT = 5.0V, VIN = 3.6V
EN = VIN
Device not switching
IQ
Operating quiescent current
into VOUT
ISD
Shutdown current
EN = GND
Falling
0.85
2.0
5.0
2.1
μA
V
VUVLO
Under-voltage lockout threshold
Hysteresis
0.1
V
ENABLE
VIL
Low-level input voltage
High-level input voltage
Input leakage current
0.4
0.5
V
V
VIH
1.0
Ilkg
Input connected to GND or VIN
µA
4
版权 © 2011–2018, Texas Instruments Incorporated
TPS61256A
www.ti.com.cn
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
Electrical Characteristics (接下页)
Minimum and maximum values are at VIN = 2.5V to 5.5V, VOUT = 5.0V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to
85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT
= 5.0V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
OUTPUT
2.5V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop
4.92
4.9
5.0 5.08
V
V
VOUT
DC output voltage accuracy
2.5V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 650mA
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1000mA
PFM/PWM operation
5.0
5.2
Power-save mode output ripple voltage
PWM mode output ripple voltage
PFM operation, IOUT = 1mA
30
15
mVpk
mVpk
ΔVOUT
PWM operation, IOUT = 200mA
POWER SWITCH
High-side MOSFET on resistance
170
100
mΩ
mΩ
µA
rDS(on)
Low-side MOSFET on resistance
Reverse leakage current into VOUT
Pre-charge current limit
Ilkg
EN = GND
3.5
165
215
265
mA
mA
°C
ILIM
Switch valley current limit
EN = VIN. Open Loop
1900
2400 2900
Overtemperature protection
Overtemperature hysteresis
140
20
°C
OSCILLATOR
fOSC
Oscillator frequency
VIN = 3.6V
3.5
MHz
µs
TIMING
IOUT = 0mA
Time from active EN to VOUT
Start-up time
700
版权 © 2011–2018, Texas Instruments Incorporated
5
TPS61256A
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
www.ti.com.cn
6.6 Typical Characteristics
100
100
98
96
94
92
90
88
86
84
82
80
78
76
74
V = 3.3 V
I
V = 3.6 V
I
95
90
85
80
75
70
65
60
V = 4.5 V
I
= 100 mA
I
O
I
= 300 mA
O
V = 3 V
I
V = 2.7 V
I
V = 2.5 V
I
I
= 10 mA
O
I
= 800 mA
O
55
50
72
70
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V - Input Voltage - V
I
0.1
1
10
100
1000
I
- Output Current - mA
O
图 2. Efficiency vs Input Voltage
图 1. Efficiency vs Output Current
5.1
5.05
5
5.05
V = 4.5 V
I
5
4.95
4.9
V = 4.2 V
I
V = 4.5 V
I
V = 5 V
I
V = 2.5 V
I
V = 2.7 V
I
V = 3.6 V
I
V = 3 V
I
V = 2.5 V
I
V = 3.3 V
I
V = 3.6 V
I
4.95
4.9
4.85
4.8
500
700
900 1100 1300 1500 1700 1900
0.1
1
10
100
1000
I
- Output Current - mA
I
- Output Current - mA
O
O
图 4. DC Output Voltage vs Output Current
图 3. DC Output Voltage vs Output Current
2300
2100
1900
1700
1500
1300
1100
900
5.55
V
= 5 V
5.5
5.45
5.4
O
PWM Operation
T
= -40°C
A
5.35
5.3
I
= 800 mA
O
T
= 25°C
A
I
= 500 mA
O
5.25
5.2
I
= 100 mA
O
T
A
= 85°C
5.15
5.1
I
= 10 mA
O
5.05
700
500
5
4.95
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V - Input Voltage - V
I
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
V - Input Voltage - V
I
图 5. DC Output Voltage vs Input Voltage
图 6. Maximum Output Currentvs Input Voltage
版权 © 2011–2018, Texas Instruments Incorporated
6
TPS61256A
www.ti.com.cn
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
Typical Characteristics (接下页)
60
80
75
70
65
60
55
50
45
40
35
30
25
V
= 5 V
V
I
= 5 V
O
PFM/PWM Operation
O
55
50
45
40
35
30
25
20
15
10
= 0 mA
O
V = 2.7 V
I
T
= 85°C
A
V = 3.3 V
I
T
= 25°C
A
V = 3.6 V
I
V = 4.5 V
I
T
= -40°C
A
5
0
20
15
0
100 200 300 400 500 600 700 800 900 1000
- Output Current - mA
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
V - Input Voltage - V
I
I
O
图 7. Peak-To-Peak Output Ripple Voltage vs Output Current
图 8. Supply Currentvs Input Voltage
250
245
240
235
230
250
245
240
235
230
225
220
215
210
205
200
195
190
185
180
175
170
165
160
225
220
215
210
205
200
195
190
185
180
175
170
165
160
V = 2.7 V,
V = 3.6 V,
I
I
V = 3.6 V,
T
= 25°C
T
= 25°C
I
A
V = 4.5 V,
A
I
T
= 85°C
A
T
= 25°C
A
V = 3.6 V,
I
V = 3.6 V,
I
T
= 25°C
A
T
= -40°C
A
155
150
155
150
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5
Differential Input - Output Voltage - V
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Differential Input - Output Voltage - V
3
3.3 3.6
图 10. DC Pre-Charge Currentvs Differential Input-Output
图 9. DC Pre-Charge Currentvs Differential Input-Output
Voltage
Voltage
30
200
V = 3.6 V
I
Sample Size = 200
V
= 5 V
O
180
160
140
120
100
80
T
= 130°C
J
25
20
15
10
T
J
= 25°C
Rectifier MOSFET
T
= -20°C
J
Switch MOSFET
60
40
5
0
20
0
-30
-10
10
30
50
70
90
110 130
T
- Junction Temperature - °C
J
I
- Valley Current Limit - mA
LIM
图 12. MOSFET Rds(On) vs Temperature
图 11. Valley Current Limit
版权 © 2011–2018, Texas Instruments Incorporated
7
TPS61256A
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
www.ti.com.cn
7 Parameter Measurement Information
TPS61256A
L
L
VOUT
VOUT
1 μH
VIN
EN
VIN
CO
22 uF
CI
10 μF
GND
Copyright © 2018, Texas Instruments Incorporated
表 1. List of Components
REFERENCE
DESCRIPTION
PART NUMBER, MANUFACTURER
DFE322512C-1R0N, TOKO
L
1.0μH, 2.5A, 50mΩ, 3.2 x 2.5 x 1.2mm max. height
10μF, 6.3V, 0603, X5R ceramic
CI
CO
GRM188R60J106ME84, muRata
GRM32ER71A226K, muRata
22μF, 10V, 1210, X5R ceramic
8
版权 © 2011–2018, Texas Instruments Incorporated
TPS61256A
www.ti.com.cn
ZHCSHT5A –JULY 2011–REVISED MARCH 2018
8 Detailed Description
8.1 Overview
The TPS61256A synchronous step-up converter typically operates at a quasi-constant 3.5-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS61256A converter
operates in power-save mode with pulse frequency modulation (PFM).
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to
achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time.
At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps
up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer
has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally,
the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.
In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain
amount above the input voltage. The TPS61256A device operates differently as it can smoothly transition in and
out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits
even though the converter is subject to an input voltage that tends to be excessive. Refer to the typical
characteristics section (DC Output Voltage vs. Input Voltage) for further details.
The current mode architecture with adaptive slope compensation provides excellent transient load response,
requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while
minimizing the number of external components.
8.2 Softstart
The TPS61256A device has an internal softstart circuit that limits the inrush current during start-up. The first step
in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the output
capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (approx. 200mA)
during this phase. This mechanism is used to limit the output current under short-circuit condition.
Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start
system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the
output voltage is reached, the regulation loop takes control and full current operation is permitted.
8.3 Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage
lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO
threshold plus its hysteresis of 100 mV at typ. 2.1V.
8.4 Thermal Regulation
The TPS61256A device contains a thermal regulation loop that monitors the die temperature during the pre-
charge phase. If the die temperature rises to high values of about 110 °C, the device automatically reduces the
current to prevent the die temperature from increasing further. Once the die temperature drops about 10 °C
below the threshold, the device will automatically increase the current to the target value. This function also
reduces the current during a short-circuit condition.
8.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typ.) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the
thermal shutdown minus its hysteresis, the device continuous the operation.
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TPS61256A
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www.ti.com.cn
8.6 Functional Block Diagram
SW
VOUT
PMOS
NMOS
VIN
Valley
Current
Sense
Modulator
Softstart
Control
VREF
Thermal
Shutdown
EN
Logic
Undervoltage
Lockout
GND
Copyright © 2018, Texas Instruments Incorporated
8.7 Feature Description
8.7.1 Power-Save Mode
The TPS61256A integrates a power-save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage.
It ramps up the output voltage with several pulses and goes into power save mode once the output voltage
exceeds the set threshold voltage.
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode.
10
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ZHCSHT5A –JULY 2011–REVISED MARCH 2018
Feature Description (接下页)
8.7.2 Current Limit Operation
The TPS61256A device employs a valley current limit sensing scheme. Current limit detection occurs during the
off-time by sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by 公
式 1.
1
IOUT(CL) = (1- D) g (IVALLEY
+
DIL )
2
(1)
The duty cycle (D) can be estimated by 公式 2
g h
D = 1-
V
IN
VOUT
(2)
(3)
and the peak-to-peak current ripple (ΔIL) is calculated by 公式 3
V
D
f
IN
DIL =
g
L
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the
current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism).
When the current limit is reached the output voltage decreases during further load increase.
illustrates the inductor and rectifier current waveforms during current limit operation.
I
PEAK
I
L
Current Limit
Threshold
I
= I
LIM
VALLEY
Rectifier
Current
I
DI
OUT(CL)
L
I
OUT(DC)
Increased
Load Current
I
IN(DC)
f
Inductorr
Current
I
IN(DC)
DI
L
V
D
f
IN
ΔI
=
×
L
L
图 13. Inductor/Rectifier Currents In Current Limit Operation
8.7.3 Enable
The TPS61256A device starts operation when EN is set high and starts up with the soft-start sequence. For
proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN pin low forces the device in shutdown, with a shutdown current of typically 1µA. In this mode, true
load disconnect between the battery and load prevents current flow from VIN to VOUT, as well as reverse flow
from VOUT to VIN.
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Feature Description (接下页)
8.7.4 Load Disconnect And Reverse Current Protection
Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will
be discharge during shutdown. The advantage of TPS61256A is that this converter is disconnecting the output
from the input of the power supply when it is disabled (so called true shutdown mode). In case of a connected
battery it prevents it from being discharge during shutdown of the converter.
8.8 Device Functional Modes
8.8.1 Load Disconnect And Reverse Current Protection
Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will
be discharge during shutdown. The advantage of TPS61256A is that this converter is disconnecting the output
from the input of the power supply when it is disabled (so called true shutdown mode). In case of a connected
battery it prevents it from being discharge during shutdown of the converter.
8.8.2 Softstart
The TPS61256A device has an internal softstart circuit that limits the inrush current during start-up. The first step
in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the output
capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (approx. 200mA)
during this phase. This mechanism is used to limit the output current under short-circuit condition.
Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start
system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the
output voltage is reached, the regulation loop takes control and full current operation is permitted.
8.8.3 Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage
lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO
threshold plus its hysteresis of 100 mV at typ. 2.1V.
8.8.4 Thermal Regulation
The TPS61256A device contains a thermal regulation loop that monitors the die temperature during the pre-
charge phase. If the die temperature rises to high values of about 110 °C, the device automatically reduces the
current to prevent the die temperature from increasing further. Once the die temperature drops about 10 °C
below the threshold, the device will automatically increase the current to the target value. This function also
reduces the current during a short-circuit condition.
8.8.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typ.) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the
thermal shutdown minus its hysteresis, the device continuous the operation.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
With a wide input voltage range of 2.5 V to 5.5 V, the TPS61256A supports applications powered by Li-Ion
batteries with extended voltage range. Intended for low-power applications, it supports up to 800-mA load current
from a battery discharged as low as 2.7 V and allows the use of low cost chip inductor and capacitors. Different
fixed voltage output versions are available from 3.15 V to 5.0 V. The TPS61256A offers a very small solution size
due to minimum amount of external components. It allows the use of small inductors and input capacitors to
achieve a small solution size. During shutdown, the load is completely disconnected from the battery.
9.2 Typical Application
VOUT
5.0V @ 800mA
TPS61256A
L
L
VOUT
VIN
2.7 V .. 4.8 V
1 μH
VIN
EN
CO
22 uF
CI
10 μF
GND
Copyright © 2018, Texas Instruments Incorporated
图 14. Typical Application
9.2.1 Design Requirements
DESIGN PARAMETERS
Input Voltage Range
Output Voltage
EXAMPLE VALUES
2.5 V to 4.5 V
5 V
Output Voltage Ripple
Transient Response
Input Voltage Ripple
Output Current
±3% VOUT
±15% VOUT
±200 mV
800 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
A boost converter normally requires two main passive components for storing energy during the conversion, an
inductor and an output capacitor are required. It is advisable to select an inductor with a saturation current rating
higher than the possible peak current flowing through the power switches.
The inductor peak current varies as a function of the load, the input and output voltages and can be estimated
using 公式 4.
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V gD
IOUT
V g h
IN
IN
IL(PEAK)
=
+
with D = 1-
2 g f g L
(1- D) g h
VOUT
(4)
Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce it's reliability.
When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating,
series resistance, and operating temperature. The inductor DC current rating should be greater (by some margin)
than the maximum input average current, refer to 公式 5 and Current Limit Operation section for more details.
VOUT
1
IL(DC)
=
g
g IOUT
V
h
IN
(5)
The TPS61256A series of step-up converters have been optimized to operate with a effective inductance in the
range of 0.7µH to 2.9µH and with output capacitors in the range of 22µF to 47µF. The internal compensation is
optimized for an output filter of L = 1µH and CO = 22µF. Larger or smaller inductor values can be used to
optimize the performance of the device for specific operating conditions. For more details, see the Checking
Loop Stability section.
9.2.2.1.1 High-frequency Converter Applications
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following frequency-
dependent components:
•
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
Radiation losses
The following inductor series from different suppliers have been used with the TPS61256A converters.
表 2. List Of Inductors
MANUFACTURER(1)
MURATA
SERIES
DIMENSIONS (in mm)
4.0 x 4.0 x 1.8 max. height
3.2 x 2.5 x 1.2 max. height
3.2 x 2.5 x 1.2 max. height
LQH44PN1R0NP0
KSLI-322512BL1-1R0
DFE322512C-1R0N
HITACHI METALS
TOKO
(1) See Third-party Products Disclaimer
14
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9.2.2.2 Output Capacitor
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly
recommended. This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC.
To get an estimate of the recommended minimum output capacitance, 公式 6 can be used.
IOUT
g
V
- V
(
f g DV g VOUT
)
OUT IN
CMIN
=
(6)
Where f is the switching frequency which is 3.5MHz (typ.) and ΔV is the maximum allowed output ripple.
With a chosen ripple voltage of 20mV, a minimum effective capacitance of 9μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using 公
式 7
VESR = IOUT g RESR
(7)
An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This
is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V
and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive
at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause
lower output voltage ripple as well as lower output voltage drop during load transients but the total output
capacitance value should not exceed ca. 50µF.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 22µF X5R 6.3V 0805 MLCC capacitor would typically show an
effective capacitance of less than 8µF (under 5V bias condition).
9.2.2.3 Input Capacitor
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible
to the device. While a 10μF input capacitor is sufficient for most applications, larger values may be used to
reduce input current ripple without limitations.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
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9.2.2.4 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted
when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
16
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9.2.3 Application Curves
V = 3.6 V,
I
V
I
= 5.0 V,
O
V = 3.6 V, V = 5.0 V, I = 50 mA
= 150 mA
I
O
O
O
图 16. PWM Operation
图 15. Power-Save Mode Operation
V
O
= 5.0 V
V = 3.6 V,
I
V
= 5.0 V
50 to 500 mA Load Step
O
50mA to 500mA
Load Step
3.3V to 3.9V Line Step
图 17. Combined Line/Load Transient Response
图 18.
Load Transient Response InPFM/PWM
Operation
0 to 400mA Load Sweep
V = 3.6 V,
I
V
= 5.0 V
O
V = 3.6 V,
I
V
I
= 5.0 V,
O
= 0 mA
O
图 19. AC Load Transient Response
图 20. Start-Up
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www.ti.com.cn
V = 2.7 V
I
V = 4.5 V
I
V = 3.6 V
I
V = 5.0 V,
O
I
= 0 mA
O
图 21. Start-Up
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 4.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.
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11 Layout
11.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to the ground pins of the IC.
11.2 Layout Example
GND
GND
U1
EN
VIN
VOUT
L1
图 22. Suggested Layout (Top)
11.3 Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
The maximum junction temperature (TJ) of the TPS61256A is 125°C.
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12 Package Summary
CHIP SCALE PACKAGE
(BOTTOM VIEW)
CHIP SCALE PACKAGE
(TOP VIEW)
A3
B3
C3
A2
A1
B1
C1
YMS
CC
D
B2
LLLL
C2
E
A1
Code:
•
•
•
•
YM - 2 digit date code
S - assembly site code
CC - chip code (see ordering table)
LLLL - lot trace code
12.1 Package Dimensions
The dimensions for the YFF-9 package are shown in 表 3. See the package drawing at the end of this data
sheet.
表 3. YFF-9 Package Dimensions
Packaged Devices
D
E
TPS61256AYFF
1.206 ±0.03 mm
1.306 ±0.03 mm
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13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OUTLINE
YFF0009
DSBGA - 0.625 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.625 MAX
C
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
0.8 TYP
C
B
SYMM
0.8
TYP
0.4 TYP
A
0.3
0.2
3
1
2
9X
SYMM
0.015
C A B
0.4 TYP
4219552/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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TPS61256A
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EXAMPLE BOARD LAYOUT
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
9X ( 0.23)
1
2
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219552/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
9X ( 0.25)
1
3
2
A
(0.4) TYP
B
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219552/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61256AYFFR
TPS61256AYFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
9
9
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
QXA
QXA
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61256AYFFR
TPS61256AYFFT
DSBGA
DSBGA
YFF
YFF
9
9
3000
250
180.0
180.0
8.4
8.4
1.41
1.41
1.31
1.31
0.69
0.69
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61256AYFFR
TPS61256AYFFT
DSBGA
DSBGA
YFF
YFF
9
9
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
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