TPS613785QWRTERQ1 [TI]
TPS61378-Q1 25-μA Quiescent Current Synchronous Boost Converter with Load Disconnect;型号: | TPS613785QWRTERQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS61378-Q1 25-μA Quiescent Current Synchronous Boost Converter with Load Disconnect |
文件: | 总36页 (文件大小:4027K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
TPS61378-Q1 25-µA Quiescent Current Synchronous Boost Converter with Load
Disconnect
1 Features
3 Description
•
•
•
AEC-Q100 qualified for automotive applications
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Function Safety-Capable
– Documentation available to aid functional safety
system design
Flexible input and output operation range
– Input voltage range: 2.3 V to 14 V
– Programmable output voltage range: 4.0 V to
18.5 V
– 5 V, 5.25 V, 5.5 V fixed output options
– Programmable peak current limit: 1 A to 4.8 A
Avoid AM band interference and crosstalk
– Dynamically programmable switching
frequency: 200 kHz to 2.2 MHz
– Spread spectrum frequency modulation
– Optional clock synchronization
Minimize solution size for space constraint
applications
– Integrated LS/HS/ISO FET: RDS(ON) 50 mΩ/50
mΩ/100 mΩ
– Support up to 2.2 MHz with small L-C
Minimized light load and idle state current
consumption
– 25-µA Quiescent current into VIN pin
– 0.5-µA Shutdown current into VIN pin
– Selectable auto PFM and forced PWM mode
– True load disconnect during shutdown or fault
conditions
The TPS61378-Q1 is a fully-integrated synchronous
boost converter with load disconnect function
integrated. The input voltage covers from 2.3 V to 14
V, while the maximal output votlage up to 18.5 V. The
switching current limit is programmable from 1 A to
4.8 A. It consumes 25 uA quiescent current from Vin.
The TPS61378-Q1 employs the peak current mode
control with the switching frequency programmable
from 200 kHz to 2.2 MHz. The device works in fixed
frequency PWM operation in medium to heavy load.
There are two optional modes in light load by
configuring the MODE pin: Auto PFM mode and
Forced PWM to balance the efficiency and noise
immunity in light load. The switching frequency can be
synchronized to an external clock. The TPS61378-Q1
uses the spread spectrum of the internal clock for
more EMI friendly at FPWM mode. In addition, there
is an internal soft-start time to limit the inrush current.
•
•
•
The TPS61378-Q1 has various fixed output voltage
versions to save the external feedback resistor. It
supports the external loop compensation so that the
stability and transient response could be optimized at
wider Vout/Vin range. It also integrates robust
protection features including the output short
protection, output over voltage protection and thermal
shutdown protection. The TPS61378-Q1 is available
in a 3-mm x 3-mm 16-pin QFN package with wettable
flank.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
Integrated protection features
TPS61378QRTE
VQFN-16
3.0-mm x 3.0-mm
– Support VIN close to VOUT operation
– Input undervoltage lockout and output
overvoltage protection
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
L1
– Hiccup output short circuit protection
– Power good indicator
– Thermal shutdown protection at 165°C
Higher than 90% efficiency under 0.8-A load from
3.3-V to 9-V conversion
SW
PG
C2
R1
VCC
BST
VIN
C6
OUT
VO
•
C1
C3
TPS61378-Q1
EN
VOUT
FREQ
R3
R6
R4
2 Applications
COMP
FB
C4
R2
C5
ILIM
•
•
•
•
Advanced driver-assistance system (ADAS)
Automotive infotainment and cluster
Body electronics and lighting
MODE/SYNC
GND
R5
Emergency call (eCall)
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics................................................8
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagrams....................................... 12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................25
11 Layout...........................................................................26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Device Support....................................................... 27
12.2 Receiving Notification of Documentation Updates..27
12.3 Support Resources................................................. 27
12.4 Trademarks.............................................................27
12.5 Glossary..................................................................27
12.6 Electrostatic Discharge Caution..............................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
Changes from Revision * (May 2020) to Revision A (October 2020)
Page
Changed TPS61378-Q1 device status from Advance Information to Production Data...................................... 1
Updated the numbering format for tables, figures and cross-references throughout the document...................1
•
•
Copyright © 2020 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
5 Device Comparison Table
PART NUMBER
OUTPUT VOLTAGE (V)
RESISTOR FROM FB TO GND (RFB_LOW
)
SPREAD SPECTRUM
5
RFB_LOW ≤ 2 kΩ
5.25
2 kΩ < RFB_LOW ≤ 4 kΩ
4 kΩ < RFB_LOW ≤ 8 kΩ
RFB_LOW ≥ 16 kΩ
TPS61378-Q1
Enable
5.5
Adjustable
5.7
RFB_LOW ≤ 2 kΩ
6.2
2 kΩ < RFB_LOW ≤ 4 kΩ
4 kΩ < RFB_LOW ≤ 8 kΩ
RFB_LOW ≥ 16 kΩ
TPS613781-Q1(1)
TPS613782-Q1(1)
TPS613783-Q1(1)
TPS613784-Q1(1)
TPS613785-Q1(1)
Enable
Enable
Disable
Disable
Disable
7
8
9
RFB_LOW ≤ 2 kΩ
10
2 kΩ < RFB_LOW ≤ 4 kΩ
4 kΩ < RFB_LOW ≤ 8 kΩ
RFB_LOW ≥ 16 kΩ
11
12
5
RFB_LOW ≤ 2 kΩ
5.25
2 kΩ < RFB_LOW ≤ 4 kΩ
4 kΩ < RFB_LOW ≤ 8 kΩ
RFB_LOW ≥ 16 kΩ
5.5
Adjustable
5.7
6.2
7
RFB_LOW ≤ 2 kΩ
2 kΩ < RFB_LOW ≤ 4 kΩ
4 kΩ < RFB_LOW ≤ 8 kΩ
RFB_LOW ≥ 16 kΩ
8
9
RFB_LOW ≤ 2 kΩ
10
11
12
2 kΩ < RFB_LOW ≤ 4 kΩ
4 kΩ < RFB_LOW ≤ 8kΩ
RFB_LOW ≥ 16 kΩ
(1) Product Preview. Contact TI factory for more information.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
6 Pin Configuration and Functions
16
15
14
13
1
VIN
ILIM
PG
12
BST
2
11
10
9
Exposed
Thermal Pad
3
4
SW
SW
OUT
VO
8
5
7
6
Figure 6-1. 16-Pin WQFN RTE Package (Transparent Top View)
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VIN
1
I
I
IC power supply input
Power supply for high-side N-MOSFET gate drivers. A capacitor must be connected
between this pin and SW pin.
BST
SW
2
The switching node pin of the converter. It is connected to the drain of the internal low-side
FET and the source of the high-side FET.
3, 4
PWR
Mode selection pin. MODE = high, forced PWM mode. MODE = low or floating, auto PFM
mode. This pin can also be used to synchronize the external clock. Refer to Table 8-1 for
details.
MODE/SYNC
VCC
5
6
I
Output of internal regulator. A ceramic capacitor with more than 1 μF must be connected
between this pin and GND.
O
GND
VO
7, 8
9
PWR
PWR
Power ground of the IC. It is connected to the source of the low-side FET.
Output of the isolation FET. Connect load to this pin to achieve input/output isolation.
Output of the drain of the HS FET. Connect this pin as the output can disable the load
disconnect/short protection feature (or short this pin with VO pin).
OUT
PG
10
11
12
PWR
O
I
Power good indicator, open drain output
Current limit setting pin. Use a resistor to set the desired peak current limit. Refer to Section
8.3.7 for details.
ILIM
Feedback pin. Use a resistor divider to set the desired output voltage. Refer to Section
9.2.2.1 for details.
FB
13
I
Output of the internal trans-conductance error amplifier. An external RC network is
connected to this pin to optimize the loop stability and response time.
COMP
EN
14
15
16
-
I
I
I
-
Enable logic input
Frequency setting pin. Connect a resistor between this pin and GND pin to set the desired
frequency.
FREQ
Thermal Pad
The thermal pad should be connected to power ground plane for good power dissipation.
Copyright © 2020 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
–0.3
–0.3
–0.3
-0.3
–40
–65
MAX
16
UNIT
V
Voltage range at terminals (2)
Voltage range at terminals (2)
VIN
VO, SW, OUT
23
V
BST
SW + 6
6
V
MODE/SYNC, FB, FREQ, ILIM, VCC, COMP, EN
PG
V
20
V
(3)
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
(3) High junction temperatures degrade operating lifetime. Operating lifetime is de-rated for junction temperatures greater than 125°C
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(2)
(1)
(1)
V(ESD)
Electrostatic discharge
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011, all pins(3)
Charged-device model (CDM), per AEC Q100-011, corner pins
(1,4,5,8,9,12,13,16)(3)
V(ESD)
±750
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.3
4
NOM
MAX
14
UNIT
V
VIN
Input voltage
VOUT
TA
Outputvoltage
18.5
125
V
Operating ambient temperature
–40
°C
7.4 Thermal Information
TPS61378-Q1
RTE
THERMAL METRIC(1)
UNIT
16 PINS
46.2
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
43.5
18.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.1
ψJB
18.5
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
TPS61378-Q1
RTE
THERMAL METRIC(1)
UNIT
16 PINS
8.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
TJ = -40 to 125°C, L = 1 µH, VIN = 3.3 V and VOUT = 9 V (VO pin). Typical values are at TJ = 25°C, (unless
otherwise noted)
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
2.3
14
2.3
2.2
V
V
VIN rising
VIN falling
2.2
2.04
160
2.2
VIN_UVLO
VIN under voltage lockout threshold
V
VIN_HYS
VIN UVLO hysteresis
mV
V
VCC_UVLO VCC UVLO threshold
VCC rising
VCC_HYS
VCC
VCC UVLO hysteresis
VCC regulation
VCC hysteresis
IVCC = 6 mA, VOUT = 9V
150
4.8
mV
V
IC enabled, no load,
VIN = 3.3 V, VOUT = 18.5 V, VFB
VREF + 0.1 V,
IQ
Quiescent current into VIN pin
Quiescent current into OUT pin
=
=
25
35
20
µA
µA
IC enabled, no load,
VIN = 3.3 V, VOUT = 18.5 V, VFB
VREF + 0.1 V,
IQ
10
ISD
Shutdown current into VIN pin
Leakage current into SW
IC disabled, VIN =14 V, EN = GND
IC disabled, VIN = OUT = SW =14 V
IC disabled, OUT= VO = 5 V, SW = 0
0.6
5
5
5
µA
µA
µA
ISW_LKG
IVO_LKG
Reverse leakage current into VO
OUTPUT VOLTAGE
Output over-voltage protection
threshold
VOVP
VIN = 3.3 V, VOUT rising
19.3
20
20.5
V
V
Output over-voltage protection
hysteresis
VOVP_HYS
VIN = 3.3 V, OVP threshold
0.5
VOLTAGE REFERENCE
TJ = -40 to 125°C, FB to GND
resistance ≥ 16 kΩ
VREF
Reference Voltage at FB pin
0.788
0.8
0.812
V
VOUT_5V
VOUT_5.25V
VOUT_5.5V
IFB_LKG
TJ = -40 to 125°C, RFB = 2.0 kΩ
TJ = -40 to 125°C, RFB = 4.0 kΩ
TJ = -40 to 125°C, RFB = 8.0 kΩ
4.85
5.1
5.000
5.238
5.500
5.15
5.35
5.65
50
V
V
5.35
V
Leakage current into FB pin
nA
POWER SWITCH
RDS(on)
RDS(on)
RDS(on)
Low-side MOSFET on resistance
VCC = 4.85 V
VCC = 4.85 V
VCC = 4.85 V
50
50
mΩ
mΩ
mΩ
High-side MOSFET on resistance
Isolation MOSFET on resistance
100
CURRENT LIMIT
ILIM_SW Peak switching current limit FPWM
RLIM = 20 kΩ , Duty cycle = 65%
RLIM = 20 kΩ , Duty cycle = 65%
4
4
4.8
4.8
5.55
5.55
A
A
Peak switching current limit Auto
PFM
ILIM_SW
RLIM = 102 kΩ, Duty cycle = 65%,
4.7uH
ILIM_SW
Peak switching current limit FPWM
0.75
A
Copyright © 2020 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
TJ = -40 to 125°C, L = 1 µH, VIN = 3.3 V and VOUT = 9 V (VO pin). Typical values are at TJ = 25°C, (unless
otherwise noted)
MIN
TYP
MAX
UNIT
Peak switching current limit Auto
PFM
RLIM = 102 kΩ, Duty cycle = 65%,
4.7uH
ILIM_SW
0.75
A
Peak switching current limit at
softstart
VIN = 3.3 V, VOUT = 0 V, RLIM = 20
kΩ
ILIM_SS_1
0.9
1.15
1.4
A
SWITCHING FREQUENCY
Fsw
Switching frequency
RFREQ = 18 kΩ
RFREQ = 218 kΩ
RFREQ = 18 kΩ
2050
180
78
2200
200
2400
230
kHz
kHz
%
Fsw
Switching frequency
Maximum Duty Cycle
Minimal on time
Dmax
tON_min
FDITHER
Fpattern
70
10%
0.4%
ns
Fsw
Fsw
ERROR AMPLIFIER
ISINK
COMP pin sink current
VFB = VREF + 0.2V
VFB = VREF - 0.2V
6
6
uA
uA
V
ISOURCE
VCCLPH
VCCLPL
GmEA
COMP pin source current
COMP pin high clamp voltage
COMP pin high low voltage
Error amplifier trans conductance
VFB = VREF - 0.2V, ILIM = 4.8 A
VFB = VREF + 0.2V,
VCOMP = 1.0 V
1.3
0.6
70
V
uS
POWER GOOD
VPG_TH
VPG_HYS
IPG_SINK
PG threhold for rising FB voltage
Reference to VREF
Reference to VREF
VPG = 0.4 V
90%
5%
20
PG hysteresis
PG pin sink current capability
mA
ms
tPG_DELAY PG delay time
2.5
3.4
4.3
DOWN MODE
Delay time between EN high and
device working
tEN_DELAY
0.4
ms
tSS
Softstart time
2.5
1.8
67
ms
ms
ms
tHCP_ON
tHCP_OFF
Hiccup on time
Hiccup off time
SYNC TIMING
fSYNC_MIN
200
kHz
kHz
fSYNC_MAX
2200
EN/SYNC LOGIC
EN, MODE/SYNC pins Logic high
threshold
VIH
1.2
V
V
EN, MODE/SYNC pins Logic Low
threshold
VIL
0.4
EN, MODE/SYNC pins internal pull
down resistor
RDOWN
800
kΩ
THERMAL SHUTDOWN
tSD_R Thermal shutdown rising threshold
tSD_F
TJ rising
165
145
°C
°C
Thermal shutdown falling threshold TJ falling
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
7.6 Typical Characteristics
VIN = 3.3 V, VOUT = 9 V (VO pin), TA = 25°C, Fsw = 2.2 MHz, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Vin = 2.7 V
Vin = 3.3 V
Vin = 3.8 V
Vin = 2.7 V
Vin = 3.3 V
Vin = 3.8 V
1E-5
0.0001
0.001
0.01
0.1
1
2
0.0001
0.001
0.01
0.1
1
2
Output Current (A)
Output Current (A)
D016
D015
VOUT = 5 V
Auto PFM
Fsw = 2.2 MHz
VOUT = 5 V
FPWM
Fsw = 2.2 MHz
Figure 7-1. 5 VOUT Efficiency vs Output Current
Figure 7-2. 5 VOUT Efficiency vs Output Current
100
100
Vin = 2.7 V
Vin = 2.7 V
Vin = 3.3 V
90
Vin = 5 V
Vin = 3.3 V
90
Vin = 5 V
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
1E-5
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
D007
D006
VOUT = 9 V
Auto PFM
Fsw = 2.2 MHz
VOUT = 9 V
FPWM
Fsw = 2.2 MHz
Figure 7-3. 9 VOUT Efficiency vs Output Current
Figure 7-4. 9 VOUT Efficiency vs Output Current
9.05
30
Vin = 2.7 V
Vin = 3.3 V
Vin = 5 V
TJ = -40 °C
TJ = 25 °C
TJ = 125 °C
9.04
9.03
9.02
9.01
9
28
26
24
22
20
0.0001
0.001
0.01
0.1
1
Output Current (A)
D009
2.3
2.6
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5
VOUT = 9 V
PFM
Fsw = 2.2 MHz
Input Voltage (V)
D001
Figure 7-6. Quiescent Current into VIN vs Input
Voltage
Figure 7-5. 9 VOUT Regulation vs Output Current
Copyright © 2020 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
0.5
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5
TJ = -40 °C
TJ = 25 °C
TJ = 125 °C
5V Output (V)
5.238V Output (V)
5.5V Output (V)
0.4
0.3
0.2
0.1
0
4.9
-40
2.3
2.6
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5
-20
0
20
40
60
80
100
120
140
Input Voltage (V)
D002
Temperature (°C)
D014
Figure 7-7. Shutdown Current vs Input Voltage
Figure 7-8. Fixed Output Voltage vs Temperature
0.805
0.804
0.803
0.802
0.801
0.8
5
FPWM
4.5
4
3.5
3
2.5
2
0.799
0.798
0.797
0.796
0.795
1.5
1
0.5
-40
-20
0
20
40
60
80
100
120
140
10
20
30
40
50
60
70
80
90
100
110
Temperature (°C)
Resistor (kW)
D003
D004
Figure 7-9. Reference Voltage vs Temperature
Figure 7-10. Current Limit vs Setting Resistance
2.4
2.3
Rising
Falling
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.2
2.1
2
0
25
50
75
100
125
150
175
200
225
-40
-20
0
20
40
60
80
100
120
140
Resistor (kW)
Temperature (°C)
D010
D005
Figure 7-12. VIN UVLO Threshold Voltage vs
Temperature
Figure 7-11. Switching Frequency vs Setting
Resistance
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
1.2
3.5
3.475
3.45
Rising
Falling
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
3.425
3.4
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
D012
D011
Figure 7-14. PG Delay Time vs Temperature
Figure 7-13. EN Threshold Voltage vs Temperature
150
5.2
Low Side FET (mW)
5Vin Current Limit (A)
3.3Vin Current Limit (A)
2.7Vin Current Limit (A)
140
High Side FET (mW)
Isolation FET (mW)
130
5.1
5
120
110
100
90
80
4.9
4.8
4.7
70
60
50
40
30
20
30
40
50
60
70
-40
-20
0
20
40
60
80
100
120
140
Duty Cycle (%)
Temperature (°C)
D008
D013
Figure 7-16. Duty Cycle vs Current Limit
Figure 7-15. RDSON vs Temperature
Copyright © 2020 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
8 Detailed Description
8.1 Overview
The TPS61378-Q1 is a fully integrated synchronous boost converter with load disconnect function. It supports
output voltage up to 18.5 V with maximum 4.8-A programmable switching peak current limit. The input voltage
ranges from 2.3 V to 14 V while consuming 25-µA quiescent current.
The TPS61378-Q1 utilizes the fixed frequency peak current control scheme, which has an internal oscillator and
supports adjustable switching frequency from 200 kHz to 2.2 MHz.
The TPS61378-Q1 operates with fixed frequency pulse width modulation (PWM) from medium to heavy load. At
the beginning of each switching cycle, the low-side N-MOSFET switch is turned on, and the inductor current
ramps up to a peak current that is determined by the output of the internal error amplifier (EA). Once the
switching peak current triggers the output of the EA, the low-side N-MOSFET is turned off and the high-side N-
MOSFET is turned on after a short dead time. The high-side N-MOSFET switch is not turned off until the next
cycle as determined by the internal oscillator. The low-side switch turns on again after a short dead time and the
switching cycle is repeated.
The TPS61378-Q1 provides either Auto PFM or Forced PWM option for the light load operation by configuring
the MODE/SYNC pin. In Forced PWM mode, the switching frequency remains constant across the entire load
range, which helps to avoid the frequency variation with load. The internal oscillator can be synchronized to an
external clock applied on the MODE / SYNC pin. Spread spectrum modulation of the frequency in Forced PWM
mode helps to optimize the EMI performance for automotive applications. In Auto PFM mode, the switching
frequency can decrease, resulting in higher efficiency.
The TPS61378-Q1 implements a cycle-by-cycle current limit to protect the device from overload during the boost
operation phase. If the output current further increases and triggers the output voltage to fall below the input
voltage, the TPS61378-Q1 enters into hiccup mode short protection.
There is a built-in soft-start time which prevents the inrush current during the start-up. The TPS61378-Q1 also
provides a power good (PG) indicator to enable the power sequence control for start-up.
The TPS61378-Q1 also has a number of protection features including output short protection, output over
voltage protection (OVP), and thermal shutdown protection (OTP).
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
8.2 Functional Block Diagrams
L1
VIN
C1
C3
C2
OUT
BST
SW
VIN
OUT
VCC
VO
VOUT
1/K
Logic
HS
BST
SW
ULVO
LDO
& BIAS
EN
C4
COMP
VUVLO
Fixed
Output
OVP
SCP
ISO
LS
VCC
OTP
Soft
Start
VCC
MODE
C6
COMP
CLIM
Slope Compensation
R6
R1
COMP
Vref
Gm
PG
FB
VO Voltage
SELECT
PGOOD
VOVP
R4
COMP
COMP
OVP
OTP
1/N
VOUT
Dithering
OSC
SYNC
MODE
FREQ
Current Limit SELECT
VOTP
Temp
R3
GND
COMP
R2
ILIM
MODE/
SYNC
R5
C5
8.3 Feature Description
8.3.1 VCC Power Supply
The internal LDO in the TPS61378-Q1 outputs a regulated voltage of 4.8 V with 10-mA output current capability.
A ceramic capacitor is connected between the VCC pin and GND pin to stabilize the VCC voltage and also
decouple the noise on the VCC pin. The value of this ceramic capacitor should be above 1 µF. A ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating higher than 10 V is recommended.
8.3.2 Input Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the UVLO threshold of 2.04 V (typical). A hysteresis of 160 mV (typical) is added so that the device cannot be
enabled again until the input voltage exceeds 2.2 V (typical). This function is implemented to prevent
malfunctioning of the device when the input voltage is between 2.04 V and 2.2 V.
8.3.3 Enable and Soft Start
When the input voltage is above the UVLO threshold and the EN pin is pulled above 1.2 V, the TPS61378-Q1 is
enabled. The TPS61378-Q1 starts to monitor the FB pin. With a typical 400-µs delay time after EN is pulled high,
the TPS61378-Q1 starts switching. There is an internal built-in start-up time which is typically 2.5 ms to limit the
inrush current during start-up.
Copyright © 2020 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
8.3.4 Shut Down
When the input voltage is below the UVLO threshold or the EN pin is pulled low, the TPS61378-Q1 is in
shutdown mode and all the functions are disabled. The input voltage is isolated from the output to minimize the
leakage currents.
8.3.5 Switching Frequency Setting
The TPS61378-Q1 uses a fixed frequency control scheme and the switching frequency can be programmed
between 200 kHz and 2.2 MHz using a resistor from the FREQ pin to GND. The resistor must be connected
when the oscillator is synchronized by an external clock. The resistance is defined by Equation 1.
41.9
(59 (/*V) =
:
;
4(4'3 GÀ + 1.05
(1)
where
RFREQ is the resistance between the FREQ pin and the GND pin
•
For instance, the switching frequency is 2.2 MHz if the resistance between the FREQ pin and GND is 18 kΩ.
This pin cannot be left floating or tied to VCC.
8.3.6 Spread Spectrum Frequency Modulation
The TPS61378-Q1 uses a triangle waveform to spread the switching frequency with ±10% of normal frequency.
The frequency of the triangle waveform is typically 0.4% of the switching frequency. For example, if the normal
switching frequency of TPS61378-Q1 is programmed to 2.2 MHz, the spread spectrum function will modulate the
switching frequency in the range of 1.98 MHz to 2.42 MHz in a triangle behavior with 8.8 kHz rate .
The spread spectrum is only available while the clock of the TPS61378-Q1 is free running at its natural
frequency. Any of the following conditions overrides spread spectrum, turning it off:
•
•
An external clock is applied to the MODE/SYNC pin
The device works in the PFM operation at light load.
8.3.7 Adjustable Peak Current Limit
The TPS61378-Q1 adopts a cycle-by-cycle peak current limit internally. The low-side switch is turned off
immediately as soon as the switch peak current triggers the limit threshold. The peak switch current limit can be
set by a resistor from the ILIM pin to ground. The relationship between the current limit and the resistor is shown
in Equation 2.
90.56
RLIM kW = 1.184 +
(
)
ILIM
A
(2)
Where
•
•
RILIM is the resistance between the ILIM pin and the GND pin
ILIM is switch peak current limit
For instance, the current limit is set to 4.8 A if the RLIM is 20 kΩ; This pin cannot be left floating or connected to
VCC.
8.3.8 Bootstrap
The TPS61378-Q1 has an integrated bootstrap regulator circuit. A small ceramic capacitor is needed between
the BST pin and SW pin to provide the gate drive supply voltage for the high-side switches. The bootstrap
capacitor is charged during the time when the low-side switch is in the ON state. The value of this ceramic
capacitor should be above 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating
higher than 6.3 V is recommended.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
8.3.9 Load Disconnect
The TPS61378-Q1 integrates a load disconnect function when the input source is DC, which completely cuts off
the path between the input side and the output side during shutdown.
The output disconnect function also allows the output short protection and minimize the inrush current at start-
up.
8.3.10 MODE/SYNC Configuration
Table 8-1 summarizes the MODE/SYNC function and the entry condition.
Table 8-1. MODE/SYNC Configuration
MODE/SYNC PIN CONFIGURATION
Logic Low or Floating
MODE
Auto PFM Mode
Forced PWM Mode
Forced PWM Mode
Logic High
External Synchronization
The TPS61378-Q1 can be synchronized to an external clock applied to the MODE / SYNC pin.
8.3.11 Overvoltage Protection (OVP)
If the output voltage exceeds the OVP threshold (typical 20 V), the TPS61378-Q1 stops switching immediately
until the output voltage drops below the recovery threshold (typical 19.5 V). This function protects the device
against excessive voltage.
8.3.12 Output Short Protection/Hiccup
In addition to the cycle-by-cycle current limit function, the TPS61378-Q1 also has the output short protection. If
the output current causes low-side FET to reach current limit and pull the output voltage below the input voltage,
the device enters into short circuit protection mode which triggers the hiccup timer. When the hiccup timer is
triggered, the device limits the current to a relative lower level for 1.8 ms and then shuts down. After 67 ms, it will
restart. If the short condition disappears, the device will automatically restart.
When FB voltage is below ≤ 0.1 V during fault condition, current limit threshold is reduced to 1/5 of the
programmed current limit, and frequency is clamped to 1.1 MHz if the FREQ pin setting is greater than 1.1 MHz.
8.3.13 Power Good Indicator
The TPS61378-Q1 integrates a power good function. The PG pin asserts when the output voltage rises above
90% of the target output voltage. The PG pin is an open-drain output before the VOUT reaches the 90% target
output voltage. The PG pin becomes active low after a typical 3.4-ms delay time after the VOUT reaches 90% of
the target output voltage. When the output voltage drops below 85% of the target output voltage, the PG logic
goes low immediately without delay.
8.3.14 Thermal Shutdown
A thermal shutdown is implemented to prevent damage due to the excessive heat and power dissipation.
Typically, the thermal shutdown occurs at the junction temperature exceeding 165°C. When the thermal
shutdown is triggered, the device stops switching and recovers when the junction temperature falls below 145°C
(typical).
8.4 Device Functional Modes
8.4.1 Forced PWM Mode
The TPS61378-Q1 enters forced PWM Mode by pulling the MODE/SYNC pin to logic high for more than five
switching cycles. In forced PWM mode, the TPS61378-Q1 keeps the switching frequency constant at light load
condition. When the load current decreases, the output of the internal error amplifier will also decrease to keep
the inductor peak current down. When the output current decreases further, the high-side switch is not turned off
even if the current of the high-side switch goes negative to keep the frequency constant.
Copyright © 2020 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
8.4.2 Auto PFM Mode
The TPS61378-Q1 enters auto PFM Mode by pulling the MODE/SYNC pin to logic low for more than five
switching cycles or leave the pin floating. The TPS61378-Q1 improves the efficiency at light load when operating
in PFM mode. When the output current decreases to a certain level, the output voltage of the error amplifier is
clamped by the internal circuit. If the output current reduces further, the inductor current through the high-side
switch will be clamped but not further lowered. Pulses are skipped to improve the efficiency at light load.
8.4.3 External Clock Synchronization
The TPS61378-Q1 supports external clock synchronization with a range of 200 kHz to 2.2 MHz. The TPS61378-
Q1 remains in the forced PWM Mode and operates in CCM across the entire load range if the oscillator is
synchronized by an external clock. Spread spectrum feature is disabled when external synchronization is used.
8.4.4 Down Mode
The TPS61378-Q1 features Down Mode operation when input voltage is close to or higher than output voltage.
In Down Mode, output voltage is regulated at target value even when VIN > VO. The high-side and low-side FETs
of the TPS61378-Q1 are switching devices that always work in boost operation, where the isolation FET always
works as a linear device.
For boost circuits, on-time or duty cycle is reduced as input voltage approaches output voltage. The TPS61378-
Q1 enters Down Mode when VIN reaches 85% (typical) of VO voltage at 2.2 MHz; while exiting Down Mode
requires VIN to be reduced below 85% (typical) of VO voltage at 2.2 MHz.
In normal operation, isolation FET is fully on.
When Down Mode is triggered and VIN is less than VO pin voltage, the OUT pin will have a fixed 2 V (typical)
above VO pin voltage. Isolation FET works in LDO mode to regulate VO pin voltage with a 2 V constant voltage
drop.
When Down Mode is triggered and VIN is 100 mV (typical) higher than VO pin voltage, the OUT pin will have an
approximated 3 V (typical) above VIN pin voltage, as VIN keeps rising, the OUT pin will continue raise with 3 V on
top of VIN, isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of OUT pin and
VO pin.
Refer to Figure 8-1.
Vin > Vo
Vin < Vo
Down Mode
Entering
Threshold
Down Mode
Exiting
Threshold
Voltage
OUT
VO
VIN
T
Figure 8-1. Down Mode
Care should be taken during short-to-ground condition when operation VIN is above 6 V. During hiccup on, the
device operates in Down Mode and isolation FET voltage drop is VIN + 3 V (OUT pin to VO pin).
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS61378-Q1 is a 25-µA quiescent current boost converter which supports 2.3-V to 14-V input voltage
range. It also supports load disconnect to minimize the leakage current. The following design procedure can be
used to select component values for the TPS61378-Q1.
9.2 Typical Application
VIN
L1
SW
PG
C2
R1
VCC
OUT
BST
VIN
C6
C1
C3
TPS61378-Q1
EN
VOUT
VO
FREQ
R3
R6
R4
COMP
FB
C4
R2
C5
ILIM
MODE/SYNC
GND
R5
Figure 9-1. Typical Application
9.2.1 Design Requirements
A typical application example is dual cameras powered through a coax cable, which normally requires 9.0-V
output as its bias voltage and consumes less than 600 mA current. 800 mA load current is designed to provide
margin. The following design procedure can be used to select external component values for the TPS61378-Q1.
Table 9-1. Design Requirements
PARAMETERS
Input Voltage
VALUES
3.3 V to 6.4 V
9.0 V
Output Voltage
Switching Frequency
Output Current
2.2 MHz
800 mA
Output Voltage Ripple
± 25 mV
9.2.2 Detailed Design Procedure
9.2.2.1 Programming the Output Voltage
There are two ways to set the output voltage of the TPS61378-Q1: adjustable or fixed. If the resistance between
FB and GND is higher than 16 kΩ during start-up, the TPS61378-Q1 works as an adjustable output version. The
FB pin is connected to the negative input of the internal error amplifier directly. The output voltage can be
programmed by adjusting the external resistor divider RUpper and RLower according to Equation 3. When the
output voltage is in well regulation, the typical voltage at the FB pin is VREF of 0.8 V.
Copyright © 2020 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
(47LLAN + 4.KSAN
)
8176 = 84'(
×
4.KSAN
(3)
For some applications where the resistor needs to be as low as possible, the low-side divider can be 20 kΩ. The
reference voltage is 0.8 V, the high-side divider is 205 kΩ for 9-V output voltage.
For other applications without specific requirements on divider resistance, you can choose RLower to be
approximately 80.6 kΩ. Slightly increasing or decreasing RLower can result in closer output voltage matching
when using standard values resistors.
For the best accuracy, RLower is recommended to be smaller than 100 kΩ to ensure that the current following
through RLower is at least 100 times larger than FB pin leakage current. Changing RLower towards the lower value
increases the robustness against noise injection. Changing the RLower to higher values reduces the quiescent
current for achieving higher efficiency at light load.
If the resistance between FB and GND is less than 16 kΩ during start-up, the TPS61378-Q1 works as a fixed
output voltage version. The TPS61378-Q1 uses the internal resistor divider.
For 5-V fixed output voltage, the FB pin can be connected to the GND directly or use a RLower with less than 2
kΩ resistance.
For 5.25-V fixed output voltage, RLower is between 2.0 kΩ and 4.0 kΩ and no RUpper is needed.
For 5.5-V fixed output voltage, the RLower is between 4.0 kΩ and 8.0 kΩ and no RUpper is needed.
9.2.2.2 Setting the Switching Frequency
The switching frequency of the TPS61378-Q1 is set at 2.2 MHz. Use Equation 1 to calculate the required resistor
value. The calculated value is 18 kΩ to get the frequency of 2.2 MHz.
9.2.2.3 Setting the Current Limit
The current limit of the TPS61378-Q1 can be programmed by an external resistor. For a target current limit of 4.8
A, use Equation 2. The calculated resistor value is 20 kΩ.
9.2.2.4 Selecting the Inductor
A boost converter normally requires two main passive components for storing the energy during the power
conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency (including the
ripple and efficiency) as well as the transient behavior and loop stability, which makes the inductor the most
critical component in application.
When selecting the inductor, as well as the inductance, the other important parameters are:
•
•
•
The maximum current rating (RMS and peak current should be considered)
The series resistance
Operating temperature
The TPS61378-Q1 has built-in slope compensation to avoid subharmonic oscillation associated with the current
mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 2 A, the
slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make
the peak-to-peak current ripple between 800 mA to 2 A when selecting the inductor.
The inductance can be calculated by Equation 4, Equation 5, and Equation 6:
V
IN ´ D
DIL =
L ´ fSW
(4)
(5)
VOUT ´ IOUT
DIL _R = Ripple% ´
h ´ V
IN
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
h ´ V
´
Ripple % VOUT ´ IOUT
V ´ D
IN
1
IN
L =
´
ƒSW
(6)
where
•
•
•
•
•
•
•
•
•
ΔIL is the peak-peak inductor current ripple
VIN is the input voltage
D is the duty cycle
L is the inductor
ƒSW is the switching frequency
Ripple % is the ripple ration versus the DC current
VOUT is the output voltage
IOUT is the output current
η is the efficiency
The current flowing through the inductor is the inductor ripple current plus the average input current. During
power-up, load faults, or transient load conditions, the inductor current can increase above the peak inductor
current calculated.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current
approaches the saturation level, its inductance can decrease 20% to 35% from the value at 0-A bias current
depending on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated
current, especially the saturation current, is larger than its peak current during the operation.
The inductor peak current varies as a function of the load, the switching frequency, the input and output voltages
and it can be calculated by Equation 7 and Equation 8.
1
IPEAK = I
+
´ DIL
IN
2
(7)
where
•
•
•
IPEAK is the peak current of the inductor
IIN is the input average current
ΔIL is the ripple current of the inductor
The input DC current is determined by the output voltage, the output current can be calculated by:
VOUT ´ IOUT
I
=
IN
VIN ´ h
(8)
where
•
•
•
•
IIN is the input current of the inductor
VOUT is the output voltage
VIN is the input voltage
η is the efficiency
While the inductor ripple current depends on the inductance, the frequency, the input voltage, and duty cycle are
calculated by Equation 4. Replace Equation 4 and Equation 8 into Equation 7 and get the inductor peak current:
IOUT
VIN ´ D
1
2
IPEAK
=
+
´
(1- D) ´ h
L ´ fSW
(9)
where
•
IPEAK is the peak current of the inductor
Copyright © 2020 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
•
•
•
•
•
•
IOUT is the output current
D is the duty cycle
η is the efficiency
VIN is the input voltage
L is the inductor
ƒSW is the switching frequency
The heat rating current (RMS) is as below:
1
(DIL )2
2
IL _RMS = I
+
IN
12
(10)
where
•
•
•
IL_RMS is the RMS current of the inductor
IIN is the input current of the inductor
ΔIL is the ripple current of the inductor
It is important the peak current does not exceed the inductor saturation current and the RMS current is not over
the temperature related rating current of the inductors.
For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation
current. The total losses of the coil consists of the DC resistance (DCR) loss and the following frequency
dependent loss:
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the
frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However,
it is usually a tradeoff between the loss and foot print. Table 9-2 lists some recommended inductors.
Table 9-2. Recommended Inductors
DCR Typ (mΩ) SATURATION
PART NUMBER
L (μH)
SIZE (L × W × H mm)
VENDOR(1)
MAX
4.1
8.9
25
CURRENT (A)
XEL4030-471MEB
0.47
1
15.5
9
4 x 4 x 3
Coilcraft
Coilcraft
Murata
Murata
TDK
XEL4030-102MEB
4 x 4 x 3
DFE2HCAHR47MJ0L
DFE322520FD-1R0M
TFM322512ALMAR47MTAA
TFM322512ALMA1R0MTAA
0.47
1
5.1
7.5
7.6
5.1
2.5 x 2 x 1.2
3.2 x 2.5 x 2
3.2 x 2.5 x 1.2
3.2 x 2.5 x 1.2
22
0.47
1
16
30
TDK
(1) See Third-party Products Disclaimer
9.2.2.5 Selecting the Output Capacitors
The output capacitor is mainly selected to meet the requirements at load transient or steady state. Then the loop
is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series
resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by Equation 11:
IOUT ´ (VOUT - V )
IN
COUT
=
fSW ´ DV ´ VOUT
(11)
where
COUT is the output capacitor
•
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
•
•
•
•
•
IOUT is the output current
VOUT is the output voltage
VIN is the input voltage
ΔV is the output voltage ripple required
ƒSW is the switching frequency
The additional output ripple component caused by ESR is calculated by Equation 12:
DVESR = IOUT ´ RESR
(12)
where
•
•
ΔVESR is the output voltage ripple caused by ESR
RESR is the resistor in series with the output capacitor
For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors,
it must be considered if used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using
Equation 13:
DISTEP
COUT
=
2p ´ fBW ´ DVTRAN
(13)
where
•
•
•
ΔISTEP is the transient load current step
ΔVTRAN is the allowed voltage dip for the load current step
ƒBW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero)
For the output capacitor on the OUT pin, the effective capacitance is recommended between 0.22 μF to 1 μF.
Care must be taken when evaluating the derating of a ceramic capacitor under the DC bias. Ceramic capacitors
can derate by as much as 70% of its capacitance at its rated voltage. Therefore, enough margins on the voltage
rating should be considered to ensure adequate capacitance at the required output voltage.
9.2.2.6 Selecting the Input Capacitors
Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they
have extremely low ESR and are available in small footprints. Input capacitors should be located as close as
possible to the device. While a 22-µF input capacitor or equivalent is sufficient for the most applications, larger
values can be used to reduce input current ripple.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, should be placed
between CIN and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CIN.
9.2.2.7 Loop Stability and Compensation
9.2.2.7.1 Small Signal Model
The TPS61378-Q1 uses the fixed frequency peak current mode control; there is an internal adaptive slope
compensation to avoid the subharmonic oscillation. With the inductor current information sensed, the small-
signal model of the power stage reduces from a two-pole system, created by L and COUT, to a single-pole
system, created by ROUT and COUT. The single-pole system is easily used with the loop compensation. Figure
9-2 shows the equivalent small signal elements of a boost converter.
Copyright © 2020 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
L
VIN
VOUT
CIN
Q
RESR
ROUT
RSENSE
COUT
Slope
Comp
ISENSE
VOUT
RUP
Q
S
FB
+
Q
R
GEA
RDOWN
VREF
+
Cc
RC
Cp
REA
Figure 9-2. TPS61378-Q1 Control Equivalent Circuitry Model
The small signal of power stage is:
5
2è × B
5
2è × B
(1 +
)(1 F
)
4176 × (1 F &)
2 × 45'05'
'54
4*2
-25 (5) =
×
5
2è × B
(1 +
)
2
(14)
where
•
•
•
D is the duty cycle
ROUT is the output load resistor
RSENSE is the equivalent internal current sense resistor, which is typically 118 mΩ
The single pole of the power stage is:
2
fP =
2p ´ ROUT ´ COUT
(15)
where
•
COUT is the output capacitance, for a boost converter having multiple, identical output capacitors in parallel,
simply combine the capacitors with the equivalent capacitance
The zero created by the ESR of the output capacitor is:
1
fESR
=
2p ´ RESR ´ COUT
(16)
where
RESR is the equivalent resistance in series of the output capacitor
•
The right-hand plane zero is:
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
ROUT ´ (1- D)2
=
2p ´ L
fRHP
(17)
where
•
•
•
D is the duty cycle
ROUT is the output load resistor
L is the inductance
Equation 18 shows the equation for feedback resistor network and the error amplifier.
S
1+
RDOWN
2´ p ´ fZ
HEA(S) = GEA ´REA
´
´
R
UP + RDOWN
S
S
(1+
)´(1+
)
2´ p ´ fP1
2´ p ´ fP2
(18)
where
•
•
REA is the output impedance of the error amplifier and typical REA = 500 MΩ.
ƒP1, ƒP2 is the pole's frequency of the compensation, fZ is the zero’s frequency of the compensation network.
network
1
fP1
=
2p ´ REA ´ Cc
(19)
where
•
CC is the zero capacitor compensation
1
fP2
=
2p ´ RC ´ CP
(20)
where
•
•
CP is the pole capacitor compensation
RC is the resistor of the compensation network
1
fZ =
2p ´RC ´CC
(21)
9.2.2.7.2 Loop Compensation Design Steps
With the small signal models coming out, the next step is to calculate the compensation network parameters with
the given inductor and output capacitance.
1. Set the Cross Over Frequency, ƒC.
The first step is to set the loop crossover frequency, ƒC. The higher crossover frequency, the faster the loop
response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of
the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then calculate the loop compensation
network values of RC, CC, and CP by following equations.
2. Set the Compensation Resistor, RC.
By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~ = RC and so RC × GEA sets the compensation
gain. Setting the compensation gain, KCOMP-dB, at ƒZ, results in the total loop gain, T(s) = KPS(s) × HEA(s) being
zero at ƒC.
Copyright © 2020 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
Therefore, to approximate a single-pole roll-off up to fP2, rearrange Equation 18 to solve for RC so that the
compensation gain, KEA, at fC is the negative of the gain, KPS, read at frequency fC for the power stage bode
plot or more simply:
RDOWN
KEA(fC ) = 20 ´ log(GEA ´ RC ´
) = - KPS(fC)
RUP + RDOWN
(22)
where
•
•
•
KEA is gain of the error amplifier network
KPS is the gain of the power stage
GEA is the transconductance of the amplifier, the typical value of GEA = 70 µA / V
3. Set the Compensation Zero capacitor, CC.
Place the compensation zero at the power stage ROUT ,COUT pole’s position, so to get:
1
fZ =
2p ´ RC ´ CC
(23)
(24)
Set ƒZ = ƒP, and get
R
OUT ´COUT
CC
=
2RC
4. Set the Compensation Pole Capacitor, CP.
Place the compensation pole at the zero produced by the RESR and the COUT. It is useful for canceling
unhelpful effects of the ESR zero.
1
fP2
=
2p ´ RC ´ CP
(25)
(26)
1
fESR
=
2p ´ RESR ´ COUT
Set ƒP2 = ƒESR, and get
RESR ´ COUT
CP =
RC
(27)
9.2.2.7.3 Selecting the Bootstrap Capacitor
The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET
device gate during each cycle’s turn-on and also supplies charge for the bootstrap capacitor. The recommended
value of the bootstrap capacitor is 0.1 µF to 1 µF. CBST should be a good quality, low ESR, ceramic capacitor
located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance.
A value of 0.1 µF was selected for this design example.
9.2.2.7.4 VCC Capacitor
The primary purpose of the VCC capacitor is to supply the peak transient currents of the driver and bootstrap
capacitor as well as provide stability for the VCC regulator. The value of CVCC should be at least 10 times greater
than the value of CBST, and should be a good quality, low-ESR, ceramic capacitor. CVCC should be placed close
to the pins of the IC to minimize potentially damaging voltage transients caused by the trace inductance. A value
of 2.2 µF was selected for this design example.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
9.2.3 Application Curves
Figure 9-3. Switching Waveform VIN = 5 V, VOUT = 9
V, IOUT = 800 mA, FPWM
Figure 9-4. Switching Waveform VIN = 5 V, VOUT = 9
V, IOUT = 0 mA, Auto PFM
Figure 9-6. Start-up from EN Waveform VIN = 5 V,
VOUT = 9 V, IOUT = 500 mA, FPWM
Figure 9-5. Load Transient VIN = 5 V, VOUT = 9 V,
IOUT = 300 mA to 800 mA, FPWM
Figure 9-7. Shutdown from EN Waveforms VIN = 5
V, VOUT = 9 V, IOUT = 500 mA, FPWM
Figure 9-8. Short Circuit Protection VIN = 5 V, VOUT
= 9 V, FPWM
Copyright © 2020 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
Figure 9-10. Hiccup Short Circuit Protection VIN = 5
V, VOUT = 9 V, FPWM
Figure 9-9. Short Circuit Recovery VIN = 5 V, VOUT
9 V, IOUT = 0 mA, FPWM
=
10 Power Supply Recommendations
The TPS61378-Q1 is designed to operate from an input voltage supply range between 2.3 V to 14 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the device, the bulk
capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 47 µF is a typical choice.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator can show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
paths. The input and output capacitor, as well as the inductor should be placed as close as possible to the IC.
11.2 Layout Example
The bottom layer is a large GND plane connected by vias.
GND
GND
GND
VIN
ILIM
BST
PG
GND
SW
OUT
VIN
SW
VO
VO
SW
GND
Figure 11-1. Recommended Layout
Copyright © 2020 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TPS61378-Q1
TPS61378-Q1
SLVSET0A – MAY 2020 – REVISED OCTOBER 2020
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS61378-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS613783QWRTERQ1
TPS613785QWRTERQ1
TPS61378QWRTERQ1
PREVIEW
PREVIEW
ACTIVE
WQFN
WQFN
WQFN
RTE
RTE
RTE
16
16
16
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
2G8H
2G9H
2ELH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61378QWRTERQ1
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS61378QWRTERQ1
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RTE0016K
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
B
A
PIN 1 INDEX AREA
3.15
2.85
0.1 MIN
(0.13)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.8
0.7
C
SEATING PLANE
0.08
0.05
0.00
1.66 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
5
8
12X 0.5
4
9
(0.16)
TYP
4X
SYMM
A
A
17
1.5
1
12
0.30
0.18
16X
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4224938/B 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016K
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.66)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224938/B 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016K
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.51)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4224938/B 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明