TPS62067-Q1 [TI]
采用 2x2 SON 封装的 3MHz、2A 汽车级降压转换器;
| 型号： | TPS62067-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x2 SON 封装的 3MHz、2A 汽车级降压转换器 转换器 |
| 文件： | 总28页 (文件大小：2027K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62065-Q1, TPS62067-Q1
ZHCSD80 –JANUARY 2015
TPS6206x-Q1 采用 2 × 2 SON 封装的 3MHz 2A 降压转换器
1 特性
3 说明
1
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
TPS62065-Q1 和 TPS62067-Q1 器件是一款高效同步
降压 DC-DC 转换器。 该器件可提供高达 2A 的输出电
流。
•
–
–
器件温度 1 级：–40°C 至 125°C 工作结温范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
该器件的输入电压范围为 2.9V 至 6V，非常适合对 5V
或
2
–
器件充电器件模型 (CDM) ESD 分类等级 C4B
3.3V 系统电源轨进行电源转换。 TPS62065-Q1 和
TPS62067-Q1 工作在 3MHz 固定频率下，并且在轻负
载电流条件下会进入节能模式，从而在整个负载电流范
围内保持高效率。 该节能模式针对低输出电压纹波进
行了优化。 对于低噪声应用，可通过将 MODE 引脚拉
为高电平来强制 TPS62065-Q1 器件进入固定频率
PWM 模式。 TPS62067-Q1 提供了开漏电源正常输
出。 在关断模式下，电流消耗降至 5µA，同时内部电
路将使输出电容放电。 TPS62065-Q1 和 TPS62067-
Q1 器件经过了优化，可与微型 1μH 电感以及小型
10μF 输出电容搭配工作，从而实现了最小解决方案尺
寸以及高稳压性能。
•
•
•
•
•
•
•
•
•
•
•
•
•
3MHz 开关频率
VIN 范围：2.9V 至 6V
效率高达 97%
节能模式和 3MHz 固定脉宽调制 (PWM) 模式
电源正常输出
PWM 模式下的输出电压精度为 ±1.5%
输出放电功能
典型值为 18µA 的静态电流
针对最低压降的 100% 占空比
电压定位
时钟抖动
支持最高 1mm 的解决方案
TPS62065-Q1 和 TPS62067-Q1 器件采用小型 2 × 2
× 0.75mm 8 引脚 WSON 封装。
采用 2 × 2 × 0.75mm 晶圆级小外形无引线
(WSON) 封装
器件信息(1)
2 应用
器件型号
TPS62065-Q1
TPS62067-Q1
封装
封装尺寸
•
•
•
•
•
负载点稳压器
汽车负载点 (POL)
WSON (8)
2.00mm x 2.00mm
汽车摄像机模块
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
汽车信息娱乐和导航系统
高级驾驶员辅助系统 (ADAS) 应用
4 典型应用电路
L
1 µH
VOUT
VIN = 2.9 V to 6 V
PVIN
1.8 V 2 A
SW
效率与负载电流间的关系
AVIN
R1
100
95
RPG
100 kΩ
360 kΩ
CIN
Cff
COUT
EN
FB
10 µF
22 pF 10 µF
R2
AGND
PGND
180 kΩ
PG
90
85
80
75
70
65
60
V
V
V
= 3.7 V
= 4.2 V
= 5 V
L = 1.2 µH (NRG4026T 1R2),
COUT = 22 µF (0603 size),
IN
IN
IN
55
50
VOUT = 3.3 V,
Mode: Auto PFM/PWM
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
Load Current (A)
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCM3
TPS62065-Q1, TPS62067-Q1
ZHCSD80 –JANUARY 2015
www.ti.com.cn
目录
10.2 Functional Block Diagram ....................................... 8
10.3 Feature Description................................................. 9
10.4 Device Functional Modes...................................... 10
11 Application and Implementation........................ 13
11.1 Application Information.......................................... 13
11.2 Typical Application ................................................ 13
12 Power Supply Recommendations ..................... 19
13 Layout................................................................... 20
13.1 Layout Guidelines ................................................. 20
13.2 Layout Example .................................................... 20
14 器件和文档支持 ..................................................... 21
14.1 器件支持................................................................ 21
14.2 相关链接................................................................ 21
14.3 商标....................................................................... 21
14.4 静电放电警告......................................................... 21
14.5 术语表 ................................................................... 21
15 机械封装和可订购信息 .......................................... 21
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
典型应用电路 ........................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings.............................................................. 4
8.3 Recommended Operating Conditions....................... 4
8.4 Thermal Information.................................................. 4
8.5 Electrical Characteristics........................................... 5
8.6 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 7
9
10 Detailed Description ............................................. 8
10.1 Overview ................................................................. 8
5 修订历史记录
日期
修订版本
注释
2015 年 1 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
TPS62065-Q1, TPS62067-Q1
www.ti.com.cn
ZHCSD80 –JANUARY 2015
6 Device Comparison Table
PART NUMBER
MODE/PG FUNCTION
TPS62065Q1
TPS62067Q1
MODE = selectable; Power Good = no
Automatic PWM/PFM transition; Power Good = yes
7 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
PGND
SW
1
2
3
4
8
7
6
5
PVIN
AVIN
AGND
FB
MODE/PG
EN
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
PGND
—
OUT
—
GND supply pin for the output stage.
This is the switch pin and is connected to the internal MOSFET switches. Connect the
external inductor between this terminal and the output capacitor.
2
3
4
SW
AGND
FB
Analog GND supply pin for the control circuit.
Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin.
In case of fixed output voltage option, connect this pin directly to the output capacitor
IN
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown
mode. Pulling this pin to high enables the device. This pin must be terminated
5
EN
IN
IN
MODE: MODE pin = high forces the device to operate in fixed frequency PWM mode. MODE
pin = low enables the power save mode with automatic transition from PFM mode to fixed
frequency PWM mode. This pin must be terminated. (TPS62065-Q1)
6
MODE/PG
PG: Power Good open-drain output. Connect an external pullup resistor to a rail which is
below or equal AVIN. (TPS62067-Q1)
Open Drain
Analog VIN power supply for the control circuit must be connected to PVIN and input
capacitor.
7
AVIN
PVIN
IN
PWR
—
8
VIN power supply pin for the output stage.
For good thermal performance, this pad must be soldered to the land pattern on the PCB.
This pad should be used as device GND.
—
Thermal Pad
Copyright © 2015, Texas Instruments Incorporated
3
TPS62065-Q1, TPS62067-Q1
ZHCSD80 –JANUARY 2015
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
AVIN, PVIN
7
(2)
Voltage
EN, MODE/PG, FB
SW
VIN + 0.3 < 7
V
7
1
Current (sink)
into PG
mA
A
Current (source)
Peak output
Internally limited
Junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
8.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Corner pins (1, 4, 5, and 8)
Other pins
V
Charged device model (CDM), per AEC
Q100-011
±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
AVIN
PVIN
,
Supply voltage
2.9
6
V
Output current capability
2000
VIN
1.6
mA
V
Output voltage range for adjustable voltage
Effective Inductance Range
0.8
0.7
L
1
µH
µF
°C
COUT
TJ
Effective Output Capacitance Range
Operating junction temperature
4.5
10
22
–40
125
8.4 Thermal Information
DSG (WSON)
8 PINS
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
64.78
80.60
34.63
1.65
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
35.02
6.61
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TPS62065-Q1, TPS62067-Q1
www.ti.com.cn
ZHCSD80 –JANUARY 2015
8.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to 125°C), typical values are at TJ = 25°C. Unless otherwise noted,
specifications apply for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 1 μH.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
2.9
6
V
IOUT = 0 mA, device operating in PFM mode
and not device not switching
IQ
Operating quiescent current
Shutdown current
18
μA
μA
ISD
EN = GND, current into AVIN and PVIN combined
0.1
1.78
1.95
5
1.83
1.99
Falling
Rising
1.73
1.9
VUVLO
Undervoltage lockout threshold
V
ENABLE, MODE
VIH
VIL
IIN
High level input voltage
2.9 V ≤ VIN ≤ 6 V
1
0
6
0.4
1
V
V
Low level input voltage
Input bias current
2.9 V ≤ VIN ≤ 6 V
EN, Mode tied to GND or AVIN
0.01
μA
POWER GOOD OPEN DRAIN OUTPUT
Rising feedback voltage
93%
87%
95%
90%
98%
92%
0.3
VTHPG
VOL
Power good threshold voltage
Output low voltage
Falling feedback voltage
IOUT = –1 mA; must be limited by external pullup
V
(1)
resistor
ILKG
Leakage current into PG pin
Internal power good delay time
V(PG) = 3.6 V
100
nA
µs
tPGDL
5
POWER SWITCH
(1)
VIN = 3.6 V
120
95
180
150
130
100
RDS(on)
High-side MOSFET on-resistance
mΩ
VIN = 5 V(1)
VIN = 3.6 V(1)
VIN = 5 V(1)
90
RDS(on)
ILIMF
Low-side MOSFET on-resistance
mΩ
mA
°C
75
Forward current limit MOSFET
high-side and low-side
2.9 V ≤ VIN ≤ 6 V
2300
2750
3300
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
150
10
TSD
Thermal shutdown hysteresis
OSCILLATOR
fSW
Oscillator frequency
2.9 V ≤ VIN ≤ 6 V
2.6
3
3.4
MHz
mV
OUTPUT
Vref
Reference voltage
600
PWM operation, MODE = VIN
2.9 V ≤ VIN ≤ 6 V, 0-mA load
device in PFM mode, voltage positioning active(2)
,
VFB(PWM)
VFB(PFM)
Feedback voltage PWM Mode
–1.5%
0% 1.5%
1%
Feedback voltage PFM mode,
Voltage Positioning
Load regulation
Line regulation
–0.5
%/A
%/V
VFB
0
200
500
Activated with EN = GND, 2.9 V ≤ VIN ≤ 6 V, 0.8 ≤
R(Discharge)
tSTART
Internal discharge resistor
Start-up time
75
1450
Ω
VOUT ≤ 3.6 V
Time from active EN to reach 95% of VOUT
μs
(1) Maximum value applies for TJ = 85°C
(2) In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref. See the parameter measurement information.
Copyright © 2015, Texas Instruments Incorporated
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TPS62065-Q1, TPS62067-Q1
ZHCSD80 –JANUARY 2015
www.ti.com.cn
8.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Shutdown Current
Quiescent Current
Oscillator Frequency
Input Voltage and Ambient Temperature
Input Voltage
Input Voltage
Input Voltage, Low-Side Switch
Input Voltage, High-Side Switch
Input Voltage vs. VOUT
Static Drain-Source On-State
Resistance
RDISCHARGE
25
20
15
10
1
T
T
= –40°C
= 25°C
= 85°C
J
J
J
T
0.75
0.50
0.25
5
0
T
T
= –40°C
J
= 25°C
= 85°C
J
J
T
0
2.5
3
3.5
4 4.5
Input Voltage (V)
5
5.5
6
2.5
3
3.5
4 4.5
Input Voltage (V)
5
5.5
6
Figure 1. Shutdown Current vs Input Voltage and Ambient
Temperature
Figure 2. Quiescent Current vs Input Voltage
0.12
3.1
3.05
3
0.1
0.08
0.06
0.04
2.95
2.9
2.85
2.8
T
T
= –40°C
= 25°C
= 85°C
T
T
= –40°C
= 25°C
= 85°C
0.02
0
J
J
J
J
J
J
T
T
2.5
3
3.5
4 4.5
Input Voltage (V)
5
5.5
6
2.5
3
3.5
4 4.5
Input Voltage (V)
5
5.5
6
Low-Side Switch
Figure 3. Oscillator Frequency vs Input Voltage
Figure 4. Static Drain-Source On-State Resistance vs Input
Voltage
6
Copyright © 2015, Texas Instruments Incorporated
TPS62065-Q1, TPS62067-Q1
www.ti.com.cn
0.2
ZHCSD80 –JANUARY 2015
600
500
400
300
200
V
V
= 1.2 V
= 1.8 V
= 3.3 V
O
0.18
0.16
0.14
0.12
0.1
O
O
V
0.08
0.06
0.04
100
0
T
T
= –40°C
= 25°C
= 85°C
J
0.02
0
J
J
T
2.5
3
3.5
4 4.5
Input Voltage (V)
5
5.5
6
2.5
3
3.5
4 4.5
Input Voltage (V)
5
5.5
6
High-Side Switch
Figure 5. Static Drain-Source On-State Resistance vs Input
Voltage
Figure 6. RDISCHARGE vs Input Voltage
9 Parameter Measurement Information
VOUT
up to 2.0 A
L
VIN = 2.9 V to 6 V
PVIN
1 µH / 1.2 µH
SW
AVIN
R1
Cff
COUT
EN
10 µF
FB
CIN
10 µF
MODE/PG
R2
AGND
PGND
L: LQH44PN1R0NP0, L = 1 µH,Murata, NRG4026T1R2, L = 1.2 µH, Taiyo Yuden
CIN/COUT: GRM188R60J106U, Murata 0603 size
Copyright © 2015, Texas Instruments Incorporated
7
TPS62065-Q1, TPS62067-Q1
ZHCSD80 –JANUARY 2015
www.ti.com.cn
10 Detailed Description
10.1 Overview
The TPS62065-Q1 and TPS62067-Q1 step-down converter operates with 3-MHz (typical) fixed-frequency pulse-
width modulation (PWM) at moderate to heavy load currents. At light load currents the converter can
automatically enter power save mode and then operate in pulse-frequency mode (PFM).
During PWM operation the converter uses an unique fast-response voltage-mode controller scheme with input-
voltage feed-forward to achieve good line and load regulation which allows the use of small ceramic input and
output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch
is turned on. The current flows from the input capacitor through the high-side MOSFET switch through the
inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips
and the control logic turns off the switch. The current-limit comparator also turns off the switch in case the
current-limit of the high-side MOSFET switch is exceeded. After a dead time preventing shoot-through current,
the low-side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the
inductor to the output capacitor and to the load. The current returns back to the inductor through the low-side
MOSFET rectifier.
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
high-side MOSFET switch.
10.2 Functional Block Diagram
AVIN
PVIN
Current
Limit Comparator
Undervoltage
Lockout 1.8V
Thermal
Shutdown
Limit
High Side
PFM Comparator
Reference
0.6V VREF
FB
VREF
Softstart
VOUT RAMP
CONTROL
Gate Driver
Anti
Shoot-Through
Control
Stage
Error Amp.
VREF
SW
Integrator
FB
PWM
Comp.
Zero-Pole
Amp.
Internal
FB
Network(1)
Limit
Low Side
MODE(1)
PG
Sawtooth
Generator
3MHz
Clock
Current
Limit Comparator
MODE/
PG
FB
VREF
RDischarge
PG Comparator(1)
EN
PGND
AGND
(1) Function depends on device option.
8
Copyright © 2015, Texas Instruments Incorporated
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ZHCSD80 –JANUARY 2015
10.3 Feature Description
10.3.1 Mode Selection (TPS62065-Q1)
The MODE pin allows mode selection between forced PWM mode and power save mode.
Connecting this pin to GND enables the power save mode with automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light
load currents which allows simple filtering of the switching frequency for noise-sensitive applications. In this
mode, the efficiency is lower compared to when the device is in power save mode during light loads.
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
For the TPS62067-Q1 where the MODE pin is replaced with power good output, the power save mode is
enabled per default.
10.3.2 Power-Good (PG) Output (TPS62067-Q1)
This function is available in the TPS62067-Q1 device only. The PG output is an open-drain output and requires
an external pullup resistor. The circuit is active once the device is enabled and AVIN is above the UVLO
threshold VUVLO. The PG output provides a high level once the feedback voltage exceeds 95% (typical) of the
nominal value. The PG output is driven to a low level when the feedback voltage falls below 90% (typical) of the
nominal value. The PG output is activated with an internal delay of 5 µs.
The PG open-drain output transistor turns on immediately with the EN pin meets the low level and pulls the
output low. The external pullup resistor can be connected to any voltage rail lower or equal the voltage applied to
AVIN pin of the device. The value of the pullup resistor must be carefully selected in order to limit the current into
the PG pin to 1 mA maximum. The external pullup resistor can be connected to VOUT or another voltage rail
which does not exceed the VIN level. The current flowing through the pullup resistor impacts the current
consumption of the application circuit in shutdown mode.
The shut down current of the device does not include the current through the external pullup and internal open-
drain stage. The PG signal can be used for sequencing various converters or to reset a microcontroller.
EN
Overload
Startup
95%
90%
VOUT
PG
Output
discharge
t
Ramp
t
Start
With EN = low
PG --> low
Figure 7. Power Good Output PG
10.3.3 Enable
Setting the EN pin high enables the device. At first, the internal reference is activated and the internal analog
circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltage
reaches 95% of the nominal value within tSTART which is 500 µs (typical) after the device has been enabled. The
EN input can be used to control power sequencing in a system with various DC-DC converters. The EN pin can
connect to the output of another converter in order to drive the EN pin high and get a sequencing of supply rails.
When EN is pulled low the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin
is connected to PGND through an internal resistor to discharge the output.
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TPS62065-Q1, TPS62067-Q1
ZHCSD80 –JANUARY 2015
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Feature Description (continued)
10.3.4 Soft Start
The TPS62065-Q1 and TPS62067-Q1 device has an internal soft-start circuit that controls the ramp up of the
output voltage. When the converter is enabled and the input voltage is above the UVLO threshold, VUVLO, the
output voltage ramps up from 5% to 95% of the nominal value with tRamp of 250 µs (typical). The ramp time limits
the inrush current in the converter during start up and prevents possible input voltage drops when a battery or
high impedance power source is used.
During soft start, the switch current-limit is reduced to 1/3 of the nominal value, ILIMF, until the output voltage
reaches 1/3 of the nominal value. When the output voltage trips this threshold, the device operates with the
nominal current limit, ILIMF
.
10.3.5 Internal Current-Limit and Foldback Current-Limit For Short-Circuit Protection
During normal operation the high-side and low-side MOSFET switches are protected by the current-limit ILIMF
.
When the high-side MOSFET switch reaches the current-limit, it turns off and the low-side MOSFET switch turns
on. The high-side MOSFET switch can only turn on again when the current in the low-side MOSFET switch
decreases below ILIMF. The device is capable to provide peak-inductor currents up to the internal current limit,
.
ILIMF.
As soon as the switch current-limits are met and the output voltage falls below 1/3 of the nominal output voltage
because of overload or short circuit condition, the foldback current-limit is enabled. In this case the switch
current-limit is reduced to 1/3 of the nominal value ILIMF
.
Because the short-circuit protection is enabled during start-up, the device does not deliver more than 1/3 of the
nominal current-limit, ILIMF, until the output voltage exceeds 1/3 of the nominal output voltage. This protection
must be considered when a load is connected to the output of the converter, which acts as a current sink.
10.3.6 Clock Dithering
In order to reduce the noise level of switch-frequency harmonics in the higher RF bands, the TPS62065-Q1 and
TPS62067-Q1 device has a built-in clock-dithering circuit. The oscillator frequency is slightly modulated with a
sub clock causing a clock dither of 6 ns (typical).
10.3.7 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device enters thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned off. The device continues operation with a soft start once
the junction temperature falls below the thermal shutdown hysteresis.
10.4 Device Functional Modes
10.4.1 Power Save Mode
At TPS62065-Q1 pulling the MODE pin low enables power save mode. In TPS62067-Q1 power-save mode is
enabled per default. If the load current decreases, the converter enters power save mode operation
automatically. During power save mode the converter skips switching and operates with reduced frequency in
PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output
voltage 1% (typical) above the nominal output voltage. This voltage positioning feature minimizes voltage drops
caused by a sudden load step.
The transition from PWM mode to PFM mode occurs when the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During the power save mode the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUTnominal +1%, the device starts a PFM current pulse. For this the high-
side MOSFET switch turns on and the inductor current ramps up. After the on-time expires, the switch is turned
off and the low-side MOSFET switch is turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current the output voltage rises. If the output voltage is equal or higher than the PFM comparator threshold, the
device stops switching and enters a sleep mode with a typical 18-µA current consumption.
10
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Device Functional Modes (continued)
In case the output voltage is still below the PFM comparator threshold, further PFM current pulses are generated
until the PFM comparator reaches its threshold. The converter starts switching again once the output voltage
drops below the PFM comparator threshold due to the load current.
In case the output current can no longer be supported in PFM mode, the device exits PFM mode and enters
PWM mode.
10.4.1.1 Dynamic Voltage Positioning
This feature reduces the voltage under or overshoots at load steps from light to heavy load and vice versa. It is
active in power save mode and regulates the output voltage 1% higher than the nominal value. This provides
more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
Output voltage
VOUT +1%
Voltage Positioning
PFM Comparator
threshold
Light load
PFM Mode
VOUT (PWM)
Moderate to heavy load
PWM Mode
Figure 8. Power Save Mode Operation with automatic Mode transition
10.4.1.2 100% Duty-Cycle Low-Dropout Operation
The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage.
In order to maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles.
With further decreasing VIN the high-side MOSFET switch is turned on completely. In this case the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
VINmin = VOmax + IOmax × (RDS(on)max + RL)
where
•
•
•
•
IOmax = maximum output current
RDS(on)max = maximum P-channel switch RDS(on)
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
(1)
10.4.1.3 Undervoltage Lockout (UVLO)
The UVLO circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of
the battery. It disables the output stage of the converter once the falling VIN trips the UVLO threshold VUVLO. The
UVLO threshold VUVLO for falling VIN is typically 1.78 V. The device starts operation once the rising VIN trips
UVLO threshold VUVLO again at typically 1.95 V.
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Device Functional Modes (continued)
10.4.1.4 Output Capacitor Discharge
With EN pulled low, the device enters shutdown mode and all internal circuits are disabled. The SW pin is
connected to PGND through an internal resistor to discharge the output capacitor. This feature ensures a startup
in a discharged output capacitor once the converter is enabled again and prevents a floating charge on the
output capacitor. The output voltage ramps up monotonic starting from 0 V.
12
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The TPS62065-Q1 and TPS62067-Q1 is a highly efficient synchronous 2-A step down DC-DC converter.
11.2 Typical Application
L
1 µH
VOUT = 1.8 V
up to 2 A
VIN = 2.9 V to 6 V
PVIN
AVIN
SW
FB
R1
COUT
Cff
360 kΩ
22 pF
10 µF
EN
CIN
MODE
R2
10 µF
AGND
PGND
180 kΩ
Figure 9. TPS62065-Q1 Adjustable 1.8-V Output-Voltage Configuration
L
1 µH
VOUT
VIN = 2.9 V to 6 V
1.8 V 2 A
PVIN
SW
R1
AVIN
EN
RPG
360 kΩ
Cff
COUT
CIN
100 kΩ
FB
22 pF
10 µF
10 µF
R2
AGND
PGND
180 kΩ
PG
Figure 10. TPS62067-Q1 Adjustable 1.8-V Output-Voltage Configuration
11.2.1 Design Requirements
The device operates over an input voltage range from 2.9 V to 6 V. The output voltage is adjustable using an
external feedback divider.
11.2.2 Detailed Design Procedure
11.2.2.1 Output Voltage Setting
The output voltage can be calculated to:
æ
ö
÷
ø
æ
ç
è
ö
R1
R2
VOUT
VREF
VOUT = VREF ´ 1+
R1 =
-1 ´ R2
ç
÷
è
ø
(2)
13
with an internal reference voltage VREF typically 0.6 V.
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ZHCSD80 –JANUARY 2015
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Typical Application (continued)
To minimize the current through the feedback divider network, R2 should be within the range of 120 kΩ to 360
kΩ. The sum of R1 and R2 should not exceed ~1 MΩ, to keep the network robust against noise. An external feed-
forward capacitor Cff is required for optimum regulation performance. Lower resistor values can be used. R1 and
Cff places a zero in the loop. The right value for Cff can be calculated as:
1
fz =
= 25 kHz
2 ´ p ´ R1 ´ Cff
(3)
(4)
1
Cff
=
2 ´ p ´ R1 ´ 25 kHz
11.2.2.2 Output Filter Design (inductor And Output Capacitor)
The internal compensation network of TPS62065-Q1 and TPS62067-Q1 is optimized for a LC output filter with a
corner frequency of:
1
f
=
= 50 kHz
C
2 ´ p ´ 1 µH ´ 10 µF
(
)
(5)
The part operates with nominal inductors of 1 µH to 1.2 µH and with 10-µF to 22-µF small X5R and X7R ceramic
capacitors. Please refer to the lists of inductors and capacitors. The part is optimized for a 1-µH inductor and 10-
µF output capacitor.
11.2.2.2.1 Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its DC
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VI or VO.
Equation 6 calculates the maximum inductor current in PWM mode under static load conditions. The saturation
current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7.
This is recommended because during heavy load transient the inductor current rises above the calculated value.
VOUT
1-
V
IN
DIL = VOUT
´
L ´ f
where
•
•
•
ΔIL = Peak-to-peak inductor ripple current
L = Inductor value
f = Switching frequency (3-MHz typical)
(6)
(7)
DIL
ILmax = IOUTmax
+
2
where
•
ILmax = Maximum inductor current
A more conservative approach is to select the inductor current rating just for the switch current limit ILIMF of the
converter.
The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both
the losses in the DC resistance R(DC) and the following frequency-dependent components:
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
14
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Table 2. List of Inductors
DIMENSIONS [mm3]
3,2 × 2,5 × 1 max
3,7 × 4 × 1,8 max
4 × 4 × 2,6 max
INDUCTANCE μH
INDUCTOR TYPE
SUPPLIER
Murata
1
LQM32PN (MLCC)
LQH44 (wire wound)
NRG4026T (wire wound)
DE3518 (wire wound)
1
Murata
1.2
1.2
Taiyo Yuden
TOKO
3,5 × 3,7 × 1,8 max
11.2.2.2.2 Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS62065-Q1 and TPS62067-Q1 allows the
use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple
and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies
and may not be used. For most applications a nominal 10-µF or 22-µF capacitor is suitable. At small ceramic
capacitors, the DC-bias effect decreases the effective capacitance. Therefore a 22-µF capacitor can be used for
output voltages higher than 2 V, see list of capacitors.
In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter,
the output capacitor COUT must be decreased in order not to exceed the recommended effective capacitance
range. In this case a loop stability analysis must be performed as described later.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as:
VOUT
1-
V
1
IN
IRMSCout = VOUT
´
´
L ´ f
2 ´
3
(8)
11.2.2.2.3 Input Capacitor Selection
Because the buck converter has a pulsating input current, a low ESR input capacitor is required for best input
voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most
applications a 10-µF ceramic capacitor is recommended. The input capacitor can be increased without any limit
for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
Table 3. List of Capacitors
CAPACITANCE
10 μF
TYPE
SIZE [ mm3]
SUPPLIER
Murata
GRM188R60J106M
GRM188R60G226M
CL10A226MQ8NRNC
CL10A106MQ8NRNC
0603: 1,6 × 0,8 × 0,8
0603: 1,6 × 0,8 × 0,8
0603: 1,6 × 0,8 × 0,8
0603: 1,6 × 0,8 × 0,8
22 μF
Murata
22 µF
Samsung
Samsung
10 µF
11.2.2.3 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal
•
•
•
Switching node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or wrong L-C output filter
combinations. As a next step in the evaluation of the regulation loop, test the load transient response. The results
are most easily interpreted when the device operates in PWM mode at medium to high load currents.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
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11.2.3 Application Curves
Table 4. Table of Graphs
FIGURE
Figure 11
Figure 12
Figure 13
Load Current, VOUT = 1.2 V, Auto PFM and PWM Mode, Linear Scale
Load Current, VOUT = 1.8 V, Auto PFM and PWM Mode, Linear Scale
Load Current, VOUT = 3.3 V, PFM and PWM Mode, Linear Scale
η
Efficiency
Load Current, VOUT = 1.8 V, Auto PFM and PWM Mode vs. Forced PWM
Mode, Logarithmic Scale
Figure 14
Load Current, VOUT = 1.8 V, Auto PFM and PWM Mode
Load Current, VOUT = 1.8 V, Forced PWM Mode
Figure 15
Figure 16
Output Voltage Accuracy
Typical Operation
PWM Mode, VIN = 3.6 V, VOUT = 1.8 V, 500 mA, L = 1.2 μH, COUT = 10
μF
Figure 17
PFM Mode, VIN = 3.6 V, VOUT = 1.8 V, 20 mA, L = 1.2 μH, COUT = 10 μF
PWM Mode, VIN = 3.6 V, VOUT = 1.2 V, 0.2 mA to 1 A
PFM Mode, VIN = 3.6 V, VOUT = 1.2 V, 20 mA to 250 mA
VIN = 3.6 V, VOUT = 1.8 V, 200 mA to 1500 mA
PWM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
PFM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
VIN = 3.6 V, VOUT = 1.8 V, Load = 2.2 Ω
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Load Transient
Line Transient
Startup into Load
Startup TPS62067-Q1
Output Discharge
Into 2.2-Ω Load with Power Good
VIN = 3.6 V, VOUT = 1.8 V, No Load
Shutdown TPS62067-Q1
VIN = 4.2 V, VOUT = 3.3 V, No Load, PG Pullup Resistor 10 kΩ
100
95
100
95
90
85
80
75
70
65
90
85
80
75
70
65
60
V
V
V
V
V
= 3 V
V
V
V
V
V
= 3 V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 3.3 V
= 3.6 V
= 4.2 V
= 5 V
= 3.3 V
= 3.6 V
= 4.2 V
= 5 V
60
55
50
55
50
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
Load Current (A)
Load Current (A)
VOUT = 1.2 V
L = 1.2 µH (NRG4026T 1R2)
Linear Scale
VOUT = 1.8 V
L = 1.2 µH (NRG4026T 1R2)
Linear Scale
COUT = 10 µF (0603 size)
COUT = 10 µF (0603 size)
Figure 11. Efficiency vs Load Current
Auto PFM and PWM MODE
Figure 12. Efficiency vs Load Current
PFM and PWM MODE
16
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100
ZHCSD80 –JANUARY 2015
100
90
95
90
85
80
75
70
65
60
80
70
60
50
40
30
20
10
0
Auto PFM/
Forced
PWM Mode PWM Mode
V
V
V
V
= 3.3 V
= 3.6 V
= 4.2 V
= 5 V
IN
IN
IN
IN
V
V
V
= 3.7 V
= 4.2 V
= 5 V
IN
IN
IN
55
50
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
0.001
0.01
0.1
Load Current (A)
1
10
Load Current (A)
VOUT = 3.3 V
L = 1.2 µH (NRG4026T 1R2)
Linear Scale
VOUT = 1.8 V
COUT = 10 µF (0603 size)
Logarithmic Scale
L = 1.2 µH (NRG4026T 1R2)
COUT = 22 µF (0603 size)
Figure 13. Efficiency vs Load Current
Figure 14. Efficiency vs Load Current
Auto PFM and PWM MODE
Auto PFM and PWM Mode vs. Forced PWM Mode
1.890
1.872
1.890
1.872
Voltage Positioning PFM Mode
1.854
1.836
1.818
1.800
1.782
1.764
1.746
1.854
1.836
1.818
1.800
1.782
1.764
PWM Mode
V
V
V
V
= 3.3 V
= 3.6 V
= 4.2 V
= 5 V
V
V
V
V
= 3.3 V
IN
IN
IN
IN
IN
IN
IN
IN
1.746
= 3.6 V
= 4.2 V
= 5 V
1.728
1.710
1.728
1.710
0.001
0.01
0.1
Load Current (A)
1
10
0.001
0.01
0.1
Load Current (A)
1
10
L = 1 µH
VOUT = 1.8 V
COUT = 10 µF
L = 1 µH
VOUT = 1.8 V
COUT = 10 µF
Figure 16. Output Voltage Accuracy vs Load Current
Forced PWM MODE
Figure 15. Output Voltage Accuracy vs Load Current
Auto PFM and PWM MODE
V
50 mV/Div
OUT
V
50 mV/Div
OUT
SW 2 V/Div
SW 2 V/Div
I
500 mA/Div
COIL
I
200 mA/Div
COIL
Time Base - 4 µs/Div
VOUT = 1.8 V
L = 1.2 µH
Time Base - 100 ns/Div
VIN = 3.6 V
MODE = GND
IOUT = 20 mA
VIN = 3.6 V
VOUT = 1.8 V
MODE = GND
IOUT = 500 mA
COUT = 10 µF
COUT = 10 µF
L = 1.2 µH
Figure 18. Typical Operation (PFM Mode)
Figure 17. Typical Operation (PWM Mode)
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V 100 mV/Div
OUT
V
100 mV/Div
OUT
SW 2 V/Div
SW 2 V/Div
I
1 A/Div
COIL
I
1 A/Div
COIL
I
500 mA/Div
LOAD
I
500 mA/Div
LOAD
Time Base - 10 µs/Div
Time Base - 10 µs/Div
VIN = 3.6 V
VOUT = 1.2 V
IOUT = 0.2 to 1 A
VIN = 3.6 V
VOUT = 1.8 V
IOUT = 20 to 2500 mA
Figure 19. Load Transient Response, MODE = VIN
PWM Mode 0.2 A to 1 A
Figure 20. Load Transient
PFM Mode 20 mA to 250 mA
VOUT
200 mV/Div
VIN
500 mV/Div
ILOAD
2 A/Div
VOUT
50 mV/Div
IINDUCTOR
1 A/Div
Time Base - 100 µs/Div
VOUT = 1.8 V
L = 1.2 µH
Time Base - 100 µs/Div
VIN = 3.6 to 4.2 V
COUT = 10 µF
IOUT = 500 mA
VIN = 3.6 V
VOUT = 1.8 V
L = 1.2 µH
COUT = 10 µF
Figure 22. Line Transient Response PWM Mode
Figure 21. Load Transient Response
200 mA To 1500 mA
EN
2 V/Div
VIN
500 mV/Div
VOUT
1 V/Div
2 A/Div
ICOIL
500 mA/Div
VOUT
50 mV/Div
ILOAD
500 mA/Div
Time Base - 100 µs/Div
VOUT = 1.8 V
L = 1.2 µH
Time Base - 100 µs/Div
VIN = 3.6 to 4.2 V
COUT = 10 µF
IOUT = 50 mA
VIN = 3.6 V
VOUT = 1.8 V
L = 1.2 µH
Load = 2R2
COUT = 10 µF
Figure 23. Line Transient PFM Mode
Figure 24. Startup Into Load
18
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ZHCSD80 –JANUARY 2015
EN
1 V/Div
EN
2 V/Div
SW
2 V/Div
VOUT
2 V/Div
V
OUT
1 V/Div
ICOIL
1 A/Div
PG
2 V/Div
Time Base - 2 ms/Div
Time Base - 100 µs/Div
VIN = 3.6 V
VOUT = 1.8 V
No load
VIN = 4.2 V
VOUT = 3.3 V
Load = 2R2
COUT = 1.8 µF
PG Pullup resistor 10 kΩ
Figure 26. Output Discharge
Figure 25. Startup TPS62067-Q1 into 2.2-Ω Load With
Power Good
EN
2 V/Div
V
OUT
2 V/Div
PG
5 V/Div
Time Base - 1 ms/Div
VIN = 4.2 V
VOUT = 3.3 V
No load
PG pullup resistor, 10 kΩ
Figure 27. Shutdown TPS62067-Q1
12 Power Supply Recommendations
The power supply to the TPS62065-Q1 and TPS62067-Q1 must have a current rating according to the supply
voltage, output voltage, and output current of the TPS62065-Q1 and TPS62067-Q1.
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13 Layout
13.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. The input capacitor needs to be
placed as close as possible to the IC pins.
It is critical to provide a low inductance, impedance ground and supply path. Therefore, use wide and short
traces for the main current paths. Connect the AGND and PGND pins of the device to the thermal pad land of
the PCB and use this pad as a star point. Use a common power PGND node and a different node for the signal
AGND to minimize the effects of ground noise. The FB divider network should be connected right to the output
capacitor and the FB line must be routed away from noisy components and traces (for example, SW line).
Due to the small package of this converter and the overall small solution size the thermal performance of the
PCB layout is important. To get a good thermal performance a four or more layer PCB design is recommended.
The PowerPAD of the IC must be soldered on the thermal pad area on the PCB to get a proper thermal
connection. For good thermal performance the exposed pad on the PCB must be connected to an inner GND
plane with sufficient via connections. Please refer to the documentation of the evaluation kit.
13.2 Layout Example
VIN
GND
CIN
COUT
VOUT
L
R2
R1
CFF
Figure 28. PCB Layout
20
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14 器件和文档支持
14.1 器件支持
14.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
14.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 5. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS62065-Q1
TPS62067-Q1
14.3 商标
14.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
15 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62065QDSGRQ1
TPS62067QDSGRQ1
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
SJF
SIP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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