TPS62087 [TI]
采用 2x2 QFN 封装、应用 DCS-Control 技术、具有间断模式短路保护功能的 3A 降压转换器;
| 型号： | TPS62087 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x2 QFN 封装、应用 DCS-Control 技术、具有间断模式短路保护功能的 3A 降压转换器 DCS 分布式控制系统 转换器 |
| 文件： | 总26页 (文件大小：1351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62085, TPS62086, TPS62087
ZHCSBQ9C –OCTOBER 2013 –REVISED JANUARY 2021
采用2mm × 2mm VSON 封装且具有断续短路保护功能的TPS6208x 3A 降压转换
器
1 特性
3 说明
• DCS-Control™ 拓扑
• 效率高达95%
• 断续短路保护
• 可实现轻负载效率的省电模式
• 100% 占空比，可实现超低压降
• 输入电压范围：2.5V 至6.0V
• 工作静态电流为17μA
• 可调输出电压：0.8V 至VIN
• 1.8V 至3.3V 固定输出电压
• 输出放电
TPS62085、TPS62086 和TPS62087 器件是高频同步
降压转换器，经优化具有小解决方案尺寸和高效率两大
优点。该器件的输入电压范围为 2.5V 至6.0V，支持常
用电池技术。
此器件主要用于宽输出电流范围内的高效降压转换。该
转换器在中等程度的负载到高负载时运行于脉宽调制
(PWM) 模式，并在轻负载时自动进入省电模式运行，
从而在整个负载电流范围内保持高效率。
为了满足系统电源轨的需求，内部补偿电路支持 10µF
到 150uF 的宽范围外部输出电容值选项。凭借 DCS-
Control 架构，该器件可实现出色的负载瞬态性能和输
出稳压精度。器件可提供2mm × 2mm VSON 封装。
• 电源正常状态输出
• 热关断保护
• 采用2mm × 2mm VSON 封装
• 借助以下工具创建定制设计方案：
器件信息
封装(1)
– TPS62085 WEBENCH® Power Designer
– TPS62086 WEBENCH® Power Designer
– TPS62087 WEBENCH® Power Designer
封装尺寸（标称值）
器件型号
TPS62085
TPS62086
TPS62087
VSON (7)
2.00mm × 2.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 电池供电的应用
• 负载点
• 处理器电源
• 硬盘驱动器
100
90
L1
0.47µH
TPS62087
VIN
2.5V to 6V
VOUT
VIN
EN
SW
VOS
FB
1.8V/3A
C1
10µF
C2
22µF
R3
1M
80
GND
PG
70
POWER GOOD
Vin = 2.5V
Vin = 3.3V
典型应用原理图
60
Vin = 4.2V
Vout = 1.8 V
Vin = 5.0V
50
0.001
0.010
0.100
Iout (A)
1.000
C004
典型应用效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSB70
TPS62085, TPS62086, TPS62087
ZHCSBQ9C –OCTOBER 2013 –REVISED JANUARY 2021
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Table of Contents
8.4 Device Functional Modes............................................9
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................16
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
11.3 Thermal Considerations..........................................16
12 Device and Documentation Support..........................17
12.1 Device Support....................................................... 17
12.2 Documentation Support.......................................... 17
12.3 接收文档更新通知................................................... 17
12.4 支持资源..................................................................17
12.5 Trademarks.............................................................17
12.6 静电放电警告.......................................................... 17
12.7 术语表..................................................................... 18
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................6
8 Detailed Description........................................................7
8.1 Overview.....................................................................7
8.2 Functional Block Diagram...........................................7
8.3 Feature Description.....................................................7
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (July 2018) to Revision C (January 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
• Changed maximum IPG,LKG specification up to 125°C TJ from 0.16 µA to 0.25 µA in Electrical Characteristics
table....................................................................................................................................................................5
Changes from Revision A (June 2015) to Revision B (July 2018)
Page
• 将特性列表中的封装名称从QFN 更改为VSON................................................................................................1
• 向数据表添加了Webench 链接.......................................................................................................................... 1
• Added SW node AC value in Absolute Maximum Ratings table ........................................................................4
• Changed fPFM To: fPSM in 方程式1 .................................................................................................................... 7
• Added 图8-1 to Power Save Mode section........................................................................................................7
• Added 表8-1 to Power Good section ................................................................................................................ 9
• Changed Murata inductor part number in 表9-4 ..............................................................................................11
Changes from Revision * (October 2013) to Revision A (June 2015)
Page
• 添加了ESD 等级表、特性说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器
件和文档支持部分以及机械、封装和可订购信息部分.......................................................................................1
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5 Device Options
PART NUMBER(1)
OUTPUT VOLTAGE
Adjustable
3.3 V
TPS62085RLT
TPS62086RLT
TPS62087RLT
1.8 V
(1) For detailed ordering information, please check the 节Mechanical, Packaging, and Orderable Information section at the end of this
datasheet.
6 Pin Configuration and Functions
1
EN
7
VIN
2
PG
6
SW
3
FB
5
GND
4
VOS
图6-1. RLT Package 7-Pin VSON Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
EN
1
IN
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device.
This pin has a pulldown resistor of typically 400 kΩwhen the device is disabled.
FB
3
5
2
IN
Feedback pin. For the fixed output voltage versions this pin must be connected to the output voltage.
Ground pin.
GND
PG
OUT Power good open drain output pin. The pullup resistor can not be connected to any voltage higher than 6 V. If
unused, leave it floating.
SW
6
7
4
PWR Switch pin of the power stage.
PWR Input voltage pin.
VIN
VOS
IN
Output voltage sense pin. This pin must be directly connected to the output capacitor.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
7
UNIT
VIN, FB, VOS, EN, PG
Voltage at Pins(2)
Temperature
V
SW (DC)
VIN + 0.3
SW (AC, less than 100ns)(3)
Operating Junction, TJ
Storage, Tstg
11
150
150
°C
°C
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN(1)
NOM MAX(1) UNIT
VIN
Input voltage range
2.5
6
1
V
mA
V
ISINK_PG Sink current at PG pin
VPG
TJ
Pullup resistor voltage
6
Operating junction temperature
125
°C
–40
(1) Refer to 节9 for further information.
7.4 Thermal Information
TPS6208x
THERMAL METRIC
RLT [VSON]
7 PINS
107.8
66.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.1
ψJT
17.1
ψJB
RθJC(bot)
N/A
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7.5 Electrical Characteristics
TJ = –40 °C to 125 °C, and VIN = 3.6 V. Typical values are at TJ = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
VIN
Input voltage range
2.5
6
V
No load, device not switching
TJ = –40 °C to 85 °C, VIN = 2.5 V to 5.5 V
IQ
Quiescent current into VIN
Shutdown current into VIN
17
25
µA
EN = Low,
ISD
0.7
5
µA
TJ = –40 °C to 85 °C, VIN = 2.5 V to 5.5 V
Undervoltage lockout threshold
Undervoltage lockout hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
VIN falling
VIN rising
TJ rising
TJ falling
2.1
1.0
2.2
200
150
20
2.3
V
VUVLO
mV
°C
°C
TJSD
LOGIC INTERFACE EN
VIH
High-level input voltage
VIN = 2.5 V to 6.0 V
VIN = 2.5 V to 6.0 V
EN = High
V
V
VIL
Low-level input voltage
0.4
IEN,LKG
RPD
Input leakage current into EN pin
Pulldown resistance at EN pin
0.01
400
0.16
µA
kΩ
EN = Low
SOFT START, POWER GOOD
tSS
Soft-start time
Time from EN high to 95% of VOUT nominal
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 1 mA
0.8
95%
90%
ms
93%
88%
98%
93%
0.4
VPG
Power good threshold
VPG,OL
IPG,LKG
IPG,LKG
Low-level output voltage
V
Input leakage current into PG pin
Input leakage current into PG pin
0.01
0.01
0.16
0.25
µA
µA
VPG = 5.0 V, TJ = –40 °C to 85 °C
VPG = 5.0 V
OUTPUT
Output voltage range, TPS62085
0.8
VIN
V
–
1.0%
1.0%
IOUT = 1 A, VIN ≥VOUT + 1 V, PWM mode
IOUT = 0 A, VIN ≥VOUT + 1 V, PSM mode
VOUT
Output voltage accuracy,
TPS62086, TPS62087(1)
–
1.0%
2.1%
792
792
800
800
808
817
0.1
IOUT = 1A , VIN ≥VOUT + 1 V, PWM mode
IOUT = 0 A, VIN ≥VOUT + 1 V, PSM mode
VFB = 1 V
VFB
Feedback regulation voltage(1) (2)
mV
µA
IFB,LKG
RDIS
Feedback input leakage current
Output discharge resistor
Line regulation
0.01
260
EN = LOW, VOUT = 1.8 V
Ω
IOUT = 1 A, VIN = 2.5 V to 6.0 V
IOUT = 0.5 A to 3 A
0.02
0.16
%/V
Load regulation
%/A
POWER SWITCH
High-side FET ON-resistance
ISW = 500 mA
ISW = 500 mA
31
23
56
45
mΩ
mΩ
A
RDS(on)
Low-side FET ON-resistance
High-side FET switch current limit
PWM switching frequency
ILIM
fSW
3.7
4.6
2.4
5.5
IOUT = 1 A
MHz
(1) For more information, see 节8.3.1.
(2) Conditions: L = 0.47 μH, COUT = 22 μF
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7.6 Typical Characteristics
10M
1M
100k
10k
Vin = 2.5 V
Vin = 3.6 V
Vin = 6.0 V
Vout = 1.2 V
1000
0.001
0.010
0.100
Iout (A)
1.000
C007
图7-1. Switching Frequency
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8 Detailed Description
8.1 Overview
The TPS62085, TPS62086, and TPS62087 synchronous step-down converters are based on the DCS-Control
(Direct Control with Seamless transition into Power Save Mode) topology. This is an advanced regulation
topology that combines the advantages of hysteretic, voltage, and current mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC
quiescent current to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PSM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. Fixed output voltage version provides smallest
solution size combined with lowest no load current. The devices offer both excellent DC voltage and superior
load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagram
PG
Hiccup
Counter
VFB
VIN
VREF
High Side
Current Sense
Bandgap
Undervoltage Lockout
Thermal Shutdown
EN
400 kΩ(2)
SW
MOSFET Driver
Control Logic
GND
VOS
Ramp
Direct Control
and
Compensation
Comparator
R1(1)
R2(1)
Timer
ton
FB
VREF
Error Amplifier
260 Ω
DCS - Control TM
Output Discharge
Logic
EN
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(2) When the device is enabled, the 400 kΩ resistor is disconnected.
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the TPS62085, TPS62086, and TPS62087 enter Power Save Mode (PSM)
operation. During Power Save Mode, the converter operates with reduced switching frequency and with a
minimum quiescent current maintaining high efficiency. The power save mode occurs when the inductor current
becomes discontinuous. Power Save Mode is based on a fixed on-time architecture, as related in 方程式 1. The
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switching frequency over the whole load current range is also shown in Switching Frequency for a typical
application.
VOUT
t ON = 420 ns´
VIN
2´IOUT
fPSM
=
VIN
V
IN - VOUT
2
t ON
´
´
VOUT
L
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage, as shown in Load
Regulation. This effect is minimized by increasing the output capacitor or inductor value. The output voltage
accuracy in PSM operation is reflected in the electrical specification table and given for a 22-μF output
capacitor.
During PAUSE period in PSM (shown in 图 8-1 ), the device does not change the PG pin state nor does it detect
an UVLO event, in order to achieve a minimum quiescent current and maintain high efficiency at light loads.
VOUT
tPAUSE
IINDUCTOR
tON
图8-1. Power Save Mode Waveform Diagram
8.3.2 100% Duty Cycle Low Dropout Operation
The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
V
= VOUT + IOUT,MAX ´(RDS(on) + RL )
IN,MIN
(2)
with
• VIN,MIN = Minimum input voltage to maintain an output voltage
• IOUT,MAX = Maximum output current
• RDS(on) = High-side FET ON-resistance
• RL = Inductor ohmic resistance (DCR)
8.3.3 Soft Start
The TPS62085, TPS62086, and TPS62087 have an internal soft-start circuitry which monotonically ramps up the
output voltage and reaches the nominal output voltage during a soft-start time of typically 0.8 ms. This avoids
excessive inrush current and creates a smooth output voltage slope. It also prevents excessive voltage drops of
primary cells and rechargeable batteries with high internal impedance. The device is able to start into a
prebiased output capacitor. The device starts with the applied bias voltage and ramps the output voltage to its
nominal value.
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8.3.4 Switch Current Limit and Hiccup Short-Circuit Protection
The switch current limit prevents the devices from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET is turned on to ramp down the inductor current. When this switch current
limits is triggered 32 times, the devices stop switching and enable the output discharge. The devices then
automatically start a new start-up after a typical delay time of 66 µs has passed. This is named HICCUP short-
circuit protection. The devices repeat this mode until the high load condition disappears.
8.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the devices at voltages lower than VUVLO with a hysteresis of 200 mV.
8.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8.4 Device Functional Modes
8.4.1 Enable and Disable
The devices are enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN
pin is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 260 Ωdischarges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, UVLO, or short-circuit protection are triggered.
An internal pulldown resistor of 400 kΩ is connected to the EN pin when the EN pin is LOW. The pulldown
resistor is disconnected when the EN pin is HIGH.
8.4.2 Power Good
The TPS62085, TPS62086, and TPS62087 have a power good output. The power good goes high impedance
once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below
typically 90% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The
power good output requires a pullup resistor connecting to any voltage rail less than 6 V. The PG signal can be
used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin
unconnected when not used. 表8-1 shows the PG pin logic.
表8-1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
LOW
EN = High, VFB ≥VPG
EN = High, VFB < VPG
EN = Low
√
Enable
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
TJ > TJSD
0.5 V < VIN < VUVLO
Power Supply
Removal
VIN ≤0.5 V
√
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS62085 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using typical applications as a reference. The TPS62086
and TPS62087 devices provide a fixed output voltage which does not need an external resistor divider.
9.2 Typical Application
L1
0.47µH
TPS62085
VIN
VOUT
VIN
EN
SW
VOS
FB
2.5V to 6V
1.2V/3A
C1
10µF
C2
22µF
R1
R3
80.6k 1M
R2
162k
GND
PG
POWER GOOD
图9-1. 1.2-V Output Voltage Application
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 as the input parameters.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
2.5 V to 6 V
1.2 V
Output voltage
Output ripple voltage
Maximum output current
<20 mV
3 A
表9-2 lists the components used for the example.
表9-2. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
C2
L1
10 µF, Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BR71A106ME51L
22 µF, Ceramic capacitor, 6.3 V, X5R, size 0805, GRM21BR60J226ME39L
0.47 µH, Power Inductor, size 4 mm × 4 mm × 1.5 mm, XFL4015-471ME
Murata
Murata
Coilcraft
Std
R1
R2
R3
Depending on the output voltage, 1%, size 0603; 0 Ωfor TPS62086, TPS62087
162 kΩ, Chip resistor, 1/16 W, 1%, size 0603; open for TPS62086, TPS62087
1 MΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
Std
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62085 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS62086 device with the WEBENCH® Power Designer.
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Click here to create a custom design using the TPS62087 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to 方程式3:
R1
R2
R1
R2
æ
ö
æ
ö
VOUT = VFB ´ 1+
= 0.8 V ´ 1+
ç
÷
ç
÷
è
ø
è
ø
(3)
R2 must not be higher than 180 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity. Lowest operating quiescent current and best output voltage accuracy are achieved with the fixed
output voltage versions. For the fixed output voltage versions, the FB pin must be connected to the output.
9.2.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, 表 9-3
outlines possible inductor and capacitor value combinations for most applications.
表9-3. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
10
22
47
+
100
+
150
+
(1)
0.47
1
+
+
+
+
+
+
2.2
(1) Typical application configuration. Other '+' mark indicates recommended filter combinations.
(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20%
and
–30%.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary
by 20% and –50%.
9.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, 方程式4 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
(4)
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where
• IOUT,MAX = Maximum output current
• ΔIL = Inductor current ripple
• fSW = Switching frequency
• L = Inductor value
TI recommends choosing the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of 方程式
4. A higher inductor value is also useful to lower ripple current but increases the transient response time as well.
The following inductors are recommended to be used in designs.
表9-4. List of Recommended Inductors
DC RESISTANCE
[mΩtypical]
INDUCTANCE
[µH]
CURRENT RATING
[A]
DIMENSIONS
PART NUMBER
L × W × H [mm3]
0.47
0.47
1
6.6
6.7
5.1
4 × 4 × 1.5
3.2 × 2.5 × 1.2
4 × 4 × 2
7.6
23
Coilcraft XFL4015-471
Murata DFE322512F-R47N
Coilcraft XFL4020-102
10.8
9.2.2.5 Capacitor Selection
The input capacitor is the low-impedance energy source for the converters which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed
between VIN and GND as close as possible to those pins. For most applications, 10 μF is sufficient, though a
larger value reduces input current ripple.
The architecture of the TPS62085, TPS62086, and TPS62087 allows the use of tiny ceramic output capacitors
with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are
recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with
temperature, TI recommends using X7R or X5R dielectrics. The recommended typical output capacitor value is
22 μF; this capacitance can vary over a wide range as outline in the output filter selection table. Output
capacitors above 150 µF may be used with a reduced load current during startup to avoid triggering the short
circuit protection.
A feed-forward capacitor is not required for device proper operation.
9.2.3 Application Curves
VIN = 3.6 V, VOUT = 1.2 V, TA = 25°C, unless otherwise noted
表9-5. Table of Graphs
FIGURE
TPS62085, VOUT = 0.95 V
TPS62085, VOUT = 1.2 V
TPS62086, VOUT = 3.3 V
TPS62087, VOUT = 1.8 V
TPS62085
Efficiency
Efficiency
Efficiency
Efficiency
Efficiency
Line Regulation
Load Regulation
Line Regulation
Load Regulation
Switching Frequency
TPS62085
Switching Frequency TPS62085
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表9-5. Table of Graphs (continued)
FIGURE
PWM Operation,
Load = 3 A
TPS62085, PWM Operation (Load = 3 A)
TPS62085, PSM Operation (Load = 100 mA)
TPS62085, Load Sweep (Load = Open to 3 A)
TPS62085, Start-Up (Load = 0.47 Ω)
TPS62085, Start-Up (Load = Open)
PSM Operation, Load
= 100 mA
Load Sweep, Load =
Open to 3 A
Start-Up, Load = 0.47
Ω
Start-Up, Load =
Open
Shutdown, Load =
TPS62085, Shutdown (Load = 0.47 Ω)
0.47 Ω
Shutdown, Load =
Open
TPS62085, Shutdown (Load = Open)
Waveforms
Load Transient, Load
= 0.5 A to 3 A
TPS62085, Load Transient (Load = 0.5 A to 3 A)
TPS62085, Load Transient (Load = 50 mA to 3 A)
Load Transient, Load
= 50 mA to 3 A
Output Short-Circuit
Protection, Load =
0.47 Ω, Entry
TPS62085, Output Short-Circuit Protection (Load = 0.47 Ω, Entry)
TPS62085, Output Short-Circuit Protection (Load = 0.47 Ω, Recovery)
Output Short-Circuit
Protection, Load =
0.47 Ω, Recovery
Output Short-Circuit
Protection, Load =
0.47 Ω, HICCUP
Zoom In
TPS62085, Output Short-Circuit Protection (Load = 0.47 Ω, HICCUP Zoom In)
100
90
80
70
60
50
100
90
80
70
Vin = 2.5 V
Vin = 2.5 V
Vin = 3.3 V
Vin = 4.2 V
Vin = 5.0 V
Vin = 3.3 V
Vin = 4.2 V
Vin = 5.0 V
60
50
Vout = 0.95 V
0.001
Vout = 1.2 V
0.010
0.100
Iout (A)
1.000
0.001
0.010
0.100
Iout (A)
1.000
C001
C002
图9-2. Efficiency
图9-3. Efficiency
100
90
80
70
60
50
100
90
80
70
60
50
Vin = 2.5V
Vin = 3.3V
Vin = 4.2V
Vin = 5.0V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
Vout = 3.3 V
0.001
Vout = 1.8 V
0.010
0.100
Iout (A)
1.000
0.001
0.010
0.100
Iout (A)
1.000
C003
C004
图9-4. Efficiency
图9-5. Efficiency
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1.212
1.206
1.200
1.194
1.212
1.206
1.200
1.194
1.188
TA = -40 °C
TA = 25 °C
TA = 85 °C
TA = -40 °C
TA = 25 °C
TA = 85 °C
Vout = 1.2 V, Iout = 1 A
1.188
Vout = 1.2 V, Vin = 3.6 V
0.010
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.001
0.100
Iout (A)
1.000
C005
C006
Vin (V)
图9-6. Line Regulation
图9-7. Load Regulation
t -- 500ns/div
t -- 300ns/div
Vout (AC, 20mV/div)
Icoil (DC, 1A/div)
Vout (AC, 20mV/div)
Icoil (DC, 1A/div)
SW (DC, 5V/div)
SW (DC, 5V/div)
图9-8. PWM Operation, Load = 3 A
图9-9. PSM Operation, Load = 100 mA
t -- 200μs/div
t -- 200μs/div
Load (DC, 2A/div)
EN (DC, 5V/div)
Vout (AC, 50mV/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
图9-10. Load Sweep, Load = Open to 3 A
图9-11. Start-Up, Load = 0.47 Ω
t -- 200μs/div
t -- 5μs/div
EN (DC, 5V/div)
EN (DC, 5V/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 0.5A/div)
图9-12. Start-Up, Load = Open
图9-13. Shutdown, Load = 0.47 Ω
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t -- 5ms/div
t -- 2μs/div
EN (DC, 5V/div)
Load (DC, 2A/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.1V/div)
Icoil (DC, 0.5A/div)
Icoil (DC, 2A/div)
图9-14. Shutdown, Load = Open
图9-15. Load Transient, Load = 0.5 A to 3 A
t -- 3μs/div
t -- 200μs/div
Load (DC, 2A/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
Vout (DC, 0.1V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
图9-16. Load Transient, Load = 50 mA to 3 A
图9-17. Output Short-Circuit Protection, Load =
0.47 Ω, Entry
t -- 200μs/div
t -- 5μs/div
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
图9-18. Output Short-Circuit Protection, Load =
0.47 Ω, Recovery
图9-19. Output Short-Circuit Protection, Load =
0.47 Ω, HICCUP Zoom In
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.5 V to 6 V. Ensure that the input
power supply has a sufficient current rating for the application.
11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TPS62085,
TPS62086, and TPS62087 devices.
The input and output capacitors and the inductor must be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
The low side of the input and output capacitors must be connected directly to the GND pin to avoid a ground
potential shift. The sense traces connected to FB and VOS pins are signal traces. Special care must be taken to
avoid noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be
used for shielding. Keep these traces away from SW nodes. See 图11-1 for the recommended PCB layout.
11.2 Layout Example
L1
VOUT
VIN
C1
C2
Solution Size
62 mm2
GND
R2
R1
图11-1. PCB Layout Recommendation
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
The Thermal Data section in the TPS62085EVM-169 Evaluation Module User's Guide (SLVU809) provides the
thermal metric of the device on the EVM after considering the PCB design of real applications. The big copper
planes connecting to the pads of the IC on the PCB improve the thermal performance of the device. For more
details on how to use the thermal parameters, see the Thermal Characteristics Application Notes, SZZA017 and
SPRA953.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62085 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS62086 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS62087 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• TPS62085EVM-169 Evaluation Module User's Guide, SLVU809
• Thermal Characteristics Application Note, SZZA017
• Thermal Characteristics Application Note, SPRA953
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
DCS-Control™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® are registered trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
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12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62085RLTR
TPS62085RLTT
TPS62086RLTR
TPS62086RLTT
TPS62087RLTR
TPS62087RLTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON-HR
VSON-HR
VSON-HR
VSON-HR
VSON-HR
VSON-HR
RLT
RLT
RLT
RLT
RLT
RLT
7
7
7
7
7
7
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
PD5Q
PD5Q
PD4Q
PD4Q
PD3Q
PD3Q
Samples
Samples
Samples
Samples
Samples
Samples
Call TI | SN
MATTE SN
MATTE SN
3000 RoHS & Green Call TI | MATTE SN
250 RoHS & Green Call TI | MATTE SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62085RLTR
TPS62085RLTR
TPS62085RLTT
TPS62085RLTT
TPS62086RLTR
TPS62086RLTT
TPS62087RLTR
TPS62087RLTT
VSON-
HR
RLT
RLT
RLT
RLT
RLT
RLT
RLT
RLT
7
7
7
7
7
7
7
7
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
VSON-
HR
VSON-
HR
VSON-
HR
250
VSON-
HR
3000
250
VSON-
HR
VSON-
HR
3000
250
VSON-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62085RLTR
TPS62085RLTR
TPS62085RLTT
TPS62085RLTT
TPS62086RLTR
TPS62086RLTT
TPS62087RLTR
TPS62087RLTT
VSON-HR
VSON-HR
VSON-HR
VSON-HR
VSON-HR
VSON-HR
VSON-HR
VSON-HR
RLT
RLT
RLT
RLT
RLT
RLT
RLT
RLT
7
7
7
7
7
7
7
7
3000
3000
250
210.0
182.0
182.0
210.0
182.0
182.0
182.0
182.0
185.0
182.0
182.0
185.0
182.0
182.0
182.0
182.0
35.0
20.0
20.0
35.0
20.0
20.0
20.0
20.0
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
1
PIN 1
INDEX AREA
2.1
1.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
0.5
0.3
3X
(0.2) TYP
(0.2) TYP
3X 0.5
2X 0.6
1.2
4
5
7
1.5
1
0.3
0.2
0.35
0.25
4X
3X
1.4
1.2
3X
0.1
C A
B
0.1
C A
B
0.05
C
PIN 1 ID
0.05
C
0.5
0.3
4220429/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
℄
(0.6)
1
(0.25)
7
2X (0.6)
PKG
℄
3X (0.5)
3X (0.25)
5
3X (0.3)
4
3X (1.5)
3X (0.6)
(0.9)
(0.45)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
PADS 1 - 4
PADS 5 - 7
SOLDER MASK DETAILS
4220429/A 09/2014
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
5. Vias should not be placed on soldering pads unless they are plugged or plated shut.
www.ti.com
EXAMPLE STENCIL DESIGN
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
℄
6X (0.65)
(0.6)
(0.21)
1
7
EXPOSED METAL
TYP
2X (0.6)
PKG
℄
3X (0.5)
METAL UNDER
SOLDER MASK
TYP
3X (0.21)
6X (0.3)
5
4
3X (0.025)
3X
EXPOSED METAL
3X (0.6)
SOLDER MASK EDGE
TYP
(0.9)
(0.875)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR ALL EXPOSED PADS
85% PRINTED SOLDER COVERAGE BY AREA
SCALE: 40X
4220429/A 09/2014
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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