TPS62095 [TI]
具有 DCS Control 的 4A 同步降压转换器;
| 型号： | TPS62095 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 DCS Control 的 4A 同步降压转换器 DCS 分布式控制系统 转换器 |
| 文件： | 总29页 (文件大小：1098K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
TPS62095 4A，高效降压转换器，具有 DCS-Control™ 功能和低截面解决
方案
1 特性
3 说明
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DCS-Control™ 拓扑技术
TPS62095 器件是一款高频同步降压转换器，此转换
器针对小解决方案尺寸、高效率进行了优化并适合于电
池供电类应用。 为了最大限度地提升效率，此转换器
以 1.4MHz 的标称开关频率运行在脉宽调制 (PWM) 模
式下并在轻负载电流时自动进入省电运行模式。 当被
用于分布式电源和负载点稳压时，此器件允许到其它电
压轨的电压跟踪并可耐受高达 150µF 甚至更高的输出
电容器。 通过使用 DCS-Control™ 技术，此器件可实
现出色的负载静态性能以及精确的输出电压调节。
与 TPS62090 引脚到引脚兼容
支持高度为 1.2mm 的总体解决方案
转换器效率 95%
20µA 运行静态电流
2.5V 至 5.5V 输入电压范围
省电模式
两级短路保护
100% 占空比，以实现最低压降
输出放电功能
输出电压启动斜坡由软启动引脚控制，从而允许作为独
立电源或者在跟踪配置下的运行。 通过配置 EN 和
PG 引脚还可实现电源排序。 在省电模式下，此器件
运行时的静态电流典型值为 20µA。 在整个负载电流范
围内，自动进入省电模式并且无缝保持高效率。
可调软启动
输出电压跟踪
0.8V 至 VIN 的可调输出电压
3mm x 3mm 16 引脚超薄四方扁平无引线 (VQFN)
封装
器件信息(1)
2 应用范围
产品型号
封装
封装尺寸（标称值）
TPS62095
VQFN (16)
3.00mm x 3.00mm
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笔记本、计算机
固态硬盘
机械硬盘
处理器电源
电池供电类应用
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
1.8V 输出应用
1.8V 输出应用效率
L1
TPS62095
1mH
Vin
Vout
1.8V/4A
12
11
1
100
2.5V to 5.5V
PVIN
SW
SW
R1
2
C1
22mF
C2
2x22mF
PVIN
200k
10
3
16
5
AVIN
DEF
EN
VOS
FB
90
80
R2
R3
500k
160k
13
4
C3
10nF
PG
SS
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
PGND PGND
14 15
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
0.01
0.1
1
5
Load (A)
D001
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSBD8
TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 11
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommend Operating Conditions........................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
10.3 Thermal Consideration.......................................... 18
11 器件和文档支持 ..................................................... 19
11.1 器件支持................................................................ 19
11.2 Trademarks........................................................... 19
11.3 Electrostatic Discharge Caution............................ 19
11.4 Glossary................................................................ 19
12 机械封装和可订购信息 .......................................... 19
7
4 修订历史记录
Changes from Original (April 2014) to Revision A
Page
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已更改 状态从产品预览更改为生产数据 - 已删除产品预览大字标题....................................................................................... 1
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Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
5 Pin Configuration and Functions
16-Pin VQFN with Thermal PAD
RGT
(Top View)
16 15 14 13
SW
SW
PVIN
PVIN
AVIN
SS
12
1
2
11
Exposed
Thermal Pad*
DEF
PG
10
9
3
4
5
6
7
8
Pin Functions
PIN
DESCRIPTION
NAME
NO.
SW
1, 2
Switch pin of the power stage.
This pin is used for internal logic and needs to be pulled high. This pin must be connected to the AVIN
pin.
DEF
PG
3
4
Power good open drain output. A pull up resistor can not be connected to any voltage higher than the
input voltage.
FB
5
6
7
8
Feedback pin, for regulating the output voltage.
AGND
CP
Analog ground.
Internal charge pump's flying capacitor. Connect a 10nF capacitor between CP and CN.
Internal charge pump's flying capacitor. Connect a 10nF capacitor between CP and CN.
CN
Soft-start control pin. A capacitor is connected to this pin and sets the soft startup time. Leaving this pin
floating sets the minimum start-up time.
SS
9
AVIN
10
11,12
13
Analog supply input voltage pin.
PVIN
Power supply input voltage pin.
EN
Enable pin. This pin has an active pull down resistor of typically 400kΩ.
Power ground.
PGND
VOS
14,15
16
Output voltage sense pin. This pin must be directly connected to the output voltage.
The exposed thermal pad must be connected to AGND.
Thermal Pad
Copyright © 2014, Texas Instruments Incorporated
3
TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
-0.3
-0.3
MAX
7.0
UNIT
Voltage at pins(2)
PVIN, AVIN, FB, SS, EN, DEF, VOS
V
SW, PG
PG
VIN+0.3
1.0
Sink current
mA
°C
Operating junction
temperature
-40
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
6.2 Handling Ratings
MIN
–65
0
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
0
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommend Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
MIN
MAX
5.5
UNIT
VIN
Input voltage range
2.5
V
V
VPG
VOUT
IOUT
TJ
Power good pull-up resistor voltage
Output voltage range
VIN
VIN
4.0
125
0.8
0
V
Output current range
A
Operating junction temperature
-40
°C
6.4 Thermal Information
THERMAL METRIC(1)
RGT (16 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47
60
RθJC(top)
RθJB
20
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
20
ψJB
RθJC(bot)
5.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
4
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
6.5 Electrical Characteristics
VIN = 3.6V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VIN
Input voltage range
Quiescent current
Shutdown current
2.5
5.5
V
µA
µA
V
IQIN
Not switching, No Load, Into PVIN and AVIN
Into PVIN and AVIN
20
0.6
2.2
200
150
20
Isd
5
Undervoltage lockout threshold VIN falling
Undervoltage lockout hysteresis
2.1
2.3
UVLO
mV
ºC
ºC
Thermal shutdown
Temperature rising
Thermal shutdown hysteresis
CONTROL SIGNAL EN
VH
VL
High level input voltage
VIN = 2.5 V to 5.5 V
VIN = 2.5 V to 5.5 V
EN = VIN
1
V
V
Low level input voltage
Input leakage current
Pull down resistance
0.4
Ilkg
RPD
10
100
nA
kΩ
EN = Low
400
SOFT STARTUP
ISS
Softstart current
6.3
7.5
8.7
µA
POWER GOOD
Output voltage rising
Output voltage falling
I(sink) = 1 mA
93%
88%
95%
90%
97%
92%
0.4
Vth
Power good threshold
VL
Low level voltage
Leakage current
V
Ilkg
VPG = 3.6 V
10
100
nA
POWER SWITCH
High side FET on-resistance
ISW = 500 mA
ISW = 500 mA
50
40
mΩ
mΩ
RDS(on)
Low side FET on-resistance
High side FET switch current
limit
ILIM
4.7
0.8
5.5
1.4
6.7
VIN
A
fSW
Switching frequency
IOUT = 3 A
MHz
OUTPUT
VOUT
RDIS
Output voltage range
V
Ω
V
Output discharge resistor
Feedback regulation voltage
EN = GND, VOUT = 1.8 V
200
0.8
IOUT = 1 A, PWM mode
-1.4%
-1.4%
-1.4%
+1.4%
+2.0%
+2.5%
100
VFB
(1)
Feedback voltage accuracy
IOUT = 1 mA, PFM mode, VOUT ≥ 1.8 V
IOUT = 1 mA, PFM mode, VOUT < 1.8 V
VFB = 0.8 V
IFB
Feedback input bias current
Line regulation
10
0.016
0.04
nA
VOUT = 1.8 V, PWM operation
VOUT = 1.8 V, PWM operation
%/V
%/A
Load regulation
(1) Conditions: L = 1 µH, COUT = 2 x 22 µF.
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TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
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6.6 Typical Characteristics
80
70
60
50
40
30
80
70
60
50
40
30
20
10
0
20
10
0
Tj = -40°C
Tj = 25°C
Tj = 85°C
Tj = 125°C
Tj = -40°C
Tj = 25°C
Tj = 85°C
Tj = 125°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
D003
D004
Figure 1. High Side FET On Resistance
Figure 2. Low Side FET On Resistance
1
0.8
0.6
0.4
0.2
0
30
20
10
0
Tj = -40°C
Tj = -40°C
Tj = 0°C
Tj = 25°C
Tj = 85°C
Tj = 0°C
Tj = 25°C
Tj = 85°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
D006
D005
Figure 4. Shutdown Current
Figure 3. Quiescent Current
6
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
7 Detailed Description
7.1 Overview
The TPS62095 synchronous step down converter is based on DCS-Control™ (Direct Control with Seamless
transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of
hysteretic and voltage mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM, the converter operates with its nominal
switching frequency of 1.4 MHz having a controlled frequency variation over the input voltage range. As the load
current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the
IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™ supports both
operation modes using a single building block and therefore has a seamless transition from PWM to Power Save
Mode without effects on the output voltage. The TPS62095 offers excellent DC voltage regulation and load
transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
PVIN PVIN
PG
CP
CN
Charge Pump
for
Gate driver
Hiccup
current limit
#32 counter
VFB
VREF
High Side
Current
Sense
Bandgap
Undervoltage
Lockout
AVIN
EN
Thermal shutdown
M1
SW
SW
400kΩ
MOSFET Driver
AGND
DEF
Anti Shoot Through
Converter Control
Logic
M2
PGND
PGND
VOS
ramp
Direct Control
and
Compensation
Comparator
Timer
ton
Error Amplifier
FB
Vref
0.8V
Vin
DCS - Control™
200Ω
Iss
Voltage clamp
Vref
÷1.56
SS
Output voltage
M3
EN
discharge
logic
Copyright © 2014, Texas Instruments Incorporated
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TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
7.3 Feature Description
7.3.1 PWM Operation
In PWM mode, the device operates with a fixed ON-time switching pulse at medium to heavy load currents. A
quasi fixed switching frequency of typical 1.4MHz over the input and output voltage range is achieved by using
an input feed forward. The ON-time is calculated as shown in Equation 2. As the load current decreases, the
converter enters Power Save Mode operation reducing its switching frequency. The device enters Power Save
Mode at the boundary to discontinuous conduction mode (DCM).
7.3.2 Low Dropout Operation (100% Duty Cycle)
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high
side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve
longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage
where the output voltage falls below set point is given by:
VIN(min) = VOUT(min) + IOUT x ( RDS(on) + RL )
(1)
Where
RDS(on) = High side FET on-resistance
RL = DC resistance of the inductor
VOUT(min) = Minimum output voltage the load can accept
7.3.3 Power Save Mode Operation
As the load current decreases, the converter enters Power Save Mode operation. During Power Save Mode, the
converter operates with reduced switching frequency and with a minimum quiescent current to maintain high
efficiency. The Power Save Mode is based on a fixed on-time architecture following Equation 2.
V
OUT
ton =
× 360ns × 2
V
IN
2 × I
OUT
f =
æ
ö
÷
V
IN
- V
OUT
V
IN
- V
ton2 1 +
x
OUT
ç
ç
÷
V
OUT
L
è
ø
(2)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage in PWM mode. This
effect is reduced by increasing the output capacitance or the inductor value. This effect is also reduced by
programming the output voltage of the TPS62095 lower than the target value. As an example, if the target output
voltage is 3.3V, then the TPS62095 can be programmed to 3.3V - 0.3%. As a result, the output voltage accuracy
is now -1.7% to +1.7% instead of -1.4% to 2%. The output voltage accuracy in PFM operation is reflected in the
electrical specification table and given for a 2 x 22µF output capacitance.
7.4 Device Functional Modes
7.4.1 Soft Startup
To minimize inrush current during startup, the device has an adjustable startup time depending on the capacitor
value connected to the SS pin. The device charges the SS capacitor with a constant current of typically 7.5µA.
The feedback voltage follows this voltage divided by 1.56, until the internal reference voltage of 0.8V is reached.
The soft startup operation is completed once the voltage at the SS capacitor has reached typically 1.25V. The
soft startup time is calculated using Equation 3. The larger the SS capacitor, the longer the soft startup time. The
relation between the SS pin voltage and the FB pin voltage is estimated using Equation 4. Leaving the SS pin
floating sets the minimum startup time.
1.25V
tSS = CSS
x
7.5μA
(3)
(4)
VSS
VFB
=
1.56
8
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
Device Functional Modes (continued)
During startup the switch current limit is reduced to 1/3 of its typical current limit of 5.5A when the output voltage
is less than 0.6V. Once the output voltage exceeds typically 0.6V, the switch current limit is released to its
nominal value. Thus, the device provides a reduced load current of 1.8A when the output voltage is below 0.6V.
A small or no soft startup time may trigger this reduced switch current limit during startup, especially for larger
output capacitor applications. This is avoided by using a larger soft start up capacitance which extends the soft
startup time. See Short Circuit Protection (Hiccup-Mode) for details of the reduced current limit during startup.
7.4.2 Voltage Tracking
The SS pin can also be used to implement output voltage tracking with other supply rails, as shown in Figure 5.
L1
1µH
TPS62095
VIN
2.5V to 5.5V
V2
1.8V/4A
12
11
1
PVIN
PVIN
SW
SW
R1
200k
2
C1
22µF
C2
2 x 22µF
10
3
16
5
AVIN
DEF
EN
VOS
R2
160k
FB
13
4
C3
10nF
PG
SS
7
8
9
CP
CN
6
AGND
PGND PGND
14 15
V1
Output of external
DC DC converter
R3
R4
Figure 5. Output Voltage Tracking
In voltage tracking applications, the resistance R4 should be set properly to achieve accurate voltage tracking by
taking 7.5μA soft startup current into account. 4.3kΩ is a sufficient value for R4. The relationship between V1 and
V2 is shown in Equation 5. To achieve V1 startup leading V2, as shown in Figure 6, Equation 5 should be less
than 1. To achieve simultaneous tracking, Equation 5 should equal to 1.
V2
1
R4
R1+ R2
= ´
V1 1.56 R3 + R4
´
R2
(5)
Voltage
Voltage
V1 = 3.3V
V1 = 3.3V
V2 = 1.8V
V2 = 1.8V
R1
R2
R3
R4
R1
R2
R3
R4
æ
ç
è
ö
æ
ç
è
ö
æ
ç
è
ö
æ
ç
è
ö
+1 < 1.56´
+1
+1 = 1.56´
+1
÷
÷
÷
÷
ø
ø
ø
ø
t
t
a) V1 startup leading V2
b) Simultaneous tracking
Figure 6. Voltage Tracking Applications
Copyright © 2014, Texas Instruments Incorporated
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TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
Device Functional Modes (continued)
7.4.3 Short Circuit Protection (Hiccup-Mode)
The device is protected against hard short circuits to GND and over-current events. This is implemented by a two
level short circuit protection. During start-up and when the output is shorted to GND, the switch current limit is
reduced to 1/3 of its typical current limit of 5.5A. Once the output voltage exceeds typically 0.6V the current limit
is released to its nominal value. The full current limit is implemented as a hiccup current limit. Once the internal
current limit is triggered 32 times, the device stops switching and starts a new start-up sequence after a typical
delay time of 66µS passed by. The device repeats these cycles until the high current condition is released.
7.4.4 Output Discharge Function
To make sure the device starts up under defined conditions, the output gets discharged via the VOS pin with a
typical discharge resistor of 200Ω whenever the device shuts down. This happens when the device is disabled or
if thermal shutdown, undervoltage lockout or short circuit hiccup-mode is triggered.
7.4.5 Power Good Output
The power good output is low when the output voltage is below its nominal value. The power good becomes high
impedance once the output is within 5% of regulation. The PG pin is an open drain output and is specified to sink
up to 1mA. This output requires a pull-up resistor to be monitored properly. The pull-up resistor cannot be
connected to any voltage higher than the input voltage of the device.
7.4.6 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts
down the device at input voltages lower than typically 2.2V with a 200mV hysteresis.
7.4.7 Thermal Shutdown
The device goes into thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C
hysteresis.
10
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
8 Application and Implementation
8.1 Application Information
The TPS62095 is a synchronous step down converter based on DCS-Control™ topology whose output voltage
can be adjusted by component selection. The following section discusses the design of the external components
to complete the power supply design for several input and output voltage options by using typical applications as
a reference.
8.2 Typical Applications
8.2.1 2.5V to 5.5V Input, 1.8V Output Converter
L1
TPS62095
1mH
Vin
2.5V to 5.5V
Vout
1.8V/4A
12
11
1
PVIN
PVIN
SW
SW
R1
2
C1
22mF
C2
2x22mF
200k
10
3
16
5
AVIN
DEF
EN
VOS
FB
R2
R3
500k
160k
13
4
C3
10nF
PG
SS
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
PGND PGND
14 15
Figure 7. 1.8-V Output Application
8.2.1.1 Design Requirements
For this design example, use the following as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2.5V to 5.5V
1.8V
Output voltage
Output ripple voltage
Output current rating
<20mV
4A
Copyright © 2014, Texas Instruments Incorporated
11
TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Filter
The first step is the selection of the output filter components. To simplify this process, Table 2 outlines possible
inductor and capacitor value combinations.
Table 2. Output Filter Selection
OUTPUT CAPACITOR VALUE [µF](2)
INDUCTOR VALUE [µH](1)
10
22
2 x 22
100
√
150
√
0.47
1.0
√
(3)
√
√
√
2.2
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and
–30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
+20% and –50%.
(3) Typical application configuration. Other check mark indicates alternative filter combinations
8.2.1.2.2 Inductor Selection
The inductor selection is affected by several parameters like inductor ripple current, output voltage ripple,
transition point into Power Save Mode, and efficiency. See Table 3 for typical inductors.
Table 3. Inductor Selection(1)
INDUCTOR VALUE
1 µH
COMPONENT SUPPLIER
Coilcraft XAL4020-102
TOKO DFE322512C
SIZE (LxWxH mm)
4.0 x 4.0 x 2.1
Isat / DCR
8.75A / 13.2 mΩ
5.9A / 21 mΩ
0.47 µH
3.2 x 2.5 x 1.2
(1) See Third-Party Products Disclaimer.
In addition, the inductor has to be rated for the appropriate saturation current and DC resistance (DCR). The
inductor needs to be rated for a saturation current as high as the typical switch current limit of 5.5A or according
to Equation 6 and Equation 7. Equation 6 and Equation 7 calculate the maximum inductor current under static
load conditions. The formula takes the converter efficiency into account. The converter efficiency can be taken
from the data sheet graphs or 80% can be used as a conservative approach. The calculation must be done for
the maximum input voltage where the peak switch current is highest.
ΔI
L
I
L
= I
OUT
+
2
(6)
æ
ç
ç
è
ö
÷
÷
ø
V
V
OUT
η
OUT
x η
x
1 -
V
IN
I
= I
OUT
+
L
2 x f x L
(7)
where
ƒ = Converter switching frequency (typically 1.4MHz)
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as a conservative
assumption)
Note: The calculation must be done for the maximum input voltage of the application
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current. A margin of 20% should be added to cover for load transients during operation.
12
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
8.2.1.2.3 Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR ceramic capacitors are recommended. The input capacitor
minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device.
A 22µF or larger input capacitor is required. The output capacitor value can range from 2x22µF up to 150µF. The
recommended typical output capacitor value is 2x22µF and can vary over a wide range as outline in the output
filter selection table.
8.2.1.2.4 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
R1
R1
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
R2
R2
è
ø
è
ø
(8)
(9)
VFB
0.8 V
5 μA
R2 =
=
» 160 kΩ
IFB
æ
ç
è
ö
VOUT
VFB
V
OUT
æ
ö
R1 = R2 ´
-1 = R2 ´
- 1
÷
÷
ç
0.8V
è
ø
ø
(10)
When sizing R2, in order to achieve low quiescent current and acceptable noise sensitivity, use a minimum of
5µA for the feedback current IFB. Larger currents through R2 improve noise sensitivity and output voltage
accuracy.
Copyright © 2014, Texas Instruments Incorporated
13
TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
8.2.1.3 Application Performance Curves
TA = 25°C, VIN = 3.6V, VOUT = 1.8V, L1 = 1µH (XAL4020-102), C2 = 2x22µF, unless otherwise noted.
0.5
0.4
0.3
0.2
0.1
0
100
90
80
-0.1
-0.2
-0.3
-0.4
-0.5
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
TA = ꢀ40qC
TA = 25qC
TA = 85qC
60
0.001
0.001
0.01
0.1
1
5
0.01
0.1
1
5
Load (A)
Load (A)
D002
D001
Figure 9. Load Regulation, VOUT = 1.8V, VIN = 3.3V
Figure 8. Efficiency, VOUT = 1.8V
0.5
0.4
0.3
0.2
0.1
0
5000
1000
100
10
1
-0.1
-0.2
-0.3
-0.4
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
VIN = 2.5 V
VIN = 3.6 V
VIN = 5.5 V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
D007
0.001
0.01
0.1
1
5
Load (A)
D008
Figure 10. Line Regulation, VOUT = 1.8V, IOUT = 1.0A
Figure 11. Switching Frequency, VOUT = 1.8V
SW = 5V/div
SW = 5V/div
VOUT = 20 mV/div, AC
ICOIL = 0.5 A/div
Time = 1 µs/div
VOUT = 20mV/div, AC
ICOIL = 1A/div
Time = 0.5 µs/div
Figure 12. Output Ripple, VOUT = 1.8V, IOUT = 100mA
Figure 13. Output Ripple, VOUT = 1.8V, IOUT = 3.5A
14
Copyright © 2014, Texas Instruments Incorporated
TPS62095
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ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
EN = 5V/div
VIN = 2V/div
VIN = 2V/div
VOUT = 1V/div
VOUT = 1V/div
ICOIL = 0.5A/div
ICOIL = 0.5A/div
Time = 500 µs/div
Time = 500 µs/div
Figure 14. Startup, Relative to VIN, RLOAD = 1.5Ω
Figure 15. Startup, Relative to EN, RLOAD = 1.5Ω
LOAD = 2A/div
LOAD = 2A/div
0.1A to 2A load step
1A to 3.5A load step
VOUT = 0.1V/div, AC
ICOIL = 2A/div
VOUT = 0.1V/div, AC
ICOIL = 2A/div
Time = 10 µs/div
Time = 10 µs/div
Figure 16. Load Transient, VOUT = 1.8V
Figure 17. Load Transient, VOUT = 1.8V
VOUT = 1V/div
VOUT = 1V/div
ICOIL = 2A/div
ICOIL = 2A/div
Time = 250 µs/div
Time = 250 µs/div
Figure 18. Short Circuit, HICCUP Protection Entry
Figure 19. Short Circuit, HICCUP Protection Exit
Copyright © 2014, Texas Instruments Incorporated
15
TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
8.2.2 2.5V to 5.5V Input, 1.2V Output Converter
L1
TPS62095
100
90
1mH
Vin
Vout
1.2V/4A
12
11
1
2.5V to 5.5V
PVIN
PVIN
SW
SW
R1
2
C1
22mF
C2
2x22mF
80k
10
3
16
5
AVIN
DEF
EN
VOS
FB
R2
R3
500k
160k
13
4
C3
10nF
PG
SS
80
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
PGND PGND
14 15
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
0.01
0.1
1
5
Load (A)
D017
Figure 20. 1.2V Output Application
Figure 21. 1.2V Output Application Efficiency
8.2.3 3.0V to 5.5V Input, 2.6V Output Converter
L1
TPS62095
100
90
1mH
Vin
Vout
2.6V/4A
12
11
1
3.0V to 5.5V
PVIN
PVIN
SW
SW
R1
2
C1
22mF
C2
2x22mF
360k
10
3
16
5
AVIN
DEF
EN
VOS
FB
R2
R3
500k
160k
13
4
C3
10nF
PG
SS
80
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
PGND PGND
14 15
70
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
0.01
0.1
1
5
Load (A)
D018
Figure 22. 2.6V Output Application
Figure 23. 2.6V Output Application Efficiency
8.2.4 5V Input, 3.3V Output Converter
L1
TPS62095
100
90
1mH
Vin
Vout
3.3V/4A
12
11
1
5.0V
PVIN
PVIN
SW
SW
R1
2
C1
22mF
C2
500k
2x22mF
10
3
16
5
AVIN
DEF
EN
VOS
FB
R2
R3
160k
500k
13
4
C3
10nF
PG
SS
80
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
70
PGND PGND
14 15
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
0.01
0.1
1
5
Load (A)
D019
Figure 24. 3.3V Output Application
Figure 25. 3.3V Output Application Efficiency
16
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.5V and 5.5V. If the input
supply is located more than a few inches from the device, an additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 47µF is a typical choice.
The average input current of the TPS62095 is calculated as:
VOUT ´IOUT
1
IIN
=
´
h
V
IN
(11)
10 Layout
10.1 Layout Guidelines
•
•
•
•
It is recommended to place all components as close as possible to the IC. Specially, the input capacitor
placement is closest to the PVIN and PGND pins of the device.
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance, like
the SW node.
The VOS pin is noise sensitive and needs to be routed as short and directly to the output pin of the inductor
and the output capacitor. This minimizes switch node jitter.
The exposed thermal pad of the package, the AGND and the PGND should have a single joint connection at
the exposed thermal pad of the package. To enhance heat dissipation of the device, the exposed thermal pad
should be connected to bottom or internal layer ground planes using vias.
•
•
•
The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of
switching waveforms into other traces and circuits.
The capacitor on the SS pin and the FB resistors divider network should be placed close to the IC and
connected directly to those pins and the AGND pin.
Refer to Figure 26 for an example of component placement, routing and thermal design.
10.2 Layout Example
VOUT
PGND
SW
SW
DEF
PG
PVIN
PVIN
AVIN
SS
VIN
Figure 26. TPS62095 PCB Layout
Copyright © 2014, Texas Instruments Incorporated
17
TPS62095
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
10.3 Thermal Consideration
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component. The Thermal Information table provides the thermal metric of the device
and its package based on JEDEC standard. For more details on how to use the thermal parameters in real
applications, see the application notes: SZZA017 and SPRA953.
18
Copyright © 2014, Texas Instruments Incorporated
TPS62095
www.ti.com.cn
ZHCSBQ2A –APRIL 2014–REVISED MAY 2014
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 Trademarks
DCS-Control is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
Copyright © 2014, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
15-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62095RGTR
TPS62095RGTT
ACTIVE
ACTIVE
VQFN
VQFN
RGT
RGT
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
SMC
SMC
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Aug-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62095RGTR
TPS62095RGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62095RGTR
TPS62095RGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
552.0
552.0
346.0
185.0
36.0
36.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS62095RGTR
TPS62095RGTT
RGT
RGT
VQFN
VQFN
16
16
3000
250
381
381
4.83
4.83
2286
2286
0
0
Pack Materials-Page 3
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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