TPS62134DRGTR [TI]
适用于 Intel SkyLake 平台且具有低功耗模式输入的 17V 输入降压转换器 | RGT | 16 | -40 to 85;
| 型号： | TPS62134DRGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 Intel SkyLake 平台且具有低功耗模式输入的 17V 输入降压转换器 | RGT | 16 | -40 to 85 开关 输出元件 转换器 |
| 文件： | 总28页 (文件大小：1126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
TPS62134x 适用于 Intel Skylake 平台且具有低功耗模式输入的 17V 输入
降压转换器
1 特性
3 说明
1
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DCS-Control™ 架构
TPS62134x 系列器件是一款易于使用的同步降压 DC-
DC 转换器，可兼容 Intel Skylake 平台应用，诸如 超
级本™ 和笔记本电脑。 高性能 DCS-Control™ 架构可
提供快速瞬态响应以及高精度输出电压。
支持系统待机模式的低功耗模式
用于在轻载时实现高效率的省电模式
固定输出电压可选择（0.7V 至 1.05V）
低功耗模式逻辑输入
静态电流为 20µA
借助其 3 至 17V 宽运行输入电压范围，此器件非常适
用于由锂离子电池或者其它电池以及由 12V 中间电源
轨供电的系统。 器件具有低功耗模式，在该模式下器
件可通过 LPM 引脚降低输出电压。 此外，器件还可通
过 VIDx 引脚支持输出电压的动态变化。 LPM 和 VIDx
引脚可帮助系统在不同工作模式下最大限度地降低功
耗。
输入电压范围：3V 至 17V
输出电流：高达 3.2A
可编程软启动
电源正常输出
短路保护
单端遥感
输出电压启动斜坡由 SS 引脚控制。 电源排序可通过
使能 (EN) 引脚和电源正常 (PG) 引脚配置。 省电模式
下，器件所示静态电流约为 20μA，该电流可在整个负
载范围内保持高效率。 短路保护和热关断功能可保护
集成电路 (IC) 和外部元件，使其不受输出接地短路时
产生的强大电流的影响。 该器件采用 3mm × 3mm 16
引脚超薄四方扁平无引线封装 (VQFN) 封装，且带有
散热焊盘。
热关断保护
采用 3mm x 3mm 超薄型四方扁平无引线 (VQFN)-
16 封装
2 应用
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Intel Skylake™ 平台超级本、笔记本电脑和 PC
标准 12V 导轨式电源
负载点 (POL) 由 1 至 4 节锂离子电池供电
固态硬盘驱动器
器件信息(1)
嵌入式系统
器件型号
TPS62134A
封装
封装尺寸（标称值）
TPS62134B
TPS62134C
TPS62134D
VQFN
3.00mm x 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
4 典型应用电路
L1
1 µH
TPS62134A
VO
0.95 V, 3 A
TPS62134A 效率
VI
3 to 17 V
PVIN
AVIN
EN
SW
VOS
FBS
C1
22 µF
C2
47 µF
100
VDD
90
80
70
VID0
VID1
LPM
R3
499 kΩ
Host
V(PG)
PG
SS
AGND
PGND
C3
470 pF
VI = 5 V
VI = 6 V
60
VI = 7.2 V
VI = 8.4 V
VI = 10.8 V
VI = 12 V
50
VO = 0.95 V
40
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2 3 45
D002
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSC20
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
目录
9.3 Feature Description................................................... 8
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ................................................ 11
11 Power Supply Recommendations ..................... 15
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
12.3 Thermal Considerations........................................ 17
13 器件和文档支持 ..................................................... 18
13.1 器件支持................................................................ 18
13.2 文档支持................................................................ 18
13.3 相关链接................................................................ 18
13.4 商标....................................................................... 18
13.5 静电放电警告......................................................... 18
13.6 术语表 ................................................................... 18
14 机械封装和可订购信息 .......................................... 18
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
典型应用电路 ........................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
8.1 Absolute Maximum Ratings ..................................... 4
8.2 ESD Ratings.............................................................. 4
8.3 Recommend Operating Conditions........................... 4
8.4 Thermal Information.................................................. 4
8.5 Electrical Characteristic............................................. 5
8.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
9.1 Overview ................................................................... 7
9.2 Functional Block Diagram ......................................... 7
9
5 修订历史记录
Changes from Revision B (August 2014) to Revision C
Page
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更改了器件信息表................................................................................................................................................................... 1
Added the Device Comparison Table .................................................................................................................................... 3
Moved the Storage temperature From the Handling Ratings table to the Absolute Maximum Ratings(1) table..................... 4
Changed the Handling Ratings table to the ESD Ratings table............................................................................................. 4
Changed the Output voltage accuracy, PSM mode MAX value From: 2% To: 3%, Add test condition: LPM = High. .......... 5
Changes from Revision A (August 2014) to Revision B
Page
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•
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Add new device to Device Comparison Table ....................................................................................................................... 3
Updated the Functional Block Diagram image....................................................................................................................... 7
Add new device to 表 1 .......................................................................................................................................................... 9
Updated the 图 15 in the Application Curves section........................................................................................................... 14
Updated 公式 7 .................................................................................................................................................................... 15
Changes from Original (August 2014) to Revision A
Page
•
Switched the pin names of pin 8 and 9 in the Pin Functions table ........................................................................................ 3
2
Copyright © 2015, Texas Instruments Incorporated
TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
6 Device Comparison Table
PART NUMBER
PACKAGE MARKING
OUTPUT VOLTAGE
TPS62134A
TPS62134B
TPS62134C
TPS62134D
134A
134B
134C
134D
See 表 1
7 Pin Configuration and Functions
RGT Package
16-Pin VQFN With Thermal Pad
Top View
4
3
2
1
FBS
5
6
16 PGND
15 PGND
AGND
Exposed
Thermal PAD
SS
7
8
14
LPM
VID1
13 EN
9
10 11 12
Pin Functions
PIN
NAME
TYPE
I
DESCRIPTION
NO.
Output voltage sense pin and connection for the control loop circuitry. The VOS pin must be connected
directly at the output capacitor.
1
VOS
SW
2
3
This pin is a switch node and is connected to the internal MOSFET switches. Connect an inductor
between the SW pin and output capacitor.
PWR
Output power-good pin. The PG pin is an open drain and requires a pullup resistor. If this pin is not in use,
leave it floating.
4
5
6
PG
FBS
O
I
Output-voltage feedback pin. This pin is used for a positive remote sense of the load voltage. The FBS pin
must be connected close to the load-supply node on the output bus.
Analog ground pin. The AGND pin must be connected directly to the exposed thermal pad and common
ground plane.
AGND
—
O
7
8
9
SS
Soft-start pin. An external capacitor connected to this pin sets the soft-start time.
VID1
VID0
I
I
Output-voltage selection pins (VIDx).
Supply-voltage pin for the internal control circuitry. Connect the AVIN pin to the same source as the PVIN
pin.
10
AVIN
PVIN
11
12
13
14
15
16
—
PWR
Supply-voltage pins for the internal power stage.
EN
I
I
Enable and disable input pin. An internal pulldown resistor maintains logic-level low if the pin is floating.
Low-power-mode input pin.
LPM
Power ground. The PGND pin must be connected directly to the exposed thermal pad and common
ground plane.
PGND
—
—
Exposed
Thermal
Pad
The exposed thermal pad must be connected to the AGND (6) pin, PGND (15 and 16) pins, and common
ground plane. The thermal pad must be soldered to achieve appropriate power dissipation and
mechanical reliability.
Copyright © 2015, Texas Instruments Incorporated
3
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings(1)
over operating junction temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
AVIN, PVIN
20
EN, SW
Voltage at pins(2)
VI + 0.3
V
SS, PG, VOS, VID0, VID1, LPM
7
3
FBS
Sink current
PG
2
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
8.2 ESD Ratings
VALUE
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS–001
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommend Operating Conditions
over operating junction temperature range, unless otherwise noted.
MIN
MAX
17
UNIT
V
VI
Input voltage (AVIN, PVIN)
PG pin pullup resistor voltage
3
0
V(PG)
6
V
3 V ≤ VI < 5 V
5 V ≤ VI ≤ 17 V
0
3
IO
Output current
A
0
3.2
125
TJ
Operating junction temperature
–40
°C
8.4 Thermal Information
TPS62134x
RGT Package
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.2
51.0
16.6
0.9
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
16.6
3.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
4
Copyright © 2015, Texas Instruments Incorporated
TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
8.5 Electrical Characteristic
TJ = –40 °C to 125 °C and VI = 3 V to 17 V. Typical values at VI = 12 V and TJ = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
VI
Input voltage range
3
17
35
58
9
V
EN = High, no load, device not switching
TJ = –40 °C to 85 °C
20
2
IQ
Operating quiescent current
µA
TJ = 125 °C
EN = Low
TJ = –40 °C to +85 °C
ISD
Shutdown current into AVIN and PVIN
Undervoltage lockout threshold
µA
TJ = 125 °C
VI falling
VI rising
18
2.8
3
2.6
2.8
2.7
2.9
160
20
V(UVLO)
V
TSD(th)
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
TJ falling
°C
TSD(hys)
CONTROL (EN, SS, PG, VIDx, LPM)
High-level input threshold voltage (EN,
VIDx, LPM)
VIH
VIL
0.8
0.54
0.47
V
V
Low-level input threshold voltage (EN,
VIDx, LPM)
0.3
1
R(PD)
R(DIS)
Ilkg
Pull down resistor at EN, VIDx, LPM
Output discharge resistor
EN, VIDx, LPM = low
EN = Low, VO = 1 V
EN, VIDx, LPM = 3.3 V
VO rising
400
20
kΩ
kΩ
µA
Input leakage current at EN, VIDx, LPM
0.01
736
696
760 784
720 752
VTH(PG)
Power good threshold DC voltage
mV
VO falling
VOL(PG)
Ilkg(PG)
Power good output low voltage
Input leakage current at PG
I(PG) = –2 mA
V(PG) = 1.8 V
PG rising
0.07
1
0.3
V
400
nA
140
20
td(PG)
I(SS)
Power good delay time
SS pin source current
µs
PG falling
2.3
3.6
2.5
2.7
µA
POWER SWITCH
rDS(on_H)
rDS(on_L)
IL
High-side MOSFET on-resistance
VI ≥ 6 V
90 170
mΩ
Low-side MOSFET on-resistance
High-side MOSFET DC current-limit
VI ≥ 6 V
40
70
VI ≥ 5 V, TJ = 25 °C
4.4
5.4
A
High-side MOSFET DC current-limit at low
output voltage
VO ≤ 0.3 V
IL(LOW)
1.6
OUTPUT
Ilkg(FBS)
Input leakage current at FBS
Output voltage accuracy
V(FBS)= 1.1 V
1
100
1%
3%
nA
PWM mode
–1%
–1%
VO(A)
PSM mode, LPM = High(1)
VI = 7.2 V, IO = 0.5 A to 3.2 A
3 V ≤ VI ≤ 17 V, IO = 1 A
ΔVO(ΔIO)
ΔVO(ΔVI)
Load regulation(2)
Line regulation(2)
0.01
%/A
%/V
0.003
(1) This is the accuracy provided by the device itself (line and load regulation effects are not included). External components effective value:
L = 1 µH and C(OUT) = 47 µF.
(2) Line and load regulation depend on external component selection and layout.
版权 © 2015, Texas Instruments Incorporated
5
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
8.6 Typical Characteristics
40
10
8
TJ = ꢀ40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
30
6
20
4
TJ = ꢀ40qC
10
TJ = 0qC
2
TJ = 25qC
TJ = 85qC
TJ = 125qC
0
0
3
5
7
9
11
13
15
17
3
5
7
9
11
13
15
17
Input Voltage (V)
Input Voltage (V)
D005
D006
图 1. Quiescent Current into PVIN and AVIN
图 2. Shutdown Current into PVIN and AVIN
6
版权 © 2015, Texas Instruments Incorporated
TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
9 Detailed Description
9.1 Overview
The TPS62134x synchronous switched-mode power converters are based on DCS-Control™ (direct control with
seamless transition into power-save mode), an advanced regulation topology that combines the advantages of
hysteretic, voltage-mode, and current-mode control including an AC loop that is directly associated to the output
voltage. This control loop uses information about output voltage changes and feeds the information directly to a
fast comparator stage. The control loop provides immediate response to dynamic load changes. For accurate DC
load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast
and stable operation with small external components and low ESR capacitors.
The DCS-Control™ topology supports PWM (pulse width modulation) mode for medium and heavy load
conditions and a power-save mode (PSM) at light loads. During PWM mode, the devices operate at the nominal
switching frequency in continuous conduction mode (CCM). This frequency is approximately 1 MHz (typical) with
a controlled frequency variation depending on the input voltage. If the load current decreases, the converter
enters PSM to sustain high efficiency down to very light loads. In PSM, the switching frequency decreases
linearly with the load current. Because DCS-Control™ supports both operation modes within one single building
block, the transition from PWM to PSM is seamless without effects on the output voltage.
9.2 Functional Block Diagram
AVIN
PVIN
PVIN
PG
Thermal
FBS
PG Control
UVLO
shutdown
High-side
limit
Comparator
EN
Control logic
SW
LPM
VID0
Power control
Gate drive
Reference voltage
control logic
V
ref
VID1
SS
SW
Soft
start
Comparator
Low-side
limit
Direct control
and
compensation
VOS
FBS
Ramp
R
(DIS)
t
on
Comparator
Error
amplifier
+
V
ref
Output
discharge
DCS-Control
EN
AGND
PGND PGND
版权 © 2015, Texas Instruments Incorporated
7
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
9.3 Feature Description
9.3.1 Enable and Shutdown (EN)
When the EN pin is set high, the device begins operation. The EN pin allows sequencing from a host or power-
good output of another device.
The devices enter shutdown mode if the EN pin is pulled low with a shutdown current of 2 µA (typical). During
shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off. The output capacitor
is smoothly discharged by a 20-kΩ internal resistor through the VOS pin. An internal pulldown resistor of
approximately 400 kΩ is connected and maintains EN logic low, if the pin is floating. The pulldown resistor is
disconnected if the EN pin is high.
9.3.2 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both
power MOSFETs. The UVLO threshold is set to 2.7 V (typical). The device is fully operational for voltages above
the UVLO threshold and turns off if the input voltage trips the threshold. The converter begins operation again
when the input voltage exceeds the threshold by a hysteresis of 200 mV (typical).
9.3.3 Soft-Start (SS) Circuitry
The internal soft-start circuitry controls the output-voltage slope during startup. This control avoids excessive
inrush current and ensures a controlled output-voltage rise time. The control also prevents unwanted voltage
drops from high-impedance power sources or batteries. When the EN pin is set high to begin device operation,
the device begins switching after a delay of approximately 50 µs and VO rises up to the nominal value set by the
VIDx pins with a slope controlled by an external capacitor connected to the SS pin. Leave the SS pin floating for
the fastest startup.
The device can startup into a pre-biased output. During monotonic pre-biased startup, both power MOSFETs are
not allowed to turn on until the internal ramp of the device sets an output voltage above the pre-bias voltage.
If the device is in shutdown mode, undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS
pin down to ensure a proper low level. Returning from those states causes a new startup sequence.
9.3.4 Switch Current-Limit and Short Circuit Protection
The TPS62134x family of devices is protected against heavy load and short circuit events. If an output short
circuit is detected (VO drops below 0.3 V), the switch current limit is reduced to 1.6 A (typical). If the output
voltage rises above 0.4 V, the device operates in normal operation again.
At heavy loads, the current-limit determines the maximum output current. The current-limit supports output
currents of 3 A with input voltages below 5 V and 3.2 A with higher input voltages. If the peak current-limit (IL) is
reached, the high-side MOSFET is turned off. Avoiding shoot-through current, the low-side MOSFET is switched
on to sink the inductor current. The high-side MOSFET turns on again, only if the current in the low-side
MOSFET has decreased below the low-side current-limit threshold of 3.2 A (typical).
Because of the internal propagation delay, the actual peak current of the high-side switch typically occurs above
the DC value listed in the Electrical Characteristic table, especially in low duty-cycle applications. Use 公式 1 to
calculate the dynamic current-limit.
V - VO
I
IL(dynamic) = IL +
´ 30 ns
L
(1)
9.3.5 Output Voltage and LPM Logic Selection (VIDx and LPM)
The output voltage of the TPS62134x family of devices is selected by two VIDx pins and one LPM pin as listed in
表 1. A pulldown resistor of 400 kΩ is internally connected to the VIDx pins and LPM pin to ensure a proper logic
level if the pin is high impedance or floating. The pulldown resistors are disconnected if the pins are pulled High.
The device has a low power mode (LPM) where the output voltage is reduced or disabled by using the LPM pin.
While the LPM pin is asserted, the PG output remains high impedance. The device also achieves a dynamic
output-voltage change by using the VIDx pins. This feature helps the system to minimize power consumption in
standby or idle mode. The TPS62134B/D devices provide the full current even if the output voltage is set at 0.7 V
in LPM mode.
8
版权 © 2015, Texas Instruments Incorporated
TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
Feature Description (接下页)
表 1. Output Voltage Selection
PART NUMBER
(INTEL SKYLAKE VRs)
LPM LOGIC
VID1 LOGIC
VID0 LOGIC
OUTPUT VOLTAGE (V)
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
x
0
0
1
1
x
0
0
1
1
x
0
0
1
1
x
0
0
1
1
x
0
1
0
1
x
0
1
0
1
x
0
1
0
1
x
0
1
0
1
0 (LPM)
0.850
0.875
0.950
0.975
0.7 (LPM)
0.80
TPS62134A
(VCC(IO) Rail)
TPS62134B
(VCC(PRIM_CORE) Rail)
0.85
0.90
0.95
0 (LPM)
0.80
TPS62134C
(VCC(EDRAM) / VCC(EOPIO) Rail)
0.95
1.00
1.05
0.7 (LPM)
0.85
TPS62134D
(VCC(PRIM_CORE) Rail)
0.90
0.95
1.00
9.3.6 Power-Good Output (PG)
The TPS62134x family of devices has a built-in power-good indicator. The PG signal can be used for startup
sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage
below 6 V. The device has a fixed power-good threshold of 760 mV (rising edge) and 720 mV (falling edge). The
PG rising edge has a delay time of 140 µs (typical) and a falling edge has a delay time of 20 µs (typical). The PG
pin can sink 2-mA of current and maintain the specified logic low level. 表 2 lists the PG logic status in different
operation conditions. The PG pin can be left floating if not used.
In LPM, the PG signal is latched as high impedance. When the device exits LPM, the PG has a 500-µs blanking
time to ensure that the output voltage returns to the nominal value.
表 2. Power Good Logic
PG LOGIC STATUS
CONDITIONS
HIGH
IMPEDANCE
LOW
EN = high, LPM = high, VO > 760 mV
EN = high, LPM = high, VO < 720 mV
EN = high, LPM = low
√
Enable
√
LPM
√
LPM, TPS62134B/D
Shutdown
EN = high, LPM = Low, VO < 0.3 V
EN = Low
√
√
√
√
Thermal shutdown
UVLO
0.5 V < V(AVIN) < V(UVLO)
V(AVIN) < 0.5 V
Power supply removal
√
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ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
9.3.7 Single-Ended Remote Sense (FBS)
The devices allow a single-ended remote sense by connecting the FBS pin at the load. This function overcomes
the parasitic resistance of the PCB traces and achieves an improved output-voltage regulation at the load. Avoid
any noise coupled into the FBS trace. Use a solid ground plane to connect the ground return of the load with the
AGND and PGND pins of the device. Connect the AGND and PGND pins directly to exposed thermal pad of the
device. 图 3 shows an example.
L1
1 µH
TPS62134x
SW
C2
47 µF
VOS
Load
FBS
C(LOAD)
Ground Plane Connection
AGND
PGND
图 3. Remote Sense Connection
9.3.8 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power MOSFETs are turned
off. When TJ decreases below the hysteresis of 20°C, the converter resumes normal operation, beginning with a
soft start.
9.4 Device Functional Modes
9.4.1 PWM Operation and Power Save Mode
The device operates with pulse width modulation (PWM) in medium and heavy load with a fixed on-time circuitry
(ton). Use 公式 2 to calculate the on-time in steady-state operation.
VO
ton = 1ms´
V
I
(2)
The typical PWM switching frequency is 1 MHz. The frequency variation in PWM is controlled and depends on
VI, VO, and the inductance. The switching frequency decreases with the input voltage to improve the efficiency in
small duty-cycle applications.
To maintain high efficiency at light loads, the device enters PSM at the boundary to discontinuous conduction
mode (DCM). In PSM, the switching frequency decreases linearly with the load current maintaining high
efficiency. Use 公式 3 to calculate the switching frequency in PSM mode.
2 ´ IO
ƒS(PSM)
=
V
V - VO
2
I
I
ton
´
´
VO
L
(3)
See 图 11 for the switching frequency variation over load and input voltage.
10
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TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS62134x family of devices are synchronous step-down converters based on the DCS-Control™ topology.
The following section discusses the design of the external components to complete the power-supply design for
power rails in the Intel Skylake platform.
10.2 Typical Application
L1
1 µH
TPS62134A
VO
0.95 V, 3 A
VI
3 to 17 V
PVIN
AVIN
EN
SW
VOS
FBS
C1
22 µF
C2
47 µF
VDD
VID0
VID1
LPM
R3
499 kΩ
Host
V(PG)
PG
SS
AGND
PGND
C3
470 pF
图 4. TPS62134A Typical Application
10.2.1 Design Requirements
The design guideline provides component selection to operate the device within the values listed in the
Recommend Operating Conditions section. Meanwhile, the design meets the time and slew rate requirements of
the Intel Skylake platform for VCC(IO), VCC(PRIM_CORE), VCC(EDRAM), and VCC(EOPIO) rails. 表 3 lists the components
used for the curves in the Application Curves section.
表 3. List of Components
REFERENCE
DESCRIPTION
High efficiency step down converter
MANUFACTURER
TPS62134x
TI
L1
C1
C2
C3
R3
Inductor, 1 µH, XFL4020-102ME
Coilcraft
Murata
Murata
Murata
Standard
Ceramic capacitor, 22 µF, GRM21BR61E226ME44L
Ceramic capacitor, 47 µF, GRM21BR60J476ME15L
Ceramic capactor, 470 pF, GRM188R71H471KA01D
Resistor, 499 kΩ
10.2.2 Detailed Design Procedure
10.2.2.1 Output Filter Selection
The first step of the design procedure is the selection of the output-filter components. The combinations listed in
表 4 are used to simplify the output filter component selection.
版权 © 2015, Texas Instruments Incorporated
11
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
表 4. Recommended LC Output Filter Combinations(1)
OUTPUT CAPACITOR
100 µF
INDUCTOR
22 µF
47 µF
200 µF
400 µF
0.47 µH
1 µH
(2)
√
√
√
2.2 µH
(1) The values in the table are nominal values, including device tolerances.
(2) This LC combination is the standard value and recommended for most applications.
10.2.2.2 Inductor Selection
The inductor selection is affected by several effects such as inductor-ripple current, output-ripple voltage, PWM-
to-PSM transition point, and efficiency. In addition, the selected inductor must be rated for appropriate saturation
current and DC resistance (DCR). Use 公式 4 to calculate the maximum inductor current under static load
conditions.
ΔI(L)max
I(L)max = IOmax +
2
æ
ö
VO
VO
V
DI(L)max =
´ 1-
ç
÷
Lmin ´ ƒS
è
I ø
where
•
•
•
•
I(L)max is the maximum inductor current
ΔI(L)max is the maximum peak-to-peak inductor ripple current
Lmin is the minimum effective inductor value
ƒS is the actual PWM switching frequency
(4)
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current. A margin of approximately 20% is recommended to be added. The inductor value also determines the
load current at which power save mode is entered:
DI(L)
IO(PSM)
=
2
(5)
表 5 lists inductors that are recommended to use with the TPS62134x device.
表 5. List of Inductors
TYPE
INDUCTANCE (µH)
CURRENT (A)
DIMENSIONS (L × B × MANUFACTURER
H, mm)
XFL4020-102ME
DFE252012F
DFE201612E
PISB25201T
PIME031B
1 µH
1 µH
1 µH
1 µH
1 µH
4.7
5.0
4.1
3.9
5.4
4 × 4 × 2
Coilcraft
Toko
2.5 × 2 × 1.2
2 × 1.6 × 1.2
2.5 × 2 × 1
3.1 × 3.4 × 1.2
Toko
Cyntec
Cyntec
10.2.2.3 Output Capacitor
The recommended value for the output capacitor is 47 µF. The architecture of the TPS62134x family of devices
allows the use of tiny ceramic output capacitors which have low equivalent series resistance (ESR). These
capacitors provide low output-voltage ripple and are recommended. Using an X7R or X5R dielectric is
recommended to maintain low resistance up to high frequencies and to achieve narrow capacitance variation
with temperature. Using a higher value can have some advantages such as smaller voltage ripple and a tighter
DC output accuracy in PWM. See Optimizing the TPS62130/40/50/60/70 Output Filter, SLVA463 for additional
information.
Note that in power save mode, the output voltage ripple depends on the output capacitance, ESR, and peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
12
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ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
10.2.2.4 Input Capacitor
For most applications, using a capacitor with a value of 22 µF is a recommended. Larger values further reduce
input-current ripple. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A ceramic capacitor which has low ESR is recommended for best filtering and should
be placed between the PVIN and PGND pins and as close as possible to those pins.
10.2.2.5 Soft-Start Capacitor
A capacitor connected between the SS pin and the AGND pin allows a user programmable startup slope of the
output voltage. A constant current source supports 2.5 µA to charge the external capacitance. Use 公式 6 to
calculate the capacitor value required for a given soft-start time.
2.5 mA
C(SS) = t(SS)
´
VO
where
•
•
C(SS) is the capacitance (F) required at the SS pin
t(SS) is the desired soft-start time (s)
(6)
Leave the SS pin floating for fastest startup.
10.2.3 Application Curves
TA = 25°C and VI = 7.2 V, unless otherwise noted.
100
90
80
70
60
50
40
100
90
80
70
VI = 5 V
VI = 6 V
VI = 7.2 V
VI = 8.4 V
VI = 10.8 V
VI = 12 V
VI = 5 V
VI = 6 V
VI = 7.2 V
VI = 8.4 V
VI = 10.8 V
VI = 12 V
60
50
40
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2
3 45
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2 3 45
D001
D016
VO = 0.975 V
VO = 0.95 V
图 5. TPS62134A Efficiency
图 6. TPS62134B Efficiency
100
100
90
80
70
60
50
40
90
80
70
60
50
40
VI = 5 V
VI = 6 V
VI = 7.2 V
VI = 8.4 V
VI = 10.8 V
VI = 12 V
VI = 5 V
VI = 6 V
VI = 7.2 V
VI = 8.4 V
VI = 10.8 V
VI = 12 V
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2
3 45
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2 3 45
D003
D004
VO = 1 V
VO = 0.8 V
图 7. TPS62134C Efficiency
图 8. TPS62134C Efficiency
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TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
TA = 25°C and VI = 7.2 V, unless otherwise noted.
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
-0.2
-0.2
-0.4
-0.6
-0.8
-0.4
TA = ꢀ40qC
TA = 25qC
TA = 85qC
TA = ꢀ40qC
TA = 25qC
TA = 85qC
-0.6
-0.8
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2
3 45
3
5
7
9
11
13
15
17
Input Voltage (V)
D008
D009
VO = 0.95 V
VI = 7.2 V
VO = 0.95 V
IO = 1 A
图 9. TPS62134A Load Regulation
图 10. TPS62134A Line Regulation
5x106
2x106
1x106
5x105
V(SW) = 10 V/div
2x105
1x105
5x104
VO = 20 mV/div, AC
2x104
1x104
5x103
I(COIL) = 1 A/div
VI = 3 V
VI = 8 V
VI = 12 V
VI = 17 V
2x103
1x103
Time = 5 µs/div
0.001
0.01 0.02 0.05 0.1 0.2
Load (A)
0.5
1
2 3 45
VO = 0.95 V
IO = 50 mA
D007
VO = 0.975 V
图 11. TPS62134A Switching Frequency
图 12. TPS62134A Output Ripple
V(EN) = 2 V/div
V(PG) = 2 V/div
V(SW) = 10 V/div
VO = 20 mV/div, AC
I(COIL) = 2 A/div
VO = 0.5 V/div
I(COIL) = 2 A/div
Time = 1 µs/div
Time = 100 µs/div
VO = 0.95 V
IO = 2 A
VO = 0.95 V
R(LOAD) = 0.47 Ω
图 13. TPS62134A Output Ripple
图 14. TPS62134A Startup and Shutdown
14
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TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
TA = 25°C and VI = 7.2 V, unless otherwise noted.
V(LPM)
=
2 V/div
Load = 0.75 A to 3 A
V(PG) = 2 V/div
VO = 50 mV/div, AC
VO = 0.5 V/div
I(COIL) = 2 A/div
I(LOAD) = 2 A/div
Time = 10 µs/div
Time = 50 µs/div
VO = 0.95 V
R(LOAD) = 0.47 Ω
图 15. TPS62134A Load Transient
图 16. TPS62134C LPM Entry and Exit
V(VID1) = 2 V/div
V(PG) = 2 V/div
VO = 0.8 to 1 V
I(COIL) = 2 A/div
Time = 10 µs/div
R(LOAD) = 0.47 Ω
图 17. TPS62134C Minimum Speed Mode (MSM) Entry and Exit
11 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3 V and 17 V. Use 公式 7 to
calculate the average input current of the TPS62134x device.
VO ´ IO
1
I =
´
I
h
V
I
(7)
Ensure that the input power supply has a sufficient current rating for the application.
版权 © 2015, Texas Instruments Incorporated
15
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
•
•
•
TI recommends to place all components as close as possible to the device. Ensure that the input capacitor
placement is as close as possible to the PVIN and PGND pins of the device.
The VOS pin is noise sensitive and must be routed short and directly to the output of the output capacitor.
This routing minimizes switch node jitter and ensures reliability.
The direct common-ground connection of the AGND and PGND pins to the exposed thermal pad and the
system ground (ground plane) is mandatory. To enhance heat dissipation of the device, the exposed thermal
pad should be connected to bottom or internal layer ground planes using vias.
•
•
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
The capacitor on the SS pin should be placed close to the device and connected directly to those pins and
the AGND pin.
•
•
•
The inductor should be placed close to the SW pins, keeping this area small.
Finally, the ground of the output capacitor should be located close to the PGND pins of the device.
See 图 18 for an example of component placement, routing, and thermal design.
12.2 Layout Example
AGND
VIN
C3
L1
VID0
AVIN
PVIN
PVIN
PG
SW
SW
VOS
C1
C2
VOUT
GND
图 18. TPS62134x Layout Example
16
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TPS62134A, TPS62134B, TPS62134C, TPS62134D
www.ti.com.cn
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
12.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
The following lists three basic approaches for enhancing thermal performance:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes, Thermal Characteristics of
Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), and Semiconductor and IC Package
Thermal Metrics (SPRA953).
版权 © 2015, Texas Instruments Incorporated
17
TPS62134A, TPS62134B, TPS62134C, TPS62134D
ZHCSD94C –JANUARY 2015–REVISED JANUARY 2015
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 文档支持
13.2.1 相关文档ꢀ
•
•
•
《优化 TPS62130/40/50/60/70 输出滤波器》，SLVA463
《半导体和 IC 封装热指标》，SPRA953
《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》，SZZA017
13.3 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 6. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
TPS62134A
TPS62134B
TPS62134C
TPS62134D
13.4 商标
DCS-Control, the DCS-Control are trademarks of Texas Instruments.
Skylake, 超级本 are trademarks of Intel.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62134ARGTR
TPS62134ARGTT
TPS62134BRGTR
TPS62134BRGTT
TPS62134CRGTR
TPS62134CRGTT
TPS62134DRGTR
TPS62134DRGTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
134A
134A
134B
134B
134C
134C
134D
134D
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62134ARGTR
TPS62134ARGTR
TPS62134ARGTT
TPS62134BRGTR
TPS62134BRGTR
TPS62134BRGTT
TPS62134BRGTT
TPS62134CRGTR
TPS62134CRGTT
TPS62134DRGTR
TPS62134DRGTR
TPS62134DRGTT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
16
16
16
16
16
16
16
3000
3000
250
330.0
330.0
330.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.5
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
3000
250
250
3000
250
3000
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62134ARGTR
TPS62134ARGTR
TPS62134ARGTT
TPS62134BRGTR
TPS62134BRGTR
TPS62134BRGTT
TPS62134BRGTT
TPS62134CRGTR
TPS62134CRGTT
TPS62134DRGTR
TPS62134DRGTR
TPS62134DRGTT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
16
16
16
16
16
16
16
3000
3000
250
338.0
552.0
338.0
338.0
552.0
205.0
552.0
338.0
338.0
552.0
338.0
338.0
355.0
346.0
355.0
355.0
346.0
200.0
185.0
355.0
355.0
346.0
355.0
355.0
50.0
36.0
50.0
50.0
36.0
33.0
36.0
50.0
50.0
36.0
50.0
50.0
3000
3000
250
250
3000
250
3000
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS62134ARGTR
TPS62134ARGTT
TPS62134BRGTR
TPS62134BRGTT
TPS62134CRGTR
TPS62134CRGTT
TPS62134DRGTR
TPS62134DRGTT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
16
16
16
16
16
16
16
16
3000
250
381
381
381
381
381
381
381
381
4.83
4.83
4.83
4.83
4.83
4.83
4.83
4.83
2286
2286
2286
2286
2286
2286
2286
2286
0
0
0
0
0
0
0
0
3000
250
3000
250
3000
250
Pack Materials-Page 3
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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