TPS62180YZFT [TI]
具有电源正常指示功能、1% 精度和可调节软启动功能的 4V 至 15V、6A 同步降压转换器 | YZF | 24 | -40 to 125;
| 型号： | TPS62180YZFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示功能、1% 精度和可调节软启动功能的 4V 至 15V、6A 同步降压转换器 | YZF | 24 | -40 to 125 开关 软启动 输出元件 转换器 |
| 文件： | 总40页 (文件大小：1979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
TPS6218x 4V 至 15V、6A、双相降压转换器，具有 AEE™
1 特性
3 说明
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双相平衡峰值电流模式
输入电压范围：4V 至 15V
TPS6218x 是一款适用于薄型电源轨的双相降压 DC-
DC 转换器。它采用峰值电流控制且两相电流平衡，
适合高度受限的应用。
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输出电压范围：0.9V 至 6V
输出电流高达 6A
该器件具有 4V 到 15V 的宽工作输入电压范围，非常
适合通过多节锂离子电池或 12V 电源轨供电运行的系
统。两相可持续提供 6A 输出电流（每相 3A），从而
允许使用薄型外部元件。两相异相运行，这样可显著减
小开关噪声。
典型静态电流为 28µA
输出电压精度达 ±1%（脉宽调制 (PWM) 模式）
自动效率提高 (AEE™)
相移操作
自动节能模式
TPS6218x 可在超轻负载时自动进入节能模式以保持高
效率，并且还集成有自动效率提高功能 (AEE™)，适用
于整个占空比范围。
可调软启动
电源正常输出
欠压闭锁
HICCUP 过流保护
与 TPS62184 引脚对引脚兼容
过热保护
该器件支持 电源正常信号和可调软启动。其静态电流
典型值为 28µA，并且能够在 100% 模式下运行，即便
在最低输出电压下也不存在占空比限制。
NanoFree™2.10mm x 3.10mm 芯片尺寸球状引脚
栅格阵列 (DSBGA) 封装
结合使用 TPS62180 和 WEBENCH® 电源设计器
创建定制设计方案
TPS6218x 提供了可调节输出电压和固定输出电压两种
选项，并且采用 24 凸点、0.5mm 间距的小型 DSBGA
封装。
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器件信息(1)
2 应用
器件型号
TPS62180
TPS62182
封装
DSBGA (24)
DSBGA (24)
封装尺寸（标称值）
2.10mm x 3.10mm
2.10mm x 3.10mm
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薄型负载点 (POL) 电源
窄 VDC (NVDC) 供电系统
两/三节锂离子电池
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
超便携式/嵌入式/平板电脑
计算网络解决方案
间距
微型服务器和固态硬盘 (SSD)
简化电路原理图
space
效率与输出电流间的关系
22µF
1µH
1µH
VIN1
VIN2
SW1
SW2
VO
4 to 15 V
3.3V/6A
470k
22µF
TPS62182
2x
47µF
PG
FB
EN
SS/TR
GND
3.3nF
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBB8
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
目录
8.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
9.3 TPS62180 Output Voltage Application Examples... 28
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 8
9
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 器件和文档支持 ..................................................... 32
12.1 器件支持................................................................ 32
12.2 相关链接................................................................ 32
12.3 商标....................................................................... 32
12.4 静电放电警告......................................................... 32
12.5 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 32
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (August 2014) to Revision B
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新增特性：与 TPS62184 引脚对引脚兼容.............................................................................................................................. 1
已添加 WEBENCH® 信息 特性、详细设计流程和开发支持部分。 ......................................................................................... 1
在器件信息表中将“封装尺寸”值从 2.14mm x 3.14mm 更改为 2.10mm x 3.10mm ................................................................. 1
Added SW1, SW2, (AC, less than 10ns) and Note (3) to the Pin voltage range in the Absolute Maximum Ratings table ... 4
Changed Handling Ratings To: ESD Ratings table................................................................................................................ 4
Added Table 1 ....................................................................................................................................................................... 9
Added the application note .................................................................................................................................................. 14
Changed the Design Requirements paragraph.................................................................................................................... 14
Added Note (2) to Table 6 ................................................................................................................................................... 17
Added Figure 31 and Figure 32............................................................................................................................................ 21
Added Figure 37 .................................................................................................................................................................. 22
Changed the Design Requirements paragraph.................................................................................................................... 24
Added Figure 38 and Figure 39 to the Inductor section....................................................................................................... 24
Changed Figure 55 .............................................................................................................................................................. 31
Changes from Original (August 2014) to Revision A
Page
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已投入量产 ............................................................................................................................................................................. 1
2
版权 © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
www.ti.com.cn
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
5 Device Comparison Table
PART NUMBER
TPS62180
OUTPUT VOLTAGE
Adjustable
TJ
-40°C to 125°C
-40°C to 125°C
TPS62182
3.3 V
Spacer
6 Pin Configuration and Functions
24-Pin DSBGA
YZF Package
(Top View - Left, Bottom View - Right)
1
2
3
4
F
E
D
C
B
A
A
B
C
D
E
F
Pin Functions
PIN(1)
DESCRIPTION
NAME
AGND
EN
NUMBER
C4
Analog Ground. Connect on PCB directly with PGND.
Enable input (High = enabled, Low = disabled)
E4
Output voltage feedback. Connect resistive voltage divider to this pin and AGND. On TPS62182,
connect to AGND.
FB
B4
F4
Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain
(requires pull-up resistor)
PG
A3, B3, C3, D3,
E3, F3
PGND
SS/TR
SW1
SW2
Common power ground.
Soft-Start and Tracking Pin. An external capacitor connected to this pin sets the internal voltage
reference rise time.
D4
Switch node for Phase 1 (master), connected to the internal MOSFET switches. Connect inductor 1
between SW1 and output capacitor.
A2, B2, C2
D2, E2, F2
Switch node for Phase 2 (follower), connected to the internal MOSFET switches. Connect inductor 2
between SW2 and output capacitor.
VIN1
VIN2
VO
A1, B1, C1
D1, E1, F1
A4
Supply voltage for Phase 1.
Supply voltage for Phase 2.
Output Voltage Connection
(1) For more information about connecting pins, see Detailed Description and Application Information sections.
Copyright © 2014–2017, Texas Instruments Incorporated
3
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–2
MAX
17
UNIT
V
VIN1, VIN2
EN, PG
VIN + 0.3
VIN + 0.3
24.5
V
SW1, SW2, (DC)
SW1, SW2, (AC, less than 10ns)(3)
V
Pin voltage range(2)
VIN + 0.3,
but ≤ 7
SS/TR
FB, VO
PG
–0.3
–0.3
V
V
7
Power good sink
current
10
mA
Operating junction
temperature range
TJ
–40
–65
150
150
°C
°C
Storage Temperature
Range
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground pin.
(3) While switching.
7.2 ESD Ratings
MIN
–1
MAX
1
UNIT
Human Body Model (HBM) ESD stress voltage(2)
Charge device model (CDM) ESD stress voltage
(1)
VESD
kV
–0.5
0.5
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
TYP
MAX
15
UNIT
V
Supply voltage range, VIN
Output voltage range, VOUT
4
0.9
6
6
V
0.9V ≤ VOUT ≤ 3.3V
Maximum Output current,
IOUT(max)
A
3.3V < VOUT
6
Operating junction temperature, TJ
–40
125
°C
7.4 Thermal Information
TPS6218x
THERMAL METRIC(1)
UNIT
YZF (24 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
61.5
0.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
ψJT
Junction-to-board thermal resistance
10.1
0.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
10.1
n/a
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
www.ti.com.cn
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +125°C) and VIN = 4 V to 15 V.
Typical values at VIN = 12 V and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
VIN
Input voltage range
4
15
55
V
EN = High, IOUT = 0 mA, Device not switching,
(TJ = –40°C to +85°C)
IQ
Operating quiescent current
Shutdown current
28
µA
ISD
EN = Low (≤ 0.3 V), (TJ = –40°C to +85°C)
Falling input voltage
2.8
3.6
300
160
20
15
µA
V
VUVLO
3.5
3.7
(1)
Undervoltage lockout threshold
Thermal shutdown
Hysteresis
mV
TSD
Rising junction temperature
Hysteresis
°C
CONTROL (EN, SS/TR, PG)
VH_EN
VL_EN
ILKG_EN
ISS/TR
High-level input threshold voltage (EN)
Low-level input threshold voltage (EN)
Input leakage current (EN)
0.97
0.87
1
0.9
0.01
5
1.03
0.93
1.2
V
V
EN = VIN or GND
µA
µA
SS/TR pin source current
4.5
5.5
Rising (%VOUT
)
94% 96%
90% 92%
98%
94%
0.3
VTH_PG
Power good threshold voltage
Falling (%VOUT
)
VOL_PG
ILKG_PG
Power good output low voltage
Input leakage current (PG)
IPG= -2 mA
V
1
100
nA
POWER SWITCH
Phase 1
Phase 2
Phase 1
Phase 2
High-side MOSFET ON-resistance
27
21
65 mΩ
45 mΩ
RDS(ON)
VIN = 7.5 V
Low-side MOSFET ON-resistance
ILIM
High-side MOSFET current limit
Phase shift delay time
Each phase, VIN = 7.5 V
4.0
4.7
5.5
A
TPSD
Phase 2 after Phase 1, PWM mode
250
ns
OUTPUT
VREF
Internal reference voltage
Input leakage current (FB)
0.792
0.8 0.808
V
nA
Ω
ILKG_FB
VFB = 0.8 V
EN = Low
VIN ≥ VOUT
1
100
RDISCHARGE Output discharge resistance
Output voltage range (TPS62180)
Output voltage (TPS62182)
60
0.9
6
V
3.3
V
PWM Mode, VIN ≥ VOUT + 1 V
–1%
1%
Power Save Mode, VOUT = 3.3 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 2 x 47 µF, (TJ = –40°C to +85°C)
Feedback voltage accuracy
(TPS62180)(2)
–1%
2%
Power Save Mode, VOUT = 1.8 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 4 x 47 µF, (TJ = –40°C to +85°C)
VOUT
Power Save Mode, VOUT = 0.9 V, Iload ≥ 1 mA,
–1%
–1%
–1%
3%
1%
2%
L = 1 µH, COUT = 4 x 47 µF, (TJ = –40°C to +85°C)
PWM Mode, VIN ≥ VOUT + 1 V
Output voltage accuracy
(TPS62182)(2)
Power Save Mode, Iload ≥ 1 mA, L = 1 µH,
COUT = 2 x 47 µF, (TJ = –40°C to +85°C)
Load regulation
Line regulation
VOUT = 3.3 V, PWM Mode operation
0.04
0.01
0.9
5
%/A
%/V
4 V ≤ VIN ≤ 15 V, VOUT = 3.3 V, IOUT = 4 A
Hiccup on time
tHICCUP
ms
Hiccup off time
(1) The minimum VIN value of 4 V is not violated by UVLO threshold and hysteresis variations.
(2) The accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple.
Copyright © 2014–2017, Texas Instruments Incorporated
5
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
7.6 Typical Characteristics
Figure 1. Quiescent Current
Figure 2. Shutdown Current
Figure 3. High-Side Switch Resistance
Figure 4. Low-Side Switch Resistance
6
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
www.ti.com.cn
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
8 Detailed Description
8.1 Overview
The TPS6218x is a high efficiency synchronous switched mode step-down converter based on a peak current
control topology. It is designed for smallest solution size low-profile applications, converting multi-cell Li-Ion
supply voltages to output voltages of 0.9 V to 6 V. While an outer voltage loop sets the regulation threshold for
the current loop based on the actual VOUT level, the inner current loop adapts the peak inductor current for every
switching cycle. The regulation network is internally compensated. The switching frequency is set by an OFF-
time control and features Power Save Mode (PSM) and AEE™ (Automatic Efficiency Enhancement) to keep the
efficiency high over the whole load current and duty cycle range. The switching frequency is set depending on
VIN and VOUT and remains unchanged for steady state operating conditions.
The TPS6218x is a dual phase converter, sharing the load current among the phases. Identical in construction,
the follower control loop is connected with a fixed delay to the master control loop. Both the phases use the
same regulation threshold and cycle-by-cycle peak current setpoint. This ensures a phase-shifted as well as
current-balanced operation. Using the advantages of the dual phase topology, a 6-A continuous output current is
provided with high performance and smallest system solution size.
While the TPS62180 offers an adjustable output voltage, the TPS62182 supports a fixed 3.3-V output voltage,
saving external components.
8.2 Functional Block Diagram
PG
1
VIN2
3
VIN1
3
Thermal
Power Save
Mode
PG control
Shutdown
VIN1
HS1
1
1
1
3
3
1
EN*
SS/TR
VO
SW1
SW2
FB
VIN2
power
control
gate
HS2
control logic
drive
phase shift
VIN
HS2
UVLO
HICCUP
follower
tf
gmout
delay
gm
60
VREF
master
tm
EN
HS1
VIN
VIN
AEETM
off-timer
7
GND
*Pin is connected to a pull down resistor internally
(see Feature Description section)
Copyright © 2017, Texas Instruments Incorporated
Figure 5. TPS62180 (Adjustable output voltage)
Copyright © 2014–2017, Texas Instruments Incorporated
7
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
Functional Block Diagram (continued)
PG
1
VIN2
3
VIN1
3
Thermal
PG control
Shutdown
Power Save
Mode
VIN1
HS1
1
1
1
3
3
1
EN*
SS/TR
VO
SW1
VIN2
power
control
gate
HS2
control logic
drive
phase shift
SW2
FB*
VIN
HS2
UVLO
HICCUP
follower
VO
tf
VREF
R1
gmout
delay
gm
60
master
R2
tm
EN
HS1
VIN
VIN
AEETM
off-timer
7
GND
*Pin is connected to a pull down resistor internally
(see Feature Description section)
Copyright © 2017, Texas Instruments Incorporated
Figure 6. TPS62182 (Fixed output voltage)
8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
The device starts operation, when VIN is present and Enable (EN) is set High. The EN threshold is 1 V for rising
and 0.9 V for falling voltages, providing a threshold accuracy of ±3%. That makes it suitable for precise switching
on and off in accurate power sequencing arrangements as well as for slowly rising EN control voltage signals
(see Using the Accurate EN Threshold for more details).
The device is disabled by pulling EN Low. A discharge resistor of about 60 Ω is then connected to the output. At
the EN pin, an internal pull down resistor of about 350 kΩ keeps the Low state, if EN gets high impedance or
floating afterwards.
The EN pin can be connected to VIN to always enable the device. A delay of 1 ms, after VIN exceeds VUVLO
,
ensures safe operating conditions before the device starts switching. If VIN is already present, a soft start
sequence is initiated about 100 µs after EN is pulled High.
8.3.2 Soft Start / Tracking (SS/TR)
The soft start circuit controls the output voltage slope during startup. This avoids excessive inrush current and
ensures a controlled output voltage rise time. It also prevents unwanted voltage drop from high impedance power
sources or batteries. When EN is set to start device operation, the device starts switching and VOUT rises with a
slope, controlled by the external capacitor connected to the SS/TR pin. There is no theoretical limit for the
longest startup time. It is not recommended to leave the SS/TR pin floating, because VOUT may overshoot.
Typical startup operation is shown in Application Performance Curves.
8
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
www.ti.com.cn
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
Feature Description (continued)
The device can track an external voltage (see Tracking). The device can monotonically start into a pre-biased
output.
8.3.3 Power Good (PG)
The TPS6218x has a built in power good (PG) function. The PG pin goes High, when the output voltage has
reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG is Low. The
PG pin is an open drain output that requires a pull-up resistor and can sink typically 2 mA. If not used, the PG pin
can be left floating or grounded.
space
Table 1. Power Good Pin Logic Table
PG Logic Status
Device Information
High Z
Low
V
FB ≥ VTH_PG
FB ≤ VTH_PG
√
Enable (EN=High)
V
√
√
√
√
Shutdown (EN=Low)
UVLO
0.7V < VIN < VUVLO
TJ > TSD
Thermal Shutdown
Power Supply Removal
VIN < 0.7V
√
space
8.3.4 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) prevents misoperation of the device, if the input voltage drops below the UVLO
threshold. It is set to 3.6 V typically with a hysteresis of typically 300mV. (See also Device Functional Modes).
8.3.5 Thermal Shutdown
The junction temperature TJ of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ.), the device goes in thermal shutdown with a hysteresis of typically 20°C. Both the power FETs are turned
off, the discharge resistor is connected to the output and the PG pin goes Low. Once TJ has decreased enough,
the device resumes normal operation with Soft Start.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TPS6218x is based on a predictive OFF-time peak current control topology, operating with PWM in
continuous conduction mode for heavier loads. Since the OFF-time is automatically adjusted according to the
actual VIN and VOUT, it provides highest efficiency over the entire input and output voltage range. The OFF-time is
calculated as:
spacing
é
ê
ë
ù
ú
û
VIN
tOFF
=
500ns + 50ns
5VOUT
(1)
spacing
While the OFF-time is predicted, the ON-time is set depending on the converter's duty cycle and calculated as:
spacing
tOFF ×VOUT
tON
=
VIN -VOUT
(2)
9
spacing
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
Device Functional Modes (continued)
Thereby the switching frequency is fixed for a given input and output voltage and is calculated as:
spacing
æ
ö
1- D
1
VOUT
VIN
ç
ç
÷
÷
fSW
=
=
1-
tOFF
tOFF
è
ø
(3)
spacing
Both the master and follower phases regulate to the same level of VOUT with separate current loops, using the
same peak current setpoint, cycle by cycle. This provides excellent peak current balancing, independent of
inductor dc resistance matching. Since the follower phase operates with a fixed delay to the master phase, also
cycle by cycle, phase shifted operation is obtained.
The device features an automatic transition into Power Save Mode, entered at light loads, running in
discontinuous conduction mode (DCM).
8.4.2 Power Save Mode (PSM) Operation
As the load current decreases, the converter enters Power Save Mode operation. During PSM, the converter
operates with a reduced switching frequency maintaining highest efficiency due to minimum quiescent current.
Power Save Mode is based on a fixed peak current architecture, where the peak current (IPEAK) is set depending
on VIN, VOUT, and L. After each single pulse, a pause time until the internal VOUT_Low level threshold is reached
completes the switching cycle in PSM.
The switching frequency for PSM in one phase operation is calculated as :
spacing
2IOUT ×VOUT (VIN -VOUT )
fPSM
=
L× IP2EAK ×VIN
(4)
spacing
Equation 4 shows the linear relationship of output current and switching frequency. Typical values of the fixed
peak current are shown in Figure 7.
space
Figure 7. Typical Fixed Peak Current (IPEAK) in Power Save Mode
space
If the load decreases to very light loads and only one phase is needed, either phase (master or follower) might
be active. The load current level at which Power Save Mode is entered is calculated as follows:
spacing
10
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Device Functional Modes (continued)
Iload (PSM ) = DIL
(5)
spacing
Equation 7 is used to calculate ΔIL.
8.4.3 Minimum Duty Cycle and 100% Mode Operation
When the input voltage comes close to the output voltage, the device enters 100% mode and both high-side
FETs are continuously switched on as long as VOUT remains below its setpoint. The minimum VIN to maintain
output voltage regulation is calculated as:
spacing
R
é
ù
DS(ON )
VIN (min) =VOUT (min) + IOUT
+ DCRL1 // DCRL2
ê
ú
2
ë
û
(6)
spacing
This allows the conversion of small input to output voltage differences, for example for the longest operation time
in battery powered applications. In 100% duty cycle mode, the low-side FET is switched off.
While the maximum ON-time is not limited, the AEE feature, explained in the next section, secures a minimum
ON-time of about 100 ns.
8.4.4 Automatic Efficiency Enhancement (AEE™)
AEE™ provides highest efficiency over the entire input voltage and output voltage range by automatically
adjusting the converter's switching frequency. This is achieved by setting the predictive off-time of the converter.
The efficiency of a switched mode converter is determined by the power losses during the conversion. The
efficiency decreases, if VOUT decreases and/or VIN increases. In order to keep the efficiency high over the entire
duty cycle range (VOUT/VIN ratio), the switching frequency is adjusted while maintaining the ripple current. The
following equation shows the relation between the inductor ripple current, switching frequency and duty cycle.
spacing
VOUT
VIN
æ
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
ø
1-
æ
ö
1- D
ç
ç
÷
÷
DIL =VOUT
×
=VOUT ×
L× fSW
L× fSW
è
ø
(7)
spacing
Efficiency increases by decreasing switching losses, preserving high efficiency for varying duty cycles, while the
ripple current amplitude remains low enough to deliver the full output current without reaching current limit. The
AEE™ feature provides an efficiency enhancement for various duty cycles, especially for lower Vout values,
where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates
for the very small duty cycles of high VIN to low VOUT conversion, which limits the control range in other
topologies.
Figure 8 shows the typical switching frequency over the input voltage range.
space
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Device Functional Modes (continued)
Figure 8. Typical Switching Frequency vs Input Voltage
space
8.4.5 Phase-Shifted Operation
While, for a buck converter, the input current source provides the average current that is needed to support the
output current, an input capacitance is needed to support pulse currents. One of the natural benefits of a two- (or
multi-) phase converter is the possibility to operate out of phase, which decreases the pulse currents and
switching noise. In PWM mode, the TPS6218x devices run with a fixed delay of typically 250 ns between the
phases. This ensures that the phases run phase-delayed, limiting input RMS current and corresponding noise. If
in PSM, both phases run, the phase delay is about 100 ns.
8.4.6 Current Limit, Current Balancing, and Short Circuit Protection
Each phase has a separate integrated peak current limit. While its minimum value limits the output current of the
phase, the maximum number gives the current that must be considered to flow in any operating case. If the
current limit of a phase is reached, the peak current setpoint is unable to increase further. The device provides its
maximum output current. Detecting this heavy load or short circuit condition for about 0.9 ms, the device
switches off for about 5 ms and then restarts again with a soft start cycle. As long as the overload condition is
present, the device hiccups that way, limiting the output power.
The two phases are peak current balanced with a variation within about ±10% at 6-A output current (see
Figure 9). Since the control topology does not depend on inductor or output current measurements, the current
balancing accuracy is independent of inductor matching (binning) and does not need matched power routing.
space
12
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Device Functional Modes (continued)
Figure 9. Typical Current Balancing vs Load Current
space
8.4.7 Tracking
VOUT can track a voltage that is applied at the SS/TR pin. The tracking range at the SS/TR pin is 50 mV to 1.2 V
and the FB pin voltage tracks this as given in Equation 8:
spacing
VFB » 0.64×VSS /TR
(8)
spacing
Due to the factor of about 0.64, the minimum output voltage for tracking is 1.25 V. Once the SS/TR pin voltage
reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage and the device goes to
normal regulation. This works for falling tracking voltage as well. If, in this case, the SS/TR voltage decreases,
the device does not sink current from the output. Thus, the resulting decrease of the output voltage may be
slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3 V.
Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a
wider tolerance than specified.
8.4.8 Operation with Fixed VOUT
The TPS62182 provides a fixed output voltage of 3.3 V (±1%). In this case, the feedback divider is integrated
and the FB pin is internally connected to GND with a resistor of about 350 kΩ. It is recommended to connect the
FB pin to PCB ground to improve thermal behavior.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS62180/2 are switched mode step-down converters, able to convert a 4-V to 15-V input voltage into a
lower 0.9-V to 6-V output voltage, providing up to 6 A. It needs a minimum amount of external components. Apart
from the LC output filter and the input capacitors only an optional pull-up resistor for Power Good (PG) and a
small capacitor for adjustable soft start are used. The TPS62180 with an adjustable output voltage needs an
additional resistive divider to set the output voltage level.
9.2 Typical Applications
9.2.1 Typical TPS62180 Application
C1
L1
L2
VIN1
VIN2
VOUT/6A
SW1
SW2
VO
4 to 15 V
470k
C2
TPS62180
C3
C4
PG
FB
EN
R1
R2
VFB
SS/TR
GND
C5
Copyright © 2017, Texas Instruments Incorporated
Figure 10. Typical 4-V to 15-V Input, 6A Converter
spacing
9.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. The component selection is given in Table 2 and gives a total solution size of about 99 mm2 with a
maximum height of 2.1 mm:
spacing
Table 2. Components Used for Application Characteristics
REFERENCE NAME
TPS62180YZF
DESCRIPTION / VALUE
2 phase step down converter, 2 x 3 mm WCSP
MANUFACTURER
Texas Instruments
L1, L2
C1, C2
C3, C4
C5
Inductor XFL4020-102ME, 1 µH ±20%, 4 x 4 x 2.1 mm
Ceramic capacitor GRM21BR61E226ME44, 2 x 22 µF, 25 V, X5R, 0805
Ceramic capacitor GRM21BR60J476ME15, 2 x 47 µF, 6.3 V, X5R, 0805
Ceramic capacitor, 3.3 nF
Coilcraft
muRata
muRata
Standard
Standard
Standard
Standard
R1
Chip resistor, value depending on VOUT
R2
Chip resistor, value depending on VOUT
R3
Chip resistor, 470 kΩ, 0603, 1/16 W, 1%
14
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62180 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Programming the Output Voltage
The output voltage of the TPS62180 is programmed using an external resistive divider. While the voltage at the
FB pin is regulated to 0.8 V, the output voltage range is specified from 0.9 up to 6 V. The value of the output
voltage is set by selection of the resistive divider (from VOUT to FB to AGND) from Equation 9.
spacing
R
VOUT
1
=
-1
R2 VFB
(9)
spacing
The current through those resistors contributes to the light load efficiency, which makes larger resistor values
beneficial. However, to get sufficient noise immunity these values should not be oversized. Using this, the
resistor values are calculated by converting Equation 9 as follows:
spacing
VFB 0.8V
=
IFB 5mA
R2 =
=160kW
(10)
spacing
Inserting the R2 value in Equation 11, R1 can be obtained.
spacing
æ
ö
VOUT
VFB
ç
ç
÷
÷
R1 = R2 ×
-1
è
ø
(11)
spacing
Calculating for VOUT = 3.3 V gives R1 = 500 kΩ. Using standard resistor values R1 = 470 kΩ and R2 = 150 kΩ are
chosen.
For applications requiring lowest current consumption, the use of fixed output voltage options is recommended.
Using the TPS62182, the FB pin can be left floating, but it is recommended to connect it to AGND which
decreases thermal resistance.
In case the FB pin of the adjustable output voltage version gets opened or an over voltage appears at the output,
an internal clamp limits the output voltage to about 7.4 V.
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9.2.1.2.3 Output Filter Selection
Since the TPS6218x is compensated internally, it is optimized for a range of external component values, which is
specified below. Table 3 and Table 4 are used to simplify the output filter component selection. Checked cells
represent combinations that are proven for stability by simulation and lab test. Further combinations should be
checked for each individual application.
Table 3. Recommended LC Output Filter Combinations for VOUT ≥ 1.8 V(1)
2 x 47 µF
4 x 47 µF
6 x 47 µF
8 x 47 µF
0.47 µH
1.0 µH
1.5 µH
√
√
√
√
(1) The values in the table are the nominal values of inductors and ceramic capacitors. The effective capacitance can vary by +20 and
–60%.
Table 4. Recommended LC Output Filter Combinations for VOUT < 1.8 V(1)
2 x 47 µF
4 x 47 µF
6 x 47 µF
8 x 47 µF
0.68 µH
1.0 µH
1.5 µH
√
√
(1) The values in the table are nominal values of inductors and ceramic capacitors. The effective capacitance can vary by +20 and –40%.
For the output capacitors, a voltage rating of 6.3 V and an X5R dielectric are chosen. If space allows for higher
voltage rated capacitors in larger case sizes, the dc bias effect is lowered and the effective capacitance value
increases.
9.2.1.2.4 Inductor Selection
The TPS6218x is designed to work with two inductors of 1 µH nominal. They have to be selected for adequate
saturation current and a low dc resistance (DCR). The minimum inductor current rating IL(min) that is needed
under static load conditions is calculated using Equation 12 and Equation 13. A current imbalance of 10% at
most is incorporated.
spacing
1.1× IOUT (max) DIL(max)
+
Ipeak(max) = IL(min)
=
(12)
spacing
spacing
VOUT
æ
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
ø
1-
VIN (max)
DIL(max) =VOUT
×
L(min) × fSW
(13)
spacing
This calculation gives the minimum saturation current of the inductor needed and an additional margin of about
20% is recommended to cover dynamic overshoot due to load transients. For low profile solutions, the physical
inductor size and the power losses have to be traded off. Smallest solution size (for example with chip inductors)
are less efficient than bigger inductors with lower losses due to lower DCR and/or core losses. The following
inductors have been tested with the TPS6218x:
16
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TYPE
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Table 5. List of Inductors
INDUCTANCE
[µH]
CURRENT RATING
DCR MAX
[mΩ]
DIMENSIONS (LxBxH) [mm] MANUFACTURER
(1)
MIN/TYP [A]
4.0/4.4
4.7/5.3
3.8/4.5
4.2/4.7
4.5/5.4
3.6/3.9
/5.0
DFE201612E-1R0M
DFE252012F-1R0M
DFE252012P-1R0M
PIFE32251B-1R0MS
PIME031B-1R0MS
PISB25201T-1R0MS
IHLP1212AB-11
1 ±20%
1 ±20%
1 ±20%
1 ±20%
1 ±20%
1 ±20%
1 ±20%
1 ±20%
1.2±20%
1 ±20%
1 ±20%
1 ±20%
48
40
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.2
2.5 x 2.0 x 1.2
3.2 x 2.5 x 1.2
3.7 x 3.3 x 1.2
2.5 x 2.0 x 1.0
3.6 x 3.0 x 1.2
3.6 x 3.0 x 1.5
4.0 x 4.0 x 1.5
4.0 x 4.0 x 2.1
2.0 x 1.6 x 1.0
2.5 x 2.0 x 1.0
TOKO
TOKO
42
TOKO
42
CYNTEC
CYNTEC
CYNTEC
VISHAY
VISHAY
COILCRAFT
COILCRAFT
TDK
55
62
37.5
33
IHLP1212AE-11
/5.3
XFL4015-122ME_
XFL4020-102ME_
TFM201610-GHM
TFM252010-GHM
/4.5
20.7
11.9
60
/5.4
3.6/3.8
3.5/4.0
56
TDK
(1) ISAT at 30% drop of inductance (ΔIL/IL).
The TPS6218x is not designed to operate with only one inductor.
9.2.1.2.5 Output Capacitor Selection
The TPS6218x provides a wide output voltage range of 0.9 V to 6 V. While stability is a critical criteria for the
output filter selection, the output capacitor value also determines transient response behavior, ripple and
accuracy of VOUT. Table 6 gives recommendations to achieve various transient design targets using 1-µH
inductors and small sized output capacitors (see Table 2).
Table 6. Recommended Output Capacitor Values
OUTPUT
VOLTAGE [V]
TYPICAL TRANSIENT RESPONSE ACCURACY
LOAD STEP [A]
(NOMINAL) CAPACITOR VALUE(1)
±mV
90
±%
10
8
4 x 47 µF
6 x 47 µF
2 x 47 µF
4 x 47 µF
8 x 47 µF
2 x 47 µF
4 x 47 µF
8 x 47 µF
0.9(2)
1.8
2-6-2(3)
70
150
120
90
8
2-6-2(3)
2-6-2(3)
7
5
170
135
100
5
3.3
4
3
(1) Ceramic capacitors have a dc bias effect where the effective capacitance differs significantly from the nominal value, depending on
package size, voltage rating and dielectric material.
(2) For output voltages < 1.8V an additional feedforward capacitor of 82pF, parallel to R1 is recommended to increase stability margin at
heavy load steps.
(3) The transient load step is tested with 1-µs/step rising/falling slopes.
spacing
The architecture of the TPS6218x allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to
use X7R or X5R dielectrics. Using even higher values than demanded for stability and transient response has
further advantages like smaller voltage ripple and tighter dc output accuracy in Power Save Mode.
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9.2.1.2.6 Input Capacitor Selection
The input current of a buck converter is pulsating. Therefore, a low ESR input capacitor is required to prevent
large voltage transients and provide peak currents. The recommended value for most applications is 2 x 22 µF,
split between the VIN1 and VIN2 inputs and placed as close as possible to these pins and PGND pins. If
additional capacitance is needed, it can be added as bulk capacitance. To ensure proper operation, the effective
capacitance at the VIN pins must not fall below 2 x 2 µF (close) + 10 µF bulk (effective capacitances).
Low ESR multilayer ceramic capacitors are recommended for best filtering. Increasing with input voltage, the dc
bias effect reduces the nominal capacitance value significantly. To decrease input ripple current further, larger
values of input capacitors can be used.
9.2.1.2.7 Soft Start Capacitor Selection
The TPS6218x provides a user programmable soft start time. A constant current source of 5 µA, internally
connected to the SS/TR pin, allows control of the startup slope by connecting a capacitor to this pin. The current
source charges the capacitor and the soft start time is given by:
spacing
5mA
CSS = tSS ×
1.25V
(14)
spacing
where CSS is the soft-start capacitance required at the SS/TR pin and tss is the resulting soft-start ramp time.
spacing
The SS/TR pin should not be left floating and a minimum capacitance of 220 pF is recommended. Using
Equation 14, and inserting tSS = 750 µs, a value of 3 nF is calculated. 3.3 nF is chosen as a standard value for
this example.
18
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9.2.1.3 Application Performance Curves
VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
VOUT = 6 V
VOUT = 6 V
Figure 11. Efficiency vs Load Current
Figure 13. Efficiency vs Load Current
Figure 15. Efficiency vs Load Current
Figure 12. Efficiency vs Input Voltage
VOUT = 3.3 V
VOUT = 3.3 V
Figure 14. Efficiency vs Input Voltage
VOUT = 1.8 V
VOUT = 1.8 V
Figure 16. Efficiency vs Input Voltage
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VOUT = 0.9 V
VOUT = 0.9 V
Figure 17. Efficiency vs Load Current
Figure 18. Efficiency vs Input Voltage
Figure 19. Output Voltage vs Output Current (Load
regulation)
Figure 20. Output Voltage vs Input Voltage (Line
regulation)
Figure 21. Maximum Output Current vs Input Voltage
Figure 22. Switching Frequency vs Output Current
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Figure 23. Startup into 33 Ω (100 mA)
Figure 25. Startup into 0.5 Ω (6.6 A)
Figure 27. Typical Operation (PWM)
Figure 24. Startup into 1 Ω (3.3 A)
Figure 26. Output Discharge (No load)
IOUT = 3 A
IOUT = 100 mA
Figure 28. Typical Operation (PSM)
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Figure 29. Load Transient Response (PSM-PWM)
Figure 30. Load Transient Response (PWM-PWM)
VOUT = 1.8 V
COUT = 6x47 µF
VOUT = 1.8 V
COUT = 6x47 µF
additional CFF = 82
pF
Figure 31. Transient Response to a load step of 1-6A
(1A/µs)
Figure 32. Transient Response to a load step of 1-6A
(1A/µs)
RLOAD = 0.33 Ω
RLOAD = 0.33 Ω
Figure 33. HICCUP at Overload Condition
Figure 34. HICCUP at Overload Condition
22
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Figure 35. HICCUP at Short Circuit
Figure 36. HICCUP at Short Circuit
Figure 37. Maximum Ambient Temperature
space
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9.2.2 TPS62180 Low Profile Solution
This design example is based on Figure 10 again, providing a very small (see Figure 38) and low profile solution,
using low profile inductors.
9.2.2.1 Design Requirements
The input parameters used for this design are given in Table 7 and give a total solution size of about 72mm2,
using inductors with a maximum height of 1.2 mm:
space
Table 7. Components Used for Application Characteristics
REFERENCE NAME
TPS62180YZF
DESCRIPTION / VALUE
2 phase step down converter, 2 x 3 mm WCSP
Inductor DFE252012P, 1 µH ±20%, 2.5 x 2 x 1.2 mm
Ceramic capacitor GRM21BR61E226ME44, 2 x 22 µF, 25 V, X5R, 0805
Ceramic capacitor GRM21BR60J476ME15, 2 x 47 µF, 6.3 V, X5R, 0805
Ceramic capacitor, 10 nF
MANUFACTURER
Texas Instruments
Toko
L1, L2
CIN
muRata
COUT
CSS
R1
muRata
Standard
Chip resistor, value depending on VOUT
Standard
R2
Chip resistor, value depending on VOUT
Standard
R3
Chip resistor, 470 kΩ, 0603, 1/16 W, 1%
Standard
space
9.2.2.2 Detailed Design Procedure
As opposed to the previous example, the solution size, including height, is limited and the soft start time is
longer. This is achieved by using smaller inductors, as well as using a different soft start capacitor.
9.2.2.2.1 Inductor
Using Table 5, the 1-µH DFE252012P is chosen with dimensions of 2.5 x 2.0 x 1.2 mm. The larger DCR of 42
mΩ maximum causes some efficiency drop (see comparison below).
space
Figure 39. Efficiency vs Inductor Size/Type
Figure 38. Ultra Small Solution Size
space
24
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9.2.2.2.2 Input and Output Capacitors
Since electrical design parameters are unchanged, the same values as chosen in the previous example are used
for these capacitors.
9.2.2.2.3 Soft Start Capacitor
Using Equation 14 again, and inserting tSS = 2.5 ms gives a capacitance of 10 nF, which is chosen.
9.2.2.2.4 Using the Accurate EN Threshold
The TPS6218x provides a very accurate EN threshold voltage. This can be used to switch on the device
according to a VIN or another voltage level by using a resistive divider as shown below.
space
VIN
VIN
REN1
EN
REN2
Figure 40. Resistive Divider for Controlled EN Threshold
space
The values of REN1 and REN2, needed to set EN = High at a specific VIN can be calculated according to
Kirchhoff's laws, shown in Equation 15 and used in the following example:
space
REN1 + REN 2
VIN =VEN _threshold
×
REN 2
(15)
space
For a typical 8-V input rail, the device turn on target value is set to 5.5 V. The current through the resistive divider
is set to 10 µA, which indicates a total resistance of about 800 kΩ. Appropriate standard resistor values, fitting
Equation 15, are REN1 = 680 kΩ and REN2 = 150 kΩ. As a result, the device switches on, when VIN has reached
5.5 V and the current through the divider is 9.6 µA. The device switches off at a threshold of 0.9 V. Using
Equation 15 again, this case gives a level of VIN = 5.0 V.
Figure 47 to Figure 50 show thresholds and appropriate device behavior with a startup time of about 800 µs.
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9.2.2.3 Application Performance Curves
VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
Figure 41. Efficiency vs Load Current
Figure 42. Efficiency vs Input Voltage
VIN = 8 V, IOUT = 4 A
Figure 43. Typical Operation (PWM)
CSS = 10 nF
Figure 44. Startup into 1 Ω (3.3 A)
Figure 45. Load Transient Response (PSM-PWM)
Figure 46. Load Transient Response (PWM-PWM)
26
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VIN = 5.5 V (Rising), VIN = 5.0 V (Falling)
Figure 47. Accurate EN Threshold
Figure 48. Accurate EN Threshold Showing VOUT
VIN = 5.5 V (Rising)
VIN = 5.0 V (Falling)
Figure 49. Accurate EN Threshold
Figure 50. Accurate EN Threshold
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9.3 TPS62180 Output Voltage Application Examples
This section provides typical schematics for commonly used output voltage values.
9.3.1 Application Schematic Examples
space
22µF
1µH
1µH
VIN1
VIN2
SW1
SW2
VO
0.9V/6A
4 to 15 V
470k
22µF
TPS62180
4x
47µF
PG
FB
EN
20k
SS/TR
GND
160k
3.3nF
Copyright © 2017, Texas Instruments Incorporated
Figure 51. 0.9-V/6-A Power Supply
space
22µF
22µF
3.3nF
1µH
VIN1
SW1
SW2
VO
1.8V/6A
4 to 15 V
1µH
VIN2
470k
TPS62180
2x
47µF
PG
FB
EN
200k
160k
SS/TR
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 52. 1.8-V/6-A Power Supply
space
28
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
www.ti.com.cn
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
TPS62180 Output Voltage Application Examples (continued)
22µF
1µH
1µH
VIN1
VIN2
SW1
SW2
VO
3.3V/6A
4 to 15 V
470k
22µF
TPS62180
2x
47µF
PG
FB
EN
470k
150k
SS/TR
GND
3.3nF
Copyright © 2017, Texas Instruments Incorporated
Figure 53. 3.3-V/6-A Power Supply
space
22µF
22µF
3.3nF
1µH
VIN1
SW1
SW2
VO
5V/6A
(4) to 15 V
1µH
VIN2
470k
TPS62180
4x
47µF
PG
FB
EN
430k
82k
SS/TR
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 54. 5-V/6-A Power Supply
9.3.2 Design Requirements
Based on Figure 10, the schematics shown in Figure 51 through Figure 54 show different output voltage divider
values to get different VOUT. Another design target is to have about 5-µA current through the divider.
9.3.3 External Component Selection
The values for the voltage divider are derived using the procedure given in Programming the Output Voltage.
While Equation 10 and Equation 11 are used to calculate R2 and R1, the values are aligned with standard
resistor values.
Copyright © 2014–2017, Texas Instruments Incorporated
29
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
10 Power Supply Recommendations
The TPS6218x are designed to operate from a 4-V to 15-V input voltage supply. The input power supply's output
current needs to be rated according to the output voltage and the output current of the power rail application.
30
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62180, TPS62182
www.ti.com.cn
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
11 Layout
11.1 Layout Guidelines
The PCB layout of the TPS6218x demands careful attention to ensure proper operation, thermal profile, low
noise emission and to achieve best performance. A poor layout can lead to issues like poor regulation, stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity. While the TPS6218x provides very high
power density, the PCB layout also contributes significantly to the thermal performance.
11.1.1 PCB Layout
A recommended PCB layout for the TPS62180 dual phase solution is shown below. It ensures best electrical and
optimized thermal performance considering the following important topics:
•
•
•
•
The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides
low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the VIN
connection, to avoid interference between the input lines.
The SW node connection from the IC to the inductor conducts high currents. It should be kept short and can
be designed in parallel with an internal or bottom layer plane, to provide low resistance and enhanced thermal
behavior.
The VOUT regulation loop is closed with COUT and its ground connection. If a ground layer or plane is used, a
direct connection by vias, as shown, is recommended. Otherwise the connection of COUT to GND must be
short for good load regulation.
The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB pin,
avoiding long trace distance. Using the TPS62182 (fixed output voltage version), the FB pin can be left
floating, but it is good practice and recommended to connect it to AGND for best thermal characteristics.
11.2 Layout Example
space
L1
VOUT
C3
C1
C2
R1
VIN
R2
C5
GND
C4
VOUT
L2
Figure 55. TPS62180 Board Layout
版权 © 2014–2017, Texas Instruments Incorporated
31
TPS62180, TPS62182
ZHCSCQ4B –AUGUST 2014–REVISED MAY 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的
快速链接。
表 8. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPS62180
TPS62182
12.3 商标
AEE, NanoFree are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
32
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62180YZFR
TPS62180YZFT
TPS62182YZFR
TPS62182YZFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
YZF
YZF
YZF
YZF
24
24
24
24
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ELC180
Samples
Samples
Samples
Samples
SNAGCU
SNAGCU
SNAGCU
ELC180
ELC182
ELC182
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62180YZFR
TPS62180YZFT
TPS62182YZFR
TPS62182YZFT
DSBGA
DSBGA
DSBGA
DSBGA
YZF
YZF
YZF
YZF
24
24
24
24
3000
250
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
2.25
2.25
2.25
2.25
3.25
3.25
3.25
3.25
0.81
0.81
0.81
0.81
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62180YZFR
TPS62180YZFT
TPS62182YZFR
TPS62182YZFT
DSBGA
DSBGA
DSBGA
DSBGA
YZF
YZF
YZF
YZF
24
24
24
24
3000
250
335.0
335.0
335.0
335.0
335.0
335.0
335.0
335.0
25.0
25.0
25.0
25.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0024
DSBGA - 0.625 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
0.35
0.15
BALL TYP
1.5 TYP
SYMM
F
E
D
C
SYMM
2.5
TYP
D: Max = 3.13 mm, Min = 3.07 mm
E: Max = 2.13 mm, Min = 2.07 mm
B
A
0.5
TYP
4
2
1
3
0.35
24X
0.015
0.25
C A B
0.5 TYP
4219412/A 01/2019
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0024
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
1
24X ( 0.245)
(0.5) TYP
4
2
3
A
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:28X
0.05 MAX
0.05 MIN
(
0.245)
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
(
0.245)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219412/A 01/2019
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0024
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
24X ( 0.25)
2
3
4
1
A
(0.5)
TYP
B
C
METAL
TYP
SYMM
D
E
F
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219412/A 01/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS62182
4V 至 15V、6A 超小型两相同步降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Photo Transistor, PHOTO TRANSISTOR DETECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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