TPS62441-Q1 [TI]
具有可调频率的汽车类 2.75V 至 6V 双路 1A 输出降压转换器;
| 型号： | TPS62441-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调频率的汽车类 2.75V 至 6V 双路 1A 输出降压转换器 转换器 |
| 文件： | 总36页 (文件大小：3085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62441-Q1, TPS62442-Q1
ZHCSPB1B – NOVEMBER 2021 – REVISED JULY 2022
TPS6244x-Q1 具有可调频率并采用 QFN 封装的 2.75V 至 6V 双路降压转换器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准
– 器件温度等级 1：
TPS6244x-Q1 系列是引脚对引脚双路 1A、双路 2A
或 3A 和 1A 高效且易于使用的同步直流/直流降压转
换器。它们基于峰值电流模式控制拓扑，这些器件专为
信息娱乐系统和高级驾驶辅助系统等汽车应用而设计。
低阻开关可在高环境温度下支持高达 3A 的持续输出电
流和高达 4A 的最大总输出电流。用户可通过外部方式
在 1.8MHz 至 4MHz 范围内调节开关频率，亦可在该
频率范围内将其同步至频率为 2MHz 至 4MHz 的外部
时钟。在 PWM 和 PFM 模式下，TPS6244x-Q1 会在
轻负载时自动进入省电模式，从而在整个负载范围内保
持高效率。TPS6244x-Q1 可在 PWM 模式下提供 1%
的输出电压精度，这有助于实现具有高输出电压精度的
电源设计。
–40°C 至 +125°C TA
•
提供功能安全型
– 可帮助进行功能安全系统设计的文档
输入电压范围：2.75V 至 6V
双通道输出，输出电压范围为 0.6V 至 5.5V
输出电压精度为 ±1%（PWM 操作）
强制 PWM 或 PWM 和 PFM 操作
可调开关频率为
•
•
•
•
•
1.8MHz 至 4MHz
•
两个精密使能输入可实现：
– 用户定义的欠压锁定
– 准确排序
TPS6244x-Q1 提供了可调节电压版本，采用 VQFN 封
装。
•
•
•
•
•
•
•
•
具有窗口比较器的两个电源正常输出
180° 相移运行
器件信息
100% 占空比模式
器件型号
封装(1)
封装尺寸（标称值）
有源输出放电
TPS62441-Q1
TPS62442-Q1
可选展频时钟
VQFN-HR
2.30 mm × 2.70 mm
可选折返过流保护
TJ = -40°C 至 +150°C
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
具有可湿性侧面的 2.3mm × 2.7mm QFN 封装
录。
2 应用
•
•
•
•
•
ADAS 摄像头和 ADAS 传感器融合
环视 ECU
混合和可重新配置仪表组
信息娱乐系统音响主机和数字驾驶舱
远程信息处理控制单元
L1
VIN
100
95
90
85
80
75
70
65
60
55
TPS6244x-Q1
VOUT1
0.47µH
2.75V - 6V
VIN1
VIN2
EN1
SW1
FB1
CFF1
COUT1
2 x 10µF
CIN1, CIN2
R1
R2
2 x 4.7 µF
EN2
L2
MODE/SYNC
0.47µH
VOUT2
SW2
CFF2
V+
R3
COUT2
FB2
PG1
2 x 10µF
R4
COMP/FSET
R5
RCF
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
50
V+
45
R6
40
100m
1m
10m
Load (A)
100m
1
PG2
D000
GND
GND
效率与输出电流间的关系；VOUT = 3.3V；PWM 和
PFM；fSW = 2.25MHz
Copyright © 2019, Texas Instruments Incorporated
原理图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDN9
TPS62441-Q1, TPS62442-Q1
ZHCSPB1B – NOVEMBER 2021 – REVISED JULY 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements..................................................7
7.7 Typical Characteristics................................................7
8 Parameter Measurement Information............................8
8.1 Schematic................................................................... 8
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram...........................................9
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................12
10 Application and Implementation................................14
10.1 Application Information........................................... 14
10.2 Typical Application.................................................. 16
11 Power Supply Recommendations..............................25
12 Layout...........................................................................25
12.1 Layout Guidelines................................................... 25
12.2 Layout Example...................................................... 26
13 Device and Documentation Support..........................27
13.1 Device Support....................................................... 27
13.2 Documentation Support.......................................... 27
13.3 接收文档更新通知................................................... 27
13.4 支持资源..................................................................27
13.5 Trademarks.............................................................27
13.6 Electrostatic Discharge Caution..............................27
13.7 术语表..................................................................... 27
14 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2022) to Revision B (July 2022)
Page
•
Removed preview note.......................................................................................................................................3
Changes from Revision * (November 2021) to Revision A (June 2022)
Page
•
将文档状态从“预告信息”更改为“量产数据”..........................................................................................................1
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5 Device Comparison Table
Device Number
Features
Foldback Current Limit
Output Voltage
2 × 1-A output current
VOUT discharge
TPS62441QWRQRRQ1
OFF
OFF
Adjustable
2 × 2-A or 3-A and 1-A output
current
TPS62442QWRQRRQ1
Adjustable
VOUT discharge
6 Pin Configuration and Functions
Top view
GND
9
EN2
10
EN1
8
VIN1
7
6
5
4
VIN2 11
SW2
12
SW1
MODE
/SYNC
PG2 13
COMP
/FSET
14
PG1
1
3
2
FB2
GND
FB1
图 6-1. 14-Pin VQFN-HR RQR Package
表 6-1. Pin Functions
Pin
Type(1)
Description
Name
NO.
This pin is the enable pin of converter 1. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN1
8
I
I
This pin is the enable pin of converter 2. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN2
10
FB1
FB2
3
1
I
Voltage feedback input for converter 1. Connect the resistive output voltage divider to this pin.
Voltage feedback input for converter 2. Connect the resistive output voltage divider to this pin.
Open-drain power-good output of converter 1
I
PG1
PG2
SW1
SW2
4
O
O
13
6
Open-drain power-good output of converter 2
This pin is the switch pin of converter 1 and is connected to the internal power MOSFETs.
This pin is the switch pin of converter 2 and is connected to the internal power MOSFETs.
12
The device runs in PFM and PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can also
be used to synchronize the device to an external frequency. See the electrical characteristics for the
detailed specification for the digital signal applied to this pin for external synchronization.
MODE/SYNC
5
I
Device compensation and frequency set input. A resistor from this pin to GND defines the
compensation of the control loop as well as the switching frequency if not externally synchronized.
Do not leave this pin floating.
COMP/FSET
VIN1
14
7
I
Power supply input. Make sure the input capacitor is connected as close as possible between pin
VIN1 and GND. Connect VIN1 to VIN2.
—
Power supply input. Make sure the input capacitor is connected as close as possible between pin
VIN2 and GND. Connect VIN2 to VIN1.
VIN2
GND
11
—
—
2, 9
Ground pins. The GND pins are internally connected.
(1) I = input; O = output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
6.5
UNIT
VIN1, VIN2
SW1, SW2 (DC)
VIN + 0.3
10
SW1, SW2 (AC, less than 10 ns)(3)
Pin voltage(2)
FB1, FB2
V
–0.3
–0.3
– .3
–65
4
PG1, PG2, COMP/FSET
EN1, EN2, MODE/SYNC
VIN + 0.3
6.5
Tstg
Storage temperature
150
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground pin.
(3) While switching
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN1, VIN2 Input voltage range
2.75
6
V
VOUT1
VOUT2
,
Output voltage range
0.6
0.32
8
5.5
0.9
V
L1, L2
Effective inductance
0.47
10
μH
μF
COUT1
COUT2
,
Effective output capacitance(1)
200
CIN1, CIN2 Effective input capacitance on each pin(1)
RCF
10
μF
kΩ
mA
°C
4.5
0
100
2
ISINK_PG
TJ
Sink current at PG pin
Junction temperature
–40
150
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer's DC bias curves for the effective capacitance versus DC voltage applied. Further restrictions can apply. Please see the
feature description for COMP/FSET for the output capacitance versus compensation setting and output voltage.
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7.4 Thermal Information
(JEDEC)
14 PINS
68.7
(EVM)
UNIT
THERMAL METRIC(1)
14 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53.9
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50.8
15.1
n/a
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.5
1.9
ΨJB
14.9
20.1
n/a
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and
TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN1 or EN2 = VIN, no load, device is not
switching, TJ = 25°C, MODE = GND, one
converter enabled
IQ
Quiescent current
27
66
38
80
µA
µA
µA
µA
EN1 or EN2 = VIN, no load, device is not
switching, MODE = GND, one converter
enabled
IQ
IQ
IQ
Quiescent current
Quiescent current
Quiescent current
22
EN1 = EN2 = VIN, no load, device is not
switching, TJ = 25°C, MODE = GND, both
converters enabled
EN1 = EN2 = VIN, no load, device is not
switching, MODE = GND, both converters
enabled
33
ISD
ISD
Shutdown current
Shutdown current
EN1 = EN2 = low, at TJ = 25°C
2
µA
µA
EN1 = EN2 = GND, nominal value at TJ =
25°C, maximum value at TJ = 150°C
1.5
26
VIN rising
VIN falling
TJ rising
TJ falling
2.5
2.3
2.6
2.5
170
15
2.75
2.6
V
V
VUVLO
Undervoltage lockout threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
CONTROL AND INTERFACE
Input-threshold voltage at EN1, EN2,
rising edge
VEN,IH
1.06
0.96
1.1
1.0
1.15
V
Input-threshold voltage at EN1, EN2,
falling edge
VEN,IL
IEN,LKG
VIH
1.05
450
V
nA
V
Input leakage current into EN1, EN2
VIH = VIN or VIL = GND
High-level input-threshold voltage at
MODE/SYNC
1.1
Low-level input-threshold voltage at
MODE/SYNC
VIL
0.3
700
300
V
ILKG
tDelay
Input leakage current into MODE/SYNC
Enable delay time
nA
µs
Time from ENx high to device starts
switching, VIN applied already
110
200
100
Enable delay time if one converter
already enabled
Time from ENx high to device starts
switching, VIN applied already
tDelay
µs
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7.5 Electrical Characteristics (continued)
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and
TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time from device starts switching to
power good; the device is not in current
limit
tRamp
Output voltage ramp time
0.7
1.1
1.5
ms
Frequency range on MODE/SYNC pin for
synchronization
fSYNC
2
0
4
MHz
kΩ
V
Resistance from COMP/FSET to GND for Internal frequency setting with
logic low
2.5
f = 2.25 MHz
Internal frequency setting with
f = 2.25 MHz
Voltage on COMP/FSET for logic high
VIN
96.5%
94.5%
107%
UVP power-good threshold voltage;
DC level
VTH_PG
VTH_PG
Rising (%VFB
)
94%
92%
99%
97%
UVP power-good threshold voltage;
DC level
Falling (%VFB
)
)
OVP power-good threshold voltage;
DC level
Rising (%VFB
)
104%
110%
107%
VTH_PG
OVP power-good threshold voltage;
DC level
Falling (%VFB
102% 104.5%
0.07
VPG,OL
IPG,LKG
Low-level output voltage at PG
Input leakage current into PG
ISINK_PG = 2 mA
VPG = 5 V
0.3
V
100
nA
For a high-level to low-level transition on
the power-good output
tPG
PG deglitch time
40
µs
OUTPUT
VFB1
VFB2
,
Feedback voltage
0.6
V
IFB1,LKG,
IFB2,LKG
Input leakage current into FB
Feedback voltage accuracy
Feedback voltage accuracy
Feedback voltage accuracy
VFB = 0.6 V
1
80
1%
nA
VFB1
,
,
,
PWM, VIN ≥ VOUT + 1 V
–1%
VFB2
VFB1
VFB2
PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.5 V,
Co,eff ≥ 22 µF, L = 0.47 µH
–1%
2.5%
2.5%
VFB1
VFB2
PFM, VIN ≥ VOUT + 1 V, 1 V ≤ VOUT < 1.5
V, Co,eff ≥ 47 µF, L = 0.47 µH
–1%
Load regulation
PWM
0.05
0.02
50
%/A
%/V
Ω
Line regulation
PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V
RDIS
fSW
fSW
fSW
Output discharge resistance
150
4
See the FSET pin functionality about
setting the switching frequency.
PWM switching frequency range
PWM switching frequency
1.8
2.025
–16%
2.25
2.25
MHz
MHz
With COMP/FSET tied to GND or VIN
2.475
17%
75
Using a resistor from COMP/FSET to
GND
PWM switching frequency tolerance
ton,min
ton,min
Minimum on time of high-side FET
Minimum on time of low-side FET
High-side FET on-resistance
VIN ≥ 3.3 V
50
30
55
25
1
ns
ns
VIN ≥ 5 V
100
50
mΩ
mΩ
µA
µA
RDS(ON)
Low-side FET on-resistance
VIN ≥ 5 V
High-side MOSFET leakage current
Low-side MOSFET leakage current
VIN = 6 V; V(SW) = 0 V
V(SW) = 6 V
86
1
205
DC value, for the TPS62442;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
3.8
4.7
5.5
A
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7.5 Electrical Characteristics (continued)
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and
TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC value, for the TPS62441;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
Low-side FET negative current limit
2.1
2.6
3.1
A
ILIMNEG
DC value
–1.8
A
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Synchronization clock frequency range
(MODE/SYNC)
Nominal fSW determined through COMP/
FSET
fSW
10%
+
fSW +
40%
f(SYNC)
MHz
Synchronization clock duty cycle range
(MODE/SYNC)
D(SYNC)
45%
55%
7.7 Typical Characteristics
105
40
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
-40.0
-10.0
20.0
Junction Temperature (°C)
50.0
80.0
110.0
140.0
-40.0
-10.0
20.0
Junction Temperature (°C)
50.0
80.0
110.0
140.0
D020
D021
图 7-1. Rds(on) of High-Side Switch
图 7-2. Rds(on) of Low-Side Switch
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8 Parameter Measurement Information
8.1 Schematic
L1
VIN
TPS6244x-Q1
VOUT1
0.47µH
2.75V - 6V
VIN1
VIN2
EN1
SW1
FB1
CFF1
COUT1
2 x 10µF
CIN1, CIN2
2 x 4.7 µF
R1
R2
EN2
L2
MODE/SYNC
0.47µH
VOUT2
SW2
CFF2
V+
R3
COUT2
FB2
PG1
2 x 10µF
R4
COMP/FSET
R5
RCF
V+
R6
PG2
GND
GND
Copyright © 2019, Texas Instruments Incorporated
图 8-1. Measurement Setup
表 8-1. List of Components
Reference
IC
Description
Manufacturer(1)
TPS62442QWRQRRQ1
Texas Instruments
L1, L2
CIN1, CIN2
COUT1, COUT2
RCF
2 × 0.47-µH inductor DFE252012PD-R47M-P2
2 × 4.7 µF / 6.3 V
2 × 10 µF / 6.3 V
8.06 kΩ
Murata
Murata
Murata
Any
CFF1, CFF2
R1
10 pF
Any
Depending on VOUT
Depending on VOUT
Depending on VOUT
Depending on VOUT
100 kΩ
Any
R2
Any
R3
Any
R4
Any
R5, R6
Any
(1) See the Third-Party Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS6244x-Q1 synchronous dual switch mode power converters are based on a peak current mode control
topology. The control loop is internally compensated. To optimize the bandwidth of the control loop to the
wide range of output capacitance that can be used with TPS6244x-Q1, the internal compensation has two
settings. See 节 9.3.2. One out of the two compensation settings is chosen either by a resistor from COMP/
FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation
with small external components and low-ESR ceramic output capacitors. The devices can be operated without
a feedforward capacitor on the output voltage divider, however, using a typically 10-pF feedforward capacitor
improves transient response.
The devices support forced fixed-frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN or in a
range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 2 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. External synchronization can only be used when there is a resistor
from COMP/FSET to GND. When COMP/FSET is directly tied to GND or VIN, the TPS6244x-Q1 cannot be
synchronized externally. The TPS6244x-Q1 allows for a change from internal clock to external clock during
operation. When the MODE pin is set to a logic low level, the device operates in power save mode (PFM) at
low output current and automatically transfers to fixed frequency PWM mode at higher output current. In PFM
mode, the switching frequency decreases linearly based on the load to sustain high efficiency down to very low
output current. When a converter switches from PFM to PWM operation, there can be a maximum delay of one
clock cycle because in this case, the converter has to synchronize to the other converter to achieve 180 degrees
phase shift.
9.2 Functional Block Diagram
VIN
SW1
Bias
Regulator
Gate Drive and Control
Oscillator
Ipeak
Izero
EN1
EN2
gm
GND
FB1
Device
Control
+
-
Bandgap
Vo control
SW2
MODE
COMP/FSET
PG1
Gate Drive and Control
Ipeak
Izero
PG2
gm
+
-
Bandgap
FB2
Vo control
Thermal
Shutdown
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9.3 Feature Description
9.3.1 Precise Enable (EN)
The voltage applied at EN1 and EN2 is compared to a 1.1-V fixed threshold for a rising voltage, which allows the
user to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve a
power-up delay.
The precise enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of EN1 and EN2.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS6244x-Q1 starts operation when the rising threshold is exceeded. For proper operation, the enable (EN) pin
must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown, with
a shutdown current of typically 1.5 μA. In this mode, the internal high-side and low-side MOSFETs are turned off
and the entire internal control circuitry is switched off.
The enable delay time is defined from EN1 or EN2 going high to when the converter starts switching. The
converter is enabled first, the internal bandgap is started, and bias currents and configuration bits are read, so its
start-up delay time is longer than the converter being enabled when this is already done.
9.3.2 COMP/FSET
This pin allows to set three different parameters:
•
•
•
Internal compensation settings for the control loop (two settings available)
The switching frequency in PWM mode from 1.8 MHz to 4 MHz
Enable and disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows the user to adopt the device to different values of output capacitance. Place the resistor
close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is sampled
at start-up of the converter, so a change in the resistor during operation only has an effect on the switching
frequency, but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not
leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on time and minimum off time.
Example: VIN = 5 V, VOUT = 1 V --> duty cycle = 1 V / 5 V = 0.2
•
•
--> ton,min = 1 / fs × 0.2
--> fsw,max = 1 / ton,min × 0.2 = 1 / 0.075 µs × 0.2 = 2.67 MHz
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in 表 9-1, up to the maximum of 200-µF effective capacitance in
both compensation ranges. If the capacitance of an output changes during operation, for example, when load
switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the
minimum capacitance on the output. With large output capacitance, the compensation must be done based on
that large capacitance to get the best load transient response. Compensating for large output capacitance but
placing less capacitance on the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
Space
18 MHz ì kW
RCF kW =
- 0.18 k
(
)
fs MHz
(1)
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
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Space
60 MHz ì kW
RCF kW =
- 0.6 k
(
)
fs MHz
(2)
Space
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
Space
180 MHz ì kW
RCF kW =
- 1.8 k
(
)
fs MHz
(3)
表 9-1. Switching Frequency, Compensation, and Spread Spectrum Clocking
Minimum Output
Capacitance
Minimum Output
Capacitance
Minimum Output
Capacitance
RCF
Compensation
Switching Frequency
For VOUT < 1 V
For VOUT < 3.3 V
For VOUT ≥ 3.3 V
for smallest output capacitance
(comp setting 1)
1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)
10 kΩ .. 4.5 kΩ
33 kΩ .. 18 kΩ
11 µF
11 µF
7 µF
7 µF
5 µF
5 µF
according to 方程式 1
SSC disabled
for smallest output capacitance
(comp setting 1)
1.8 MHz (33 kΩ) .. 4 MHz (18 kΩ)
according to 方程式 2
SSC enabled
for best transient response
(larger output capacitance)
(comp setting 2)
1.8MHz (100 kΩ) ..4 MHz (45 kΩ)
100 kΩ .. 45 kΩ
tied to GND
tied to VIN
30 µF
11 µF
30 µF
18 µF
7 µF
15 µF
5 µF
according to 方程式 3
SSC disabled
for smallest output capacitance
(comp setting 1)
internally fixed 2.25 MHz
internally fixed 2.25 MHz
SSC disabled
for best transient response
(larger output capacitance)
(comp setting 2)
18 µF
15 µF
SSC enabled
Refer to 节 10.1.2.2.2 for further details on the output capacitance required depending on the output voltage.
A too-high resistor value for RCF is decoded as "tied to VIN," a value below the lowest range as "tied to GND."
The minimum output capacitance in 表 9-1 is for capacitors close to the output of the device. If the capacitance is
distributed, a lower compensation setting can be required.
9.3.3 MODE/SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The
MODE/SYNC pin allows the user to force PWM mode when set high. The pin also allows the user to apply an
external clock in a frequency range from 2 MHz to 4 MHz for external synchronization. Similar to COMP/FSET,
the specifications for the minimum on time and minimum off time have to be observed when setting the external
frequency. The external synchronization frequency applied on the MODE/SYNC pin must be 10% to 40% higher
than the nominal internal switching frequency set by RCF (calculated with 方程式 1 to 方程式 3). Ensuring
this makes sure that, if the external clock fails, the converter can continue normal operation with the internal
switching frequency in a range where the compensation settings are still valid. When there is no resistor from
COMP/FSET to GND but the pin is pulled high or low, external synchronization is not possible. If the device
is externally synchronized, both converters are forced to run on that clock frequency preserving 180° phase
relation. The internally generated spread spectrum clocking is turned off while running on an external clock.
9.3.4 Spread Spectrum Clocking (SSC)
The device offers spread spectrum clocking as an option. When SSC is enabled, the switching frequency is
modulated in a triangular manner when in PWM mode using the internal clock. The frequency variation is
typically between the nominal switching frequency and up to 20% above the nominal switching frequency set
by RCF. When the device is externally synchronized by applying a clock signal to the MODE/SYNC pin, the
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TPS6244x-Q1 follows the external clock and the internal spread spectrum block is turned off. SSC is also
disabled during soft start and PFM mode.
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both
the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power-Good Output (PG)
Power good is an open-drain output driven by a window comparator. PG is held low when the device is:
•
•
•
•
Disabled
In undervoltage lockout
In thermal shutdown
In soft start
When the output voltage is in regulation hence, within the window defined in the electrical characteristics, the
output is high impedance.
表 9-2. PG Status
EN
X
Device Status
PG State
undefined
low
VIN < 2 V
low
VIN ≥ 2 V
2 V ≤ VIN ≤ UVLO OR in thermal shutdown OR VOUT is not in
regulation OR device in soft start
high
high
low
VOUT in regulation
high impedance
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds
170°C (typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs of both
converters are turned off and PG goes low. When TJ decreases below the hysteresis amount of typically 20°C,
the converters resume normal operation, beginning with soft start. When both converters are in a PFM pause,
the thermal shutdown is not active. After the PFM pause, the device needs up to 9 µs to detect a too high
junction temperature. If the PFM burst is shorter than this delay, the device does not detect a too high junction
temperature. As long as one converter is in PWM, thermal shutdown is always active.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS6244x-Q1 has two operating modes. Forced PWM mode is discussed in this section and PWM and
PFM as discussed in 节 9.4.2.
With the MODE/SYNC pin set to high, the TPS6244x-Q1 operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the
TPS6244x-Q1 follows the frequency applied to the pin. The frequency needs to be in a range the device can
operate at, taking the minimum on time into account.
9.4.2 Power Save Mode Operation (PWM and PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of approximately 0.8 A. When the peak inductor current
drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time
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of 30 ns (typical) is reached, the TPS6244x-Q1 skips switching cycles while it approaches 100% mode. In 100%
mode, the device keeps the high-side switch on continuously. The high-side switch stays turned on as long as
the output voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum dropout
voltage in 100% mode is the product of the on-resistance of the high-side switch plus the series resistance of the
inductor and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS6244x-Q1 is protected against overload and short circuit events. The converter is not switching with the
fixed frequency when in current limit. The converter resumes the fixed-frequency operation when the converter
leaves current limit condition. If the inductor current exceeds the current limit, ILIMH, the high-side switch is turned
off and the low-side switch is turned on to ramp down the inductor current. The high-side switch turns on again
only if the current in the low-side switch has decreased below the low-side current limit, which can cause bursts
or single pulses between the high-side and low-side current limit. Due to internal propagation delay, the actual
current can exceed the static current limit. The dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
×tPD
(4)
where
•
•
•
•
ILIMH is the static current limit as specified in the electrical characteristics.
L is the effective inductance at the peak current.
VL is the voltage across the inductor (VIN – VOUT).
tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V
IN -VOUT
Ipeak(typ) = ILIMH
+
×50ns
L
(5)
9.4.5 Foldback Current Limit and Short Circuit Protection
Foldback current limit and short circuit protection are valid for devices where foldback current limit is enabled.
When the TPS6244x-Q1 detects current limit for more than 1024 subsequent switching cycles, the device
reduces the current limit from its nominal value to typically 1.3 A (TPS62441-Q1) and 1.45 A (TPS62442-Q1).
Foldback current limit is left when the current limit indication goes away. If device operation continues in current
limit, it would, after 3072 switching cycles, try again for full current limit for 1024 switching cycles.
9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the
device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output
discharge feature is only active once the TPS6244x-Q1 has been enabled at least once since the supply voltage
was applied. The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or
in undervoltage lockout. The minimum supply voltage required for the discharge function to remain active is
typically 2 V. Output discharge is not activated during a current limit or foldback current limit event.
9.4.7 Soft Start
The internal soft-start circuitry controls the output voltage slope during start-up, which avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN1 and EN2 are set high, the device starts switching after tDelay
.
The output voltage is ramped with a slope defined by tRamp
.
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS6244x-Q1 is adjustable. The device can be programmed for output voltages from
0.6 V to 5.5 V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The
value of the output voltage is set by the selection of the resistor divider from 方程式 6. Choose resistor values
that allow a current of at least 6 µA, meaning the value of R2 must not exceed 100 kΩ. Lower resistor values are
recommended for the highest accuracy and most robust design.
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(6)
10.1.2 External Component Selection
10.1.2.1 Inductor Selection
The TPS6244x-Q1 is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.
Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on
efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple, which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly.
The inductor selection is affected by several effects like the following:
•
•
•
•
Inductor ripple current
Output ripple voltage
PWM-to-PFM transition point
Efficiency
In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). 方
程式 7 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(7)
(8)
V
OUT
æ
ö
V
1-
OUT × ç
÷
IN
1
V
è
Lmin
ø
DIL(max)
=
×
f
SW
where
•
•
•
IL(max) is the maximum inductor current.
ΔIL(max) is the peak-to-peak inductor ripple current.
Lmin is the minimum inductance at the operating point.
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表 10-1. Typical Inductors
Nominal Switching
Dimensions
[L × B × H] mm
Inductance [µH]
Current [A](1)
For Device
Manufacturer(2)
Frequency
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
XEL3520-801ME
XEL3520-561ME
XEL3515-561ME
XFL3012-681ME
XPL2010-681ML
0.80 µH, ±20%
0.56 µH, ±20%
0.56 µH, ±20%
0.68 µH, ±20%
0.68 µH, ±20%
2.0
2.4
4.5
2.1
1.5
TPS62441-Q1
TPS62441-Q1
TPS62442-Q1
TPS62441-Q1
TPS62441-Q1
3.5 × 3.2 × 2.0
3.5 × 3.2 × 2.0
3.5 × 3.2 × 1.5
3.0 × 3.0 × 1.2
2 × 1.9 × 1
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
DFE252012PD-
R68M
0.68 µH, ±20%
0.47 µH, ±20%
0.68 µH, ±20%
0.47 µH, ±20%
see data sheet
see data sheet
see data sheet
see data sheet
TPS62442-Q1
TPS62442-Q1
TPS62441-Q1
TPS62442-Q1
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.5 × 2 × 1.2
2.5 × 2 × 1.2
2 × 1.6 × 1.2
2 × 1.6 × 1.2
Murata
Murata
Murata
Murata
DFE252012PD-
R47M
DFE201612PD-
R68M
DFE201612PD-
R47M
(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.
(2) See the Third-Party Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. TI recommends adding a margin of approximately 20%. A larger inductor value is
also useful to get lower ripple current, but increases the transient response time and size as well.
10.1.2.2 Capacitor Selection
10.1.2.2.1 Input Capacitor
For most applications, 10-µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.2.2.2 Output Capacitor
The architecture of the TPS6244x-Q1 allows the use of tiny ceramic output capacitors with low-equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, use X7R or X5R
dielectric. Using a higher value has advantages like smaller voltage ripple and a tighter DC output accuracy in
power save mode. By changing the device compensation with a resistor from COMP/FSET to GND, the device
can be compensated in three steps based on the minimum capacitance used on the output. The maximum
capacitance is 200 µF in any of the compensation settings.
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10.2 Typical Application
L1
VIN
TPS6244x-Q1
VOUT1
0.47µH
2.75V - 6V
VIN1
VIN2
EN1
SW1
FB1
CFF1
COUT1
2 x 10µF
CIN1, CIN2
R1
R2
2 x 4.7 µF
EN2
L2
MODE/SYNC
0.47µH
VOUT2
SW2
CFF2
V+
R3
COUT2
FB2
PG1
2 x 10µF
R4
COMP/FSET
R5
RCF
V+
R6
PG2
GND
GND
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图 10-1. Typical Application Schematic
10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
10.2.2 Detailed Design Procedure
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(9)
With VFB = 0.6 V:
表 10-2. Setting the Output Voltage
Nominal Output Voltage VOUT
R1, R3
R2, R4
51 kΩ
30 kΩ
47 kΩ
68 kΩ
51 kΩ
40.2 kΩ
15 kΩ
19.6 kΩ
CFF1, CFF2
Exact Output Voltage
0.8 V
1.0 V
1.1 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
16.9 kΩ
20 kΩ
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
0.7988 V
1.0 V
39.2 kΩ
68 kΩ
1.101 V
1.2 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
1.5 V
1.803 V
2.5 V
3.315 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless otherwise noted.
The BOM is according to 表 8-1.
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D000
D002
D004
D001
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图 10-2. Efficiency vs Output Current
图 10-3. Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
VIN = 2.75 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D003
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图 10-4. Efficiency vs Output Current
图 10-5. Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
VIN = 2.75 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D005
VOUT = 1.2 V
PFM
TA = 25°C
VOUT = 1.2 V
PWM
TA = 25°C
图 10-6. Efficiency vs Output Current
图 10-7. Efficiency vs Output Current
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10.2.3 Application Curves (continued)
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D006
D007
VOUT = 1.0 V
PFM
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图 10-8. Efficiency vs Output Current
图 10-9. Efficiency vs Output Current
90
85
80
75
70
65
60
55
50
45
40
85
80
75
70
65
60
55
50
45
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
100m
1m
10m
Load (A)
100m
1
1
2
3
Load (A)
D008
D009
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图 10-10. Efficiency vs Output Current
图 10-11. Efficiency vs Output Current
3.36
3.35
3.34
3.33
3.32
3.31
3.3
3.36
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.29
3.28
3.27
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Ouput Current (A)
1
100m
1m
10m 100m
Ouput Current (A)
1
D010
D011
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图 10-12. Output Voltage vs Output Current
图 10-13. Output Voltage vs Output Current
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10.2.3 Application Curves (continued)
1.84
1.836
1.832
1.828
1.824
1.82
1.84
1.836
1.832
1.828
1.824
1.82
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.816
1.812
1.816
1.812
1.808
1.804
1.8
1.808
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.804
1.8
1.796
1.792
1.796
1.792
100m
1m
10m 100m
Ouput Current (A)
1
100m
1m
10m 100m
Ouput Current (A)
1
D012
D014
D016
D013
D015
D017
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图 10-14. Output Voltage vs Output Current
图 10-15. Output Voltage vs Output Current
1.2275
1.225
1.2225
1.22
1.21
1.2075
1.205
1.2025
1.2
1.2175
1.215
1.2125
1.21
1.1975
1.195
1.1925
1.19
1.2075
1.205
1.2025
1.2
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.1875
1.185
1.1825
1.1975
1.195
1.1925
100m
1m
10m
Ouput Current (A)
100m
1
100m
1m
10m
Ouput Current (A)
100m
1
VOUT = 1.2 V
PFM
TA = 25°C
VOUT = 1.2 V
PWM
TA = 25°C
图 10-16. Output Voltage vs Output Current
图 10-17. Output Voltage vs Output Current
1.03
1.0275
1.025
1.0225
1.02
1.0075
1.005
1.0025
1
0.9975
0.995
0.9925
0.99
1.0175
1.015
1.0125
1.01
0.9875
0.985
0.9825
0.98
0.9775
0.975
0.9725
0.97
1.0075
1.005
1.0025
1
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
0.9975
0.995
0.9925
0.9675
100m
1m
10m
Ouput Current (A)
100m
1
100m
1m
10m
Ouput Current (A)
100m
1
VOUT = 1.0 V
PFM
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图 10-18. Output Voltage vs Output Current
图 10-19. Output Voltage vs Output Current
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10.2.3 Application Curves (continued)
0.634
0.63
0.606
0.605
0.604
0.603
0.602
0.601
0.6
0.626
0.622
0.618
0.614
0.61
0.599
0.598
0.597
0.596
0.595
0.594
0.606
0.602
VIN = 2.75 V
VIN = 3.3 V
VIN = 2.75 V
VIN = 3.3 V
VIN = 4.0 V
0.598
VIN = 4.0 V
0.594
100m
1m
10m 100m
Ouput Current (A)
1
100m
1m
10m 100m
Ouput Current (A)
1
D018
D019
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图 10-20. Output Voltage vs Output Current
图 10-21. Output Voltage vs Output Current
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图 10-23. Load Transient Response
图 10-22. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图 10-24. Load Transient Response
图 10-25. Load Transient Response
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10.2.3 Application Curves (continued)
VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图 10-26. Load Transient Response
图 10-27. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图 10-28. Load Transient Response
图 10-29. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图 10-31. Load Transient Response
图 10-30. Load Transient Response
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10.2.3 Application Curves (continued)
VOUT = 3.3 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 3.3 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图 10-33. Line Transient Response
图 10-32. Line Transient Response
VOUT = 1.8 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.8 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图 10-35. Line Transient Response
图 10-34. Line Transient Response
VOUT = 1.2 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.2 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图 10-37. Line Transient Response
图 10-36. Line Transient Response
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10.2.3 Application Curves (continued)
VOUT = 1.0 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 1.0 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图 10-39. Line Transient Response
图 10-38. Line Transient Response
VOUT = 0.6 V
IOUT = 3 A
PWM
TA = 25°C
VOUT = 0.6 V
IOUT = 0.3 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图 10-41. Line Transient Response
图 10-40. Line Transient Response
VOUT = 3.3 V
IOUT = 3 A
图 10-43. Output Voltage Ripple
PWM
TA = 25°C
VOUT = 3.3 V
IOUT = 0.3 A
图 10-42. Output Voltage Ripple
PFM
TA = 25°C
VIN = 5.0 V
BW = 20 MHz
VIN = 5.0 V
BW = 20 MHz
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10.2.3 Application Curves (continued)
VOUT = 1.8 V
IOUT = 3 A
PWM
TA = 25°C
VIN = 5.0 V
BW = 20 MHz
VOUT = 1.2 V
IOUT = 0.4 A
TA = 25°C
VIN = 3.3 V
图 10-44. Output Voltage Ripple
图 10-45. Switching Waveform in PFM Mode
VOUT = 3.3 V
IOUT = 3 A
PWM
TA = 25°C
VOUT1/2 = 1.8 V
IOUT1 = 2 A
PWM
TA = 25°C
VIN = 5.0 V
VIN = 5.0 V
图 10-46. Start-Up Timing
IOUT2 = 2 A
图 10-47. Start-Up Timing
VOUT1/2 = 1.2 V
IOUT1 = 1 A
PWM
TA = 25°C
VIN = 5.0 V
VOUT = 1.0 V
IOUT1 = 3 A
图 10-49. Start-Up Timing
PWM
TA = 25°C
IOUT2 = 3 A
VIN = 5.0 V
图 10-48. Start-Up Timing
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10.2.3 Application Curves (continued)
VOUT = 0.6V
PWM
TA = 25°C
VIN = 5.0 V
IOUT1 = 3 A
图 10-50. Start-Up Timing
11 Power Supply Recommendations
The TPS6244x-Q1 device family has no special requirements for its input power supply. The output current of
the input power supply needs to be rated according to the supply voltage, output voltage, and output current of
the TPS6244x-Q1.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS6244x-Q1 demands careful attention to ensure operation and
to get the performance specified. A poor layout can lead to issues like the following:
•
•
•
•
Poor regulation (both line and load)
Stability and accuracy weaknesses
Increased EMI radiation
Noise sensitivity
See 图 12-1 for the recommended layout of the TPS6244x-Q1, which is designed for common external ground
connections. The input capacitor should be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes)
for wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible
to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops that
conduct an alternating current must outline an area as small as possible, as this area is proportional to the
energy radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,
SW). As they carry information about the output voltage, nodes must be connected as close as possible to the
actual output voltage (at the output capacitor). The FB resistors, R1 and R2, as well as R3 and R4 must be kept
close to the IC and connect directly to those pins and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread
the heat into the PCB.
The recommended layout is implemented on the EVM and shown in the TPS62442EVM-122 User's Guide.
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12.2 Layout Example
图 12-1. Example Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, TPS62442EVM-122 User's Guide
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62441QWRQRRQ1
TPS62442QWRQRRQ1
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RQR
RQR
14
14
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
441QW
442QW
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
OTHER QUALIFIED VERSIONS OF TPS62442-Q1 :
Catalog : TPS62442
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62441QWRQRRQ1 VQFN-
HR
RQR
RQR
14
14
3000
3000
180.0
8.4
2.6
3.0
1.2
4.0
8.0
Q1
TPS62442QWRQRRQ1 VQFN-
HR
180.0
8.4
2.6
3.0
1.2
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62441QWRQRRQ1
TPS62442QWRQRRQ1
VQFN-HR
VQFN-HR
RQR
RQR
14
14
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RQR 14
2.3 x 2.7, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229224/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQR0014A
2.4
2.2
A
B
PIN 1 INDEX AREA
2.8
2.6
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.5
0.525
0.325
5X
(0.8 MIN)
0.875
2X
(0.2) TYP
0.675
4
7
4X (0.2 MIN)
10X 0.5
3
1
8
(0.16)
PKG
1
10
0.575
0.375
6X
0.3
0.2
14X
0.1
0.05
C A B
C
11
14
0.125
∠45°
1.125
0.925
4225624/B 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQR0014A
(2.075)
(1.225)
(0.7375)
14
11
(R0.05) TYP
2X (0.975)
1
3
10
PKG
(2.425) (2.125)
8
14X (0.25)
7
4
6X (0.675)
5X (0.625)
10X (0.5)
LAND PATTERN EXAMPLE
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225624/B 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271)
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQR0014A
(2.075)
(1.225)
(0.7375)
14
11
(R0.05) TYP
2X (0.975)
1
3
10
PKG
(2.425) (2.125)
8
14X (0.25)
7
4
6X (0.675)
5X (0.625)
10X (0.5)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 18X
4225624/B 02/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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