TPS62736 [TI]
Programmable Output Voltage Ultra-Low Power Buck Converter with up to 50mA / 200 mA Output Current; 可编程输出电压超低功耗降压转换器，具有高达50mA / 200 mA输出电流
| 型号： | TPS62736 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Programmable Output Voltage Ultra-Low Power Buck Converter with up to 50mA / 200 mA Output Current |
| 文件： | 总35页 (文件大小：1835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62736
TPS62737
www.ti.com
SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
Programmable Output Voltage Ultra-Low Power Buck Converter with up to 50mA / 200 mA
Output Current
Check for Samples: TPS62736, TPS62737
1
FEATURES
APPLICATIONS
•
Industry's highest efficiency at low output
currents: > 90% with IOUT = 15 µA
•
•
Ultra Low Power Applications
2-Cell and 3-Cell Alkaline-Powered
Applications
•
Ultra-Low Power Buck Converter
–
–
–
TPS62736 Optimized for 50 mA Output
Current
•
•
•
•
•
•
•
•
•
•
Energy Harvesting
Solar Charger
TPS62737 Optimized for 200mA Output
Current
Thermal Electric Generator (TEG) Harvesting
Wireless Sensor Networks (WSN)
Low Power Wireless Monitoring
Environmental Monitoring
1.3 V – 5 V Resistor Programmable Output
Voltage Range
–
–
2 V – 5.5 V Input Operating Range
Bridge and Structural Health Monitoring (SHM)
Smart Building Controls
380 nA / 375 nA Quiescent Current During
Active Operation for TPS62736 / TPS62737
Portable and Wearable Health Devices
Entertainment System Remote Controls
–
–
10 nA Quiescent Current During Ship Mode
Operation
2% Voltage Regulation Accuracy
100
TPS62736
95
•
•
100% Duty Cycle (Pass Mode)
EN1 and EN2 Control
90
85
80
75
70
–
Two Power off states:
–
–
1) Shipmode (full power off state)
2) Standby mode includes VIN_OK
Indication
•
Input Power Good Indication (VIN_OK)
65
Test Conditions:
V
T
= 2.5V, V = 3V,
IN
O
–
–
Push-pull Driver
60
55
= 25oC, L = 10mH (Toko DFE252012C)
A
Resistor Programmable Threshold Level
0.001
0.01
0.1
Iout (mA)
1
10
100
G000
ꢀꢀ> 90% at
IOUT = 15 PA
L
10 PH
VIN
SW
OUT
IN
VOUT
4.7ꢀF
22PF
TPS62736
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS62736
TPS62737
SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TPS6273X family provides a highly integrated ultra low power buck converter solution that is well suited for
meeting the special needs of ultra low power applications such as energy harvesting. The TPS6273X provides
the system with an externally programmable regulated supply in order to preserve the overall efficiency of the
power management stage compared to a linear step down converter. This regulator is intended to step down the
voltage from an energy storage element such as a battery or super capacitor in order to supply the rail to low
voltage electronics. The regulated output has been optimized to provide high efficiency across low output
currents (<10 µA) to high currents (200 mA).
The TPS6273X integrates an optimized hysteretic controller for low power applications. The internal circuitry
utilizes a time based sampling system in order to reduce the average quiescent current.
To further assist users in the strict management of their energy budgets, the TPS6273X toggles the input power
good indicator to signal an attached microprocessor when the voltage on the input supply has dropped below a
pre-set critical level. This signal is intended to trigger the reduction of load currents to prevent the system from
entering an under-voltage condition. There are also independent enable signals to allow the system to control
whether the converter is regulating the output, only monitoring the input voltage, or shut down in an ultra-low
quiescent sleep state.
The input power good threshold and output regulator levels are programmed independently via external resistors.
All the capabilities of TPS6273X are packed into a small foot-print 14-lead 3.5mm x 3.5 mm QFN package
(RGY).
ORDERING INFORMATION
ORDERING
NUMBER (TAPE
AND REEL)
OUTPUT
VOLTAGE
MAX OUTPUT
CURRENT
INPUT
UVLO
PACKAGE
MARKING
TA
PART NO.
QUANTITY
TPS62736RGYR
TPS62736RGYT
TPS62737RGYR
TPS62737RGYT
3000
250
Resistor
Programmable
–40°C to 85°C
–20°C to 85°C
TPS62736(1)
TPS62737(1)
50 mA
2 V
2V
TPS62736
TPS62737
3000
250
Resistor
Programmable
200 mA
(1) The RGY package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE(2)
UNIT
MIN
MAX
Input voltage range on IN, EN1, EN2, VRDIV, VIN_OK_SET,
VOUT_SET, VIN_OK, OUT, SW,NC
Pin voltage
–0.3
5.5
V
TPS62736
TPS62737
TJ
Peak currents
IN, OUT
100
370
125
150
1
mA
mA
°C
°C
kV
V
Peak currents
IN, OUT
Temperature range
Operating junction temperature range
Storage temperature range
–40
–65
TSTG
Human Body Model - (HBM)
Machine Model (MM)
ESD(3)
150
500
Charge Device Model - (CDM)
V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS/ground terminal
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
2
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
THERMAL INFORMATION
RGY
UNITS
14-Pins
THERMAL METRIC(1)
θJA
Junction-to-ambient thermal resistance
33.7
37.6
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
10.1
°C/W
0.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
10.3
2.9
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
2
NOM
MAX
UNIT
IN
IN voltage range
5.5
V
TPS62736 Input Capacitance
TPS62737 Input Capacitance
Output Capacitance
4.7
22
10
CIN
COUT
μF
μF
22
13
10
R1
R2
R3
+
+
Total Resistance for setting reference voltage
MΩ
μH
TPS62736 Inductance
4.7
10
LBUCK
TPS62737 Inductance
TPS62736 Operating free air ambient temperature
TPS62737 Operating free air ambient temperature
Operating junction temperature
–40
–20
–40
85
85
TA
TJ
°C
°C
105
ELECTRICAL CHARACTERISTICS
Over recommended ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for conditions of VIN = 4.2 V, VOUT = 1.8 V External components, CIN = 4.7 µF for TPS62736 and 22 µF for TPS62737 , LBUCK
= 10 µH, COUT = 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
TPS62736 Buck enabled state
(EN1 = 0, EN2 = 1)
380
550
TPS62736 Buck disabled VIN_OK active state
(EN1 = 0, EN2 = 0)
nA
340
10
520
65
TPS62736 Ship mode state (EN1 = 1, EN2 = x)
IQ
VIN = 2 V, No load on VOUT
TPS62737 Buck enabled state
(EN1 = 0, EN2 = 1)
375
600
TPS62737 Buck disabled VIN_OK active state
(EN1 = 0, EN2 = 0)
nA
345
11
560
45
TPS62737 Ship mode state (EN1 = 1, EN2 = x)
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for conditions of VIN = 4.2 V, VOUT = 1.8 V External components, CIN = 4.7 µF for TPS62736 and 22 µF for TPS62737 , LBUCK
= 10 µH, COUT = 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VBIAS
Output regulation reference
1.205
–2%
1.21
0%
1.217
2%
V
IOUT = 10 mA;
1.3 V < VOUT < 3.3 V
TPS62736 Output regulation (Spec does not include
the resistor accuracy error)
IOUT = 100 mA;
1.3 V < VOUT < 3.3 V;
TPS62737 Output regulation (Spec does not include
the resistor accuracy error)
–2%
0%
0.01
0.31
0.01
0.01
20
2%
IOUT = 100 µA;
VIN = 2.4 V to 5.5 V
TPS62736 Output line regulation
TPS62737 Output line regulation
TPS62736 Output load regulation
TPS62737 Output load regulation
TPS62736 Output ripple
%/V
IOUT = 10 mA;
VIN = 2.3 V to 5.5 V
IOUT = 100 µA to 50 mA,
VIN = 2.2 V
VOUT
%/mA
%/mA
mVpp
mVpp
V
IOUT = 100 µA to 200 mA,
VIN = 2.2 V; -20 °C < TA < 85°C
VIN = 4.2V, IOUT = 1 mA,
COUT = 22 μF
VIN = 4.2V, IOUT = 1 mA,
COUT = 22 μF
TPS62737 Output ripple
40
Programmable voltage range for output voltage
threshold
IOUT = 10 mA
1.3
VIN - 0.2
30
VIN = 2.1 V, VOUT(SET) = 2.5 V,
IOUT = 10 mA, 100% duty cycle
TPS62736 Drop-out-voltage when VIN is less than
VOUT(SET)
24
mV
VDO
VIN = 2.1 V, VOUT(SET) = 2.5 V,
IOUT = 100 mA, 100% duty cycle
TPS62737 Drop-out-voltage when VIN is less than
VOUT(SET)
180
220
mV
TPS62736, COUT = 22 µF
TPS62737, COUT = 22 µF
COUT = 22 µF
400
300
100
μs
μs
Startup time with EN1 low and EN2 transition to high
(Standby Mode)
tSTART-STBY
tSTART-SHIP
Startup time with EN2 high and EN1 transition from
high to low (Ship Mode)
ms
POWER SWITCH
TPS62736 High side switch ON resistance
VIN = 3 V
2.4
1.1
1.8
0.9
3
1.5
2.2
1.3
Ω
Ω
Ω
Ω
TPS62736 Low side switch ON resistance
TPS62737 High side switch ON resistance
TPS62737 Low side switch ON resistance
VIN = 3 V
RDS(on)
VIN = 2.1 V
VIN = 2.1 V
2.4 V < VIN < 5.25 V;
1.3 V < VOUT < 3.3 V
TPS62736 Cycle-by-cycle current limit
68
86
100
370
mA
ILIM
2.4 V < VIN < 5.25 V;
1.3 V < VOUT < 3.3 V;
-20 °C < TA < 85°C
TPS62737 Cycle-by-cycle current limit
Max switching frequency
295
340
2
mA
fSW
MHz
INPUT
VIN-UVLO
VIN-OK
Input under voltage protection
VIN falling
1.91
2
1.95
2
5.5
2
V
V
Input power good programmable voltage range
TPS62736 Accuracy of VIN-OK setting
TPS62737 Accuracy of VIN-OK setting
Fixed hysteresis on VIN_OK threshold, OK_HYST
VIN-OK output high threshold voltage
VIN-OK output low threshold voltage
VIN increasing
-2
%
VIN-OK-ACC
-3
3
VIN-OK-HYS
VIN_OK-OH
VIN_OK-OL
EN1 and EN2
VIH
VIN increasing
Load = 10 µA
40
mV
V
VIN - 0.2
VIN - 0.2
0.1
0.2
V
Voltage for EN High setting. Relative to VIN
Voltage for EN Low setting.
V
V
VIN = 4.2V
VIL
4
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
PIN ASSIGNMENTS
TPS62736 RGY PACKAGE
(TOP VIEW)
1
14
2
3
4
5
6
13
12
SW
NC
NC
VSS
11 OUT
NC
10
EN1
VIN_OK
VOUT_SET
9
EN2
7
8
PIN DESCRIPTION
PIN
NO. NAME
I/O Type
Input
Description
1
2
3
4
5
IN
Input supply to the buck regulator
Connect to VSS
NC
NC
NC
EN1
Input
Input
Connect to VSS
Input
Connect to VSS
Input
Digital input for chip enable, standby, and ship-mode. EN1 = 1 sets ship mode independent of
EN2. EN1=0, EN2 = 0 disables the buck converter and sets standby mode. EN1=0, EN2=1
enables the buck converter. Do not leave either pin floating.
6
EN2
Input
7
VRDIV
Output
Input
Resistor divider biasing voltage
8
VIN_OK_SET
VOUT_SET
VIN_OK
OUT
Resistor divider input for VIN_OK threshold. Pull to VIN to disable. Do not leave pin floating.
Resistor divider input for VOUT regulation level
Push-pull digital output for power good indicator for the input voltage. Pulled up to VIN pin.
Step down (buck) regulator output
9
Input
10
11
12
13
14
15
Output
Output
Input
VSS
Ground connection for the device
SW
Input
Inductor connection to switching node
NC
Input
Connect to VSS
Thermal Pad
Input
Connect to VSS
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TPS62737 RGY PACKAGE
(TOP VIEW)
1
14
2
3
4
5
6
13
12
SW
SW
VSS
NC
VSS
11 OUT
10
EN1
VIN_OK
VOUT_SET
9
EN2
7
8
PIN DESCRIPTION
PIN
NO. NAME
IN
I/O Type
Input
Description
1
Input supply to the buck regulator
Inductor connection to switching node
Ground connection for the device
Connect to VSS
2, 13 SW
3, 12 VSS
4, 14 NC
Input
Input
Input
5
6
EN1
EN2
Input
Digital input for chip enable, standby, and ship-mode. EN1 = 1 sets ship mode independent of
EN2. EN1=0, EN2 = 0 disables the buck converter and sets standby mode. EN1=0, EN2=1
enables the buck converter. Do not leave either pin floating.
Input
7
8
VRDIV
Output
Input
Resistor divider biasing voltage
VIN_OK_SET
VOUT_SET
VIN_OK
Resistor divider input for VIN_OK threshold. Pull to VIN to disable. Do not leave pin floating.
Resistor divider input for VOUT regulation level
Push-pull digital output for power good indicator for the input voltage. Pulled up to VIN pin.
Step down (buck) regulator output
9
Input
10
11
15
Output
Output
Input
OUT
Thermal Pad
Connect to VSS
6
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
FUNCTIONAL BLOCK DIAGRAM
IN
VSS
SW
OUT
Buck
Controller
EN2
VIN > UV?
TPS6273x Functional Block
Diagram
VOUT_SET
VIN_OK
VIN_OK_SET
+
Input Threshold Control
OK
Vref
Nano-Power Management
and Reference Generation
Vref
VIN_UV
EN1
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TYPICAL APPLICATION SCHEMATIC
TPS62736
L
10 PH
IN
SW
VIN
System Load
C
IN1
C
IN2
OUT
4.7PF 0.1PF
COUT
22PF
Buck
Controller
GPIO1
VIN_OK
EN1
VSS
Host
GPIO2
GPIO2
EN2
VRDIV
R3
VOUT_SET
Nano-Power
Management
R2
R1
VIN_OK_SET
Figure 1. Typical Application Circuit for a 3-resistor String
TPS62737
L
10 PH
IN
SW
VIN
System Load
C
IN1
C
IN2
OUT
22PF 0.1PF
COUT
22PF
Buck
Controller
GPIO1
VIN_OK
EN1
VSS
Host
GPIO2
GPIO2
EN2
VRDIV
R3
VOUT_SET
Nano-Power
Management
R2
R1
VIN_OK_SET
Figure 2. Typical Application Circuit
8
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
TPS62736
L
10 PH
IN
SW
VIN
System Load
C
IN1
C
IN2
OUT
4.7PF 0.1PF
COUT
22PF
Buck
Controller
GPIO1
VIN_OK
EN1
VSS
Host
GPIO2
GPIO2
EN2
VRDIV
R3
VOUT_SET
Nano-Power
Management
R2
R1
VIN_OK_SET
R4
Figure 3. Typical Application Circuit for a 4-resistor String
TPS62736
L
10 PH
IN
SW
VIN
System Load
C
IN1
C
IN2
OUT
4.7PF 0.1PF
COUT
22PF
Buck
Controller
GPIO1
VIN_OK
EN1
VSS
Host
GPIO2
GPIO2
EN2
VRDIV
R3
R4
VOUT_SET
Nano-Power
Management
VIN_OK_SET
VIN
Figure 4. Typical Application Circuit for Disabling VIN_OK
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TYPICAL CHARACTERISTICS
Table of Graphs for TPS62736
Unless otherwise noted, graphs were taken using Figure 1 with L = Toko 10 µH DFE252012C
FIGURE
vs. Output Current
VO = 2.5 V Efficiency
Figure 5
Figure 6
vs. Input Voltage
vs. Output Current
VO = 1.8 V Efficiency
Figure 7
η
vs. Input Voltage
Figure 8
vs. Output Current
VO = 1.3 V Efficiency
Figure 9
vs. Input Voltage
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
vs. Output Current
VO = 2.5 V
VO = 1.8 V
VO = 1.3 V
vs. Input Voltage
vs. Temperature
vs. Output Current
vs. Input Voltage
vs. Temperature
vs. Output Current
vs. Input Voltage
vs. Temperature
VOUT (DC)
VO = 2.5 V
IOUT MAX (DC)
Input IQ
VO = 1.8 V
vs. Input Voltage
vs. Input Voltage
VO = 1.3 V
EN1 = 1, EN2 = 0 (Ship Mode)
EN1 = 0, EN2 = 0 (Standby Mode)
EN1 = 0, EN2 = 1 (Active Mode)
vs. Output Current
vs. Input Voltage
vs.Output Current
vs. Input Voltage
RO = 50 Ω
Switching Frequency
Output Ripple
VO = 2.5 V
VO = 2.5 V
VIN = 3 V, VO = 2.5 V
Steady State Operation
RO = 100 kΩ
VIN = 3 V, VO = 1.8 V, L = 4.7 µH
VRDIV Behavior
RO = 50 Ω
Power Management Response
VO = 2.5 V
Line Transient, VIN = 3.0V -> 5.0V,
ROUT = 50 Ω
Figure 35
Figure 36
Load Transient, VIN = 4.0V, ROUT
=
Transient Response
Startup Behavior
VO = 2.5 V
none -> 50 Ω
IR Pulse Transient, VIN = 4.0V, 200mA
transient every 1us
Figure 37
Figure 38
Figure 39
EN1 1 to 0, EN2=1 - Ship mode startup
VIN = 4.0 V, VO = 1.8 V
EN1 = 0, EN2 0 to 1 - Standy mode
startup
10
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
100
95
90
85
80
75
70
65
60
55
50
100
98
96
94
92
90
88
IO = 0.1 mA
IO =1mA
IO = 10 mA
IO = 45 mA
V=4.2V
IN
Test Conditions:
VO = 2.5 V, TA = 25C
L = 10 µH (Toko DFE252012C)
Test Conditions:
VO = 2.5 V, TA = 25C
L = 10 µH (Toko DFE252012C
V
V
V
= 3.6 V
IN
= 3 V
= 2.7 V
IN
IN
0.001
0.01
0.1
IOUT (mA)
1
10
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C001
C002
VIN (V)
Figure 5. Efficiency Vs Output Current, VOUT = 2.5 V
Figure 6. Efficiency vs Input Voltage, VOUT = 2.5 V
100
100
98
96
94
92
90
88
86
84
IO =0.1mA
95
90
85
80
75
70
65
60
55
50
45
40
Test Conditions:
VO = 1.8 V, TA = 25C
L = 10 µH (Toko DFE252012C)
I
= 1 mA
O
I
= 10 mA
O
I
= 45 mA
O
VIN =4.2V
VIN =3.6V
VIN =3V
Test Conditions:
VO = 1.8 V, TA = 25C
L = 10 µH (Toko DFE252012C)
VIN =2.1V
0.001
0.01
0.1
IOUT (mA)
1
10
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C003
C004
VIN (V)
Figure 7. Efficiency Vs Output Current, VOUT = 1.8 V
Figure 8. Efficiency vs Input Voltage, VOUT = 1.8 V
100
100
98
96
94
92
90
88
86
84
82
80
IO =0.1mA
IO = 1 mA
IO = 10 mA
IO = 45 mA
95
90
85
80
75
70
65
60
55
50
45
40
35
30
Test Conditions:
VO = 1.3 V, TA = 25C
L = 10 µH (Toko DFE252012C)
VIN=4.2V
Test Conditions:
VO = 1.3 V, TA = 25C
L = 10 µH (Toko DFE252012C)
V
V
V
= 3.6 V
IN
= 3 V
IN
= 2.1 V
IN
0.001
0.01
0.1
IOUT (mA)
1
10
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C00
C006
VIN (V)
Figure 9. Efficiency Vs Output Current, VOUT = 1.3 V
Figure 10. Efficiency vs Input Voltage, VOUT = 1.3 V
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2.520
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
2.515
2.510
2.505
IO = 0.1 mA
IO =1mA
IO =10mA
IO =45mA
VIN = 4.2 V
Test Conditions:
VO = 2.5 V, TA = 25C
Test Conditions:
VO = 2.5 V, TA = 25C
L = 10 µH (Toko DFE252012C)
2.500
2.495
VIN=3.6V
V
V
= 3 V
L = 10 µH (Toko DFE252012C)
IN
= 2.7 V
IN
0.001
0.01
0.1
IOUT (mA)
1
10
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C007
C008
VIN (V)
Figure 11. Output Voltage vs Output Current. VOUT = 2.5 V
Figure 12. Output Voltage vs Input Voltage, VOUT = 2.5 V
2.525
1.805
Test Conditions:
VO = 2.5 V, VIN = 3 V
2.520
1.800
1.795
1.790
1.785
1.780
L = 10 µH (Toko DFE252012C)
2.515
2.510
2.505
2.500
I
= 1 mA
O
VIN =4.2V
2.495
2.490
2.485
Test Conditions:
VO = 1.8 V, TA = 25C
L = 10 µH (Toko DFE252012C)
V
V
V
= 3.6 V
IN
= 3 V
IN
= 2.7 V
IN
I
= 10 mA
O
I
= 50 mA
O
±40
±20
0
20
40
60
80
0.001
0.01
0.1
IOUT (mA)
1
10
100
C009
C010
Temperature (C)
Figure 13. Output Voltage vs Temperature, VOUT = 2.5 V
Figure 14. Output Voltage vs Output Current,
VOUT = 1.8 V
1.815
1.805
1.8
IO =0.1mA
= 1 mA
Test Conditions:
VO = 1.8 V, VIN = 3 V
L = 10 µH (Toko DFE252012C)
I
O
1.81
1.805
1.8
I
= 10 mA
O
= 45 mA
I
O
1.795
1.79
1.785
1.78
1.795
1.79
Test Conditions:
VO = 1.8 V, TA = 25C
L = 10 µH (Toko DFE252012C)
I
= 1 mA
O
1.785
1.78
I
= 10 mA
O
I
= 50 mA
O
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
±40
±20
0
20
40
60
80
C011
C012
VIN (V)
Temperature (C)
Figure 15. Output Voltage vs Input Voltage, VOUT = 1.8 V
Figure 16. Output Voltage vs Temperature, VOUT = 1.8 V
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1.303
SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
1.305
1.3
1.301
1.299
1.295
1.29
1.285
1.28
1.297
1.295
1.293
V
V
V
V
= 4.2 V
IN
IO =1mA
IO = 10 mA
IO = 0.1 mA
Test Condition:
VO = 1.3 V, TA = 25C
L = 10 µH (Toko DFE252012C)
Test Conditions:
VO = 1.3 V, TA = 25C
L = 10 uH (Toko DFE252012C)
= 3 V
IN
1.291
= 3.6 V
IN
IO = 45 mA
= 2.1 V
IN
1.289
0.001
0.01
0.1
IOUT (mA)
1
10
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C013
C014
VIN (V)
Figure 17. Output Voltage vs Output Current, VOUT = 1.3 V
Figure 18. Output Voltage vs Input Voltage, VOUT = 1.3 V
1.305
100
Test Conditions:
VO = 2.5 V ± 100 mV
L = 10 µH (Toko DFE252012C)
Test Conditions:
VO =1.3 V, VIN = 3 V
L = 10 µH (Toko DFE252012C)
80
60
40
20
0
1.300
1.295
1.290
TA = ±40C
I
= 1 mA
TA = 0C
O
T
T
= 25C
IO = 10 mA
A
I
= 50 mA
= 85C
O
A
1.285
-40
-20
0
20
40
60 80
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C015
C016
Temperature (C)
VIN (V)
Figure 19. Output Voltage vs Temperature, VOUT = 1.3 V
Figure 20. Maximum Output Current vs. Input Voltage
VOUT = 2.5 V
100
100
Test Conditions:
VO = 1.3 V ± 100 mV
L = 10 µH (Toko DFE252012C)
90
90
80
70
60
50
40
Test Conditions:
VO =1.8 V ± 100 mV
L = 10 µH (Toko DFE252012C)
80
70
60
50
40
TA=±40C
T=±40C
A
T
T
T
= 0C
T
T
T
= 0C
A
A
= 25C
= 25C
A
A
= 85C
= 85C
A
A
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C018
VIN (V)
C017
VIN (V)
Figure 21. Maximum Output Current vs. Input Voltage,
VOUT = 1.8 V
Figure 22. Maximum Output Current vs. Input Voltage,
VOUT = 1.3 V
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450
1200
1000
800
600
400
200
0
TA = 85°C
TA = 85°C
400
350
300
250
200
150
100
50
T
= 55°C
T
= 55°C
A
A
T=25°C
TA = 25°C
A
T
= 0°C
T= 0°C
A
A
T
= ±40°C
T
= ±40°C
A
A
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C019
C020
Input Voltage (V)
Input Voltage (V)
Figure 23. Input Quiescent Current vs. Input Voltage
Ship Mode
Figure 24. Input Quiescent Current vs. Input Voltage
Standby Mode
1200
1000
800
600
400
200
0
800
700
600
500
400
300
200
100
0
TA = 85°C
TA=55°C
T
R
= 1 Mꢀ
sum
R=13Mꢀ
sum
= 25°C
A
T
T
= 0°C
A
= ±40°C
A
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C021
C026
Input Voltage (V)
Input Voltage (V)
Figure 25. Input Quiescent Current vs. Input Voltage Active
Mode
Figure 26. Input Quiescent Current vs. Input Voltage Active
Mode where RSUM = R1+R2+R3
120
130
IOUT = 100 ꢀA
VO = 1.3 V
L = 10 PH
VO = 1.3 V
L = 10ꢀP+ꢀ
120
110
100
90
80
70
60
50
40
30
20
10
0
IOUT = 1 mA
100
IOUT = 10 mA
IOUT=50mA
80
60
40
20
0
V= 2 V
IN
V= 3 V
IN
V= 4 V
IN
VIN = 5 V
0
10
20
30
40
50
60
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C022
C023
Output Current (mA)
Input Voltage (V)
Figure 27. Major Switching Frequency vs Output Current
Figure 28. Major Switching Frequency vs Input Voltage
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
30
25
20
15
10
5
25
IOUT = 100 ꢀA
IOUT = 1 mA
20
15
10
5
IOUT = 10 mA
IOUT=50mA
V= 2 V
IN
V= 3 V
IN
VO = 1.3 V
C = 22 PF
V= 4 V
VO = 1.3 V
C = 22 PF
IN
VIN = 5 V
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
10
20
30
40
50
60
C024
C025
Input Voltage (V)
Output Current (mA)
Figure 29. Output Voltage Ripple vs Output Current
Figure 30. Output Voltage Ripple vs Input Voltage
IL
IL
VOUT-AC
SW
VOUT-AC
SW
10 Ps/div
2 Ps/div
Figure 31. Steady State Operation with RO = 50 Ω, L = 10 µH
Figure 32. Steady State Operation with RO = 100 kΩ, L = 10
µH
IL
VIN
VOUT-AC
VOUT
VRDIV
SW
2 ms/div
4 Ps/div
Figure 33. Steady State Operation with RO = 50 Ω and
Figure 34. Sampling Waveform
L = 4.7 µH
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VIN
IL
IOUT
VOUT-AC
SW
VOUT-AC
40 ms/div
Figure 35. Line Transient Response
10 Ps/div
Figure 36. Load Transient Response
IOUT
EN1
VOUT
VIN_OK
VOUT
SW
SW
20 ms/div
4 Ps/div
Figure 37. IR Pulse Transient Response
Figure 38. Ship-Mode Startup Behavior
EN2
VIN_OK
VOUT
SW
400 Ps/div
Figure 39. Standby-Mode Startup Behavior
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
Table of Graphs for TPS62737
Unless otherwise noted, graphs were taken using Figure 2 with L = Toko 10 µH DFE252012C
FIGURE
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 46
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 64
Figure 64
Figure 65
Figure 66
Figure 67
vs. Output Current
VO = 2.5 V Efficiency
vs. Input Voltage
vs. Output Current
VO = 1.8 V Efficiency
η
vs. Input Voltage
vs. Output Current
VO = 1.3 V Efficiency
vs. Input Voltage
vs. Output Current
VO = 2.5 V
VO = 1.8 V
VO = 1.3 V
vs. Input Voltage
vs. Temperature
vs. Output Current
vs. Input Voltage
vs. Temperature
vs. Output Current
vs. Input Voltage
vs. Temperature
VOUT (DC)
VO = 2.5 V
IOUT MAX (DC)
Input IQ
VO = 1.8 V
vs. Input Voltage
vs. Input Voltage
VO = 1.3 V
EN1 = 1, EN2 = 0 (Ship Mode)
EN1 = 0, EN2 = 0 (Standby Mode)
EN1 = 0, EN2 = 1 (Active Mode)
vs. Output Current
vs. Input Voltage
vs.Output Current
vs. Input Voltage
RO = 100 kΩ
Switching Frequency
Output Ripple
VO = 1.8 V
VO = 1.8 V
Steady State Operation
VIN = 3.6 V, VO = 1.8 V
VRDIV Behavior
RO = 9 Ω
Power Management Response
VO = 2.5 V
Load Transient, VIN = 3.6V, ROUT
none -> 9 Ω
=
Figure 68
Figure 69
VO = 1.8 V
Line Transient, VIN = 3.6V -> 4.6V,
ROUT = 9 Ω
Transient Response
Startup Behavior
IR Pulse Transient, VIN = 4.0V, 200mA
transient every 1us
VO = 2.5 V
Figure 70
Figure 71
Figure 72
VIN = 0 V to 5 V to 0 V, VO = 1.8 V
EN1 = 0, EN2=1
EN1 = 1 to 0, EN2=1 - Ship mode
startup
VIN = 3.6 V, VO = 1.8 V
EN1 = 0, EN2 0 to 1 - Standy mode
startup
Figure 73
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100.0
95.0
90.0
85.0
80.0
75.0
100
90
80
70
60
50
40
IO = 0.1 mA
IO = 1 mA
IO = 10 mA
IO=100mA
I
= 200 mA
O
I5
VIN = 3.0 V
V=4.2V
IN
V
= 5.5 V
IN
0.001
0.01
0.1
1
10
100
1000
2.5
3
3.5
4
4.5
5
5.5
C048
C045
IOUT (mA)
VIN (V)
Figure 40. Efficiency Vs Output Current, VOUT = 2.5 V
Figure 41. Efficiency vs Input Voltage, VOUT = 2.5 V
100
95
90
85
80
75
70
100
IO = 0.01 mA
IO = 0.1 mA
IO=1mA
IO=10mA
90
80
70
60
50
40
IO=100mA
IIO=200mA
VIN = 2.5 V
VIN = 3.0 V
VIN = 3.6 V
VIN=4.2V
VIN=5.5V
0.001
0.01
0.1
1
10
100
1000
2
3
4
5
6
C047
C044
IOUT (mA)
VIN (V)
Figure 42. Efficiency Vs Output Current, VOUT = 1.8 V
Figure 43. Efficiency vs Input Voltage, VOUT = 1.8 V
100
90
85
80
75
70
65
IO=0.1mA
IO=1mA
95
90
85
80
75
70
65
IO=10mA
I
= 100 mA
O
I
= 200 mA
O
60
55
50
45
40
VIN = 2.5 V
VIN = 3.0 V
VIN = 3.6 V
VIN=4.2V
VIN=5.5V
0.001
0.01
0.1
1
10
100
1000
2
3
4
5
6
C046
C043
IOUT (mA)
VIN (V)
Figure 44. Efficiency Vs Output Current, VOUT = 1.3 V
Figure 45. Efficiency vs Input Voltage, VOUT = 1.3 V
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2.53
SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
2.54
2.52
2.5
2.52
2.51
2.48
2.46
2.44
2.42
2.4
2.5
2.49
VIN = 3.0 V
2.48
IO = 0.001 mA
IO = 0.01 mA
VIN = 3.6 V
IO = 0.1 mA
IO=10mA
IO = 1 mA
IO = 100 mA
2.47
VIN = 4.2 V
2.38
2.36
V=5.5V
I
= 170 mA
I
= 200 mA
IN
O
O
2.46
0.001
0.01
0.1
1
10
100
1000
2.5
3
3.5
4
4.5
5
5.5
C061
C058
IOUT (mA)
VIN (V)
Figure 46. Output Voltage vs Output Current. VOUT = 2.5 V
Figure 47. Output Voltage vs Input Voltage, VOUT = 2.5 V
2.52
1.8
IO = 1 mA
1.795
2.51
1.79
1.785
1.78
2.50
IO = 10 mA
2.49
1.775
1.77
2.48
VIN = 2.5 V
IO = 100 mA
2.47
VIN = 3.0 V
1.765
1.76
IO = 180 mA
VIN = 3.6 V
2.46
2.45
VIN = 4.2 V
1.755
VIN = 5.5 V
1.75
0.001
0.01 0.1
1
10
100
1000
±20
±5
10
25
40
55
70
85
C020
Temperature (oC)
C060
IOUT (mA)
Figure 48. Output Voltage vs Temperature, VOUT = 2.5 V
Figure 49. Output Voltage vs Output Current,
VOUT = 1.8 V
1.81
1.8
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
IO = 1 mA
1.79
1.78
1.77
1.76
1.75
1.74
IO = 10 mA
IO = 0.001 mA
IO = 0.1 mA
IO = 10 mA
IO = 0.01 mA
IO = 1 mA
IO = 100 mA
1.73
1.72
1.71
IO = 100 mA
IO = 180 mA
70
I
= 170 mA
I
= 200 mA
O
O
2
3
4
5
±20
±5
10
25
40
55
85
C020
Temperature (oC)
C057
VIN (V)
Figure 50. Output Voltage vs Input Voltage, VOUT = 1.8 V
Figure 51. Output Voltage vs Temperature, VOUT = 1.8 V
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1.335
1.33
1.33
1.325
1.32
1.325
1.32
1.315
1.31
1.305
1.3
1.315
1.295
1.29
VIN = 2.5 V
1.31
1.305
1.3
VIN = 3.0 V
IO = 0.001 mA
IO = 0.01 mA
1.285
1.28
VIN = 3.6 V
IO = 0.1 mA
IO = 1 mA
VIN = 4.2 V
I
= 10 mA
I
= 100 mA
O
O
1.275
1.27
I
= 170 mA
I = 200 mA
O
VIN = 5.5 V
O
1.295
0.001
0.01 0.1
1
10
100
1000
2
3
4
5
C059
C056
IOUT (mA)
VIN (V)
Figure 52. Output Voltage vs Output Current, VOUT = 1.3 V
Figure 53. Output Voltage vs Input Voltage, VOUT = 1.3 V
1.325
300
280
260
240
220
200
180
IO = 1 mA
1.320
1.315
1.310
IO = 10 mA
1.305
1.300
1.295
TA = 85°C
TA = 55°C
1.290
160
140
120
100
IO = 100 mA
1.285
TA =25°C
TA =0°C
1.280
IO = 180 mA
55 70
T
= ±20°C
A
1.275
±20
±5
10
25
40
85
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C020
C020
Temperature (oC)
Input Voltage (V)
Figure 54. Output Voltage vs Temperature, VOUT = 1.3 V
Figure 55. Maximum Output Current vs. Input Voltage
VOUT = 2.5 V
330
280
230
180
330
280
230
180
130
80
TA = 85°C
TA = 55°C
TA = 85°C
TA = 55°C
130
80
TA =25°C
TA =0°C
TA =25°C
TA =0°C
T
= ±20°C
A
T
= ±20°C
A
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
C020
C020
Input Voltage (V)
Input Voltage (V)
Figure 56. Maximum Output Current vs. Input Voltage,
VOUT = 1.8 V
Figure 57. Maximum Output Current vs. Input Voltage,
VOUT = 1.3 V
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500
450
400
350
300
250
200
150
100
50
1,200
1,000
800
600
400
200
0
o
TA = 85 C
T
= 25oC
A
T
= 0oC
A
TA = -40oC
TA = 85oC
TA = 0oC
TA = 25oC
TA = -40oC
4.5
0
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
5
5.5
C054
C055
Input Voltage (V)
Input Voltage (V)
Figure 58. Input Quiescent Current vs. Input Voltage
Ship Mode
Figure 59. Input Quiescent Current vs. Input Voltage
Standby Mode
1,000
100
90
80
70
60
50
40
30
20
10
0
TA = 85oC
800
600
400
200
0
TA = 0oC
TA = 25oC
VIN = 2.45 V
VIN = 3.0 V
TA = -40oC
VIN = 4.2 V
VIN = 5.5 V
0
20
40
60
80 100 120 140 160 180 200
2
2.5
3
3.5
4
4.5
5
5.5
C053
C049
Output Current (mA)
Input Voltage (V)
Figure 60. Input Quiescent Current vs. Input Voltage Active
Mode
Figure 61. Major Switching Frequency vs Output Current
120
70
60
50
40
30
110
IO = 100 mA
100
90
80
70
60
50
40
30
20
10
0
IO = 5 mA
IO = 10 mA
VIN = 2.45 V
IO = 50 mA
20
10
0
IO = 500 PA
VIN = 3.0 V
VIN = 4.2 V
VIN = 5.5 V
0
20
40
60
80 100 120 140 160 180 200
2.1
2.6
3.1
3.6
4.1
4.6
5.1
C051
C050
Output Current (mA)
Input Voltage (V)
Figure 62. Major Switching Frequency vs Input Voltage
Figure 63. Output Voltage Ripple vs Output Current
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80
70
60
IL
VOUT
VIN
IO = 100 mA
IO = 10 mA
IO = 5 mA
SW
50
40
30
20
10
0
IL
VOUT
VIN
IO = 50 mA
SW
IO = 500 PA
2.1
2.6
3.1
3.6
4.1
4.6
5.1
1 ms/div
C052
Input Voltage (V)
Figure 64. Output Voltage Ripple vs Input Voltage
Figure 65. Steady State Operation with RO = 100 kΩ
IL
VIN
VOUT
VRDIV
VIN-OK
SW
VOUT
10 μs/div
100 ms/div
Figure 66. Steady State Operation with RO = 9 Ω
Figure 67. Power Management Response
IL
IL
IOUT
VOUT
VOUT
VSW
VSW
20 μs/div
50 μs/div
Figure 68. Load Transient Response
Figure 69. Line Transient Response
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IOUT
VOUT
VOUT
VIN
SW
VIN-OK
5 μs/div
10 s/div
Figure 70. IR Pulse Transient Response
Figure 71. Startup Behavior with Slow Ramping VIN, EN1=0,
EN2=1
EN1
EN2
VIN-OK
VIN-OK
VOUT
VSW
VOUT
VSW
200 μs/div
20 ms/div
Figure 72. Ship-Mode Startup Behavior
Figure 73. Standby-Mode Startup Behavior
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DETAILED PRINCIPLE OF OPERATION
Step Down (Buck) Converter Operation
The buck regulator in the TPS6273X takes input power from VIN, steps it down and provides a regulated voltage
at the OUT pin. It employs pulse frequency modulation (PFM) control to regulate the voltage close to the desired
reference voltage. The reference voltage is set by the user programmed resistor divider. The current through the
inductor is controlled through internal current sense circuitry. The peak current in the inductor is controlled to
maintain high efficiency of the converter across a wide input current range. The TPS62736 converter delivers an
average output current of 50mA with a peak inductor current of 100 mA. The TPS62737 converter delivers an
average output current of 200 mA with a peak inductor current of 370 mA.The buck regulator is disabled when
the voltage on VIN reaches the UVLO condition. The UVLO level is continuously monitored. The buck regulator
continues to operate in pass (100% duty cycle) mode, passing the input voltage to the output, as long as VIN is
greater than UVLO and less than VIN minus IOUT times RDS(on) of the high-side FET (i.e., VIN - IOUT x RDS(on)-HS).
In order to save power from being dissipated through other IC’s on this supply rail while allowing for a faster
wake up time, the buck regulator can be enabled and disabled via the EN2 pin for systems that desire to
completely turn off the regulated output.
Nano-Power Management and Efficiency
The high efficiency of the TPS6273X is achieved via the proprietary Nano-Power management circuitry and
algorithm. This feature essentially samples and holds all references in order to reduce the average quiescent
current. That is, the internal circuitry is only active for a short period of time and then off for the remaining period
of time at the lowest feasible duty cycle. A portion of this feature can be observed in Figure 34 where the VRDIV
node is monitored. Here the VRDIV node provides a connection to the input (larger voltage level) and generates
the output reference (lower voltage level) for a short period of time. The divided down value of input voltage is
compared to VBIAS and the output voltage reference is sampled and held to get the VOUT_SET point. Since
this biases a resistor string, the current through these resistors is only active when the Nano-Power management
circuitry makes the connection—hence reducing the overall quiescent current due to the resistors. This process
repeats every 64 ms. Similarly,the VIN_OK level is monitored every 64ms, as shown in Figure 67.
The efficiency versus output current and versus input voltage are plotted for three different output voltages for
both the TPS62736 and TPS62737 in the Typical Characteristics section.
All data points were captured by
averaging the overall input current. This must be done due to the periodic biasing scheme implemented via the
Nano-Power management circuitry. The input current efficiency data was gathered using a source meter set to
average over at least 25 samples and at the highest accuracy sampling rate. Each data point takes a long
period of time to gather in order to properly measure the resulting input current when calculating the efficiency.
Programming OUT Regulation Voltage and VIN_OK
To set the proper output regulation voltage and input voltage power good comparator, the external resistors must
be carefully selected. Figure 1 illustrates an application diagram which uses the minimal resistor count for setting
both VOUT and VIN_OK. Note that VBIAS is nominally 1.21V per the electrical specification table. Referring to
Figure 1, the OUT dc set point is given by:
æ
ç
è
ö
÷
ø
R1 + R2 + R3
R1 + R2
VOUT = VBIAS
(1)
The VIN_OK setting is given by:
æ
ç
è
ö
÷
ø
R1 + R2 + R3
VIN_OK = VBIAS
R1
(2)
The sum of the resistors is recommended to be no greater than 13 MΩ , that is, RSUM = R1 + R2 + R3 = 13
MΩ. Due to the sampling operation of the output resistors, lowering RSUM only increases quiescent current
slightly as can be seen in Figure 26. Higher resistors may result in poor output voltage regulation and/or input
voltage power good threshold accuracies due to noise pickup via the high impedance pins or reduction of
effective resistance due to parasitic resistances created from board assembly residue. See Layout
Considerations section for more details.
If it is preferred to separate the VOUT and VIN_OK resistor strings, two separate strings of resistors could be
used as shown in Figure 3. The OUT dc set point is then given by Equation 3:
24
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
æ
ç
è
ö
÷
ø
R3 + R4
VOUT = VBIAS
R4
(3)
The VIN_OK setting is then given by Equation 4:
æ
ç
è
ö
÷
ø
R1 + R2
VIN_OK = VBIAS
R1
(4)
If it is preferred to disable the VIN_OK setting, the VIN_OK_SET pin can be tied to VIN as shown in Figure 4. To
set VOUT in this configuration, use Equation 3. To tighten the dc set point accuracy, use external resistors with
better than 1% resistor tolerance. Since output voltage ripple has a large effect on input line regulation and the
output load regulation, using a larger output capacitor will improve both line and load regulation.
Enable Controls
There are two enable pins implemented in the TPS6273X in order to maximize the flexibility of control for the
system. The EN1 pin is considered to be the chip enable. If EN1 is set to a 1 then the entire chip is placed into
ship mode. If EN1 is 0 then the chip is enabled. EN2 enables and disables the switching of the buck converter.
When EN2 is low, the internal circuitry remains ON and the VIN_OK indicator still functions. This can be used to
disable down-stream electronics in case of a low input supply condition. When EN2 is 1, the buck converter
operates normally.
Table 1. Enable Functionality Table
EN1 PIN
EN2 PIN
FUNCTIONAL STATE
Partial standby mode. Buck switching converter is off, but VIN_OK indication is on
Buck mode and VIN_OK enabled
0
0
1
0
1
x
Full standby mode. Switching converter and VIN_OK indication is off (ship mode)
Startup Behavior
The TPS6273X has two startup responses: 1) from the ship-mode state (EN1 transitions from high to low), and
2) from the standby state (EN2 transitions from low to high). The first startup response out of the ship-mode
state has the longest time duration due to the internal circuitry being disabled. This response is shown in
Figure 38 for the TPS62736 and Figure 72 for the TPS62737. The startup time takes approximately 100ms due
to the internal Nano-Power management circuitry needing to complete the 64 ms sample and hold cycle.
Startup from the standby state is shown in Figure 39 for the TPS62736 and Figure 73 for the TPS62737. This
response is much faster due to the internal circuitry being pre-enabled. The startup time from this state is
entirely dependent on the size of the output capacitor. The larger the capacitor, the longer it will take to charge
during startup. The TPS6273X can startup into a pre-biased output voltage.
Steady State Operation and Cycle by Cycle Behavior
The steady state operation at full load is shown in Figure 31 for the TPS62736 and Figure 66 for TPS62737.
This plot highlights the inductor current waveform, the output voltage ripple, and the switching node. The output
voltage is maintained by charging and discharging the output capacitor at a primary duty cycle (major frequency)
which in turn dictates the output voltage ripple frequency. When VOUT is increasing in value, the output
capacitor is charged by the hysteretic buck controller. This is achieved by controlling the peak cycle-by-cycle
inductor current to ILIM. The cycle-by-cycle current is maintained by turning on and off the high side FET at a
secondary duty cycle (minor frequency). When VOUT reaches a peak value, all hysteretic control is disabled until
a minimum value is reached. The rate at which the converter stays off is dictated by the load and the size of the
output capacitor. At heavier output loads (larger output current), the time the converter is off is smaller when
compared to light load conditions. The light load condition is shown in Figure 32 for the TPS62736 and
Figure 65 for the TPS62737. Note that the converter is inactive for a longer period of time when compared to the
active time.
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The minor switching frequency is of concern when choosing the inductor. This maximum switching frequency is
1 MHz. The major switching frequency dictates the voltage ripple frequency. Figure 27 and Figure 28 show the
major switching frequency versus load current and input voltage for the TPS62736, respectively. Figure 61 and
Figure 62 show the major switching frequency versus load current and input voltage for the TPS62737,
respectively.
Inductor Selection
The internal control circuitry is designed to control the switching behavior with a nominal inductance of 10 µH ±
20%. The inductor's saturation current should be at least 25% higher than the maximum cycle-by-cycle current
limit per the electrical specs table (ILIM) in order to account for load transients. Since this device is a hysteretic
controller, it is a naturally stable system (single order transfer function). However, the smaller the inductor value
is, the faster the switching currents are. The speed of the peak current detect circuit sets the TPS62736
inductor's lower bound to 4.7 µH. When using a 4.7 µH, the peak inductor current will increase when compared
to that of a 10 µH inductor. The steady-state operation with a 4.7 µH inductor with a 50 mA load for the
TPS62736 is shown in Figure 33.
A list of inductors recommended for this device is shown in Table 2.
Table 2.
Inductance (µH)
Dimensions (mm)
2.0 x 2.5 x 1.2
4.0x4.0x1.7
Part Number
DFE252012C-H-100M
LPS4018-103M
Manufacturer
Toko
10
10
Coilcraft
Toko
4.7 (TPS62736 only)
2.0 x 2.5 x 1.2
DFE252012R-H-4R7M
Output Capacitor Selection
The output capacitor is chosen based on transient response behavior and ripple magnitude. The lower the
capacitor value, the larger the ripple will become and the larger the droop will be in the case of a transient
response. It is recommended to use at least a 22 µF output capacitor for most applications.
Input Capacitor Selection
The bulk input capacitance is recommended to be a minimum of 4.7 µF ± 20% for the TPS62736 and 22 µF ±
20% for the TPS62737. This bulk capacitance is used to suppress the lower frequency transients produced by
the switching converter. There is no upper bound to the input bulk capacitance. In addition, a high frequency
bypass capacitor of 0.1 µF is recommended in parallel with the bulk capacitor. The high frequency bypass is
used to suppress the high frequency transients produced by the switching converter.
Layout and PCB Assembly Considerations
To minimize switching noise generation, the step-down converter (buck) power stage external components must
be carefully placed. The most critical external component for a buck power stage is its input capacitor. The bulk
input capacitor (CIN1) and high frequency decoupling capacitor (CIN2) must be placed as close as possible
between the power stage input (IN pin 1) and ground (VSS pin 12). Next, the inductor (L1) must be placed as
close as possible beween the switching node (SW pin 13) and the output voltage (OUT pin 11). Finally, the
output capacitor (COUT) should be placed as close as possible between the output voltage (OUT pin 11) and
GND (VSS pin 12). In the diagram below, the input and output capacitor grounds are connected to VSS pin 12
through vias to the PCB's bottom layer ground plane.
To minimize noise pickup by the high impedance voltage setting nodes (VIN_OK_SET pin 8 and VOUT_SET pin
9), the external resistors (R1, R2 and R3) should be placed so that the traces connecting the midpoints of the
string are as short as possible. In the diagram below, the connection to VOUT_SET is by a bottom layer trace.
The remaining pins are either NC pins, that should be connected to the PowerPAD™ as shown below, or digital
signals with minimal layout restrictions.
26
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SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1MΩ is recommended.
However, during board assembly, contaminants such as solder flux and even some board cleaning agents can
leave residue that may form parasitic resistors across the physical resistors and/or from one end of a resistor to
ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold
levels changing significantly from those expected per the installed resistor values. Therefore, it is highly
recommended that no ground planes be poured near the voltage setting resistors. In addition, the boards must
be carefully cleaned, possibly rotated at least once during cleaning, and then rinsed with de-ionized water until
the ionic contamination of that water is well above 50 MOhm. If this is not feasible, then it is recommended that
the sum of the voltage setting resistors be reduced to at least 5X below the measured ionic contamination.
VIAS to
GND PLANE
VIAS to
GND PLANE
CIN1
CIN1
VIAS to
GND PLANE
CIN2
CIN2
VIN
VIN
1
1
COUT
COUT
L1
L1
VOUT
VOUT
VIA to
GND PLANE
VIA to
GND PLANE
R3
R1
R3
R1
R2
R2
Figure 74. Recommended Layout, TPS62736
Figure 75. Recommended Layout, TPS62737
REVISION HISTORY
Changes from Original (October 2012) to Revision A
Page
•
Changed the device From: Preview To: Active .................................................................................................................... 1
Changes from Revision A (March 2013) to Revision B
Page
•
•
•
•
•
Added the TPS62737 Pinout information ............................................................................................................................. 6
Added the TPS62737 Application Circuit, Figure 2 .............................................................................................................. 9
Added graphs for TPS62737 to the Typical Characteristics ............................................................................................... 17
Changed Figure 74 ............................................................................................................................................................. 27
Added Figure 75 ................................................................................................................................................................. 27
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2013
PACKAGING INFORMATION
Orderable Device
TPS62736RGYR
TPS62736RGYT
TPS62737RGYR
TPS62737RGYT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
RGY
14
14
14
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
62736
62736
62737
62737
ACTIVE
ACTIVE
ACTIVE
RGY
RGY
RGY
250
3000
250
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-20 to 85
Green (RoHS
& no Sb/Br)
-20 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62736RGYR
TPS62736RGYT
TPS62737RGYR
TPS62737RGYT
VQFN
VQFN
VQFN
VQFN
RGY
RGY
RGY
RGY
14
14
14
14
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62736RGYR
TPS62736RGYT
TPS62737RGYR
TPS62737RGYT
VQFN
VQFN
VQFN
VQFN
RGY
RGY
RGY
RGY
14
14
14
14
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
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