TPS62812MWRWYR_技术文档

TPS62810M, TPS62811M, TPS62812M, TPS62813M

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TPS6281xM, Extended Temperature, 2.75-V to 6-V Adjustable-Frequency Step-Down

DC/DC Converter

1 Features

3 Description

•

Functional Safety-Capable

– Documentation available to aid functional safety

system design

Extended junction temperature from –55°C to

+150°C

Input voltage range: 2.75 V to 6 V

Family of 1-A, 2-A, 3-A, and 4-A converters

Quiescent current: 15 µA typical

Output voltage from 0.6 V to 5.5 V

Output voltage accuracy ±1% (FPWM operation)

Adjustable soft start

The TPS6281xM is family of pin-to-pin 1-A, 2-A, 3-A,

and 4-A synchronous step-down DC/DC converters.

All devices offer high efficiency and ease of use.

The family of devices is based on a peak current

mode control topology. Low-resistive switches allow

up to 4-A continuous output current at high ambient

temperature. The switching frequency is externally

adjustable from 1.8 MHz to 4 MHz and can also

be synchronized to an external clock in the same

frequency range. The device can automatically enter

power save mode (PSM) at light loads to maintain

high efficiency across the whole load range. The

device provides 1% output voltage accuracy in PWM

mode which helps design a power supply with high

output voltage accuracy. The SS/TR pin allows the

user to set the start-up time or form tracking of the

output voltage to an external source, allowing external

sequencing of different supply rails and limiting the

inrush current during start-up.

•

Start-up at –55°C

Forced PWM or PWM and PFM operation

Adjustable switching frequency of

1.8 MHz to 4 MHz

Precise ENABLE input allows

– User-defined undervoltage lockout

– Exact sequencing

100% duty cycle mode

Active output discharge

Spread spectrum clocking - optional

Power good output with window comparator

Package with wettable flanks

•

The TPS6281xM device is available in a 2-mm × 3-

mm VQFN package with wettable flanks.

•

Device Information

PART NUMBER

TPS62810M

TPS62811M

TPS62812M

TPS62813M

PACKAGE⁽¹⁾

BODY SIZE (NOM)

2 Applications

VQFN

2 mm × 3 mm

•

Aircraft electrical power

Defense radio

Seeker front end

In-flight entertainment

Rail transport

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

100

95

90

85

80

75

70

65

60

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

55

50

100m

1m

10m 100m

Output Current (A)

1

4

D002

Efficiency Versus Output Current;

V_OUT= 3.3 V; PWM and PFM; f_S= 2.25 MHz

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Product Folder Links: TPS62810M TPS62811M TPS62812M TPS62813M

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TPS62810M, TPS62811M, TPS62812M, TPS62813M

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................2

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Recommended Operating Conditions ........................4

7.4 Thermal Information ...................................................4

7.5 Electrical Characteristics ............................................5

7.6 Typical Characteristics................................................7

8 Parameter Measurement Information............................8

8.1 Schematic................................................................... 8

9 Detailed Description......................................................10

9.1 Overview...................................................................10

9.2 Functional Block Diagram.........................................10

9.3 Feature Description...................................................11

9.4 Device Functional Modes..........................................13

10 Application and Implementation................................16

10.1 Application Information........................................... 16

10.2 Typical Application.................................................. 18

10.3 System Examples................................................... 29

11 Power Supply Recommendations..............................32

12 Layout...........................................................................33

12.1 Layout Guidelines................................................... 33

12.2 Layout Example...................................................... 33

13 Device and Documentation Support..........................34

13.1 Device Support....................................................... 34

13.2 Documentation Support.......................................... 34

13.3 Receiving Notification of Documentation Updates..34

13.4 Support Resources................................................. 34

13.5 Trademarks.............................................................34

13.6 Electrostatic Discharge Caution..............................34

13.7 Glossary..................................................................34

14 Mechanical, Packaging, and Orderable

Information.................................................................... 34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

March 2021

*

Initial release

5 Device Comparison Table

DEVICE NUMBER

OUTPUT

CURRENT

VOUT

DISCHARGE

FOLDBACK

CURRENT LIMIT

SPREAD SPECTRUM

CLOCKING (SSC)

OUTPUT VOLTAGE

TPS62811MWRWYR

TPS62812MWRWYR

TPS62813MWRWYR

TPS62810MWRWYR

1 A

2 A

3 A

4 A

ON

OFF

adjustable

2

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6 Pin Configuration and Functions

bottom view

top view

8

7

8

COMP/

FSET

EN

9

6

9

PG

SS/TR

PG

GND

SW

VIN

GND

SW

VIN

FB

5

3

4

2

4

3

1

Figure 6-1. 9-Pin (VQFN) RWY Package

Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

This is the enable pin of the device. Connect to logic low to disable the device. Pull high to

enable the device. Do not leave this pin unconnected.

EN

8

I

Voltage feedback input. Connect the resistive output voltage divider to this pin. For the fixed

voltage versions, connect the FB pin directly to the output voltage.

FB

5

4

GND

Ground pin

The device runs in PFM/PWM mode when this pin is pulled low. If the pin is pulled high,

the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin

can also be used to synchronize the device to an external frequency. See Section 7 for the

detailed specification of the digital signal applied to this pin for external synchronization.

MODE/SYNC

COMP/FSET

1

7

I

Device compensation and frequency set input. A resistor from this pin to GND defines

the compensation of the control loop as well as the switching frequency if not externally

synchronized. If the pin is tied to GND or VIN, the switching frequency is set to 2.25 MHz.

Do not leave this pin unconnected.

Open-drain power-good output. Low impedance when not "power good", high impedance

when "power good". This pin can be left open or be tied to GND when not used.

PG

9

6

O

I

Soft Start / Tracking pin. A capacitor connected from this pin to GND defines the rise time

for the internal reference voltage. The pin can also be used as an input for tracking and

sequencing; see Section 9.4.7.

SS/TR

SW

VIN

3

2

Switch pin of the converter. This pin is connected to the internal power MOSFETs.

Power supply input. Connect the input capacitor as close as possible between the VIN pin

and GND.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–3

MAX

6.5

UNIT

V

VIN

SW

V_IN+ 0.3

10

V

Pin voltage range⁽¹⁾

SW (transient for less than 10 ns)⁽²⁾

FB

V

–0.3

–65

4

V

PG, SS/TR, COMP/FSET

EN, MODE/SYNC

V_IN+ 0.3

6.5

V

Pin voltage range⁽¹⁾

V

Storage temperature, T_stg

150

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) While switching

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification

JESD22-C101⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

2.75

0.6

0.32

0.25

15

NOM

MAX

6

UNIT

V_IN

V_OUT

L

Supply voltage range

V

Output voltage range

5.5

0.9

470

V

Effective inductance for a switching frequency of 1.8 MHz to 3.5 MHz

Effective inductance for a switching frequency of 3.5 MHz to 4 MHz

Effective output capacitance for 1-A and 2-A version⁽¹⁾

Effective output capacitance for 3-A and 4-A version ⁽¹⁾

Effective input capacitance⁽¹⁾

0.47

0.33

22

µH

µF

kΩ

°C

L

C_OUT

C_IN

R_CF

T_J

27

47

5

10

4.5

–55

100

Operating junction temperature

+150

(1) The values given for the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias

effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the

manufacturers DC bias curves for the effective capacitance versus DC voltage applied. Further restrictions may apply. Please see the

feature description for COMP/FSET about the output capacitance versus compensation setting and output voltage.

7.4 Thermal Information

TPS6281xM

THERMAL METRIC⁽¹⁾

RWY (VQFN)

9 PINS

71.1

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

37.2

16.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.9

ψ_JB

16.1

4

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TPS6281xM

THERMAL METRIC⁽¹⁾

RWY (VQFN)

9 PINS

UNIT

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

over operating junction temperature (T_J= –55°C to +150°C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J=

25°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

EN = high, I_OUT= 0 mA, device not switching,

T_J= 125°C

I_Q

Operating quiescent current

21

µA

I_Q

Operating quiescent current

Shutdown current

EN = high, I_OUT= 0 mA, device not switching

EN = 0 V, at T_J= 125 °C

15

30

18

µA

I_SD

EN = 0 V, nominal value at T_J= 25 °C,

max value at T_J= 150°C

I_SD

Shutdown current

1.5

26

µA

Rising input voltage

Falling input voltage

2.5

2.6

2.5

2.75

2.6

V

Undervoltage lockout

threshold

V_UVLO

2.25

Thermal shutdown

temperature

Rising junction temperature

170

15

T_SD

°C

Thermal shutdown hysteresis

CONTROL (EN, SS/TR, PG, MODE)

High level input voltage for

MODE pin

V_IH

1.1

V

Low level input voltage for

MODE pin

V_IL

0.3

4

Frequency range on MODE

pin for synchronization

Requires a resistor from COMP/FSET to GND, see the

Application and Implementation section

f_SYNC

1.8

MHz

Duty cycle of synchronization

signal at MODE pin

40%

50%

50

60%

Time to lock to external

frequency

µs

V

Input threshold voltage for EN

pin; rising edge

V_IH

1.06

0.96

1.1

1.0

1.15

1.05

150

2.5

Input threshold voltage for EN

pin; falling edge

V_IL

V

Input leakage current for EN,

MODE/SYNC

I_LKG

V_IH= V_INor V_IL= GND

nA

kΩ

V

Resistance from COMP/FSET

to GND for logic low

Internal frequency setting with f = 2.25 MHz

0

Voltage on COMP/FSET for

logic high

VIN

95%

UVP power good threshold

voltage; dc level

Rising (%V_FB

)

92%

87%

98%

93%

UVP power good threshold

voltage; dc level

Falling (%V_FB

)

90%

V_{TH_PG}

OVP power good threshold;

dc level

Rising (%V_FB

)

107%

104%

110%

113%

111%

OVP power good threshold;

dc level

Falling (%V_FB

)

107%

40

Power good de-glitch time

For a high level to low level transition on power good

µs

V

Power good output low

V_{OL_PG}

voltage

I_PG= 2 mA

V_PG= 5 V

0.07

0.3

I_{LKG_PG}

I_SS/TR

Input leakage current (PG)

SS/TR pin source current

Tracking gain

100

2.8

nA

µA

2.1

2.5

1

V_FB/V_SS/TR

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over operating junction temperature (T_J= –55°C to +150°C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J=

25°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Tracking offset

Feedback voltage with V_SS/TR= 0 V

17

mV

POWER SWITCH

High-side MOSFET ON-

resistance

R_DS(ON)

V_IN≥ 5 V

37

15

60

35

30

mΩ

µA

Low-side MOSFET ON-

resistance

V_IN≥ 5 V

High-side MOSFET leakage

current

V_IN= 6 V; V(SW) = 0 V

Low-side MOSFET leakage

current

V(SW) = 6 V

55

30

µA

A

SW leakage

V(SW) = 0.6 V; current into SW pin

DC value, for TPS62810; V_IN= 3 V to 6 V

–0.025

4.8

High-side MOSFET current

limit

I_LIMH

5.6

4.5

3.4

6.65

High-side MOSFET current

limit

DC value, for TPS62813; V_IN= 3 V to 6 V

DC value, for TPS62812; V_IN= 3 V to 6 V

3.9

2.8

2.0

5.35

4.3

A

High-side MOSFET current

limit

High-side MOSFET current

limit

I_LIMH

I_LIMNEG

f_S

DC value, for TPS62811; V_IN= 3 V to 6 V

DC value

2.6

–1.8

2.25

3.35

A

Negative valley current limit

PWM switching frequency

range

1.8

2.025

–19%

4

MHz

PWM switching frequency

f_S

With COMP/FSET tied to VIN or GND

2.25

2.475

MHz

PWM switching frequency

tolerance

Using a resistor from COMP/FSET to GND, fs = 1.8 MHz to 4

MHz

18%

75

t_on,min

Minimum on time of HS FET

Minimum on time of LS FET

T_J= –40°C to 125°C, V_IN= 3.3 V

V_IN= 3.3 V

50

30

ns

t_on,min

OUTPUT

V_FB

Feedback voltage

0.6

1

V

I_{LKG_FB}

Input leakage current (FB)

V_FB= 0.6 V

70

nA

V_IN≥ V_OUT+ 1 V

PWM mode

–1%

1%

PFM mode;

Co,eff ≥ 22 µF,

L = 0.47 µH

V_IN≥ V_OUT+ 1 V;

V_OUT≥ 1.5 V

2%

V_FB

Feedback voltage accuracy

PFM mode;

Co,eff ≥ 47 µF,

L = 0.47 µH

1 V ≤ V_OUT< 1.5 V

–1%

2.5%

7%

Feedback voltage accuracy

with voltage tracking

V_IN≥ V_OUT+ 1 V;

V_SS/TR= 0.3 V

V_FB

PWM mode

Load regulation

PWM mode operation

0.05

0.02

%/A

%/V

Ω

Line regulation

PWM mode operation, I_OUT= 1 A, V_IN≥ V_OUT+ 1 V

Output discharge resistance

50

I_OUT= 0 mA, time from EN = high to start switching; V_IN

applied already

t_delay

t_ramp

Start-up delay time

135

100

250

150

650

µs

I_OUT= 0 mA, time from first switching pulse until 95% of

nominal output voltage; device not in current limit

Ramp time; SS/TR pin open

200

6

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7.6 Typical Characteristics

80

40

76

72

68

64

60

56

52

48

44

40

36

32

28

24

20

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

W

-55

25

85

125

150

-55

25

85

125

150

Junction Temperature (èC)

D000

D001

Figure 7-1. R_ds(on)of High-side Switch

Figure 7-2. R_ds(on)of Low-side Switch

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8 Parameter Measurement Information

8.1 Schematic

Figure 8-1. Measurement Setup for TPS62810M (4 A) and TPS62813M (3 A)

Table 8-1. List of Components

DESCRIPTION

REFERENCE

MANUFACTURER ⁽¹⁾

Texas Instruments

Coilcraft

IC

L

TPS62810M or TPS62813M

0.47-µH inductor; XEL4030-471MEB

22 µF / 10 V; GCM31CR71A226KE02L

C_IN

Murata

2 × 22 µF / 10 V; GCM31CR71A226KE02L

+ 1 × 10 µF, 6.3 V; GCM188D70J106ME36

C_OUT

Murata

C_SS

R_CF

C_FF

R₁

4.7 nF (equal to 1-ms start-up ramp)

Any

8.06 kΩ

10 pF

Depending on VOUT

100 kΩ

R₂

R₃

(1) See the Third-party Products Disclaimer.

8

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Figure 8-2. Measurement Setup for TPS62811M (1 A) and TPS62812M (2 A)

Table 8-2. List of Components

DESCRIPTION

REFERENCE

MANUFACTURER ⁽¹⁾

Texas Instruments

Coilcraft

IC

L

TPS62812M or TPS62811M

0.56-µH inductor; XEL4020-561MEB

22 µF / 10 V; GCM31CR71A226KE02L

C_IN

Murata

1 × 22 µF / 10 V; GCM31CR71A226KE02L

+ 1 × 10 µF, 6.3 V; GCM188D70J106ME36

C_OUT

Murata

C_SS

R_CF

C_FF

R₁

4.7 nF (equal to 1-ms start-up ramp)

Any

8.06 kΩ

10 pF

Depending on VOUT

100 kΩ

R₂

R₃

(1) See the Third-party Products Disclaimer.

Table 8-3. List of Key Components, Operation at –55°C

REFERENCE

DESCRIPTION

MANUFACTURER⁽¹⁾

Texas Instruments

TDK

IC

L

TPS62810M, TPS62811M, TPS62812M, or TPS62813M

0.47-µH inductor; TFM252012ALMAR47MTAA

22 µF / 10 V; GCJ31CL8ED226KE07

C_IN

Murata

2 × 22 µF / 10 V; GCJ31CL8ED226KE07

+ 1 × 10 µF, 16 V; GCJ32ER91C106KE01

C_OUT

Murata

(1) See the Third-party Products Disclaimer.

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9 Detailed Description

9.1 Overview

The TPS6281xM synchronous switch mode DC/DC converter is based on a peak current mode control topology.

The control loop is internally compensated. To optimize the bandwidth of the control loop to the wide range

of output capacitance that can be used with the TPS6281xM, one of three internal compensation settings can

be selected. See Section 9.3.2. The compensation setting is selected either by a resistor from COMP/FSET

to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation with

small external components and low-ESR ceramic output capacitors. The device can be operated without a

feedforward capacitor on the output voltage divider, however, using a 10-pF (typical) feedforward capacitor

improves transient response.

The device support forced fixed-frequency PWM operation with the MODE pin tied to a logic high level. The

frequency is defined as either internally fixed 2.25 MHz when COMP/FSET is tied to GND or VIN, or in a

range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be

synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no

need for additional passive components. External synchronization is only possible if a resistor from COMP/FSET

to GND is used. If COMP/FSET is directly tied to GND or VIN, the device cannot be synchronized externally. An

internal PLL allows a change from an internal clock to an external clock during operation. The synchronization to

the external clock is done on a falling edge of the clock applied at MODE to the rising edge on the SW pin. This

allows roughly a 180° phase shift when the SW pin is used to generate the synchronization signal for a second

converter. When the MODE pin is set to a logic low level, the devices operate in power save mode (PFM) at low

output current and automatically transfer to fixed-frequency PWM mode at higher output current. In PFM mode,

the switching frequency decreases linearly based on the load to sustain high efficiency down to very low output

current.

9.2 Functional Block Diagram

VIN

SW

Bias

Regulator

Gate Drive and Control

Oscillator

Ipeak

Izero

EN

MODE

gm

GND

FB

_

+

PG

Device

Control

+

-

Bandgap

SS/TR

Thermal

Shutdown

COMP/FSET

10

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9.3 Feature Description

9.3.1 Precise Enable

The voltage applied at the enable pin of the TPS6281xM device is compared to a fixed threshold of 1.1 V for a

rising voltage. This lets the user drive the pin with a slowly changing voltage and enables the use of an external

RC network to achieve a power-up delay.

The precise enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the

input of the enable pin.

The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The

TPS6281xM device starts operation when the rising threshold is exceeded. For proper operation, the EN pin

must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown with a

shutdown current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off and

the entire internal control circuitry is switched off.

9.3.2 COMP/FSET

This pin lets the user set two different parameters independently:

•

Internal compensation settings for the control loop

The switching frequency in PWM mode from 1.8 MHz to 4 MHz

A resistor from COMP/FSET to GND changes the compensation and switching frequency. The change in

compensation allows the user to adapt the device to different values of output capacitance. The resistor must

be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting

is sampled when the converter starts up, so a change in the resistor during operation only has an effect on the

switching frequency, but not on the compensation.

To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching

frequency or compensation. Do not leave the pin floating.

The switching frequency has to be selected based on the input voltage and the output voltage to meet the

specifications for the minimum on time and minimum off time.

For example: V_IN= 5 V, V_OUT= 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2

•

with t_on= DC × T --> t_on,min= 1 / f_s,max× DC

--> f_s,max= 1 / t_on,min× DC = 1 / 0.075 µs × 0.2 = 2.67 MHz

The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be

increased from the minimum value as given in Table 9-1 and Table 9-2, up to a maximum of 470 µF in all of

the three compensation ranges. If the capacitance of an output changes during operation, for example, when

load switches are used to connect or disconnect parts of the circuitry, the compensation must be chosen for the

minimum capacitance on the output. With large output capacitance, the compensation must be done based on

that large capacitance to get the best load transient response. Compensating for large output capacitance, but

placing less capacitance on the output, can lead to instability.

The switching frequency for the different compensation settings is determined by the following equations.

For compensation (comp) setting 1:

Space

18MHz ×kW

RCF(kW) =

fS(MHz)

(1)

For compensation (comp) setting 2:

Space

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60MHz ×kW

RCF(kW) =

fS(MHz)

(2)

Space

For compensation (comp) setting 3:

Space

180MHz ×kW

RCF(kW) =

fS(MHz)

(3)

Table 9-1. Switching Frequency and Compensation for TPS62810M (4 A) and TPS62813M (3 A)

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

COMPENSATION

R_CF

SWITCHING FREQUENCY

FOR VOUT < 1 V

FOR 1 V ≤ VOUT < 3.3 V

FOR VOUT ≥ 3.3 V

for the smallest

output capacitance

(comp setting 1)

1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)

according to Equation 1

10 kΩ ... 4.5 kΩ

33 kΩ ... 15 kΩ

100 kΩ ... 45 kΩ

tied to GND

53 µF

100 µF

200 µF

53 µF

32 µF

60 µF

27 µF

50 µF

for medium output

capacitance

(comp setting 2)

1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)

according to Equation 2

for large output

capacitance

(comp setting 3)

1.8 MHz (100 kΩ) ... 4 MHz (45 kΩ)

according to Equation 3

120 µF

32 µF

100 µF

27 µF

for the smallest

output capacitance

(comp setting 1)

internally fixed 2.25 MHz

for large output

capacitance

tied to V_IN

200 µF

120 µF

100 µF

(comp setting 3)

Table 9-2. Switching Frequency and Compensation for TPS62812M (2 A) and TPS62811M (1 A)

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

COMPENSATION

R_CF

SWITCHING FREQUENCY

FOR VOUT < 1 V

FOR 1 V ≤ VOUT < 3.3 V

FOR VOUT ≥ 3.3 V

for the smallest

output capacitance

(comp setting 1)

1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)

according to Equation 1

10 kΩ ... 4.5 kΩ

33 kΩ ... 15 kΩ

100 kΩ ... 45 kΩ

tied to GND

30 µF

60 µF

18 µF

36 µF

80 µF

18 µF

80 µF

15 µF

30 µF

68 µF

15 µF

68 µF

for medium output

capacitance

(comp setting 2)

1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)

according to Equation 2

for large output

capacitance

(comp setting 3)

1.8MHz (100 kΩ) ...4 MHz (45 kΩ)

according to Equation 3

130 µF

30 µF

for the smallest

output capacitance

(comp setting 1)

internally fixed 2.25 MHz

for large output

capacitance

tied to V_IN

130 µF

(comp setting 3)

Refer to Section 10.1.3.2 for further details on the required output capacitance required depending on the output

voltage.

A too-high resistor value for R_CFis decoded as "tied to V_IN". A value below the lowest range is decoded as "tied

to GND". The minimum output capacitance in Table 9-1 and Table 9-2 is for capacitors close to the output of the

device. If the capacitance is distributed, a lower compensation setting can be required. All values are effective

capacitance including, but not limited to:

•

All tolerances

Aging

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•

DC bias effect

9.3.3 MODE/SYNC

When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The

MODE/SYNC pin lets the user force PWM mode when set high. The pin also lets the user apply an external

clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET, take the

specifications for the minimum on time and minimum off time into account when setting the external frequency.

For use with external synchronization on the MODE/SYNC pin, the internal switching frequency must be set

by R_CFto a similar value of the externally applied clock. This ensures a fast settling to the external clock

and, if the external clock fails, the switching frequency stays in the same range and the compensation settings

are still valid. When there is no resistor from COMP/FSET to GND but the pin is pulled high or low, external

synchronization is not possible.

9.3.4 Spread Spectrum Clocking (SSC)

For device versions with SSC enabled, the switching frequency is randomly changed in PWM mode when the

internal clock is used. The frequency variation is typically between the nominal switching frequency and up

to 288 kHz above the nominal switching frequency. When the device is externally synchronized by applying a

clock signal to the MODE/SYNC pin, the TPS6281xM device follows the external clock and the internal spread

spectrum block is turned off. SSC is also disabled during soft start.

9.3.5 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both of

the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the

input voltage trips below the threshold for a falling supply voltage.

9.3.6 Power Good Output (PG)

Power good is an open-drain output driven by a window comparator. PG is held low when the device is disabled,

in undervoltage lockout, and in thermal shutdown. When the output voltage is in regulation hence, within the

window defined in the electrical characteristics, the output is high impedance.

Table 9-3. PG Status

EN

X

DEVICE STATUS

V_IN< 2.75 V

V_IN< 2.25 V

V_IN≥ 2.75 V

PG STATE

undefined

low

high

low

2.25 V ≤ V_IN≤ UVLO OR in thermal shutdown OR V_OUTnot in

regulation

high

low

V_OUTin regulation

high impedance

9.3.7 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_Jexceeds 170°C

(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG

goes low. When T_Jdecreases by the hysteresis amount of typically 15°C, the device resumes normal operation,

beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause, the

device needs up to 9 µs to detect a too-high junction temperature. If the PFM burst is shorter than this delay, the

device does not detect a too-high junction temperature.

9.4 Device Functional Modes

9.4.1 Pulse Width Modulation (PWM) Operation

The TPS6281xM device has two operating modes: forced PWM mode (discussed in this section) and PWM/PFM

(discussed in Section 9.4.2).

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With the MODE/SYNC pin set to high, the TPS6281xM device operates with pulse width modulation in

continuous conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP

pin to GND or by an external clock signal applied to the MODE/SYNC pin. With an external clock is applied to

MODE/SYNC, the device follows the frequency applied to the pin. To maintain regulation, the frequency needs to

be in a range the device can operate at, taking the minimum on time into account.

9.4.2 Power Save Mode Operation (PWM/PFM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long

as the peak inductor current is above the approximately 1.2-A PFM threshold. When the peak inductor current

drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching

frequency decreases with the load current maintaining high efficiency.

9.4.3 100% Duty-Cycle Operation

The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle

increases as the input voltage comes close to the output voltage and the off time gets smaller. When the

approximately 30-ns minimum off time is reached, the TPS6281xM device skips switching cycles while it

approaches 100% mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side

switch stays turned on as long as the output voltage is below the target. In 100% mode, the low-side switch

is turned off. The maximum dropout voltage in 100% mode is the product of the on-resistance of the high-side

switch plus the series resistance of the inductor and the load current.

9.4.4 Current Limit and Short Circuit Protection

The TPS6281xM device is protected against overload and short circuit events. If the inductor current exceeds

the current limit I_LIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the

inductor current. The high-side switch turns on again only if the current in the low-side switch has decreased

below the low-side current limit. Due to internal propagation delay, the actual current can exceed the static

current limit. The dynamic current limit is given as:

V

L

Ipeak(typ) = ILIMH

+

×tPD

L

(4)

where

•

I_LIMHis the static current limit as specified in the Electrical Characteristics

L is the effective inductance at the peak current

V_Lis the voltage across the inductor (V_IN- V_OUT

)

t_PDis the internal propagation delay of typically 50 ns

The current limit can exceed static values, especially if the input voltage is high and very small inductances are

used. The dynamic high-side switch peak current can be calculated as:

V

IN -VOUT

Ipeak(typ) = ILIMH

+

×50ns

L

(5)

9.4.5 Foldback Current Limit and Short Circuit Protection

This is valid for devices where foldback current limit is enabled.

When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current

limit from its nominal value to typically 1.8 A. Foldback current limit is left when the current limit indication goes

away. If device operation continues in current limit, after 3072 switching cycles, the device tries for full current

limit again after 1024 switching cycles.

9.4.6 Output Discharge

The purpose of the discharge function is to ensure a defined down ramp of the output voltage when the device is

being disabled and to keep the output voltage close to 0 V when the device is off. The output discharge feature

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is only active once the TPS6281xM device has been enabled at least once since the supply voltage was applied.

The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage

lockout. The minimum supply voltage required for the discharge function to remain active is typically 2 V. Output

discharge is not activated during a current limit or foldback current limit event.

9.4.7 Soft Start/Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush

current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high

impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a

delay of about 200 μs, then the internal reference and hence, V_OUT, rises with a slope controlled by an external

capacitor connected to the SS/TR pin.

Leaving the SS/TR pin un-connected provides the fastest start-up ramp with typically 150 µs. A capacitor

connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until it

reaches the 0.6-V reference voltage. The capacitance required to set a certain ramp-time (t_ramp) is:

(6)

If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor

pulls the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new start-up

sequence.

A voltage applied at SS/TR can be used to track a main voltage. The output voltage follows this voltage up

and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current. The

SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied on SS/TR is

internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the external voltage on

SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R₅and R₆on SS/TR, this

ensures the device "switches" to the internal reference voltage when the power-up sequencing is finished. See

Figure 10-57.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

10.1.1 Programming the Output Voltage

The output voltage of the TPS6281xM device is adjustable. It can be programmed for output voltages from 0.6 V

to 5.5 V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value

of the output voltage is set by the selection of the resistor divider from Equation 7. It is recommended to choose

resistor values that allow a current of at least 2 µA, meaning the value of R₂must not exceed 400 kΩ. Lower

resistor values are recommended for the highest accuracy and most robust design.

V

OUT

æ

ö

R1

= R

-1

FB

^{2 ×}ç

è

÷

V

ø

(7)

10.1.2 Inductor Selection

The TPS6281xM device is designed for a nominal 0.47-µH inductor with a typical switching frequency of 2.25

MHz. Larger values can be used to achieve a lower inductor current ripple, but they can have a negative impact

on efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple, which

causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower

nominal switching frequency, the inductance must be changed accordingly.

The inductor selection is affected by several effects like the following:

•

Inductor ripple current

Output ripple voltage

PWM-to-PFM transition point

Efficiency

In addition, the selectec inductor has to be rated for appropriate saturation current and DC resistance (DCR).

Equation 8 calculates the maximum inductor current.

DI_L(max)

I_L(max)= I_OUT(max)

+

2

(8)

(9)

V

OUT

æ

ö

V

1-

^{OUT ×}ç

÷

IN

1

V

è

Lmin

ø

DIL(max)

=

×

f

SW

where

•

I_L(max)is the maximum inductor current

ΔI_L(max)is the peak-to-peak inductor ripple current

Lmin is the minimum inductance at the operating point

16

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Table 10-1. Typical Inductors

NOMINAL

SWITCHING

FREQUENCY

INDUCTANCE

[µH]

CURRENT

[A] ⁽¹⁾

DIMENSIONS MANUFACTURER OPERATION AT –

FOR DEVICE

(2)

[LxBxH] mm

55°C

TPS62810M,

TPS62813M,

TPS62812M

ML433PYA601MLZ 0.6 µH, ±20%

ML433PYA401MLZ 0.4 µH, ±20%

10.4

2.25 MHz

4 × 4 × 2.1

Coilcraft

yes

TPS62810M,

TPS62813M,

TPS62812M

12.5

3.5

2.25 MHz

4 × 4 × 2.1

4 × 4 × 1.6

4 × 4 × 2.1

Coilcraft

yes

no

TPS62813M,

TPS62812M

XFL4015-471ME

XEL4020-561ME

0.47 µH, ±20%

0.56 µH, ±20%

TPS62810M,

TPS62813M,

TPS62812M

9.9

no

TPS62810M,

TPS62813M,

TPS62812M

XEL4030-471ME

XEL3515-561ME

0.47 µH, ±20%

0.56 µH, ±20%

12.3

4.5

2.25 MHz

4 × 4 × 3.1

Coilcraft

no

TPS62813M,

TPS62812M

3.5 × 3.2 × 1.5

TPS62811M,

TPS62812M

XFL3012-331MEB 0.33 µH, ±20%

2.6

1.5

≥ 3.5 MHz

2.25 MHz

3 × 3 × 1.3

2 × 1.9 × 1

Coilcraft

no

XPL2010-681ML

0.68 µH, ±20%

0.47 µH, ±20%

TPS62811M

see data

sheet

TPS62811M,

TPS62813M,

TPS62812M

DFE252012PD-

R47M

2.25 MHz

2.5 × 2 × 1.2

Murata

no

(1) Lower of I_RMSat 20°C rise or I_SATat 20% drop

(2) See the Third-party Products Disclaimer.

Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation

current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also

useful to get lower ripple current, but increases the transient response time and size as well.

10.1.3 Capacitor Selection

10.1.3.1 Input Capacitor

For most applications, 22 µF nominal is sufficient and is recommended. The input capacitor buffers the input

voltage for transient events and decouples the converter from the supply. A low-ESR multilayer ceramic

capacitor (MLCC) is recommended for the best filtering and must be placed between VIN and GND as close as

possible to those pins.

10.1.3.2 Output Capacitor

The architecture of the TPS6281xM device allows the use of tiny ceramic output capacitors with low equivalent

series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep

its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is

recommended to use dielectric X7R, X7T, or an equivalent. Using a higher value has advantages like smaller

voltage ripple and tighter DC output accuracy in power save mode. By changing the device compensation with

a resistor from COMP/FSET to GND, the device can be compensated in three steps based on the minimum

capacitance used on the output. The maximum capacitance is 470 µF in any of the compensation settings.

The minimum capacitance required on the output depends on the compensation setting as well as on the current

rating of the device. The TPS62810M and TPS62813M devices require a minimum output capacitance of 27

µF while the lower current versions (the TPS62812M and TPS62811M devices) require 15 µF at minimum. The

required output capacitance also changes with the output voltage.

For output voltages below 1 V, the minimum increases linearly from 32 µF at 1 V to 53 µF at 0.6 V for the

TPS62810M device. Use the TPS62813M device with the compensation setting for smallest output capacitance.

Other compensation ranges and ranges for TPS62811M and TPS62812M are equivalent. See Table 9-1 and

Table 9-2 for details.

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10.2 Typical Application

Figure 10-1. Typical Application

10.2.1 Design Requirements

The design guidelines provide a component selection to operate the device within the recommended operating

conditions.

10.2.2 Detailed Design Procedure

V

OUT

æ

ö

R1

= R

-1

FB

^{2 ×}ç

è

÷

V

ø

(10)

With V_FB= 0.6 V:

Table 10-2. Setting the Output Voltage

NOMINAL OUTPUT VOLTAGE

V_OUT

R₁

R₂

C_FF

EXACT OUTPUT VOLTAGE

0.8 V

1.0 V

1.1 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

16.9 kΩ

20 kΩ

51 kΩ

30 kΩ

47 kΩ

68 kΩ

51 kΩ

40.2 kΩ

15 kΩ

19.6 kΩ

10 pF

0.7988 V

1.0 V

39.2 kΩ

68 kΩ

1.101 V

1.2 V

76.8 kΩ

80.6 kΩ

47.5 kΩ

88.7 kΩ

1.5 V

1.803 V

2.5 V

3.315 V

18

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10.2.3 Application Curves

All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless

otherwise noted. The BOM is according to Table 8-1.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 3.3 V

PFM

T_A= 25°C

V_OUT= 3.3 V

PWM

T_A= 25°C

Figure 10-2. Efficiency versus Output Current

Figure 10-3. Efficiency versus Output Current

100

95

90

85

80

75

70

100

95

90

85

80

75

65

60

55

50

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

70

65

60

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 1.8 V

PFM

T_A= 25°C

V_OUT= 1.8 V

PWM

T_A= 25°C

Figure 10-4. Efficiency versus Output Current

Figure 10-5. Efficiency versus Output Current

100

95

90

85

80

75

70

100

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 1.2 V

PFM

T_A= 25°C

V_OUT= 1.2 V

PWM

T_A= 25°C

Figure 10-6. Efficiency versus Output Current

Figure 10-7. Efficiency versus Output Current

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100

95

90

85

80

75

70

100

95

90

85

80

75

70

65

60

65

60

55

50

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 1.0 V

PFM

T_A= 25°C

V_OUT= 1.0 V

PWM

T_A= 25°C

Figure 10-8. Efficiency versus Output Current

Figure 10-9. Efficiency versus Output Current

90

85

80

75

70

65

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

55

50

55

50

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 0.6 V

PFM

T_A= 25°C

V_OUT= 0.6 V

PWM

T_A= 25°C

Figure 10-10. Efficiency versus Output Current

Figure 10-11. Efficiency versus Output Current

3,32

3,315

3,31

3,32

3,316

3,312

3,308

3,304

3,3

3,305

3,3

3,295

3,29

3,296

3,292

3,288

3,285

3,28

3,284

3,28

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

3,275

3,27

3,276

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 3.3 V

PFM

T_A= 25°C

V_OUT= 3.3 V

PWM

T_A= 25°C

Figure 10-12. Output Voltage versus Output

Current

Figure 10-13. Output Voltage versus Output

Current

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1,82

1,816

1,812

1,808

1,804

1,8

1,82

1,816

1,812

1,808

1,804

1,8

1,796

1,792

1,788

1,784

1,78

1,796

1,792

1,788

1,784

1,78

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 1.8 V

PFM

T_A= 25°C

V_OUT= 1.8 V

PWM

T_A= 25°C

Figure 10-14. Output Voltage versus Output

Current

Figure 10-15. Output Voltage versus Output

Current

1,2125

1,21

1,2075

1,205

1,2025

1,2

1,2075

1,205

1,2025

1,2

1,1975

1,195

1,1925

1,19

1,195

1,1925

1,19

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

1,1875

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 1.2 V

PFM

T_A= 25°C

V_OUT= 1.2 V

PWM

T_A= 25°C

Figure 10-16. Output Voltage versus Output

Current

Figure 10-17. Output Voltage versus Output

Current

1,01

1,008

1,006

1,004

1,002

1

1,01

1,008

1,006

1,004

1,002

1

0,998

0,996

0,994

0,992

0,99

0,996

0,994

0,992

0,99

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 1.0 V

PFM

T_A= 25°C

V_OUT= 1.0 V

PWM

T_A= 25°C

Figure 10-18. Output Voltage versus Output

Current

Figure 10-19. Output Voltage versus Output

Current

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0,612

0,61

0,606

0,6045

0,603

0,6015

0,6

0,608

0,606

0,604

0,602

0,6

0,5985

0,597

0,5955

0,594

V_IN= 2.7 V

0,598

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

0,596

0,594

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 0.6 V

PWM

T_A= 25°C

V_OUT= 0.6 V

PFM

T_A= 25°C

Figure 10-21. Output Voltage versus Output

Current

Figure 10-20. Output Voltage versus Output

Current

V_OUT= 3.3 V

V_IN= 5.0 V

PWM

T_A= 25°C

V_OUT= 3.3 V

V_IN= 5.0 V

PFM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 10-23. Load Transient Response

Figure 10-22. Load Transient Response

V_OUT= 1.8 V

V_IN= 5.0 V

PWM

T_A= 25°C

V_OUT= 1.8 V

V_IN= 5.0 V

PFM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 10-25. Load Transient Response

Figure 10-24. Load Transient Response

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V_OUT= 1.2 V

V_IN= 5.0 V

PFM

T_A= 25°C

V_OUT= 1.2 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 10-26. Load Transient Response

Figure 10-27. Load Transient Response

V_OUT= 1.0 V

V_IN= 5.0 V

PWM

T_A= 25°C

V_OUT= 1.0 V

V_IN= 5.0 V

PFM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 10-29. Load Transient Response

Figure 10-28. Load Transient Response

V_OUT= 0.6 V

V_IN= 3.3 V

PFM

T_A= 25°C

V_OUT= 0.6 V

V_IN= 3.3 V

PWM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 10-30. Load Transient Response

Figure 10-31. Load Transient Response

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V_OUT= 3.3 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-33. Line Transient Response

Figure 10-32. Line Transient Response

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-35. Line Transient Response

Figure 10-34. Line Transient Response

V_OUT= 1.2 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.2 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-37. Line Transient Response

Figure 10-36. Line Transient Response

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V_OUT= 1.0 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.0 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-39. Line Transient Response

Figure 10-38. Line Transient Response

V_OUT= 0.6 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 0.6 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 3.0 V to 3.6 V to 3.0 V

Figure 10-41. Line Transient Response

Figure 10-40. Line Transient Response

V_OUT= 3.3 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5.0 V

BW = 20 MHz

Figure 10-42. Output Voltage Ripple

Figure 10-43. Output Voltage Ripple

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V_OUT= 1.8 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

BW = 20 MHz

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5.0 V

Figure 10-44. Output Voltage Ripple

Figure 10-45. Output Voltage Ripple

V_OUT= 1.2 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.2 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5.0 V

BW = 20 MHz

Figure 10-47. Output Voltage Ripple

Figure 10-46. Output Voltage Ripple

V_OUT= 1.0 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_OUT= 1.0 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5.0 V

BW = 20 MHz

Figure 10-48. Output Voltage Ripple

Figure 10-49. Output Voltage Ripple

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V_OUT= 0.6 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 0.6 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 3.3 V

BW = 20 MHz

V_IN= 3.3 V

BW = 20 MHz

Figure 10-51. Output Voltage Ripple

Figure 10-50. Output Voltage Ripple

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5 V

C_SS= 4.7 nF

V_IN= 5 V

C_SS= 4.7 nF

Figure 10-53. Start-Up Timing

Figure 10-52. Start-Up Timing

V_OUT= 1.2 V

I_OUT= 4 A

PWM

T_A= 25°C

C_SS= 4.7 nF

V_OUT= 1.0 V

I_OUT= 4 A

PWM

T_A= 25°C

C_SS= 4.7 nF

V_IN= 5 V

Figure 10-54. Start-Up Timing

Figure 10-55. Start-Up Timing

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V_OUT= 0.6 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 3.3 V

C_SS= 4.7 nF

Figure 10-56. Start-Up Timing

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10.3 System Examples

10.3.1 Voltage Tracking

The TPS6281xM device follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps

the output voltage according to the 0.6-V feedback voltage.

Tracking the 3.3 V of device 1, such that both rails reach their target voltage at the same time, requires a resistor

divider on SS/TR of device 2 equal to the output voltage divider of device 1. The output current of 2.5 µA on

the SS/TR pin causes an offset voltage on the resistor divider formed by R₅and R₆. The equivalent resistance

of R₅// R₆, so it must be kept below 15 kΩ. The current from SS/TR causes a slightly higher voltage across R6

than 0.6 V, which is desired because device 2 switches to its internal reference as soon as the voltage at SS/TR

is higher than 0.6 V.

In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of device 2 to the

output voltage or the power good signal of device 1, the main device. The TPS6281xM device has a duty cycle

limitation defined by the minimum on time. For tracking down to low output voltages, device 2 cannot follow once

the minimum duty cycle is reached. Enabling PFM mode while tracking is in progress allows the user to ramp

down the output voltage close to 0 V.

Figure 10-57. Schematic for Output Voltage Tracking

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Figure 10-58. Scope Plot for Output Voltage Tracking

10.3.2 Synchronizing to an External Clock

The TPS6281xM device can be externally synchronized by applying an external clock on the MODE/SYNC pin.

There is no need for any additional circuitry as long as the input signal meets the requirements given in the

electrical specifications. The clock can be applied or removed during operation, letting the user switch from an

externally defined fixed frequency to power save mode or to an internally fixed-frequency operation. The value of

the R_CFresistor must be chosen so that the internally defined frequency and the externally applied frequency are

close to each other. This ensures a smooth transition from internal to external frequency and vice versa.

Figure 10-59. Schematic Using External Synchronization

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V_IN= 5 V

V_OUT= 1.8 V

R_CF= 8.06 kΩ

f_EXT= 2.5 MHz

I_OUT= 0.1 A

V_IN= 5 V

R_CF= 8.06 kΩ

f_EXT= 2.5 MHz

I_OUT= 1 A

V_OUT= 1.8 V

Figure 10-60. Switching from External

Figure 10-61. Switching from External

Syncronization to Power-Save Mode (PFM)

Synchronization to Internal Fixed Frequency

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11 Power Supply Recommendations

The TPS6281xM device family has no special requirements for its input power supply. The output current of the

input power supply needs to be rated according to the supply voltage, output voltage, and output current of the

TPS6281xM device.

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12 Layout

12.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more so at high switching

frequencies. Therefore, the PCB layout of the TPS6281xM device demands careful attention to ensure operation

and to get the specificed performance. A poor layout can lead to issues like poor regulation (both line and load),

stability, and accuracy weaknesses increased like EMI radiation and noise sensitivity.

See Section 12.2 for the recommended layout of the TPS6281xM device, which is designed for common

external ground connections. The input capacitor must be placed as close as possible between the VIN and

GND pin.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for

wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC

pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an

alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example

SW). Since they carry information about the output voltage, they must be connected as close as possible to the

actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R₁

and R₂, must be kept close to the IC and connect directly to those pins and the system ground plane.

The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help spread the heat

into the PCB.

The recommended layout is implemented on the EVM and shown in the TPS62810EVM-015 Evaluation Module

User's Guide.

12.2 Layout Example

GND

VIN

VOUT

Figure 12-1. Example Layout

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPS62810EVM-015 Evaluation Module, SLVUBG0

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

1-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS62811MWRWYR

TPS62813MWRWYR

VQFN-

HR

RWY

9

3000

180.0

12.4

2.25

3.25

1.15

4.0

12.0

Q1

VQFN-

HR

180.0

12.4

2.25

3.25

1.15

4.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS62811MWRWYR

TPS62813MWRWYR

VQFN-HR

RWY

9

3000

213.0

191.0

35.0

Pack Materials-Page 2

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS62812MWRWYR
厂家：	TEXAS INSTRUMENTS
描述：	TPS6281xM, Extended Temperature, 2.75-V to 6-V Adjustable-Frequency Step-Down DC/DC Converter
文件：	总39页 (文件大小：5073K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS62812MWRWYR [TI]

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TPS628132DQWRWYRQ1

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