TPS62816-Q1 [TI]
采用 2mm x 3mm 可湿性侧面 QFN 封装的汽车类 2.75V 至 6V、6A 降压转换器;
| 型号： | TPS62816-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2mm x 3mm 可湿性侧面 QFN 封装的汽车类 2.75V 至 6V、6A 降压转换器 转换器 |
| 文件： | 总43页 (文件大小：8261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62816-Q1
ZHCSNV7A –MARCH 2020 –REVISED DECEMBER 2021
TPS62816-Q1 采用3mm x 2mm 可湿性侧面QFN 封装的2.7V 至6V、6A 汽车类降
压转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TPS62816-Q1 是一款易于使用的引脚对引脚高效同步
降压直流/直流转换器。它基于峰值电流模式控制拓
扑，专为信息娱乐系统和高级驾驶辅助系统等汽车应用
而设计。低阻开关可支持高达 6A 的持续输出电流。用
户可通过外部方式在 1.8MHz 至 4MHz 范围内调节开
关频率，亦可在该频率范围内将其同步至外部时钟。在
PWM/PFM 模式下，TPS62816-Q1 会在轻负载情况下
自动进入省电模式，从而在整个负载范围内维持高效
率。TPS62816-Q1 可在 PWM 模式下提供 1% 的输出
电压精度，这有助于实现具有高输出电压精度的电源设
计。通过 SS/TR 引脚，可设置启动时间或跟踪向外部
源提供的输出电压。此特性可实现不同电源轨的外部时
序控制并限制启动期间的浪涌电流。
– 器件温度等级1：
–40°C 至+125°C TA
• 提供功能安全型
– 可帮助进行功能安全系统设计的文档
• 输入电压范围：2.7V 至6V
• 静态电流：26µA（典型值）
• 输出电压范围为0.6V 至5.5V
• 输出电压精度为±1%（PWM 操作）
• 可调软启动
• 强制PWM 或PWM/PFM 操作
• 可调开关频率为
1.8MHz 至4MHz
• 精密使能输入可实现
– 用户定义的欠压锁定
– 准确排序
TPS62816-Q1 是一个可调节版本，采用了具有可湿性
侧面的3mm x 2mm VQFN 封装。
器件信息
封装(1)
• 100% 占空比模式
• 有源输出放电
封装尺寸（标称值）
器件型号
• 展频时钟- 可选
TPS62816-Q1
VQFN
3.00mm × 2.00mm
• 具有窗口比较器的电源正常输出
• 封装具有可湿性侧面
• TJ = -40°C 至150°C
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
• ADAS 传感器融合
• 环视ECU
• 数字驾驶舱
• 外部放大器
L
100
95
90
85
80
75
70
65
V
IN
TPS62816-Q1
0.22mH
VOUT
2.7 V - 6 V
VIN
SW
C
IN
R1
22mF
CFF
EN
FB
COUT
MODE/SYNC
R2
R3 3 * 22 mF
COMP/FSET
SS/TR
CSS
PG
60
GND
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
55
50
典型应用原理图
100m
1m
10m 100m
Output Current (A)
1
6
D002
效率与输出电流间的关系；
VOUT = 3.3V；PWM/PFM；fS = 2.25MHz
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDM1
TPS62816-Q1
ZHCSNV7A –MARCH 2020 –REVISED DECEMBER 2021
www.ti.com.cn
Table of Contents
10 Application and Implementation................................15
10.1 Application Information........................................... 15
10.2 Typical Application.................................................. 16
10.3 System Examples................................................... 27
11 Power Supply Recommendations..............................30
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Example...................................................... 31
13 Device and Documentation Support..........................32
13.1 Device Support....................................................... 32
13.2 Documentation Support.......................................... 32
13.3 接收文档更新通知................................................... 32
13.4 支持资源..................................................................32
13.5 Trademarks.............................................................32
13.6 Electrostatic Discharge Caution..............................32
13.7 术语表..................................................................... 32
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Parameter Measurement Information............................8
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram...........................................9
9.3 Feature Description.....................................................9
9.4 Device Functional Modes..........................................12
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2020) to Revision A (December 2021)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Device Comparison Table
DEVICE NUMBER
FOLDBACK
CURRENT LIMIT
SPREAD SPECTRUM
OUTPUT VOLTAGE
CLOCKING (SSC)
VOUT DISCHARGE
ON
TPS62816QWRWYRQ1
OFF
by COMP/FSET pin
adjustable
6 Pin Configuration and Functions
bottom view
top view
7
COMP/FSET
8
8
7
COMP/FSET
EN
EN
6
9
9
6
SS/TR
PG
PG
SS/TR
GND
GND
SW
SW
VIN
VIN
MODE/SYNC
1
FB
FB
5
3
2
4
5
4
2
3
1
图6-1. 9-Pin VQFN RWY Package (Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN
8
I
I
FB
5
4
Voltage feedback input. Connect the resistive output voltage divider to this pin.
Ground pin
GND
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external frequency. See the Electrical
Characteristics for the detailed specification for the digital signal applied to this pin for
external synchronization.
MODE/SYNC
1
I
Device compensation and frequency set input. A resistor from this pin to GND defines the
compensation of the control loop as well as the switching frequency if not externally
synchronized.
COMP/FSET
PG
7
9
6
I
O
I
Open-drain power-good output
Soft-start / tracking pin. An external capacitor connected from this pin to GND defines the
rise time for the internal reference voltage. The pin can also be used as an input for tracking
and sequencing. See 节10.
SS/TR
SW
VIN
3
2
O
This is the switch pin of the converter and is connected to the internal power MOSFETs.
Power supply input. Make sure the input capacitor is connected as close as possible
between the VIN pin and PGND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
6.5
UNIT
VIN
SW (DC)
VIN + 0.3
10
SW (AC, less than 10 ns)(3)
Pin voltage(2)
V
FB
4
–0.3
–0.3
–0.3
–65
COMP/FSET, PG, SS/TR
EN, MODE/SYNC
VIN + 0.3
6.5
Tstg
Storage temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the network ground terminal
(3) While switching
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD classification level 2 (1)
Charged device model (CDM), per AEC Q100-011 CDM ESD classification level C5
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
2.7
0.6
0.15
32
NOM
MAX
6
UNIT
V
VIN
Input voltage range
VOUT
L
Output voltage range
5.5
0.3
470
V
Effective inductance
0.22
66
μH
μF
μF
kΩ
mA
°C
COUT
CIN
Effective output capacitance(1)
Effective input capacitance(1)
5
10
RCF
ISINK_PG
TJ
4.5
0
100
2
Sink current at PG pin
Junction temperature
150
–40
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer's DC bias curves for the effective capacitance versus DC voltage applied. Further restrictions may apply. Please see the
feature description for COMP/FSET about the output capacitance versus compensation setting and output voltage.
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7.4 Thermal Information
TPS62816-Q1
TPS62816-Q1
THERMAL METRIC(1)
RWY (JEDEC)
RWY (EVM)
UNIT
9 PINS
71
9 PINS
48
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
37
n/a
16.4
0.9
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
n/a
ΨJT
YJB
16.1
n/a
n/a
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, no load, device not switching,
TJ = 125°C, MODE = GND
IQ
Quiescent current
36
μA
EN = VIN, no load, device not switching,
MODE = GND, VOUT = 0.6 V
IQ
Quiescent current
Shutdown current
Shutdown current
26
50
90
μA
μA
μA
ISD
ISD
EN = GND, at TJ = 125°C
EN = GND, nominal value at TJ = 25°C,
max value at TJ = 150°C
2.2
230
VIN rising
VIN falling
TJ rising
TJ falling
2.45
2.1
2.6
2.5
180
15
2.7
2.6
V
V
VUVLO
Undervoltage lockout threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
CONTROL and INTERFACE
VIH,EN Input threshold voltage at EN, rising edge
VIL,EN
1.05
0.96
1.1
1.0
1.15
1.05
V
V
Input threshold voltage at EN, falling edge
High-level input-threshold voltage at
MODE/SYNC
VIH
1.1
V
nA
V
IIH,EN
VIL
Input leakage current into EN
VIH = VIN or VIL = GND
125
0.3
Low-level input-threshold voltage at
MODE/SYNC
IIH
Input leakage current into MODE/SYNC
Enable delay time
250
520
nA
µs
Time from EN high to device starts
switching; VIN applied already
tDelay
135
90
270
150
IOUT = 0 mA, time from device starts
switching to power good; device not in
current limit
Output voltage ramp time, SS/TR pin
open
tRamp
220
µs
ISS/TR
RDIS
SS/TR source current
8
10
12
µA
Internal discharge resistance on SS/TR
when EN = low
0.7
1.1
1.5
kΩ
Tracking gain
Tracking offset
VFB / VSS/TR
1
VFB when VSS/TR = 0 V
±1
mV
Frequency range on MODE/SYNC pin for
synchronization
fSYNC
1.8
4
MHz
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Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
%
Duty cycle of synchronization signal at
MODE/SYNC
20
80
Time to lock to external frequency
50
µs
resistance from COMP/FSET to GND for Internal frequency setting with f = 2.25
0
2.5
kΩ
logic low
MHz
internal frequency setting with f = 2.25
MHz
Voltage on COMP/FSET for logic high
VIN
95%
V
UVP power good threshold voltage; dc
level
VTH_PG
VTH_PG
rising (%VFB
)
92%
87%
98%
93%
UVP power good threshold voltage; dc
level
falling (%VFB
)
)
90%
OVP power good threshold voltage; dc
level
rising (%VFB
)
107%
104%
110%
113%
111%
VTH_PG
OVP power good threshold voltage; dc
level
falling (%VFB
107%
0.01
VOL,PG
IIH,PG
Low-level output voltage at PG
Input leakage current into PG
ISINK_PG = 2 mA
VPG = 5 V
0.3
V
100
nA
For a high level to low level transition on
the power good output
tPG
PG deglitch time
40
µs
OUTPUT
VFB
Feedback voltage
0.6
1
V
IIH,FB
VFB
Input leakage current into FB
Feedback voltage accuracy
VFB = 0.6 V
70
nA
1%
PWM, VIN ≥VOUT + 1 V
–1%
–1%
PFM, VIN ≥VOUT + 1 V, VOUT ≥1.5 V,
Co,eff ≥47 µF
VFB
VFB
VFB
Feedback voltage accuracy
Feedback voltage accuracy
2%
2.5%
5%
PFM, VIN ≥VOUT + 1 V, VOUT < 1.5 V,
Co,eff ≥68 µF
–1%
–5%
Feedback voltage accuracy with voltage
tracking
VIN ≥VOUT + 1 V, VSS/TR = 0.3 V, PWM
mode
Load regulation
PWM
0.05
0.02
%/A
%/V
Ω
Line regulation
PWM, IOUT = 1 A, VIN ≥VOUT + 1 V
RDIS
fSW
fSW
fSW
Output discharge resistance
50
4
MODE = high, see the FSET pin
functionality about setting the switching
frequency
PWM switching frequency range
1.8
2.25
2.25
MHz
MHz
PWM switching frequency
With COMP/FSET tied to GND or VIN
2.08
2.4
12%
67
using a resistor from COMP/FSET to
GND
PWM switching frequency tolerance
–12%
ton,min
ton,min
Minimum on time of high-side FET
Minimum on time of low-side FET
45
15
ns
ns
VIN ≥3.3 V, TJ = –40°C to 125°C
VIN ≥5 V
VIN ≥5 V
High-side FET on-resistance
11
26
mΩ
RDS(ON)
Low-side FET on-resistance
High-side MOSFET leakage current
Low-side MOSFET leakage current
SW leakage
9
0.01
0.01
19
230
290
30
mΩ
µA
µA
µA
A
IIH
IIH
V(SW) = 6 V
IIH
V(SW) = 0.6V, current into SW pin
DC value, VIN = 3 V to 6 V
-0.05
7.3
ILIMH
High-side FET switch current limit
9.2
10.4
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Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILIMNEG
Low-side FET negative current limit
DC value
-3
A
7.6 Typical Characteristics
30
20
19
18
17
16
15
14
13
12
11
10
9
VIN = 2.7V
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 2.7V
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
27.5
25
22.5
20
17.5
15
12.5
10
8
7
7.5
5
6
5
-40
-40
0
25 85
Junction Temperature (°C)
125
150
0
25 85
Junction Temperature (°C)
125
150
D002
D002
图7-1. RDS(ON) of High-Side Switch
图7-2. RDS(ON) of Low-Side Switch
4
3.6
3.2
2.8
2.4
2
25
24
23
22
21
20
19
18
17
16
15
VIN = 2.7V
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 2.7V
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
1.6
1.2
0.8
0.4
0
-40
0
25 85
Junction Temperature (°C)
125
150
-40
0
25 85
Junction Temperature (°C)
125
150
D002
D002
图7-3. Shutdown Current vs Temperature
图7-4. Quiescent Current vs Temperature
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8 Parameter Measurement Information
The graphs in this data sheet have been taken based on the schematic and BOM as listed in 表 8-1 if not
otherwise mentioned in the plots.
L
V
IN
TPS62816-Q1
0.22mH
VOUT
2.7 V - 6 V
VIN
SW
C
IN
R1
22mF
CFF
EN
FB
COUT
MODE/SYNC
R2
R3 3 * 22 mF
COMP/FSET
SS/TR
CSS
PG
GND
图8-1. Measurement Setup for TPS62816-Q1
表8-1. List of Components
DESCRIPTION
REFERENCE
MANUFACTURER (1)
IC
TPS62816-Q1
Texas Instruments
L
0.25-µH inductor; XGL4020-251ME
22 µF / 10 V; GCM31CR71A226KE02L
5 × 22 µF / 10 V; GCM31CR71A226KE02L
3 × 22 µF / 10 V; GCM31CR71A226KE02L
Coilcraft
Murata
Murata
Murata
any
CIN
COUT for VOUT = 0.6 V
COUT for VOUT ≥1 V
CSS
RCF
CFF
R1
15 nF (equal to 0.9-ms start-up ramp)
any
8.06 kΩ
10 pF
any
Depending on VOUT
Depending on VOUT
100 kΩ
any
R2
any
R3
any
(1) See the Third Party-Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS62816-Q1 synchronous switch mode power converter is based on a peak current mode control
topology. The control loop is internally compensated.
To optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with the
TPS62816-Q1, the internal compensation has two settings. See 节 9.3.2. One out of the two compensation
settings is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin. The regulation
network achieves fast and stable operation with small external components and low-ESR ceramic output
capacitors. The device requires a small feedforward capacitor on the output voltage divider for best transient
response. See 表10-2.
The device supports forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in a range
of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. An internal PLL allows the device to change from internal clock to
external clock during operation. The synchronization to the external clock is done on a falling edge of the clock
applied at MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is
used to generate the synchronization signal for a second converter. When the MODE pin is set to a logic low
level, the device operates in power save mode (PFM) at low output current and automatically transfers to fixed-
frequency PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based
on the load to sustain high efficiency down to very low output current.
9.2 Functional Block Diagram
VIN
SW
Bias
Regulator
Gate Drive and Control
Oscillator
Ipeak
Izero
EN
MODE
gm
GND
FB
_
+
PG
Device
Control
+
-
Bandgap
SS/TR
Thermal
Shutdown
COMP/FSET
9.3 Feature Description
9.3.1 Precise Enable
The voltage applied at the Enable (EN) pin of the TPS62816-Q1 is compared to a fixed threshold of 1.1 V for a
rising voltage. This allows the user to drive the pin by a slowly changing voltage and enables the use of an
external RC network to achieve a power-up delay.
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The precise enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of the EN pin.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62816-Q1 starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be
terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown
current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off and the
entire internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows the user to set two different parameters independently:
• Internal compensation settings for the control loop (three settings available)
• The switching frequency in PWM mode from 1.8 MHz to 4 MHz
• Enable/ disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows the user to adopt the device to different values of output capacitance. The resistor must
be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting
is sampled at the start-up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency, but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching
frequency or compensation. Do not leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on time and minimum off time.
Example: VIN = 5 V, VOUT = 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2
• with ton = DC × T --> ton,min = 1/fs,max × DC
• --> fs,max = 1/ton,min × DC = 1/0.075 µs × 0.2 = 2.6 MHz
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in 表 9-1, up to the maximum of 470 µF in all of the three
compensation ranges. If the capacitance of an output changes during operation, for example, when load
switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the
minimum capacitance on the output. With large output capacitance, the compensation must be done based on
that large capacitance to get the best load transient response. Compensating for large output capacitance but
placing less capacitance on the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
Space
18MHz ×kW
RCF(kW) =
fS(MHz)
(1)
(2)
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
Space
60MHz ×kW
RCF(kW) =
fS(MHz)
Space
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
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Space
180MHz ×kW
RCF(kW) =
fS(MHz)
(3)
表9-1. Switching Frequency and Compensation
MINIMUM OUTPUT
CAPACITANCE
COMPENSATION
RCF
SWITCHING FREQUENCY
for smallest output capacitance
(comp setting 1)
1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)
according to 方程式1
32 µF × V / VOUT[V]
32 µF × V / VOUT[V]
10 kΩ... 4.5 kΩ
SSC disabled
for smallest output capacitance
(comp setting 1)
1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)
according to 方程式2
33 kΩ... 15 kΩ
100 kΩ... 45 kΩ
tied to GND
SSC enabled
for best transient response
(larger output capacitance)
(comp setting 2)
1.8 MHz (100 kΩ) ... 4 MHz (45 kΩ)
according to 方程式3
72 µF × V / VOUT[V]
32 µF × V / VOUT[V]
72 µF × V / VOUT[V]
SSC disabled
for smallest output capacitance
(comp setting 1)
internally fixed 2.25 MHz
internally fixed 2.25 MHz
SSC disabled
for best transient response
(larger output capacitance)
(comp setting 2)
tied to VIN
SSC enabled
The minimum output capacitance required for stability depends on the output voltage as stated in 表 9-1. Refer
to 节10.1.2.2.2 for further details on the output capacitance required depending on the output voltage.
A too-high resistor value for RCF is decoded as "tied to VIN" and a value below the lowest range is decoded as
"tied to GND". The minimum output capacitance in 表9-1 is for capacitors close to the output of the device. If the
capacitance is distributed, a lower compensation setting can be required.
9.3.3 MODE/SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode depending on the output current. The
MODE/SYNC pin forces PWM mode when set high. The pin also allows the user to apply an external clock in a
frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET, the specifications
for the minimum on time and minimum off time have to be observed when setting the external frequency. For use
with external synchronization on the MODE/SYNC pin, the internal switching frequency must be set by RCF to a
similar value than the externally applied clock. This ensures that if the external clock fails, the switching
frequency stays in the same range. When there is no resistor from COMP/FSET to GND but the pin is pulled
high or low, external synchronization is not possible.
9.3.4 Spread Spectrum Clocking (SSC)
The device offers spread spectrum clocking as an option, set by the COMP/FSET pin. When SSC is enabled,
the switching frequency is randomly changed in PWM mode when the internal clock is used. The frequency
variation is typically between the nominal switching frequency and up to 288 kHz above the nominal switching
frequency. When the device is externally synchronized by applying a clock signal to the MODE/SYNC pin, the
TPS62816-Q1 follows the external clock and the internal spread spectrum block is turned off. SSC is also
disabled during soft start.
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both of
the power FETs. When enabled, the device is fully operational for input voltages above the rising UVLO
threshold and turns off if the input voltage trips below the threshold for a falling supply voltage.
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9.3.6 Power Good Output (PG)
Power good is an open-drain output driven by a window comparator. PG is held low when the device is disabled,
in undervoltage lockout, and thermal shutdown. When the output voltage is in regulation hence, within the
window defined in the electrical characteristics, the output is high impedance.
表9-2. PG Status
EN
X
DEVICE STATUS
PG STATE
undefined
low
VIN < 2 V
low
VIN ≥2 V
2 V ≤VIN ≤UVLO OR in thermal shutdown OR VOUT not in
high
high
low
regulation
VOUT in regulation
high impedance
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and
PG goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,
the device needs up to 9 µs to detect a too-high junction temperature. If the PFM burst is shorter than this delay,
the device does not detect a too-high junction temperature.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS62816-Q1 has two operating modes: Forced PWM mode as discussed in this section and PWM/PFM as
discussed in 节9.4.2.
With the MODE/SYNC pin set to high, the TPS62816-Q1 operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the
TPS62816-Q1 follows the frequency applied to the pin. In general, the frequency range in forced PWM mode is
1.8 MHz to 4 MHz. However, the frequency needs to be in a range the TPS62816-Q1 can operate at, taking the
minimum on time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of approximately 1.8 A. When the peak inductor current
drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency. In addition, the frequency set with the
resistor on COMP/FSET must be in a range of 1.8 MHz to 3.5 MHz. The high-side switch in a PFM pulse is
turned on until the inductor current reaches its peak current limit.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle
increases as the input voltage comes close to the output voltage and the off time gets smaller. When the
minimum off time of typically 10 ns is reached, the TPS62816-Q1 skips switching cycles while it approaches
100% mode. In 100% mode, it keeps the high-side switch on continuously. The high-side switch stays turned on
as long as the output voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum
dropout voltage in 100% mode is the product of the on-resistance of the high-side switch plus the series
resistance of the inductor and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS62816-Q1 is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the
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inductor current. The high-side switch turns on again only if the current in the low-side switch has decreased
below the low-side current limit. Due to internal propagation delay, the actual current can exceed the static
current limit. The dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
×tPD
(4)
where:
• ILIMH is the static current limit as specified in the electrical characteristics
• L is the effective inductance at the peak current
• VL is the voltage across the inductor (VIN - VOUT
)
• tPD is the internal propagation delay of typically 50 ns
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V
IN -VOUT
Ipeak(typ) = ILIMH
+
×50ns
L
(5)
9.4.5 Foldback Current Limit and Short Circuit Protection
This is valid for devices where foldback current limit is enabled.
When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current
limit from its nominal value to a typical peak current of 3.7 A. Foldback current limit is left when the current limit
indication goes away. For the case that device operation continues in current limit, it would, after 3072 switching
cycles, try again full current limit for again 1024 switching cycles.
9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled, but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active once the TPS62816-Q1 has been enabled at least once since the supply voltage was
applied. The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in
undervoltage lockout. The minimum supply voltage required for the discharge function to remain active typically
is 2 V. Output discharge is not activated during a current limit or foldback current limit event.
9.4.7 Soft Start/Tracking (SS/TR)
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs, then the internal reference and hence VOUT rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving the SS/TR pin disconnected provides the fastest start-up ramp with 150 µs typically. A capacitor
connected from SS/TR to GND is charged with 10 µA by an internal current source during soft start until it
reaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (tramp), therefore, is:
Css[nF]=10µA*tramp[ms]/0.6V
(6)
If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor
pulls the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new startup
sequence.
A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in both
directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load
current. The SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied on
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SS/TR is internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the external
voltage on SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R5 and R6 on
SS/TR, this makes sure the device "switches" to the internal reference voltage when the power-up sequencing is
finished. See 图10-57.
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10 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS62816-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to
5.5 V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of
the output voltage is set by the selection of the resistor divider from 方程式 7. It is recommended to choose
resistor values that allow a current of at least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lower
resistor values are recommended for the highest accuracy and most robust design.
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(7)
10.1.2 External Component Selection
10.1.2.1 Inductor Selection
The TPS62816-Q1 is designed for a nominal 0.22-µH inductor with a switching frequency of typically 2.25 MHz.
Larger values can be used to achieve a lower inductor current ripple, but they can have a negative impact on
efficiency and transient response. Smaller values than 0.22 µH cause a larger inductor current ripple, which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly. See the Recommended Operating
Conditions for details.
The inductor selection is affected by several effects like the following:
• Inductor ripple current
• Output ripple voltage
• PWM-to-PFM transition point
• Efficiency
In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). 方
程式8 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(8)
(9)
V
OUT
æ
ö
V
1-
OUT × ç
÷
IN
1
V
è
Lmin
ø
DIL(max)
=
×
f
SW
where:
• IL(max) is the maximum inductor current.
• ΔIL(max) is the peak-to-peak inductor ripple current.
• Lmin is the minimum inductance at the operating point.
表10-1. Typical Inductors
NOMINAL SWITCHING
FREQUENCY
DIMENSIONS [L × W ×
H] mm
TYPE
INDUCTANCE [µH]
CURRENT [A](1)
MANUFACTURER(2)
XEL4020-201ME
0.20 µH, ±20%
14
2.25 MHz
4 × 4 × 2.1
Coilcraft
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表10-1. Typical Inductors (continued)
NOMINAL SWITCHING
FREQUENCY
DIMENSIONS [L × W ×
H] mm
TYPE
INDUCTANCE [µH]
CURRENT [A](1)
MANUFACTURER(2)
XGL4020-251ME
XEL4030-201ME
0.25 µH, ±20%
0.20 µH, ±20%
12
17
2.25 MHz
2.25 MHz
4 × 4 × 2.1
4 × 4 × 3.2
Coilcraft
Coilcraft
(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.
(2) See the Third Party-Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well.
10.1.2.2 Capacitor Selection
10.1.2.2.1 Input Capacitor
For most applications, 22 µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for the best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.2.2.2 Output Capacitor
The architecture of the TPS62816-Q1 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended
to use dielectric X7R, X7T, or equivalent. Using a higher value has advantages, like smaller voltage ripple and a
tighter DC output accuracy in Power Save mode. The COMP/FSET pin allows the user to select two different
compensation settings based on the minimum capacitance used on the output. The maximum capacitance is
470 µF in any of the compensation settings.
The minimum capacitance required on the output depends on the compensation setting and output voltage.
For output voltages below 1 V, the minimum increases linearly from 32 µF at 1 V to 53 µF at 0.6 V with the
compensation setting for smallest output capacitance. Other compensation ranges are equivalent. See 表9-1 for
details.
10.2 Typical Application
L
V
IN
TPS62816-Q1
0.22mH
VOUT
2.7 V - 6 V
VIN
SW
C
IN
R1
22mF
CFF
EN
FB
COUT
MODE/SYNC
R2
R3 3 * 22 mF
COMP/FSET
SS/TR
CSS
PG
GND
图10-1. Typical Application
10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
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10.2.2 Detailed Design Procedure
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(10)
With VFB = 0.6 V:
表10-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
VOUT
R1
R2
CFF
EXACT OUTPUT VOLTAGE
0.8 V
1.0 V
1.1 V
1.2 V
15 pF
13 pF
6.8 pF
3.9 pF
0.7988 V
1.0 V
16.9 kΩ
20 kΩ
51 kΩ
30 kΩ
47 kΩ
68 kΩ
1.101 V
1.2 V
39.2 kΩ
68 kΩ
1.5 V
1.8 V
2.5 V
3.3 V
3.3 pF
3.3 pF
5.6 pF
3 pF
1.5 V
1.803 V
2.5 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
51 kΩ
40.2 kΩ
15 kΩ
3.315 V
19.6 kΩ
The maximum value for the feedforward capacitor CFF at minimum output capacitance is determined by 方程式
11:
CFF,max(F) = 2.661 × 10-7 F × Ω/ R1 (Ω)
(11)
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless otherwise noted.
The BOM is according to 表8-1.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
6
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
5.5
6
D002
D002
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-2. Efficiency Versus Output Current
图10-3. Efficiency Versus Output Current
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
VIN = 2.7 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
6
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
5.5
6
D002
D002
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-4. Efficiency Versus Output Current
图10-5. Efficiency Versus Output Current
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
VIN = 2.7 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
6
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
5.5
6
D002
D002
VOUT = 1.2 V
PFM
TA = 25°C
VOUT = 1.2 V
PWM
TA = 25°C
图10-6. Efficiency Versus Output Current
图10-7. Efficiency Versus Output Current
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10.2.3 Application Curves (continued)
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
6
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
5.5
6
D002
D002
VOUT = 1.0 V
PFM
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图10-8. Efficiency Versus Output Current
图10-9. Efficiency Versus Output Current
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
100m
1m
10m 100m
Output Current (A)
1
6
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
5.5
6
D002
D002
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图10-10. Efficiency Versus Output Current
图10-11. Efficiency Versus Output Current
3.4
3.33
3.39
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.3
3.324
3.318
3.312
3.306
3.3
3.294
3.288
3.282
3.276
3.27
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.29
3.28
3.27
100m
1m
10m 100m
Output Current (A)
1
6
100m
1m
10m 100m
Output Current (A)
1
6
D002
D002
VOUT = 3.3 V
PWM
TA = 25°C
VOUT = 3.3 V
PFM
TA = 25°C
图10-13. Output Voltage Versus Output Current
图10-12. Output Voltage Versus Output Current
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10.2.3 Application Curves (continued)
1.82
1.816
1.812
1.808
1.804
1.8
1.82
1.816
1.812
1.808
1.804
1.8
1.796
1.796
1.792
1.788
1.784
1.78
1.792
1.788
1.784
1.78
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
6
100m
1m
10m 100m
Output Current (A)
1
6
D002
D002
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-14. Output Voltage Versus Output Current
图10-15. Output Voltage Versus Output Current
1.224
1.2125
1.21
1.2075
1.205
1.2025
1.2
1.22
1.216
1.212
1.208
1.204
1.2
1.1975
1.195
1.1925
1.19
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.196
1.192
1.188
1.184
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.1875
100m
1m
10m 100m
Output Current (A)
1
6
100m
1m
10m 100m
Output Current (A)
1
6
D002
D002
VOUT = 1.2 V
PWM
TA = 25°C
VOUT = 1.2 V
PFM
TA = 25°C
图10-17. Output Voltage Versus Output Current
图10-16. Output Voltage Versus Output Current
1.02
1.01
1.017
1.014
1.011
1.008
1.005
1.002
0.999
0.996
0.993
0.99
1.008
1.006
1.004
1.002
1
0.998
0.996
0.994
0.992
0.99
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
6
100m
1m
10m 100m
Output Current (A)
1
6
D002
D002
VOUT = 1.0 V
PFM
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图10-18. Output Voltage Versus Output Current
图10-19. Output Voltage Versus Output Current
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10.2.3 Application Curves (continued)
0.612
0.61
0.606
0.6045
0.603
0.6015
0.6
0.608
0.606
0.604
0.602
0.6
0.5985
0.597
0.5955
0.594
0.598
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
0.596
0.594
100m
1m
10m 100m
Output Current (A)
1
6
100m
1m
10m 100m
Output Current (A)
1
6
D002
D002
VOUT = 0.6 V
PWM
TA = 25°C
VOUT = 0.6 V
PFM
TA = 25°C
图10-21. Output Voltage Versus Output Current
图10-20. Output Voltage Versus Output Current
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
IOUT = 0.6 A to 5.4 A to 0.6 A
图10-22. Load Transient Response
图10-23. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
IOUT = 0.6 A to 5.4 A to 0.6 A
图10-24. Load Transient Response
图10-25. Load Transient Response
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10.2.3 Application Curves (continued)
VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
IOUT = 0.6 A to 5.4 A to 0.6 A
图10-26. Load Transient Response
图10-27. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
图10-29. Load Transient Response
图10-28. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
IOUT = 0.6 A to 5.4 A to 0.6 A
IOUT = 0.6 A to 5.4 A to 0.6 A
图10-31. Load Transient Response
图10-30. Load Transient Response
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10.2.3 Application Curves (continued)
VOUT = 3.3 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 3.3 V
IOUT = 6 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-32. Line Transient Response
图10-33. Line Transient Response
VOUT = 1.8 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.8 V
IOUT = 6 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-34. Line Transient Response
图10-35. Line Transient Response
VOUT = 1.2 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.2 V
IOUT = 6 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-36. Line Transient Response
图10-37. Line Transient Response
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10.2.3 Application Curves (continued)
VOUT = 1.0 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.0 V
IOUT = 6 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-38. Line Transient Response
图10-39. Line Transient Response
VOUT = 0.6 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 0.6 V
IOUT = 6 A
PWM
TA = 25°C
VIN = 3.0 V to 3.6 V to 3.0 V
VIN = 3.0 V to 3.6 V to 3.0 V
图10-40. Line Transient Response
图10-41. Line Transient Response
VOUT = 3.3 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 6 A
IOUT = 0.2 A
图10-42. Output Voltage Ripple
图10-43. Output Voltage Ripple
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10.2.3 Application Curves (continued)
VOUT = 1.8 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 6 A
VOUT = 1.8 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
图10-45. Output Voltage Ripple
图10-44. Output Voltage Ripple
VOUT = 1.2 V
VIN = 5 V
图10-47. Output Voltage Ripple
PWM
TA = 25°C
IOUT = 6 A
VOUT = 1.2 V
VIN = 5 V
图10-46. Output Voltage Ripple
PFM
TA = 25°C
IOUT = 0.2 A
VOUT = 1.0 V
VIN = 5 V
图10-49. Output Voltage Ripple
PWM
TA = 25°C
IOUT = 6 A
VOUT = 1.0 V
VIN = 5 V
图10-48. Output Voltage Ripple
PFM
TA = 25°C
IOUT = 0.2 A
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10.2.3 Application Curves (continued)
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 6 A
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
IOUT = 0.2 A
图10-51. Output Voltage Ripple
图10-50. Output Voltage Ripple
VOUT = 3.3 V
VIN = 5 V
PWM or PFM
CSS = 15 nF
TA = 25°C
IOUT = 6 A
VOUT = 1.8 V
VIN = 5 V
PWM or PFM
CSS = 15 nF
TA = 25°C
IOUT = 6 A
图10-52. Start-Up Timing
图10-53. Start-Up Timing
VOUT = 1.0 V
VIN = 5 V
PWM or PFM
CSS = 15 nF
TA = 25°C
IOUT = 6 A
VOUT = 1.2 V
VIN = 5 V
PWM or PFM
CSS = 15 nF
TA = 25°C
IOUT = 6 A
图10-55. Start-Up Timing
图10-54. Start-Up Timing
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10.2.3 Application Curves (continued)
VOUT = 0.6 V
VIN = 3.3 V
PWM or PFM
CSS = 15 nF
TA = 25°C
IOUT = 6 A
图10-56. Start-Up Timing
10.3 System Examples
10.3.1 Voltage Tracking
The TPS62816-Q1 follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps the
output voltage according to the 0.6-V feedback voltage.
Tracking the 3.3 V of the primary device such that both rails reach their target voltage at the same time, requires
a resistor divider on SS/TR of the secondary device equal to the output voltage divider of the primary device.
The output current of 10 µA on the SS/TR pin causes an offset voltage on the resistor divider formed by R5 and
R6. The equivalent resistance of R5 // R6 must therefore be kept below 4 kΩ. The current from SS/TR causes a
slightly higher voltage across R6 than 0.6 V, which is desired because the secondary device switches to its
internal reference as soon as the voltage at SS/TR is higher than 0.6 V.
In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of the secondary
device to the output voltage or the power good signal of the primary device. The TPS62816-Q1 has a duty cycle
limitation defined by the minimum on time. For tracking down to low output voltages, the secondary device
cannot follow once the minimum duty cycle is reached. Enabling PFM mode while tracking is in progress
allowsthe user to ramp down the output voltage close to 0 V.
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Primary converter
TPS62816-Q1
VIN
2.7 V - 6 V
L
0.22 ꢀH
3.3 V
VIN
SW
10 pF
CIN
MODE/SYNC
22ꢀF
FB
COUT
EN
EN
3 * 22 ꢀF
SS/TR
COMP/FSET
22 nF
PG
GND
Secondary converter
TPS62816-Q1
L
0.22 ꢀH
1.8 V
VIN
SW
10 pF
CIN
22ꢀF
EN
FB
R5
COUT
MODE/SYNC
SS/TR
3 * 22 ꢀF
COMP/FSET
PG
R6
GND
图10-57. Schematic for Output Voltage Tracking
图10-58. Scope Plot for Output Voltage Tracking
10.3.2 Synchronizing to an External Clock
The TPS62816-Q1 can be externally synchronized by applying an external clock on the MODE/SYNC pin. There
is no need for any additional circuitry as long as the input signal meets the requirements given in the electrical
specifications. The clock can be applied or removed during operation, allowing the user to switch from an
externally defined fixed frequency to power save mode or to internal fixed-frequency operation. The value of the
RCF resistor must be chosen such that the internally defined frequency and the externally applied frequency are
close to each other. This ensures a smooth transition from internal to external frequency and vice versa.
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L
V
IN
TPS62816-Q1
0.22 mH
VOUT
2.7 V - 6 V
VIN
SW
C
IN
R1
22mF
C
FF
EN
FB
COUT
MODE/SYNC
R2
R 3 3 * 22 mF
COMP/FSET
SS/TR
fEXT
CSS
PG
GND
图10-59. Schematic Using External Synchronization
VIN = 5 V
VOUT = 1.8 V
IOUT = 0.2 A
VIN = 5 V
IOUT = 2 A
RCF = 8.06 kΩ
RCF = 8.06 kΩ
fEXT = 2.5 MHz
VOUT = 1.8 V
fEXT = 2.5 MHz
图10-60. Switching from External Synchronization 图10-61. Switching from External Synchronizaion
to Power Save Mode (PFM)
to Internal Fixed Frequency
10.3.3 Compensation Settings
The TPS62816-Q1 offers two different compensations settings using the COMP/FSET pin. This allows the user
to optimize the device regarding its transient response. For applications with no high requirements on transient
response, a small output capacitance is desired for small size and low cost. In such cases, COMP1 must used
so the TPS62816-Q1 is stable with as low as 32 μF of output capacitance. When the load is very dynamic,
adding output capacitance improves transient response, but its effect is limited since this also reduces the cross-
over frequency of the control loop. For such cases, COMP2 must be used as it increases the bandwidth, but
requires a larger output capacitance for stable operation. The following scope plots are taken for the same
conditions, but differ in the compensation setting. Since COMP2 demands 72-μF minimum output capacitance
for stability, both plots were both taken with 72 μF on the output to allow the user to compare the results. One
plot was taken for the COMP1 (RCF = 8.06 kΩ) and one for the COMP2 (RCF = 80.6 kΩ) compensation setting.
The scope plots show that for the same output capacitance of 72 μF, the transient response for COMP2 is
improved over the COMP1 setting.
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L
V
IN
TPS62816-Q1
0.22 ꢀH
VOUT
2.7 V - 6 V
VIN
SW
C
IN
R1
R2
22
ꢀF
CFF
EN
FB
COUT
MODE/SYNC
R3
72 ꢀF
COMP/FSET
SS/TR
CSS
PG
GND
图10-62. Schematic
VIN = 5 V
VIN = 5 V
VOUT = 1.8 V
RCF = 8.06 kΩ
COUT = 72 μF
RCF = 80.6 kΩ
COUT = 72 μF
VOUT = 1.8 V
IOUT = 0.6 A to 5.4 A to 0.6 A
IOUT = 0.6 A to 5.4 A to 0.6 A
图10-63. Load Transient Response with Setting
图10-64. Load Transient Response with Setting
COMP1
COMP2
11 Power Supply Recommendations
The TPS62816-Q1 device family does not have special requirements for its input power supply. The output
current of the input power supply needs to be rated according to the supply voltage, output voltage, and output
current of the TPS62816-Q1.
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12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS62816-Q1 demands careful attention to ensure operation and
to get the performance specified. A poor layout can lead to issues like the following:
• Poor regulation (both line and load)
• Stability and accuracy weaknesses
• Increased EMI radiation
• Noise sensitivity
See 节 12.2 for the recommended layout of the TPS62816-Q1, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances and narrow traces must be avoided. Loops that conduct an
alternating current must outline an area as small as possible, since this area is proportional to the energy
radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,
SW). Since they carry information about the output voltage, they must be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1
and R2, must be kept close to the IC and connect directly to those pins and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat
into the PCB.
The recommended layout is implemented on the EVM and shown in the TPS62816EVM-140 Evaluation Module
User's Guide.
12.2 Layout Example
GND
GND
VIN
VOUT
图12-1. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments, TPS62816EVM-140 Evaluation Module User's Guide
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62816QWRWYRQ1
ACTIVE
VQFN-HR
RWY
9
3000 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
816Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62816QWRWYRQ1 VQFN-
HR
RWY
9
3000
180.0
12.4
2.25
3.25
1.15
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RWY
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TPS62816QWRWYRQ1
9
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RWY 9
2 x 3, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226729/A
www.ti.com
PACKAGE OUTLINE
RWY0009A
VQFN-HR - 1 mm max height
SCALE 5.000
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
1.1
0.55
0.675
0.575
(0.2) TYP
6
0.55
0.45
5
7
A
A
4
SYMM
3
2
2
0.2 0.05
(0.9)
0.3
9X
0.2
0.1
0.05
0.5 TYP
C A B
C
8
1
9
0.4
0.3
4X
SYMM
0.675
0.575
0.1
C A B
C
0.05
4224015/B 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RWY0009A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
9
(0.65)
(0.55)
(0.35)
SEE SOLDER MASK DETAIL
(0.25)
(0.5)
1
8
3X (0.25)
2
(0.5)
SYMM
(2.65)
3
4
3X (2.3)
(R0.05) TYP
5
7
(0.775)
6
(0.775)
0.25
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MAX
ALL AROUND
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4224015/B 01/2018
NOTES: (continued)
3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RWY0009A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.25)
(0.65)
(0.775)
(0.31)
9
EXPOSED METAL
TYP
(0.775)
1
(0.21)
8
2
(0.5)
6X (1.05)
(2.65)
SYMM
3
4
6X (0.25)
7
(R0.05) TYP
5
6
SYMM
(1.25)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 1, 5, 7 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 25X
4224015/B 01/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RWY0009C
VQFN-HR - 1 mm max height
SCALE 5.000
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
A
-
A
3
0
.
0
0
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.1
0.55
(0.2) TYP
0.675
0.575
6
0.55
0.45
5
7
4
SYMM
3
2
A
A
2
0.2 0.05
(0.9)
0.3
9X
0.2
0.1
0.05
0.5 TYP
C A B
C
8
1
12X (0.16)
9
0.4
4X
SYMM
0.3
4X (0.2)
0.1
0.05
C A B
C
0.675
0.575
4226803/A 05/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RWY0009C
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
9
(0.65)
(0.55)
(0.35)
SEE SOLDER MASK DETAIL
(0.25)
(0.5)
1
8
3X (0.25)
2
(0.5)
SYMM
(2.65)
3
4
3X (2.3)
(R0.05) TYP
5
7
(0.775)
6
(0.775)
0.25
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MAX
ALL AROUND
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4226803/A 05/2021
NOTES: (continued)
3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RWY0009C
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.25)
(0.65)
(0.775)
(0.31)
9
EXPOSED METAL
TYP
(0.775)
1
(0.21)
8
2
(0.5)
6X (1.05)
(2.65)
SYMM
3
4
6X (0.25)
7
(R0.05) TYP
5
6
SYMM
(1.25)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 1, 5, 7 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 25X
4226803/A 05/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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