TPS628513DRLR [TI]
采用 SOT-583 封装的 2.7V 至 6V、3A 固定频率降压转换器 | DRL | 8 | -40 to 150;
| 型号： | TPS628513DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-583 封装的 2.7V 至 6V、3A 固定频率降压转换器 | DRL | 8 | -40 to 150 转换器 |
| 文件： | 总39页 (文件大小：3219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS628510, TPS628511, TPS628512, TPS628513
ZHCSLS6B –AUGUST 2020 –REVISED JUNE 2022
TPS62851x 采用SOT583 封装的2.7V 至6V、0.5A/1A/2A/3A 降压转换器
1 特性
3 说明
• 提供功能安全
TPS62851x 是引脚对引脚 0.5A、1A、2A（持续）和
3A（峰值）易用型高效同步降压直流/直流转换器系
列。它们基于峰值电流模式控制拓扑，低阻开关可支持
高达 2A 的持续输出电流和 3A 的峰值电流。开关频率
由内部固定为 2.25MHz，也可在 1.8MHz 至 4MHz 范
围内与外部时钟同步。在 PWM/PFM 模式下，
TPS62851x 会在轻负载时自动进入省电模式，从而在
整个负载范围内保持高效率。TPS62851x 可在 PWM
模式下提供1% 的输出电压精度，这有助于实现具有高
输出电压精度的电源设计。通过 SS/TR 引脚，用户可
设置启动时间或跟踪向外部源提供的输出电压，从而实
现不同电源轨的外部定序和限制启动期间的浪涌电流。
– 可帮助进行功能安全系统设计的文档
• 输入电压范围：2.7V 至6V
• 输出电压范围为0.6V 至5.5V
• 反馈电压精度为1%（整个温度范围）
• TJ = -40°C 至+150°C
• 0.5A、1A、2A（持续）和3A（峰值）系列器件
• PWM 中的开关频率：2.25MHz
• 外部同步为1.8MHz 至4MHz
• 强制PWM 或PWM/PFM 操作
• 静态电流：17µA（典型值）
• 可调软启动时间为10ms
• 精密使能输入可实现：
TPS62851x 采用 8 引脚 1.6mm × 2.1mm SOT583 封
装，可提供高功率密度解决方案。
– 用户定义的欠压锁定
– 准确排序
器件信息
封装(1)
• 100% 占空比模式
• 有源输出放电
封装尺寸（标称值）
器件型号
• 具有窗口比较器的电源正常输出
• 有关具有可选补偿的器件选项，请参阅TPS628501
TPS628510
TPS628511
TPS628512
TPS628513
1.60mm × 2.10 mm
SOT583
（包括引脚）
2 应用
• 电机驱动器
• 工厂自动化和控制
• 楼宇自动化
• 测试和测量
• 多功能打印机(MFP)
• 通用POL
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
95
90
85
80
75
70
65
L
V
IN
TPS62851x
0.47mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
2*10 mF
0603
R 1
CFF
COUT
EN
FB
2*10 mF
0603
MODE/SYNC
R2
R3
SS/TR
60
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
PG
55
50
GND
100m
1m
10m 100m
Output Current (A)
1
3
简化版原理图
效率和IOUT 间的关系，VOUT = 3.3V
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDO4
TPS628510, TPS628511, TPS628512, TPS628513
ZHCSLS6B –AUGUST 2020 –REVISED JUNE 2022
www.ti.com.cn
Table of Contents
9.4 Device Functional Modes..........................................11
10 Application and Implementation................................14
10.1 Application Information........................................... 14
10.2 Typical Application.................................................. 15
10.3 System Examples................................................... 26
11 Power Supply Recommendations..............................28
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 29
13 Device and Documentation Support..........................30
13.1 Device Support....................................................... 30
13.2 接收文档更新通知................................................... 30
13.3 支持资源..................................................................30
13.4 Trademarks.............................................................30
13.5 Electrostatic Discharge Caution..............................30
13.6 术语表..................................................................... 30
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................8
8 Parameter Measurement Information............................9
8.1 Schematic................................................................... 9
9 Detailed Description......................................................10
9.1 Overview...................................................................10
9.2 Functional Block Diagram.........................................10
9.3 Feature Description...................................................10
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (March 2021) to Revision B (June 2022)
Page
• 添加了TPS628513.............................................................................................................................................1
Changes from Revision * (August 2020) to Revision A (March 2021)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
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ZHCSLS6B –AUGUST 2020 –REVISED JUNE 2022
5 Device Comparison Table
TYPICAL
OUTPUT
CAPACITOR
OUTPUT
DEVICE NUMBER
VOUT
DISCHARGE
FOLDBACK
CURRENT LIMIT
SOFT
START
OUTPUT
VOLTAGE
PACKAGE
TYPE
CURRENT
External capacitor
on the SS/TR pin
TPS628510DRLR
TPS628511DRLR
TPS628512DRLR
TPS628513DRLR
0.5 A
1 A
ON
ON
ON
ON
OFF
OFF
OFF
OFF
Adjustable
Adjustable
Adjustable
Adjustable
DRL
DRL
DRL
DRL
2 × 10 μF
2 × 10 μF
2 × 10 μF
2 × 10 μF
External capacitor
on the SS/TR pin
External capacitor
on the SS/TR pin
2 A
External capacitor
on the SS/TR pin
3 A
TPS6285010MQDYCRQ1(1)
TPS62850140QDYCRQ1(1)
TPS62850240QDYCRQ1(1)
1A
1A
2A
ON
ON
ON
OFF
ON
Internal 1 ms
Internal 1 ms
Internal 1 ms
Fixed 1.8 V
Adjustable
Adjustable
DYC
DYC
DYC
2 × 10 μF
2 × 10 μF
2 × 10 μF
ON
(1) Preview
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6 Pin Configuration and Functions
FB
GND SW
PG
1
VIN
EN
MODE
SS/TR
图6-1. 8-Pin SOT583 DRL Package (Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN
2
I
I
FB
5
8
Voltage feedback input. Connect the resistive output voltage divider to this pin.
Ground pin
GND
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external frequency. See 节7.5 for the detailed
specification for the digital signal applied to this pin for external synchronization.
MODE/SYNC
3
I
PG
6
4
O
I
Open-drain power-good output
Soft-Start / Tracking pin. An external capacitor connected from this pin to GND defines the
rise time for the internal reference voltage. The pin can also be used as an input for tracking
and sequencing - see 节10.3.1 in this data sheet.
SS/TR
SW
VIN
7
1
This is the switch pin of the converter and is connected to the internal power MOSFETs.
Power supply input. Make sure the input capacitor is connected as close as possible
between the VIN pin and GND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
6.5
UNIT
V
VIN
SW (DC)
VIN + 0.3
10
Pin voltage(2)
SW (AC, less than 10 ns)(3)
SS/TR, PG
VIN + 0.3
6.5
–0.3
–0.3
–65
EN, MODE/SYNC, FB
Storage temperature
Tstg
150
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal.
(3) While switching
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
2.7
0.6
0.32
8
NOM
MAX
6
UNIT
V
VIN
Input voltage range
VOUT
L
Output voltage range
5.5
1.2
200
V
Effective inductance
0.47
10
μH
μF
μF
mA
A
COUT
CIN
Effective output capacitance(1)
Effective input capacitance(1)
Sink current at the PG pin
Output current, TPS628513(2)
Junction temperature
5
10
ISINK_PG
IOUT
TJ
0
2
3
0
150
°C
–40
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer's DC bias curves for the effective capacitance vs DC voltage applied.
(2) This part is designed for a 2-A continuous output current at a junction temperature of 105°C or 3-A continuous output current at a
junction temperature of 85°C; exceeding the output current or the junction temperature can significantly reduce lifetime.
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UNIT
7.4 Thermal Information
DRL (JEDEC)(2)
DRL (EVM)
8 PINS
60
THERMAL METRIC(1)
8 PINS
110
41.3
20
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
n/a
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
n/a
ΨJT
YJB
20
n/a
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) JEDEC standard PCB with four layers, no thermal vias
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, no load, device not switching,
MODE = GND, VOUT = 0.6 V
IQ
Quiescent current
17
36
48
μA
μA
EN = GND, nominal value at TJ = 25°C,
maximum value at TJ = 150°C
ISD
Shutdown current
1.5
VIN rising
VIN falling
TJ rising
TJ falling
2.45
2.1
2.6
2.5
170
15
2.7
2.6
V
V
VUVLO
Undervoltage lockout threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
CONTROL AND INTERFACE
VEN,IH Input threshold voltage at EN, rising edge
VEN,IL
1.05
0.96
1.1
1.0
1.15
1.05
V
V
Input threshold voltage at EN, falling edge
High-level input-threshold voltage at
MODE/SYNC
VIH
1.1
V
nA
V
IEN,LKG
VIL
ILKG
tDelay
Input leakage current into EN
VIH = VIN or VIL = GND
125
0.3
Low-level input-threshold voltage at
MODE/SYNC
Input leakage current into MODE/SYNC
Enable delay time
100
470
nA
µs
Time from EN high to device starts
switching; VIN applied already
85
150
1.3
Time from device starts switching to
power good; device not in current limit
tRamp
Output voltage ramp time
0.8
1.8
ms
Output voltage ramp time, SS/TR pin
open
Time from device starts switching to
power good; device not in current limit
tRamp
ISS/TR
90
2
150
210
2.8
µs
SS/TR source current
Tracking gain
2.5
1
μA
VFB / VSS/TR
Tracking offset
VFB when VSS/TR = 0 V
±1
mV
Frequency range on MODE/SYNC pin for
synchronization
fSYNC
1.8
4
MHz
Duty cycle of synchronization signal at
MODE/SYNC
20%
80%
Time to lock to external frequency
50
µs
UVP power-good threshold voltage;
DC level
VTH_PG
Rising (%VFB
)
92%
95%
98%
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Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Falling (%VFB
MIN
TYP
MAX
UNIT
UVP power-good threshold voltage;
DC level
VTH_PG
)
87%
90%
93%
OVP power-good threshold voltage;
DC level
Rising (%VFB
)
107%
104%
110%
113%
111%
VTH_PG
OVP power-good threshold voltage;
DC level
Falling (%VFB
)
107%
0.07
VPG,OL
IPG,LKG
Low-level output voltage at PG
Input leakage current into PG
ISINK_PG = 2 mA
VPG = 5 V
0.3
V
100
nA
For a high level to low level transition on
the power-good output
tPG
PG deglitch time
40
µs
OUTPUT
VFB
Feedback voltage, adjustable version
0.6
1
V
Input leakage current into FB, adjustable
version
IFB,LKG
VFB
VFB = 0.6 V
70
1%
2%
nA
Feedback voltage accuracy
PWM, VIN ≥VOUT + 1 V
–1%
–1%
PFM, VIN ≥VOUT + 1 V, VOUT ≥1.0 V,
VFB
Feedback voltage accuracy
C
o,eff ≥10 µF, L = 0.47µH
PFM, VIN ≥VOUT + 1 V, VOUT < 1.0 V,
o,eff ≥15 µF, L = 0.47 µH
VFB
VFB
Feedback voltage accuracy
3%
4%
–1%
–4%
C
Feedback voltage accuracy with voltage
tracking
VIN ≥VOUT + 1 V, VSS/TR = 0.3 V
Load regulation
PWM
0.05
0.02
%/A
%/V
Line regulation
PWM, IOUT = 1 A, VIN ≥VOUT + 1 V
RDIS
fSW
ton,min
ton,min
Output discharge resistance
PWM switching frequency
Minimum on time of high-side FET
Minimum on time of low-side FET
High-side FET on-resistance
Low-side FET on-resistance
High-side MOSFET leakage current
Low-side MOSFET leakage current
SW leakage
100
2.475
52
Ω
2.025
2.25
35
MHz
ns
ns
VIN = 3.3 V, TJ = –40°C to 125°C
10
65
120
70
44
70
11
VIN ≥5 V
VIN ≥5 V
mΩ
mΩ
µA
RDS(ON)
33
0.01
0.01
µA
V(SW) = 0.6 V, current into SW
µA
–0.05
DC value, for TPS628513;
VIN = 3 V to 6 V
ILIMH
ILIMH
ILIMH
High-side FET switch current limit
High-side FET switch current limit
High-side FET switch current limit
3.45
4.5
3.4
2.6
5.1
3.9
3.0
2.5
A
A
A
DC value, for TPS628512;
VIN = 3 V to 6 V
2.85
2.1
DC value, for TPS628511;
VIN = 3 V to 6 V
DC value, for TPS628510;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
Low-side FET negative current limit
1.6
2.1
A
A
ILIMNEG
DC value
–1.8
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7.6 Typical Characteristics
140
80
76
72
68
64
60
56
52
48
44
40
36
32
28
24
20
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
VIN = 6.0V
130
120
VIN = 6.0V
110
100
90
80
70
60
50
40
-40
0
25 85
Junction Temperature (°C)
125
150
-40
0
25 85
Junction Temperature (°C)
125
150
D002
D002
图7-1. RDS(ON) of High-Side Switch
图7-2. RDS(ON) of Low-Side Switch
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8 Parameter Measurement Information
8.1 Schematic
L
V
IN
TPS62851x
0.47mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
2*10 mF
0603
R 1
CFF
COUT
2*10 mF
0603
EN
FB
MODE/SYNC
R2
R3
SS/TR
PG
GND
图8-1. Measurement Setup
表8-1. List of Components
DESCRIPTION
REFERENCE
MANUFACTURER (1)
IC
L
TPS628512
Texas Instruments
Murata
Murata
Murata
Murata
Any
0.47-µH inductor DFE201210U
CIN
COUT
COUT
CSS
CFF
R1
2 × 10 µF / 6.3 V GRM188D70J106MA73
2 × 10 µF / 6.3 V GRM188D70J106MA73 for VOUT ≥1 V
3 × 10 µF / 6.3 V GRM188D70J106MA73 for VOUT < 1 V
4.7 nF (equal to 1-ms start-up ramp); GCM188R72A472KA37
10 pF
Any
Depending on VOUT
Any
R2
Depending on VOUT
Any
R3
Any
100 kΩ
(1) See the Third-Party Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS62851x synchronous switch mode power converters are based on a peak current mode control
topology. The control loop is internally compensated.
The regulation network achieves fast and stable operation with small external components and low-ESR ceramic
output capacitors. The devices can be operated without a feedforward capacitor on the output voltage divider,
however, using a typically 10-pF feedforward capacitor improves transient response.
The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as 2.25 MHz internally fixed. Alternatively, the devices can be synchronized to an external
clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no need for additional passive
components. An internal PLL allows you to change from internal clock to external clock during operation. The
synchronization to the external clock is done on a falling edge of the clock applied at MODE to the rising edge on
the SW pin. This allows a roughly 180° phase shift when the SW pin is used to generate the synchronization
signal for a second converter. When the MODE pin is set to a logic low level, the device operates in power save
mode (PFM) at low output current and automatically transfers to fixed frequency PWM mode at higher output
current. In PFM mode, the switching frequency decreases linearly based on the load to sustain high efficiency
down to very low output current.
9.2 Functional Block Diagram
VIN
SW
Bias
Regulator
Gate Drive and Control
Oscillator
Ipeak
Izero
EN
MODE
gm
GND
FB
Device
Control
PG
+
-
Bandgap
SS/TR
Thermal
Shutdown
9.3 Feature Description
9.3.1 Precise Enable (EN)
The voltage applied at the enable pin of the TPS62851x is compared to a fixed threshold of 1.1 V for a rising
voltage. This allows you to drive the pin by a slowly changing voltage and enables the use of an external RC
network to achieve a power-up delay.
The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of the Enable pin.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62851x starts operation when the rising threshold is exceeded. For proper operation, the enable (EN) pin
must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown, with
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a shutdown current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off
and the entire internal control circuitry is switched off.
9.3.2 MODE / SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The
MODE/SYNC pin allows you to force PWM mode when set high. The pin also allows you to apply an external
clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. The specifications for the
minimum on-time and minimum off-time have to be observed when setting the external frequency. The external
clock must be set to about 2.25 MHz initially and then increased or decreased to the desired frequency. This
ensures a low distortion of the output voltage when the external frequency is applied.
9.3.3 Spread Spectrum Clocking (SSC)
If interested in this option, please contact Texas Instruments. The device offers spread spectrum clocking as an
option. When SSC is enabled, the switching frequency is randomly changed in PWM mode when the internal
clock is used. The frequency variation is typically between the nominal switching frequency and up to 288 kHz
above the nominal switching frequency. When the device is externally synchronized by applying a clock signal to
the MODE/SYNC pin, the TPS62851x follows the external clock and the internal spread spectrum block is turned
off. SSC is also disabled during soft start.
9.3.4 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the
power FETs. When enabled, the device is fully operational for input voltages above the rising UVLO threshold
and turns off if the input voltage trips below the threshold for a falling supply voltage.
9.3.5 Power Good Output (PG)
Power good is an open-drain output that requires a pullup resistor to any voltage up to the recommended input
voltage level. It is driven by a window comparator. PG is held low when the device is disabled, in undervoltage
lockout in thermal shutdown, and not in soft start. When the output voltage is in regulation hence, within the
window defined in the electrical characteristics, the output is high impedance.
VIN must remain present for the PG pin to stay low. If the power good output is not used, it is recommended to tie
to GND or leave open. The PG indicator features a de-glitch, as specified in the electrical characteristics, for the
transition from "high impedance" to "low" of its output.
表9-1. PG Status
EN
X
DEVICE STATUS
PG STATE
undefined
low
VIN < 2 V
low
VIN ≥2 V
2 V ≤VIN ≤UVLO OR in thermal shutdown OR VOUT not in
high
high
low
regulation OR device in soft start
VOUT in regulation
high impedance
9.3.6 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,
the device needs up to 9 µs to detect a junction temperature that is too high. If the PFM burst is shorter than this
delay, the device does not detect a junction temperature that is too high.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS62851x has two operating modes: forced PWM mode, which is discussed in this section, and
PWM/PFM as discussed in 节9.4.2.
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With the MODE/SYNC pin set to high, the TPS62851x operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is 2.25 MHz or defined by an external clock signal applied to
the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the TPS62851x follow the frequency
applied to the pin. In general, the frequency range in forced PWM mode is 1.8 MHz to 4 MHz. However, the
frequency needs to be in a range the TPS62851x can operate at, taking the minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of about 0.8 A. When the peak inductor current drops
below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle
increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the
minimum off-time of typically 10 ns is reached, the TPS62851x skips switching cycles while it approaches 100%
mode. In 100% mode, it keeps the high-side switch on continuously. The high-side switch stays turned on as
long as the output voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum
dropout voltage in 100% mode is the product of the on-resistance of the high-side switch plus the series
resistance of the inductor and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS62851x is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side switch turns on again only if the current in the low side-switch has decreased
below the low side current limit. Due to internal propagation delay, the actual current can exceed the static
current limit. The dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
×tPD
(1)
where
• ILIMH is the static current limit as specified in the electrical characteristics
• L is the effective inductance at the peak current
• VL is the voltage across the inductor (VIN - VOUT
)
• tPD is the internal propagation delay of typically 50 ns
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V
IN -VOUT
Ipeak(typ) = ILIMH
+
×50ns
L
(2)
9.4.5 Foldback Current Limit and Short Circuit Protection
This is valid for devices where foldback current limit is enabled. If interested in this option, please contact Texas
Instruments.
When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current
limit from its nominal value to typically 1.3 A. Foldback current limit is left when the current limit indication goes
away. If device operation continues in current limit, it would, after 3072 switching cycles, try for full current limit
again for 1024 switching cycles.
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9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled and to keep the output voltage close to 0 V when the device is off. The output discharge feature
is only active once the TPS62851x have been enabled at least once since the supply voltage was applied. The
discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage lockout.
The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output
discharge is not activated during a current limit or foldback current limit event.
9.4.7 Soft Start / Tracking (SS/TR)
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs, then the internal reference and hence VOUT rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving the SS/TR pin un-connected provides the fastest start-up ramp with 160 µs typically. A capacitor
connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until it
reaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (tramp) therefore is:
(3)
If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor
pulls the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new start-up
sequence.
A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in both
directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load
current. The SS/TR pin must not be connected to the SS/TR pin of other devices. The maximum value for CSS is
47 nF to ensure proper discharge before the device starts to ramp the output voltage.
9.4.8 Input Overvoltage Protection
When the input voltage exceeds the absolute maximum rating, the device is set to PFM mode so it cannot
transfer energy from the output to the input.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS62851x is adjustable. It can be programmed for output voltages from 0.6 V to 5.5
V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of the
output voltage is set by the selection of the resistor divider from Equation 6. It is recommended to choose
resistor values that allow a current of at least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lower
resistor values are recommended for highest accuracy and most robust design.
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(4)
10.1.2 Inductor Selection
The TPS62851x is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.
Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on
efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly. See 节7.3 for details.
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). 方程式5 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(5)
(6)
V
OUT
æ
ö
V
1-
OUT × ç
÷
IN
1
V
è
Lmin
ø
DIL(max)
=
×
f
SW
where
• IL(max) is the maximum inductor current
• ΔIL(max) is the peak-to-peak inductor ripple current
• Lmin is the minimum inductance at the operating point
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TYPE
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表10-1. Typical Inductors
NOMINAL
SWITCHING
FREQUENCY
INDUCTANCE
[µH]
CURRENT [A]
DIMENSIONS
[LxBxH] mm
FOR DEVICE
MANUFACTURER(2)
(1)
DFE201210U-R47M
DFE201210U-1R0M
0.47 µH, ±20%
1 µH, ±20%
see data sheet
see data sheet
TPS628510/511 / 512
TPS628510/511 / 512
2.25 MHz
2.25 MHz
2.0 x 1.2 x 1.0
2.0x 1.2 x 1.0
Murata
Murata
DFE201210U-R68
XEL3515-561ME
XFL4015-701ME
XFL4015-471ME
0.68 µH, ±20%
0.56 µH, ±20%
0.70 µH, ±20%
0.47 µH, ±20%
see data sheet
TPS628510/511 / 512
TPS628510/511 / 512
TPS628510/511 / 512
TPS628510/511 / 512
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.0x 1.2 x 1.0
3.5 x 3.2 x 1.5
4.0 x 4.0 x 1.6
4.0 x 4.0 x 1.6
Murata
Coilcraft
Coilcraft
Coilcraft
4.5
3.3
3.5
(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.
(2) See the Third-Party Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well.
10.1.3 Capacitor Selection
10.1.3.1 Input Capacitor
For most applications, 10-µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.3.2 Output Capacitor
The architecture of the TPS62851x allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended
to use X7R or X5R dielectric. Using a higher value has advantages like smaller voltage ripple and a tighter DC
output accuracy in power save mode.
10.2 Typical Application
L
V
IN
TPS62851x
0.47mH
VOUT
2.7 V - 6 V
CIN
VIN
SW
R 1
CFF
2*10 mF
0603
COUT
EN
FB
2*10 mF
0603
MODE/SYNC
R2
R3
SS/TR
PG
GND
图10-1. Typical Application for Indy
10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
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10.2.2 Detailed Design Procedure
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(7)
With VFB = 0.6 V:
表10-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE VOUT
R1
R2
CFF
EXACT OUTPUT VOLTAGE
0.8 V
1.0 V
1.1 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
0.7988 V
1.0 V
16.9 kΩ
20 kΩ
51 kΩ
30 kΩ
47 kΩ
68 kΩ
51 kΩ
40.2 kΩ
15 kΩ
19.6 kΩ
1.101 V
1.2 V
39.2 kΩ
68 kΩ
1.5 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
1.803 V
2.5 V
3.315 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless
otherwise noted. The BOM is according to 图8-1.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Output Current (A)
100m
1
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3
3
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-2. Efficiency Versus Output Current
图10-3. Efficiency Versus Output Current
100
95
90
85
80
75
70
95
90
85
80
75
65
60
55
50
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
70
65
100m
1m
10m 100m
Output Current (A)
1
3
0
0.5
1
1.5
Output Current (A)
2
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-4. Efficiency Versus Output Current
图10-5. Efficiency Versus Output Current
100
95
90
85
80
75
70
95
90
85
80
75
70
65
60
55
50
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
65
60
55
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
3
0
0.5
1
1.5
Output Current (A)
2
2.5
VOUT = 1.1 V
PFM
TA = 25°C
VOUT = 1.1 V
PWM
TA = 25°C
图10-6. Efficiency Versus Output Current
图10-7. Efficiency Versus Output Current
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90
85
80
75
70
65
60
55
90
85
80
75
70
65
60
55
50
45
VIN = 2.7 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
50
45
40
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
100m
1m
10m 100m
Output Current (A)
1
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图10-8. Efficiency Versus Output Current
图10-9. Efficiency Versus Output Current
3.33
3.324
3.318
3.312
3.306
3.3
3.33
3.324
3.318
3.312
3.306
3.3
3.294
3.288
3.282
3.294
3.288
3.282
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.276
3.27
3.276
3.27
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-10. Output Voltage Versus Output Current
图10-11. Output Voltage Versus Output Current
1.82
1.816
1.812
1.808
1.804
1.8
1.82
1.816
1.812
1.808
1.804
1.8
1.796
1.796
1.792
1.788
1.784
1.78
1.792
1.788
1.784
1.78
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-12. Output Voltage Versus Output Current
图10-13. Output Voltage Versus Output Current
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1.11
1.108
1.106
1.104
1.102
1.1
1.11
1.108
1.106
1.104
1.102
1.1
1.098
1.096
1.094
1.092
1.098
1.096
1.094
1.092
1.09
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
1.09
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 1.1 V
PFM
TA = 25°C
VOUT = 1.1 V
PWM
TA = 25°C
图10-14. Output Voltage Versus Output Current
图10-15. Output Voltage Versus Output Current
0.612
0.606
0.6045
0.603
0.6015
0.6
0.61
0.608
0.606
0.604
0.602
0.6
0.5985
0.597
VIN = 2.7 V
VIN = 3.3 V
VIN = 2.7 V
0.598
VIN = 3.3 V
0.5955
0.594
VIN = 4.0 V
VIN = 5.0 V
VIN = 4.0 V
VIN = 5.0 V
0.596
0.594
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 0.6 V
PWM
TA = 25°C
VOUT = 0.6 V
PFM
TA = 25°C
图10-17. Output Voltage Versus Output Current
图10-16. Output Voltage Versus Output Current
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
1.00
0.75
0.50
0.25
0.00
1.00
0.75
0.50
0.25
0.00
35
45
55
65
75
85
95
105 115 125
35
45
55
65
75
85
95
105 115 125
Ambient temperature (èC)
Ambient temperature (èC)
VOUT = 0.6 V
PWM
VOUT = 1.1 V
PWM
θJA = 60°C/W
θJA = 60°C/W
图10-18. Output Current Versus Ambient
图10-19. Output Current Versus Ambient
Temperature
Temperature
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3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
1.00
0.75
0.50
0.25
0.00
VIN=4.2V
VIN=5.0V
VIN=6.0V
35
45
55
65
75
85
95
105 115 125
35
45
55
65
75
85
95
105 115 125
Ambient temperature (èC)
Ambient temperature (èC)
VOUT = 1.8 V
PWM
VOUT = 3.3 V
PWM
θJA = 60°C/W
θJA = 60°C/W
图10-20. Output Current Versus Ambient
图10-21. Output Current Versus Ambient
Temperature
Temperature
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-22. Load Transient Response
图10-23. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-24. Load Transient Response
图10-25. Load Transient Response
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VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-26. Load Transient Response
图10-27. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-28. Load Transient Response
图10-29. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-30. Load Transient Response
图10-31. Load Transient Response
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VOUT = 3.3 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 3.3 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-32. Line Transient Response
图10-33. Line Transient Response
VOUT = 1.8 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.8 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-34. Line Transient Response
图10-35. Line Transient Response
VOUT = 1.2 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.2 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-36. Line Transient Response
图10-37. Line Transient Response
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VOUT = 1.0 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.0 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-38. Line Transient Response
图10-39. Line Transient Response
VOUT = 0.6 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 0.6 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 3.0 V to 3.6 V to 3.0 V
VIN = 3.0 V to 3.6 V to 3.0 V
图10-40. Line Transient Response
图10-41. Line Transient Response
VOUT = 3.3 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
图10-42. Output Voltage Ripple
图10-43. Output Voltage Ripple
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VOUT = 1.8 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
图10-44. Output Voltage Ripple
图10-45. Output Voltage Ripple
VOUT = 1.2 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
VOUT = 1.2 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
图10-46. Output Voltage Ripple
图10-47. Output Voltage Ripple
VOUT = 1.0 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
VOUT = 1.0 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
图10-48. Output Voltage Ripple
图10-49. Output Voltage Ripple
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VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
图10-50. Output Voltage Ripple
图10-51. Output Voltage Ripple
VOUT = 3.3 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
VOUT = 1.8 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
IOUT = 2 A
图10-52. Start-Up Timing
图10-53. Start-Up Timing
VOUT = 1.2 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
VOUT = 1.0 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
图10-54. Start-Up Timing
图10-55. Start-Up Timing
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VOUT = 0.6 V
VIN = 3.3 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
图10-56. Start-Up Timing
10.3 System Examples
10.3.1 Voltage Tracking
The TPS62851x follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps the
output voltage according to the 0.6-V feedback voltage.
Tracking the 3.3 V of device 1, so that both rails reach their target voltage at the same time, requires a resistor
divider on SS/TR of device 2 equal to the output voltage divider of device 1. The output current of 2.5 µA on the
SS/TR pin causes an offset voltage on the resistor divider formed by R5 and R6. The equivalent resistance of
R5 // R6 must be kept below 15 kΩ. The current from SS/TR causes a slightly higher voltage across R6 than 0.6
V, which is desired because device 2 switches to its internal reference as soon as the voltage at SS/TR is higher
than 0.6 V.
In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of device 2 to the
output voltage or the power good signal of device 1, the master device. The TPS6281x does have a duty cycle
limitation defined by the minimum on-time. For tracking down to low output voltages, device 2 cannot follow once
the minimum duty cycle is reached. Enabling PFM mode while tracking is in progress allows the user to ramp
down the output voltage close to 0 V.
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Device 1 (Primary)
TPS62851x
V
L
IN
0.47 μH
2.7 V - 6 V
3.3 V
VIN
SW
10 pF
CIN
MODE/SYNC
2*10 μF
FB
0603
COUT
EN
EN
2*10 μF
0603
SS/TR
22 nF
PG
GND
Device 2 (Secondary)
TPS62851x
L
0.47 μH
1.8 V
VIN
SW
2*10 μF
CIN
10 pF
0603
EN
FB
R
5
COUT
2*10 μF
0603
MODE/SYNC
SS/TR
PG
R
6
GND
图10-57. Schematic for Output Voltage Tracking
图10-58. Scope Plot for Output Voltage Tracking
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10.3.2 Synchronizing to an External Clock
The TPS62851x can be externally synchronized by applying an external clock on the MODE/SYNC pin. There is
no need for any additional circuitry as long as the input signal meets the requirements given in the electrical
specifications. The clock can be applied / removed during operation, allowing you to switch from an externally
defined fixed frequency to power-save mode or to internal fixed frequency operation.
L
V
IN
TPS62851x
0.47 mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
R1
2*10 mF
0603
CFF
EN
FB
COUT
MODE/SYNC
R2
R 3
2*10 mF
0603
SS/TR
fEXT
PG
GND
图10-59. Schematic using External Synchronization
VIN = 5 V
VOUT = 1.8 V
IOUT = 0.1 A
VIN = 5 V
IOUT = 0.1 A
RCF = 8.06 kΩ
RCF = 8.06 kΩ
fEXT = 2.5 MHz
fEXT = 2.5 MHz
VOUT = 1.8 V
图10-60. Switching from External Syncronization 图10-61. Switching from External Synchronizaion
to Power-Save Mode (PFM)
to Internal Fixed Frequency
11 Power Supply Recommendations
The TPS62851x device family does not have special requirements for its input power supply. The output current
of the input power supply needs to be rated according to the supply voltage, output voltage, and output current
of the TPS62851x.
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12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS62851x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like the following:
• Poor regulation (both in 节12.2 and load)
• Stability and accuracy weaknesses
• Increased EMI radiation
• Noise sensitivity
See 图 12-1 for the recommended layout of the TPS62851x, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances and narrow traces must be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy
radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,
SW). As they carry information about the output voltage, they must be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1
and R2, must be kept close to the IC and be connected directly to the pin and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat
into the PCB.
The recommended layout is implemented on the EVM and shown in the TPS62851xEVM-139 Evaluation Module
User's Guide.
12.2 Layout Example
COUT
V
OUT
GND
2
Solution size = 30mm
L
CIN
R2
U1
Css
V
IN
GND
图12-1. Example Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS628510DRLR
TPS628511DRLR
TPS628512DRLR
TPS628513DRLR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
8
8
8
8
4000 RoHS & Green
4000 RoHS & Green
4000 RoHS & Green
4000 RoHS & Green
Call TI | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
1000
1100
1200
1300
Samples
Samples
Samples
Samples
Call TI | SN
Call TI | SN
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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31-Jan-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS628510DRLR
TPS628511DRLR
TPS628512DRLR
TPS628513DRLR
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
8
8
8
8
4000
4000
4000
4000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.75
2.75
2.75
2.75
1.9
1.9
1.9
1.9
0.8
0.8
0.8
0.8
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS628510DRLR
TPS628511DRLR
TPS628512DRLR
TPS628513DRLR
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
8
8
8
8
4000
4000
4000
4000
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
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EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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