TPS6286910CRQYR [TI]
TPS62868x 2.4-V to 5.5-V Input, 4-A/6-A Synchronous Step-Down Converter with I2C Interface in QFN Package;型号: | TPS6286910CRQYR |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS62868x 2.4-V to 5.5-V Input, 4-A/6-A Synchronous Step-Down Converter with I2C Interface in QFN Package |
文件: | 总40页 (文件大小:2576K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS62868, TPS62869
SLVSFS3B – SEPTEMBER 2020 – REVISED JULY 2021
TPS62868x 2.4-V to 5.5-V Input, 4-A/6-A Synchronous Step-Down Converter with I2C
Interface in QFN Package
1 Features
2 Applications
•
•
•
•
11-mΩ and 10.5-mΩ internal power MOSFETs
>90% efficiency (0.9-V output)
DCS-Control topology for fast transient response
Available output voltage ranges for dynamic
voltage scaling (DVS) through I2C
– Output voltage range from 0.2-V to 0.8375-V
with 2.5-mV step size
– Output voltage range from 0.4-V to 1.675-V
with 5-mV step size
– Output voltage range from 0.8-V to 3.35-V with
10-mV step size
•
Core supply for FPGAs, CPUs, ASICs, or video
chipsets
IP network camera
Solid-state drives
Optical modules
•
•
•
•
LPDDR5 VDDQ rail supply
3 Description
The TPS62868 and TPS62869 devices are high-
frequency synchronous step-down converters with I2C
interface which provide an efficient, adaptive, and
high power-density solution. At medium to heavy
loads, the converter operates in PWM mode and
automatically enters Power Save Mode operation at
light load to maintain high efficiency over the entire
load current range. The device can also be forced
in PWM mode operation for smallest output voltage
ripple. Together with its DCS-Control architecture,
excellent load transient performance and tight output
voltage accuracy are achieved. Through the I2C
interface and a dedicated VID pin, the output voltage
is quickly adjusted to adapt the power consumption of
the load to the ever-changing performance needs of
the application.
•
•
•
1% output voltage accuracy
2.4-MHz switching frequency
Selection by external resistor
– Start-up output voltage
– I2C target address
•
Selection by I2C interface
– Power save mode or forced PWM mode
– Output discharge
– Hiccup or latching short-circuit protection
– Output voltage ramp speed
•
•
Thermal pre-warning and thermal shutdown
Power good indicator pin option with window
comparator
•
•
I2C-compatible interface up to 3.4 Mbps
Available in 1.5-mm x 2.5-mm x 1.0-mm 9-pin QFN
package with 0.5-mm pitch
Device Information
PART NUMBER
TPS62868
TPS62869
PACKAGE(1)
BODY SIZE (NOM)
QFN (9)
1.5 x 2.5 x 1.0 mm
•
•
Also available in WCSP package: TPS62866,
6-A synchronous step-down converter with I2C
interface in 1.05-mm x 1.78-mm WCSP package
Create a custom design using with TPS62868/9
with the WEBENCH® Power Designer
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
95
90
85
80
75
70
VIN
2.4 V to 5.5 V
L1
0.22 µH
TPS62868/9
VOUT
VIN
EN
SW
C1
VOS
C2
65
VSET/VID
or PG
VOUT = 0.6V, PWM
SCL
SDA
I2C
60
55
50
45
VOUT = 0.6V, PSM
VOUT = 1.2V, PSM
VOUT = 0.9V, PWM
VOUT = 0.9V, PSM
VOUT = 1.2V, PWM
R1
AGND PGND
100m
1m
10m
Load (A)
100m
1
6
D000
Typical Application
Efficiency at VIN = 3.3 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62868, TPS62869
SLVSFS3B – SEPTEMBER 2020 – REVISED JULY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................7
7.6 I2C InterfaceTiming Characteristics ........................... 8
7.7 Typical Characteristics.............................................. 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................14
8.5 Programming............................................................ 16
8.6 Register Map.............................................................19
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
9.3 Typical Application – TPS6286x0A and
TPS6286x0xC Devices............................................... 28
10 Power Supply Recommendations..............................30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................32
12.1 Device Support....................................................... 32
12.2 Documentation Support.......................................... 32
12.3 Support Resources................................................. 32
12.4 Receiving Notification of Documentation Updates..32
12.5 Trademarks.............................................................32
12.6 Glossary..................................................................32
12.7 Electrostatic Discharge Caution..............................32
13 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (July 2021)
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Globally changed instances of legacy terminology to controller and target where I2C is mentioned..................1
Corrected start-up output voltage for TPS6286xxxC device variants in Device Options table...........................3
Changed "VID" to "VSET/VID" in Device Options table......................................................................................3
Added inductor values to Recommended Operating Conditons table................................................................5
Corrected number of pins in Thermal Information table..................................................................................... 5
Added quiescent current specification for TPS6286x0A/C devices in Electrical Characteristics table .............7
Changed high-level input voltage threshold in Electrical Characteristics table ..................................................7
Added separate enable delay time parameter for TPS6286x0C device variants............................................... 7
Added footnote................................................................................................................................................... 7
Added power-good deglitch block to Functional Block Diagram ......................................................................12
Added 100% Duty Cycle Mode Operation section............................................................................................13
Added section describing the start-up output voltage for TPS6286xxC device variants.................................. 14
Corrected value of C1 in List of Components table.......................................................................................... 22
Updated data in Thermal Derating plot for VOUT = 1.675 V.............................................................................. 25
Added typical application example for TPS6286x0A and TPS6286x0xC device variants................................28
Changed Layout Example image......................................................................................................................31
Changes from Revision * (September 2020) to Revision A (December 2020)
Page
•
Changed device status from Advance Information to Production Data.............................................................. 1
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5 Device Options
FULL OUTPUT
VOLTAGE RANGE
START-UP OUTPUT
VOLTAGE
DVS STEP
OUTPUT
CURRENT
PART NUMBER(1)
VSET/VID OR PG PIN
SIZE
TPS628680ARQY
TPS6286800CRQY
TPS628681ARQY
TPS6286810CRQY
TPS628682ARQY
TPS6286820CRQY
TPS628690ARQY
TPS6286900CRQY
TPS628691ARQY
TPS6286910CRQY
TPS628692ARQY
TPS6286920CRQY
0.2 V to 0.575 V, Selectable
VSET/VID
PG
0.2 V to 0.8375 V
0.4 V to 1.675 V
0.8 V to 3.35 V
0.2 V to 0.8375 V
0.4 V to 1.675 V
0.8 V to 3.35 V
2.5 mV
0.5 V
0.4 V to 1.15 V, Selectable
0.9 V
VSET/VID
PG
5 mV
10 mV
2.5 mV
5 mV
4 A
0.8 V to 2.3 V, Selectable
1.2 V
VSET/VID
PG
0.2 V to 0.575 V, Selectable
0.5 V
VSET/VID
PG
0.4 V to 1.15 V, Selectable
0.9 V
VSET/VID
PG
6 A
0.8 V to 2.3 V, Selectable
1.2 V
VSET/VID
PG
10 mV
(1) For all available packages, see the orderable addendum at the end of the data sheet.
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6 Pin Configuration and Functions
TOP VIEW
BOTTOM VIEW
VSET/VID
VSET/VID
or
or
PG
AGND
1
VOS
8
VOS
8
AGND
1
PG
9
9
PGND
2
PGND
2
SW
SW
7
7
VIN
3
3
VIN
4
5
6
6
5
4
EN
SCL
SCL
EN
SDA
SDA
Figure 6-1. 9-Pin RQY QFN Package (Top View)
Table 6-1. Pin Functions
PIN
DESCRIPTION
NAME
NO.
AGND
1
Analog ground pin
Start-up output voltage and device address selection pin. An external resistor must be
connected.
After start-up, the pin can be used to select the VOUT registers for the output voltage (Low =
VOUT register 1; high = VOUT register 2). See Section 8.4.4. This pin is pulled to GND when
the device is in shutdown.
VSET/VID
9
The function after start-up depends on the device option. See the Device Options.
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5
V. If unused, leave it floating. This pin is pulled to GND when the device is in shutdown.
The function after start-up depends on the device option. See Section 5.
PG
9
VOS
PGND
SW
8
2
7
3
Output voltage sense pin. This pin must be directly connected to the output capacitor.
Power ground pin
Switch pin of the power stage
VIN
Power supply input voltage pin
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
EN
4
SDA
SCL
5
6
I2C serial data pin. Do not leave it floating. Connect it to AGND if not used.
I2C serial clock pin. Do not leave it floating. Connect it to AGND if not used.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
-0.3
-0.3
-2.5
MAX
UNIT
VIN, EN, SDA, SCL, VOS, VSET/VID, VSET/PG
6
Voltage(2)
SW (DC)
VIN + 0.3
V
SW (AC, less than 10ns)(3)
Source current at VSET/PG
Sink current at SDA, SCL
Junction temperature
Storage temperature
10
1
ISOURCE_PG
ISINK_SDA,SCL
TJ
mA
mA
°C
2
-40
-65
150
150
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
5.5
10
4
UNIT
V
VIN
Input voltage
2.4
tF_VIN
Falling transition time at VIN(1)
Output current, TPS62868 (2)
Output current, TPS62869 (3)
mV/µs
0
0
IOUT
A
6
TPS628680x, TPS628690x
110
220
L
Output inductor
nH
°C
TPS628681x, TPS628682x,
TPS628691x, TPS628692x
TJ
Junction temperature
-40
125
(1) The falling slew rate of VIN should be limited if VIN goes below VUVLO
.
(2) Lifetime is reduced when operating continuously at 4-A output current and the junction temperature is higher than 105 °C.
(3) Lifetime is reduced when operating continuously at 6-A output current and the junction temperature is higher than 85 °C.
7.4 Thermal Information
TPS62868/ TPS62869 RQY
THERMAL METRIC(1)
JEDEC 51-7
9 PINS
90.9
TPS62869RQYEVM-118
UNIT
9 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
60.3
°C/W
°C/W
°C/W
RθJC(top)
RθJB
68.2
n/a(2)
n/a(2)
25.0
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UNIT
SLVSFS3B – SEPTEMBER 2020 – REVISED JULY 2021
TPS62868/ TPS62869 RQY
THERMAL METRIC(1)
JEDEC 51-7
TPS62869RQYEVM-118
9 PINS
1.9
9 PINS
3.3
ΨJT
ΨJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
24.7
31.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM.
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7.5 Electrical Characteristics
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
TPS6286x1A/C,
TPS6286x2A/C
4
9
10
15
IQ
Quiescent current
EN = High, no load, device not switching
µA
µA
TPS6286x0A/C
EN = High, no load, device not switching,
VVOS = 1.8 V
IQ_VOS
ISD
VUVLO
Operating quiescent current into VOS pin
Shutdown current
18
EN = Low, TJ = –40°C to 85°C
VIN rising
0.24
2.3
2.2
130
20
1
2.4
2.3
µA
V
2.2
2.1
Undervoltage lockout threshold
VIN falling
V
Thermal warning threshold
Thermal warning hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
°C
°C
°C
°C
TJW
TJ falling
TJ rising
150
20
TJSD
TJ falling
LOGIC INTERFACE EN, SDA, SCL
High-level input threshold voltage at EN,
SCL, SDA, VSET/VID
VIH
VIL
0.84
V
V
Low-level input threshold voltage at EN,
SCL, SDA, VSET/VID
0.4
ISCL,LKG Input leakage current into SCL pin
ISDA,LKG Input leakage current into SDA pin
0.01
0.01
0.01
1
0.8
0.1
0.1
µA
µA
µA
pF
pF
IEN,LKG
CSCL
Input leakage current into EN pin
Parasitic capacitance at SCL
Parasitic capacitance at SDA
CSDA
2.4
STARTUP, POWER GOOD
Time from EN high to device starts switching, R1
= 249kΩ
TPS6286xA
420
700 1100
tDelay
Enable delay time
µs
TPS6286x0C
Time from EN high to device starts switching
Time from device starts switching to power good
VVOS referenced to VOUT nominal
100
0.85
85
350
1
900
1.5
96
tRamp
VPG
Output voltage ramp time
Power good lower threshold(1)
Power good upper threshold
Power good deglitch delay
ms
%
91
111
34
VVOS referenced to VOUT nominal
103
120
%
tPG,DLY
Rising and falling edges
µs
OUTPUT
FPWM, no Load, TJ = 0℃ to 85℃
-1
-2
1
2
%
%
VOUT
Output voltage accuracy
FPWM, no Load
EN = Low, Output discharge disabled, VVOS = 1.8
V, TPS6286x1A/C
IVOS,LKG Input leakage current into VOS pin
0.2
2.5
µA
RDIS
Output discharge resistor at VOS pin
Load regulation
3.5
Ω
VOUT = 0.9 V, FPWM
0.04
%/A
POWER SWITCH
High-side FET on-resistance
11
10.5
5.5
7.7
4.5
6.5
-3
mΩ
mΩ
A
RDS(on)
Low-side FET on-resistance
TPS62868
5
7
6
High-side FET forward current limit
TPS62869
8.5
A
ILIM
TPS62868
A
Low-side FET forward current limit
Low-side FET negative current limit
TPS62869
A
TPS62868, TPS62869
A
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TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
fSW
PWM switching frequency
IOUT = 1 A, VOUT = 0.9 V
2.4 MHz
(1) TPS6286x0A and TPS6286x00C device variants do not have a lower PG threshold. In these device variants the PG signal is high if the
start-up ramp is complete and the output voltage is below the upper PG threshold.
7.6 I2C InterfaceTiming Characteristics
PARAMETER (1) (2)
SCL Clock Frequency
SCL Clock Frequency
SCL Clock Frequency
SCL Clock Frequency
SCL Clock Frequency
SCL Clock Frequency
SCL Clock Frequency
TEST CONDITIONS
MIN
MAX
100
400
1
UNIT
kHz
f(SCL)
f(SCL)
f(SCL)
f(SCL)
f(SCL)
f(SCL)
f(SCL)
Standard mode
Fast mode
kHz
Fast mode plus
MHz
MHz
MHz
MHz
MHz
High-speed mode (write operation), CB – 100 pF max
High-speed mode (read operation), CB – 100 pF max
High-speed mode (write operation), CB – 400 pF max
High-speed mode (read operation), CB – 400 pF max
3.4
3.4
1.7
1.7
Bus Free Time Between a STOP and
START Condition
tBUF
Standard mode
Fast mode
4.7
1.3
0.5
4
µs
µs
µs
µs
ns
ns
ns
Bus Free Time Between a STOP and
START Condition
tBUF
Bus Free Time Between a STOP and
START Condition
tBUF
Fast mode plus
Standard mode
Fast mode
Hold Time (Repeated) START
condition
tHD, tSTA
tHD, tSTA
tHD, tSTA
tHD, tSTA
Hold Time (Repeated) START
condition
600
260
160
Hold Time (Repeated) START
condition
Fast mode plus
High-speed mode
Hold Time (Repeated) START
condition
tLOW
tLOW
tLOW
tLOW
tLOW
tHIGH
tHIGH
tHIGH
tHIGH
tHIGH
LOW Period of the SCL Clock
LOW Period of the SCL Clock
LOW Period of the SCL Clock
LOW Period of the SCL Clock
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
HIGH Period of the SCL Clock
HIGH Period of the SCL Clock
HIGH Period of the SCL Clock
HIGH Period of the SCL Clock
Standard mode
4.7
1.3
0.5
160
320
4
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
Fast mode
Fast mode plus
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
Fast mode
600
260
60
Fast mode plus
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
120
Setup Time for a Repeated START
Condition
tSU, tSTA
tSU, tSTA
tSU, tSTA
tSU, tSTA
Standard mode
Fast mode
4.7
600
260
160
µs
ns
ns
ns
Setup Time for a Repeated START
Condition
Setup Time for a Repeated START
Condition
Fast mode plus
High-speed mode
Setup Time for a Repeated START
Condition
tSU, tDAT Data Setup Time
tSU, tDAT Data Setup Time
tSU, tDAT Data Setup Time
tSU, tDAT Data Setup Time
Standard mode
Fast mode
250
100
50
ns
ns
ns
ns
Fast mode plus
High-speed mode
10
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PARAMETER (1) (2)
TEST CONDITIONS
MIN
0
MAX
3.45
0.9
UNIT
µs
tHD, tDAT Data Hold Time
tHD, tDAT Data Hold Time
tHD, tDAT Data Hold Time
tHD, tDAT Data Hold Time
tHD, tDAT Data Hold Time
Standard mode
Fast mode
0
µs
Fast mode plus
0
µs
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
0
70
150
ns
0
ns
tRCL
tRCL
Rise Time of SCL Signal
1000
ns
20 +
0.1 CB
Rise Time of SCL Signal
Fast mode
300
ns
tRCL
tRCL
tRCL
Rise Time of SCL Signal
Rise Time of SCL Signal
Rise Time of SCL Signal
Rise Time of SCL Signal After a
Fast mode plus
120
40
ns
ns
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
10
20
80
20 +
0.1 CB
tRCL1
tRCL1
tRCL1
tRCL1
Repeated START Condition and After Standard mode
an Acknowledge BIT
1000
300
120
80
ns
ns
ns
ns
Rise Time of SCL Signal After a
Repeated START Condition and After Fast mode
an Acknowledge BIT
20 +
0.1 CB
Rise Time of SCL Signal After a
Repeated START Condition and After Fast mode plus
an Acknowledge BIT
Rise Time of SCL Signal After a
Repeated START Condition and After High-speed mode, CB – 100 pF max
an Acknowledge BIT
10
20
Rise Time of SCL Signal After a
Repeated START Condition and After High-speed mode, CB – 400 pF max
an Acknowledge BIT
tRCL1
160
300
ns
ns
20 +
0.1 CB
tFCL
Fall Time of SCL Signal
Standard mode
tFCL
tFCL
tFCL
tFCL
tRDA
Fall Time of SCL Signal
Fall Time of SCL Signal
Fall Time of SCL Signal
Fall Time of SCL Signal
Rise Time of SDA Signal
Fast mode
300
120
40
ns
ns
ns
ns
ns
Fast mode plus
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
80
1000
20 +
0.1 CB
tRDA
Rise Time of SDA Signal
Fast mode
300
ns
tRDA
tRDA
tRDA
tFDA
Rise Time of SDA Signal
Rise Time of SDA Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Fast mode plus
120
80
ns
ns
ns
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
160
300
20 +
0.1 CB
tFDA
Fall Time of SDA Signal
Fast mode
300
ns
tFDA
tFDA
tFDA
Fall Time of SDA Signal
Fall Time of SDA Signal
Fall Time of SDA Signal
Fast mode plus
120
80
ns
ns
ns
µs
ns
ns
ns
pF
pF
pF
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
10
20
160
tSU, tSTO Setup Time of STOP Condition
tSU, tSTO Setup Time of STOP Condition
tSU, tSTO Setup Time of STOP Condition
tSU, tSTO Setup Time of STOP Condition
4
Fast mode
600
260
160
Fast mode plus
High-Speed mode
Standard mode
CB
CB
CB
Capacitive Load for SDA and SCL
Capacitive Load for SDA and SCL
Capacitive Load for SDA and SCL
400
400
550
Fast mode
Fast mode plus
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PARAMETER (1) (2)
TEST CONDITIONS
MIN
MAX
UNIT
CB
Capacitive Load for SDA and SCL
High-Speed mode
400
pF
(1) All values referred to VIL MAX and VIH MIN levels in ELECTRICAL CHARACTERISTICS table.
(2) For bus line loads CB between 100 pF and 400 pF, the timing parameters must be linearly interpolated.
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7.7 Typical Characteristics
30
30
20
10
0
TJ = -40 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
20
10
0
2.4
2.8
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
2.4
2.8
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
D000
D001
Figure 7-1. High-Side FET On-Resistance
Figure 7-2. Low-Side FET On-Resistance
7.0
0.40
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.30
0.20
0.10
TJ = -40 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 25 èC
TJ = 85 èC
2.4
2.8
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
2.4
2.8
3.2
3.6
4.0
Input Voltage (V)
4.4
4.8
5.2
5.6
D003
D003
Figure 7-3. Quiescent Current
Figure 7-4. Shutdown Current
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8 Detailed Description
8.1 Overview
The DCS-Control™ topology operates in PWM (pulse width modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal
switching frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. Because
DCS-Control supports both operation modes (PWM and PFM) within a single building block, the transition from
PWM mode to Power Save Mode is seamless and without effects on the output voltage. The devices offer both
excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple.
8.2 Functional Block Diagram
VIN
EN
PG
Control Logic
Reference Selection
UVLO
Thermal Shutdown
Startup Ramp
VSET/VID
VPG_H
+
–
or
PG
VFB
34-µs
Deglitch
+
–
SDA
SCL
VPG_L
I2C Interface
HS-FET
Forward Current Limit
VSW
VIN
TON
HICCUP (1)
Direct Control
&
VSW
Compensation
SW
Gate
Drive
Modulator
VREF
+
EA
Comparator
_
VOS
LS-FET
(1)
RDIS
Forward Current Limit
Zero Current Detect
Negative Current Limit
PGND
AGND
(1) enabled via I2C
PGND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the
inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. Power Save
Mode is based on a fixed on-time architecture, as shown in Equation 1.
V
OUT
t
∂416ns
ON
V
IN
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
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When VIN decreases to typically 15% above the VOUT, the TPS6286x does not enter Power Save Mode,
regardless of the load current. The device maintains output regulation in PWM mode.
8.3.2 Forced PWM Mode
With I2C, set the device in forced PWM (FPWM) mode by the CONTROL register. The device switches at 2.4
MHz, even with a light load. This reduces the output voltage ripple and allows simple filtering of the switching
frequency for noise-sensitive applications. Efficiency at light load is lower in FPWM mode.
8.3.3 100% Duty Cycle Mode Operation
There is no limitation for small duty cycles since even at very low duty cycles, the switching frequency is reduced
as needed to always ensure a proper regulation.
If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side
switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is
determined by the voltage drop across the high-side MOSFET and the DC resistance of the inductor. The
minimum VIN that is needed to maintain a specific VOUT value is estimated as:
V
IN,MIN
= VOUT + (RDS (ON) + RL)IOUT ,MAX
(2)
where
•
•
•
•
VIN,MIN is the minimum input voltage to maintain an output voltage
IOUT,MAX is the maximum output current
RDS(on) is the high-side FET ON-resistance
RL is the inductor ohmic resistance (DCR)
8.3.4 Start-up
After enabling the device, there is an enable delay (tDelay) before the device starts switching. During this period,
the device sets the internal reference voltage, and determines the start-up output voltage through the resistor
connected to the VSET/VID pin. After tdelay, all registers can be read and written by the I2C interface.
VIN
EN
VOUT
ttDelay
t
ttRamp
ttStartupt
t
Figure 8-1. Start-up Sequence
After the enable delay, an internal soft start-up circuitry ramps up the output voltage with a period of 1 ms
(tRamp). This avoids excessive inrush current and creates a smooth output voltage rising-slope. It also prevents
excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current can occur with a shorted or saturated inductor or a heavy load
or shorted output circuit condition. If the inductor current reaches the threshold ILIM, cycle by cycle, the high-side
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MOSFET is turned off and the low-side MOSFET is turned on, while the inductor current ramps down to the
low-side MOSFET current limit.
When the high-side MOSFET current limit is triggered 32 times, the device stops switching. The device then
automatically re-starts, with an internal soft start-up, after a typical delay time of 128 µs has passed. This is
named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears.
The HICCUP is disabled by the CONTROL register bit Enable HICCUP. Disabling HICCUP changes the
overcurrent protection to latching protection. The device stops switching after the high-side MOSFET current
limit is triggered 32 times. Toggling the EN pin, removing and reapplying the input voltage, or writing to the
CONTROL register bit Software Enable Device unlatches the device.
8.3.6 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) is implemented when
the input voltage is lower than VUVLO. The device stops switching and the output voltage discharge is active (if
enabled through I2C) when the device is in UVLO. When the input voltage recovers, the device automatically
returns to operation with an internal soft start-up. During UVLO, the internal register values are kept.
The UVLO bit in the STATUS Register is set when the input voltage is less than the UVLO falling threshold.
When the input voltage is below 1.8 V (typ.), all registers are reset.
8.3.7 Thermal Warning and Shutdown
When the junction temperature goes up to TJW, the device gives a pre-warning indicator in the STATUS register.
The device keeps running.
When the junction temperature exceeds TJSD, the device goes into thermal shutdown, stops switching, and
activates the output voltage discharge. When the device temperature falls below the threshold by 20°C, the
device returns to normal operation automatically with an internal soft start-up. During thermal shutdown, the
internal register values are kept.
8.4 Device Functional Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic High. In shutdown mode (EN = Low), the internal power
switches as well as the entire control circuitry are turned off, and all the registers are reset, except for the Enable
Output Discharge bit. Do not leave the EN pin floating.
In shutdown mode (EN = Low), all registers cannot be read and written by the I2C interface.
The typical threshold value of the EN pin is 0.61 V for rising input signals, and 0.51 V for falling input signals.
The device is also enabled or disabled by setting the bit, Software Enable Device in CONTROL register while
EN = High. After being disabled/enabled by this bit, the device stops switching and has a new start-up beginning
with tRamp. There is no TDelay time and the registers are not reset.
8.4.2 Output Discharge
An internal MOSFET switch smoothly discharges the output through the VOS pin in shutdown mode (EN = Low
or Software Enable Device bit = 0). The output discharge is also active when the device is in thermal shutdown
and UVLO.
When the Enable Output Discharge bit is set to 0, the output discharge function is disabled. The input voltage
must remain higher than 1 V (typ.) to keep the output discharge function operational and the status of the Enable
Output Discharge bit retained. The Enable Output Discharge bit is reset on the rising edge of the EN pin.
8.4.3 Start-Up Output Voltage and I2C Target Address Selection
During the ramp up period (tRamp), the output voltage ramps to the start-up output voltage first, then ramps up or
down to the new value when the value of the output register is changed by I2C interface commands.
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8.4.3.1 TPS6286xxA Devices
During the enable delay (tDelay), the start-up output voltage and device I2C target address are set by an external
resistor connected to the VSET/VID pin through an internal R2D (resistor to digital) converter. Table 8-1 shows
the options.
Table 8-1. Start-up Output Voltage and I2C Target Address Options
RESISTOR (E96 SERIES, ±1%
ACCURACY) AT VSET/VID
START-UP OUTPUT VOLTAGE (TYP)
I2C TARGET ADDRESS
249 kΩ
Voltage Factor * 1.15 V
Voltage Factor * 1.10 V
Voltage Factor * 1.05 V
Voltage Factor * 1.00 V
Voltage Factor * 0.95 V
Voltage Factor * 0.90 V
Voltage Factor * 0.85 V
Voltage Factor * 0.80 V
Voltage Factor * 0.75 V
Voltage Factor * 0.70 V
Voltage Factor * 0.65 V
Voltage Factor * 0.60 V
Voltage Factor * 0.55 V
Voltage Factor * 0.50 V
Voltage Factor * 0.45 V
Voltage Factor * 0.40 V
0b1000110 (0x46)
0b1000101 (0x45)
0b1000100 (0x44)
0b1000011 (0x43)
0b1000010 (0x42)
0b1000001 (0x41)
0b1001000 (0x48)
0b1001001 (0x49)
0b1001010 (0x4A)
0b1001011 (0x4B)
0b1001100 (0x4C)
0b1001101 (0x4D)
0b1001110 (0x4E)
0b1001111 (0x4F)
0b1000000 (0x40)
0b1000111 (0x47)
205 kΩ
162 kΩ
133 kΩ
105 kΩ
86.6 kΩ
68.1 kΩ
56.2 kΩ
44.2 kΩ
36.5 kΩ
28.7 kΩ
23.7 kΩ
18.7 kΩ
15.4 kΩ
12.1 kΩ
10 kΩ
Table 8-2. Device Option Voltage Factors
DEVICE OPTION
VOLTAGE FACTOR
TPS6286x0A
TPS6286x1A
TPS6286x2A
0.5
1
2
The R2D converter has an internal current source which applies current through the external resistor, and an
internal ADC which reads back the resulting voltage level. Depending on the level, the correct start-up output
voltage and I2C target address are set. Once this R2D conversion is finished, the current source is turned off to
avoid current flowing through the external resistor. Ensure that there is no additional current path or capacitance
greater than 30 pF from this pin to GND during R2D conversion, otherwise a false value is set.
8.4.3.2 TPS6286xxxC Devices
The start-up output voltage, voltage factor, and I2C target address of the TPS6286xxxC devices are factory-set
according to Table 8-3.
Table 8-3. Device Option Start-Up Voltage, Voltage Factor, and I2C Target Address
DEVICE OPTION
TPS6286x0xC
TPS6286x1xC
TPS6286x2xC
VOLTAGE FACTOR
START-UP OUTPUT VOLTAGE
I2C TARGET ADDRESS
0.5
1
0.5 V
0.9 V
1.2 V
0b1000010 (0x42)
2
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8.4.4 Select Output Voltage Registers (VID)
After the start-up period (tStartup), the output voltage can be selected between two output voltage registers by
the VID pin. When VID is pulled low, the output voltage is set by Table 8-6. When VID is pulled high, the output
voltage is set by Table 8-7. This is also called dynamic voltage scaling (DVS).
During an output voltage change through I2C or the VSET/VID pin, the device can be set in FPWM by the
Enable FPWM Mode during Output Voltage Change bit in CONTROL register. The output voltage change speed
is set by the Voltage Ramp Speed bit.
8.4.5 Power Good ( PG)
The TPS62868 and TPS62869 families provide device options with the PG pin instead of a VSET/VID pin. Refer
to Section 5 to see the according device options.
The PG pin goes high impedance once the output voltage is above 91% and less than 110% of the nominal
voltage, and is driven low once the voltage is out of the range. The PG pin is an open-drain output and is
specified to sink up to 1 mA. The power good output requires a pullup resistor connecting to any voltage rail less
than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other
converters. Leave the PG pin unconnected when not used.
The PG has a deglitch time, before the signal goes high or low, during normal operation.
Table 8-4. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH
LOW
0.91 × VOUT_NOM ≤ VVOS ≤ 1.11 × VOUT_NOM
√
Enable
VVOS < 0.91 × VOUT_NOM or VVOS > 1.11 × VOUT_NOM
√
√
√
√
Shutdown
EN = Low
Thermal Shutdown
UVLO
TJ > TJSD
1.8 V < VIN < VUVLO
Power Supply
Removal
VIN < 1.8 V
undefined
8.5 Programming
8.5.1 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors. The bus
consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open drain I/O
pins, SDA and SCL. A controller device, usually a microcontroller or a digital signal processor, controls the bus.
The controller is responsible for generating the SCL signal and device addresses. The controller also generates
specific conditions that indicate the START and STOP of data transfer. A target device receives or transmits data
on the bus under control of the controller device, or both.
The device works as a target and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps) and fast mode (400 kbps), fast mode plus (1 Mbps), and high-speed
mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as the input voltage remains above 1.8 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode.
It is recommended that the I2C controller initiates a STOP condition on the I2C bus after the initial power up of
SDA and SCL pullup voltages to ensure reset of the I2C engine.
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8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
The controller initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 8-2. All I2C-compatible devices
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 8-2. START and STOP Conditions
The controller then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the controller ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 8-3). All devices
recognize the address sent by the controller and compare it to their internal fixed addresses. Only the target
device with a matching address generates an acknowledge (see Figure 8-4) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows that
communication link with a target has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 8-3. Bit Transfer on the Serial Interface
The controller generates further SCL cycles to either transmit data to the target (R/W bit 0) or receive data from
the target (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the controller or by the target, depending on which one is
the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 8-2). This releases the bus and stops the communication link with
the addressed target. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 0x00 being read out.
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Data Output by
Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
8
SCL from
Controller
1
2
9
S
START
Clock pulse for
Condition
acknowledgment
Figure 8-4. Acknowledge on the I2C Bus
Figure 8-5. Bus Protocol
8.5.3 HS-Mode Protocol
The controller generates a start condition followed by a valid serial byte containing HS controller code
00001XXX. This transmission is made in F/S-mode at no more than 400 kbps. No device is allowed to
acknowledge the HS controller code, but all devices must recognize it and switch their internal setting to support
3.4 Mbps operation.
The controller then generates a repeated start condition (a repeated start condition has the same timing as
the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the target devices to support the F/S-mode. Instead of using a stop condition, repeated start
conditions must be used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section results in 0x00 being read out.
8.5.4 I2C Update Sequence
The sequence requires a start condition, a valid I2C target address, a register address byte, and a data byte for
a single update. After the receipt of each byte, the device acknowledges by pulling the SDA line low during the
high period of a single clock pulse. A valid I2C address selects the device. The device performs an update on the
falling edge of the acknowledge signal that follows the LSB byte.
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1
7
1
1
8
1
8
1
1
S
Target Address
R/W
A
Register Address
A
Data
A/A
P
“0” Write
From Controller to Target
From Target to Controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
Figure 8-6. “Write” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
1
7
1
1
8
1
1
8
1
1
8
1
1
S
Target Address
R/W
A
Register Address
A
Sr
Target Address
R/W
A
Data
A/A
P
"0" Write
"1" Read
From Controller to Target
From Target to Controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
Figure 8-7. “Read” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
tF/S Modet
tHS Modet
8
F/S Mode
1
8
1
1
7
1
1
1
8
1
1
S
HS-Controller Code
A
Sr
Target Address
R/W
A
Register Address
A
Data
A/A
P
tn × bytes + Acknowledget
HS Mode continues
Target Address
Sr
From Controller to Target
From Target to Controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
Figure 8-8. Data Transfer Format in HS-Mode
8.5.5 I2C Register Reset
The I2C registers can be reset by:
•
•
•
Pulling the input voltage below 1.8 V (typ.)
A high to low transition on EN
Setting the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new start-up is begun immediately. After tDelay, the I2C registers can be programmed again.
8.6 Register Map
Table 8-5. Register Map
REGISTER ADDRESS
(HEX)
FACTORY DEFAULT
(HEX)
REGISTER NAME
DESCRIPTION
Sets the target output voltage
0x01
0x02
0x03
0x05
VOUT Register 1
VOUT Register 2
0x64
0x64
0x6F
0x00
Sets the target output voltage
Sets miscellaneous configuration bits
Returns status flags
CONTROL Register
STATUS Register
8.6.1 Target Address Byte
7
6
5
4
3
2
1
0
1
x
x
x
x
x
x
R/W
The target address byte is the first byte received following the START condition from the controller device. The
target addresses can be assigned by an external resistor, see Table 8-1.
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8.6.2 Register Address Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the target address, the bus controller sends a byte to the device,
which contains the address of the register to be accessed.
8.6.3 VOUT Register 1
Table 8-6. VOUT Register 1 Description
REGISTER ADDRESS 0X01 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)
Voltage Factor * 400 mV
7:0
VO1_SET
0x00
0x01
...
Voltage Factor * 405 mV
0x64
...
Voltage Factor * 900 mV
0xFE
0xFF
Voltage Factor * 1670 mV
Voltage Factor * 1675 mV
8.6.4 VOUT Register 2
Table 8-7. VOUT Register 2 Description
REGISTER ADDRESS 0X02 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)
Voltage Factor * 400 mV
7:0
VO2_SET
0x00
0x01
...
Voltage Factor * 405 mV
0x64
...
Voltage Factor * 900 mV (default value)
0xFE
0xFF
Voltage Factor * 1670 mV
Voltage Factor * 1675 mV
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8.6.5 CONTROL Register
Table 8-8. CONTROL Register Description
REGISTER ADDRESS 0X03 WRITE ONLY
BIT
7
FIELD
TYPE
R/W
DEFAULT DESCRIPTION
Reset
0
1
1 - Reset all registers to default.
6
Enable FPWM Mode during Output
Voltage Change
R/W
0 - Keep the current mode status during output voltage change
1 - Force the device in FPWM during output voltage change.
5
Software Enable Device
R/W
1
0 - Disable the device. All registers values are still kept.
1 - Re-enable the device with a new start-up without the tDelay
period.
4
3
Enable FPWM Mode
Enable Output Discharge
Enable HICCUP
R/W
R/W
R/W
R/W
0
1
0 - Set the device in power save mode at light loads.
1 - Set the device in forced PWM mode at light loads.
0 - Disable output discharge.
1 - Enable output discharge.
2
1
0 - Disable HICCUP. Enable latching protection.
1 - Enable HICCUP, Disable latching protection.
0:1
Voltage Ramp Speed
11
00 - 20mV/µs (0.25 µs/step)
01 - 10 mV/µs (0.5 µs/step)
10 - 5 mV/µs (1 µs/step)
11 - 1 mV/µs (5 µs/step, default)
8.6.6 STATUS Register
Table 8-9. STATUS Register Description
REGISTER ADDRESS 0X05 READ ONLY(1)
BIT
7:5
4
FIELD
TYPE
DEFAULT DESCRIPTION
Reserved
Thermal Warning
HICCUP
R
R
0
0
1: Junction temperature is higher than 130°C.
3
1: Device has HICCUP status once.
2
Reserved
Reserved
UVLO
1
0
R
0
1: The input voltage is less than UVLO threshold (falling edge).
(1) All bit values are latched until the device is reset, or the STATUS register is read. Then, the STATUS register is reset to its default
values.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
VIN
2.4 V to 5.5 V
L1
0.22 µH
TPS62868/9
VOUT
VIN
SW
C1
VOS
C2
EN
VSET/VID
or PG
SCL
SDA
I2C
R1
AGND PGND
Figure 9-1. Typical Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
2.4 V to 5.5 V
0.9 V
Output voltage
Maximum output current
6 A
Table 9-2 lists the components used for the example.
Table 9-2. List of Components of Table 9-1
REFERENCE
DESCRIPTION
MANUFACTURER(1)
Samsung Electro-
Mechanics
C1
2 × 10 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, CL10B106MQ8NRNC
C2
L1
R1
2 × 22 µF, Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44L
0.22 µH, Power inductor, XAL4020-221ME (12 A, 5.81 mΩ)
Depending on the start-up output voltage, size 0603
Murata
Coilcraft
Std
(1) See Third-party Products disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Setting The Output Voltage
The initial output voltage is set by an external resistor connected to the VSET/VID pin, according to Table 8-1.
After the soft start-up, the output voltage can be changed in the VOUT Registers. Refer to Table 8-6 and Table
8-7.
9.2.2.2 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 9-3
outlines possible inductor and capacitor value combinations for most applications. Checked cells represent
combinations that are proven for stability by simulation and lab test. Further combinations should be checked for
each individual application.
Table 9-3. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
22
2 x 22 or 47
3 x 22
150
(1)
0.24
+
+
+
(1) This LC combination is the standard value and recommended for most applications.
(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –30%.
9.2.2.3 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 3 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
(3)
where
•
•
•
•
IOUT,MAX = maximum output current
ΔIL = inductor current ripple
fSW = switching frequency
L = inductor value
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher
than IL,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate
inductor. Table 9-4 lists recommended inductors.
Table 9-4. List of Recommended Inductors
INDUCTANCE CURRENT RATING,
DIMENSIONS
[L x W x H mm]
DC RESISTANCE
[mΩ]
PART NUMBER
[µH]
0.22
0.24
ISAT [A]
18.7
4 x 4 x 2
5.81
13
Coilcraft, XAL4020-221ME
Murata, DFE201612E-R24M
6.6
2 x 1.6 x 1.2
9.2.2.4 Capacitor Selection
The input capacitor is the low-impedance energy source for the converter which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is recommended for best filtering and must be placed
between VIN and PGND as close as possible to those pins. For most applications, 8 μF is a sufficient value
for the effective input capacitance, though a larger value reduces input current ripple.
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The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended minimum output effective capacitance is 30 μF; this
capacitance can vary over a wide range as outline in the output filter selection table.
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9.2.3 Application Curves
VIN = 5.0 V, VOUT = 0.9 V, TA = 25°C, BOM = Table 9-2, unless otherwise noted.
90
85
80
75
70
65
60
55
50
45
40
0.612
0.606
0.6
0.594
0.588
0.582
VIN = 3.3V, PSM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
VIN = 3.3 V, PSM
VIN = 3.3 V, PWM
VIN = 4.2 V, PSM
VIN = 4.2 V, PWM
VIN = 5.0 V, PSM
VIN = 5.0 V, PWM
100m
1m
10m
Load (A)
100m
1
1
1
6
100m
1m
10m
Load (A)
100m
1
1
1
6
D001
D002
VOUT = 0.6 V
VOUT = 0.6 V
Figure 9-2. Efficiency
Figure 9-3. Load Regulation
95
90
85
80
75
70
65
60
55
50
45
40
0.918
0.909
0.9
0.891
0.882
0.873
VIN = 3.3V, PSM
VIN = 3.3 V, PSM
VIN = 3.3 V, PWM
VIN = 4.2 V, PSM
VIN = 4.2 V, PWM
VIN = 5.0 V, PSM
VIN = 5.0 V, PWM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
100m
1m
10m
Load (A)
100m
6
100m
1m
10m
Load (A)
100m
6
D003
D004
VOUT = 0.9 V
VOUT = 0.9 V
Figure 9-4. Efficiency
Figure 9-5. Load Regulation
95
90
85
80
75
70
65
60
55
50
45
40
1.212
1.2
1.188
1.176
1.164
VIN = 3.3V, PSM
VIN = 3.3 V, PSM
VIN = 3.3 V, PWM
VIN = 4.2 V, PSM
VIN = 4.2 V, PWM
VIN = 5.0 V, PSM
VIN = 5.0 V, PWM
VIN = 3.3V, PWM
VIN = 4.2V, PSM
VIN = 4.2V, PWM
VIN = 5.0V, PSM
VIN = 5.0V, PWM
100m
1m
10m
Load (A)
100m
6
100m
1m
10m
Load (A)
100m
6
D005
D006
VOUT = 1.2 V
VOUT = 1.2 V
Figure 9-6. Efficiency
Figure 9-7. Load Regulation
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3
3
2
1
2
VOUT = 0.6 V, FPWM
1
VOUT = 0.6 V, PSM
VOUT = 0.9 V, FPWM
VOUT = 0.9 V, PSM
VOUT = 1.2 V, FPWM
VOUT = 1.2 V, PSM
VOUT = 0.6 V
VOUT = 0.9 V
VOUT = 1.2 V
0.5
1
1.5
2
2.5
3
Load (A)
3.5
4
4.5
5
5.5
6
2.5
3
3.5 4
Input Voltage (V)
4.5
5
5.5
D007
D006
VIN = 5.0 V
IOUT = 1.0 A
Figure 9-8. Switching Frequency
Figure 9-9. Switching Frequency
7
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
45
55
65
75
85
95
105
115
125
45
55
65
75
85
95
105
115
125
Ambient Temperature (°C)
Ambient Temperature (°C)
VOUT = 0.9 V
θJA = 60.3°C/W
VOUT = 1.675 V
θJA = 60.3°C/W
Figure 9-10. Thermal Derating
Figure 9-11. Thermal Derating
IOUT = 6.0 A
IOUT = 0.1 A
Figure 9-12. PWM Operation
Figure 9-13. PSM Operation
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IOUT = 0.1 A
No Load
Figure 9-14. Forced PWM Operation
Figure 9-15. Startup and Shutdown by EN Pin
No Load
IOUT = 0.06 A to 5.4 A
PSM
Figure 9-16. Start-up by Software Enable Device
Bit
Figure 9-17. Load Transient
IOUT = 0.06 A to 5.4 A
Forced PWM
IOUT = 2.5 A
Figure 9-18. Load Transient
Figure 9-19. HICCUP Protection
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9.3 Typical Application – TPS6286x0A and TPS6286x0xC Devices
L1
0.1 µH
TPS6286900C
VIN
2.4 V to 5.5 V
SW
VOUT
VIN
EN
C2
VOS
C1
VIO
R1
SCL
SDA
I2C
PG
PG
PGND AGND
Figure 9-20. Typical Application
9.3.1 Design Requirements
For this design example, use the parameters listed in Table 9-5 as the input parameters.
Table 9-5. Design Parameters
DESIGN PARAMETER
Input Voltage Range
Output Voltage
EXAMPLE VALUE
2.4 V to 5.5 V
0.5 V
Maximum Output Current
6 A
Table 9-6 lists the components used in this example.
Table 9-6. List of Components of Table 9-5
REFERENCE
DESCRIPTION
MANUFACTURER1
C1
2 × 10 μF Ceramic capacitor, 6.3 V, X7R, size 0603, CL10B106MQ8NRNC
Samsung Electro-
Mechanics
C2
L1
R1
3 × 22 μF Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44L
0.1 μH Power inductor, XEL4020-101ME
Murata
Coilcraft
Standard
10 kΩ, size 0603
1. See the Third-Party Products Disclaimer.
9.3.2 Detailed Design Procedure
9.3.2.1 Setting the Output Voltage
The start-up output voltage of the TPS6286900C device is factory-programmed to 0.5 V and therefore no
additional external components are needed. After start-up, the output voltage can be changed by using the I2C
interface to program the VOUT Register 1.
9.3.2.2 Output Filter Design
The inductor and output capacitor form a low-pass filter. To simplify the design process, Table 9-7 outlines
possible inductor and capacitor combinations for most applications. Checked cells represent combinations that
have been proven for stability by simulation and lab testing. Further combinations, not listed in , should be
checked for the specific application.
Table 9-7. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
22
2 × 22 or 47
3 × 22
150
(1)
0.1
+
+
+
(1) This LC combination is the standard value and recommended for most applications.
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(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –30%.
9.3.2.3 Inductor Selection
Inductor selection for the TPS6286x0A and TPS6286x0xC (0.2-V to 0.8375-V) device variants follows the same
procedure as for the other device variants (see Section 9.2.2.3). Table 9-8 lists recommended inductors for the
low-voltage device variants.
Table 9-8. List of Recommended Inductors
INDUCTANCE CURRENT RATING,
DIMENSIONS [L × W
× H mm]
DC RESISTANCE
[mΩ]
PART NUMBER
[μH]
ISAT [A]
0.1
28.5
4 × 4 × 2
2
Coilcraft, XEL4020-101ME
9.3.2.4 Capacitor Selection
Capacitor selection for the TPS6286x0A and TPS6286x0xC (0.2-V to 0.8375-V) device variants follows the
same procedure as for the other device variants (see Section 9.2.2.4).
9.3.3 Application Curves
VIN = 5.0 V, VOUT = 0.5 V, TA = 25°C, BOM = Table 9-6, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
0.31
0.30
0.29
0.28
+1%
–1%
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
1m
10m
100m
Output Current (A)
1
10
1m
10m
100m
Output Current (A)
1
10
VOUT = 0.3 V
VOUT = 0.3 V
Figure 9-21. Efficiency
Figure 9-22. Load Regulation
100
90
80
70
60
50
40
30
20
10
0
0.51
0.50
0.49
0.48
+1%
–1%
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
1m
10m
100m
Output Current (A)
1
10
1m
10m
100m
Output Current (A)
1
10
VOUT = 0.5 V
VOUT = 0.5 V
Figure 9-23. Efficiency
Figure 9-24. Load Regulation
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3.0
2.5
2.0
1.5
1.0
0.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT = 0.6 V, FPWM
VOUT = 0.6 V, PSM
VOUT = 0.4 V
VOUT = 0.6 V
0.0
0
1
2
3
4
5
6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Output Current (A)
Input Voltage (V)
VIN = 5 V
IOUT = 1 A
Figure 9-25. Switching Frequency
Figure 9-26. Switching Frequency
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application. The power supply must avoid a fast ramp down.
The falling ramp speed must be slower than 10 mV/µs, if the input voltage drops below VUVLO
.
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11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device.
•
The input/output capacitors and the inductor must be placed as close as possible to the IC. This keeps
the power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
•
•
•
The low side of the input and output capacitors must be connected properly to the PGND to avoid a GND
potential shift.
The sense traces connected to the VOS pin is a signal trace. Special care must be taken to avoid noise being
induced. Keep the trace away from SW.
Refer to Figure 11-1 for an example of component placement, routing, and thermal design.
11.2 Layout Example
Solution
Size
GND
2
56
mm
R1
D
VOUT
V O S
A G N D
V S E T / V I
PGND
SW
VIN
VIN
U1
GND
L1
Figure 11-1. Layout Example
11.2.1 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are improving the power dissipation capability of the
PCB design and introducing airflow in the system. For more details on how to use the thermal parameters, see
the Semiconductor and IC Package Thermal Metrics Application Report.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.5 Trademarks
DCS-Control™ is a trademark of TI.
I2C™ is a trademark of NXP Semiconductors.
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS6286800CRQYR
TPS628680ARQYR
TPS6286810CRQYR
TPS628681ARQYR
TPS6286820CRQYR
TPS628682ARQYR
TPS6286900CRQYR
TPS628690ARQYR
TPS6286910CRQYR
TPS628691ARQYR
TPS6286920CRQYR
TPS628692ARQYR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
9
9
9
9
9
9
9
9
9
9
9
9
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2JOH
2I8H
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
2JPH
2ECH
2JQH
2IAH
2JRH
2I7H
2JSH
2EBH
2JTH
2I9H
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2021
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS6286800CRQYR
TPS628680ARQYR
TPS6286810CRQYR
TPS628681ARQYR
TPS6286820CRQYR
TPS628682ARQYR
TPS6286900CRQYR
TPS628690ARQYR
TPS6286910CRQYR
TPS628691ARQYR
TPS6286920CRQYR
VQFN-
HR
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
9
9
9
9
9
9
9
9
9
9
9
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
1.12
1.12
1.12
1.12
1.12
1.12
1.12
1.12
1.12
1.12
1.12
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HR
TPS628692ARQYR
VQFN-
HR
RQY
9
3000
180.0
8.4
1.8
2.8
1.12
4.0
8.0
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS6286800CRQYR
TPS628680ARQYR
TPS6286810CRQYR
TPS628681ARQYR
TPS6286820CRQYR
TPS628682ARQYR
TPS6286900CRQYR
TPS628690ARQYR
TPS6286910CRQYR
TPS628691ARQYR
TPS6286920CRQYR
TPS628692ARQYR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
RQY
9
9
9
9
9
9
9
9
9
9
9
9
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQY0009A
1.6
1.4
B
A
2.6
2.4
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
0.85
0.65
3X
(0.1) TYP
6
4
0.25
0.15
3X
0.1
C
C
A B
3
2
0.05
PKG
7
2X 0.4
0.4
0.3
6X
PIN 1 ID
(45° X 0.1)
8
1
0.3
0.2
6X
4X 0.5
PKG
4225639/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQY0009A
PKG
(0.95)
3X (0.95)
1
8
3X (0.2)
2
PKG
7
(2.35)
2X (0.4)
3
(R0.05) TYP
6
4
6X (0.55)
6X (0.25)
4X (0.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED
METAL
EXPOSED
METAL UNDER
SOLDER MASK
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225639/A 03/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RQY0009A
PKG
(0.95)
3X (0.95)
1
8
3X (0.2)
2
PKG
7
(2.35)
2X (0.4)
3
(R0.05) TYP
6
4
6X (0.55)
6X (0.25)
4X (0.5)
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
SCALE: 25X
4225639/A 03/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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