TPS62873QWRXSRQ1 [TI]
汽车级 2.7V 至 6V 输入、15A 可堆叠同步降压转换器 | RXS | 16 | -40 to 125;
| 型号： | TPS62873QWRXSRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级 2.7V 至 6V 输入、15A 可堆叠同步降压转换器 | RXS | 16 | -40 to 125 转换器 |
| 文件： | 总61页 (文件大小：2516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62870-Q1, TPS62871-Q1, TPS62872-Q1, TPS62873-Q1
ZHCSQI6B –MAY 2022 –REVISED JANUARY 2023
TPS6287x-Q1 具有快速瞬态响应功能的2.7V 至6V 输入，6A、9A、12A、15A 可
堆叠同步降压转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TPS6287x-Q1 是具有远程差分检测功能的引脚对引脚
6A、9A、12A 和 15A 同步直流/直流降压转换器系
列。对于每个电流额定值，都有适用的具有I2C 接口且
功能全面的器件型号，以及不具有I2C 接口且功能有限
的器件型号。所有器件都具有高效率且易于使用。低阻
电源开关可在高温环境下支持高达 15A 的持续输出电
流。
– 温度等级1：–40°C 至+125°C，TA
• 功能安全型
– 可提供用于功能安全系统设计的文档
– 可提供用于功能安全系统设计的文档
– 可提供用于功能安全系统设计的文档
• 输入电压范围为2.7V 至6V
• 引脚对引脚兼容器件系列：6A、9A、12A 和15A
• 四个输出电压范围：
这些器件可在堆叠模式下运行，以提供更高的输出电流
或将功耗分散到多个器件上。
– 0.4V 至0.71875V（阶跃为1.25mV）
– 0.4V 至1.0375V（阶跃为2.5mV）
– 0.4V 至1.675V（阶跃为5mV）
– 0.8V 至3.35V（阶跃为10mV）
• 输出电压精度为±1%
TPS6287x-Q1 系列实现了增强型 DCS 控制方案，该
方案支持具有固定频率操作的快速瞬变。器件可以在省
电模式下运行以充分提高效率，也可以在强制PWM 模
式下运行以实现出色瞬态性能和超低输出电压纹波。
可选的远程检测功能可充分提升负载点的电压调节，并
且该器件在所有运行条件下均可实现优于 ±1% 的直流
电压精度。
• 7mΩ和4.5mΩ内部功率MOSFET
• 可调节外部补偿
• 电阻可选启动输出电压
• 电阻可选开关频率
• 节电或强制PWM 操作
器件信息
电流额定值
器件型号
封装
• 与I2C 兼容的接口频率高达1MHz
• 远程差分检测
TPS62870-Q1
TPS62871-Q1
TPS62872-Q1
TPS62873-Q1
6A
9 A
RXS（VQFN-
FCRLF，16）
• 旨在提高输出电流能力的可选堆叠操作
• 热警告和热关断
• 精密使能输入
12A
15A
• 有源输出放电
• 可选展频时钟
L
VIN
2.7 V to 6 V
VIN
VIN
SW
• 具有窗口比较器的电源正常输出
• 采用具有可湿性侧面的2.55mm × 3.55mm × 1mm
VQFN 封装
COUT
Load
CIN
VIO
REN
MODE/SYNC
EN
VOSNS
GOSNS
SDA
SCL
I2C
• 结温范围为–40°C 至150°C，TJ
RZ
VSEL
FSEL
VIO
CC2
2 应用
CC
RVSEL RFSEL
• 信息娱乐系统与仪表组
• ADAS
RPG
COMP
PG
1k
PG
• FPGA、ASIC 和数字内核电源
• DDR 存储器电源
SYNC_OUT GND
GND
10pF
TPS6287x-Q1 简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFJ3
TPS62870-Q1, TPS62871-Q1, TPS62872-Q1, TPS62873-Q1
ZHCSQI6B –MAY 2022 –REVISED JANUARY 2023
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Table of Contents
9.4 Device Functional Modes..........................................30
9.5 Programming............................................................ 31
9.6 Register Map.............................................................35
10 Application and Implementation................................41
10.1 Application Information........................................... 41
10.2 Typical Application.................................................. 41
10.3 Best Design Practices.............................................49
10.4 Power Supply Recommendations...........................50
10.5 Layout..................................................................... 50
11 Device and Documentation Support..........................52
11.1 Device Support........................................................52
11.2 Documentation Support ......................................... 52
11.3 接收文档更新通知................................................... 52
11.4 支持资源..................................................................52
11.5 Trademarks............................................................. 52
11.6 静电放电警告...........................................................52
11.7 术语表..................................................................... 52
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Options ............................................................... 3
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 I2C Interface Timing Characteristics......................... 10
8.7 Timing Requirements................................................ 11
8.8 Typical Characteristics..............................................12
9 Detailed Description......................................................13
9.1 Overview...................................................................13
9.2 Functional Block Diagram.........................................14
9.3 Feature Description...................................................15
Information.................................................................... 52
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (July 2022) to Revision B (January 2023)
Page
• Updated the Device Options Table..................................................................................................................... 3
• Modified MODE/SYNC pin Description in Pin Functions ...................................................................................5
• Changed the title of 图8-5 ...............................................................................................................................12
• Added approximate minimum on time value.....................................................................................................15
• Added behavior of device when EN is toggled and input voltage is applied.....................................................17
• Modified 表9-5 to reflect new available Orderable Part Number..................................................................... 21
• Added a comment on how to connect secondary devices SYNC_OUT pin..................................................... 27
• Added a footnote to 表9-10 .............................................................................................................................31
• Added I2C Register Reset ................................................................................................................................34
• Added Number of phases Nɸ and adapted passive component selection equations in Typical Application ...41
Changes from Revision * (May 2022) to Revision A (July 2022)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 说明（续）
通过 FSEL 引脚实现电阻可选开关频率。开关频率可设置为 1.5MHz、2.25MHz、2.5MHz 或 3.0MHz，也可与频
率范围相同的外部时钟同步。
I2C 兼容接口提供多种控制、监控和警告功能，例如电压监控和温度相关警告。通过I2C 兼容接口可快速调整输出
电压，使负载功耗适应应用性能需求。通过VSEL 引脚，默认启动电压可实现电阻可选。
6 Device Options
表6-1. Devices With I2C Interface
Start-Up Voltage, I2C
Address(1) (2)
Spread Spectrum
Clocking
Device Number
Output Current
VSEL Settings
Soft-Start Time
TPS62870QWRXSRQ1
TPS62871QWRXSRQ1
TPS62872QWRXSRQ1
TPS62873QWRXSRQ1
TPS62870Y1QWRXSRQ1
TPS62871Y1QWRXSRQ1
TPS62872Y1QWRXSRQ1
TPS62873Y1QWRXSRQ1
6 A
9 A
0.850 V, 0x40
0.750 V, 0x41
0.875 V, 0x42
1.000 V, 0x43
0.800 V, 0x40
0.750 V, 0x41
0.875 V, 0x42
0.800 V, 0x43
0.500 V, 0x40
0.750 V, 0x41
0.875 V, 0x42
1.050 V, 0x43
1.800 V, 0x30
1.500 V, 0x31
1.750 V, 0x32
3.300 V, 0x33
0.810 V, 0x40
0.750 V, 0x41
0.875 V, 0x42
1.000 V, 0x43
6.2 kΩto GND
Short to GND
Short to VIN
Default setting =
off
Default setting = 1
ms
12 A
15 A
6 A
47 kΩto VIN
6.2 kΩto GND
Short to GND
Short to VIN
9 A
Default setting =
off
Default setting = 1
ms
12 A
15 A
47 kΩto VIN
6.2 kΩto GND
Short to GND
Short to VIN
Default setting =
off
Default setting = 1
ms
TPS62870Y0QWRXSRQ1
TPS62870Y2QWRXSRQ1
TPS62870Y3QWRXSRQ1
6 A
6 A
6 A
47 kΩto VIN
6.2kΩto GND
Short to GND
Short to VIN
Default setting =
off
Default setting = 1
ms
47 kΩto VIN
6.2 kΩto GND
Short to GND
Short to VIN
Default setting =
off
Default setting = 1
ms
47 kΩto VIN
(1) The I2C address is linked to the selected start-up voltage. The user cannot select the start-up voltage and I2C address independently.
(2) The user can use the VSEL pin to select which of the four start-up voltages the device uses. For more information, see 表9-5 and 表
9-10.
表6-2. Devices Without I2C Interface
Spread Spectrum
Device Number
Output Current
Start-Up Voltage(2)
VSEL Settings
Soft-Start Time
Clocking
TPS62870N0QWRXSRQ1
TPS62871N0QWRXSRQ1
TPS62872N0QWRXSRQ1
TPS62873N0QWRXSRQ1
6 A
9 A
0.500 V
0.750 V
0.875 V
1.050 V
6.2 kΩto GND
Short to GND
Short to VIN
On
0.5 ms
12 A
15 A
47 kΩto VIN
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Soft-Start Time
表6-2. Devices Without I2C Interface (continued)
Spread Spectrum
Clocking
Device Number
Output Current
Start-Up Voltage(2)
VSEL Settings
TPS62870N1QWRXSRQ1
TPS62871N1QWRXSRQ1
TPS62872N1QWRXSRQ1
TPS62873N1QWRXSRQ1
6 A
9 A
0.800 V
0.750 V
0.875 V
0.840 V
1.800 V
1.500 V
1.750 V
3.300 V
6.2kΩto GND
Short to GND
Short to VIN
47 kΩto VIN
6.2 kΩto GND
Short to GND
Short to VIN
47kΩto VIN
On
Off
12 A
15 A
1 ms
TPS62872N2QWRXSRQ1
12 A
Unless otherwise noted, device variants without I2C operate with the same default settings as device variants
with I2C.
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7 Pin Configuration and Functions
1
13
COMP
GOSNS
VOSNS
EN
SCL
2
3
4
5
12 SDA
11 MODE/SYNC
10 PG
Thermal
Pad
VIN
9
VIN
GND
GND
6
8
7
SW
Not to scale
图7-1. 16-Pin RXS VQFN Package (Top View)
表7-1. Pin Functions
Pin
Type(1)
Description
Name
No.
Device compensation input. A resistor and capacitor from this pin to GOSNS define the
compensation of the control loop.
In stacked operation, connect the COMP pins of all stacked devices together and connect a
resistor and capacitor between the common COMP node and GOSNS.
COMP
1
—
GOSNS
VOSNS
2
3
I
I
Output ground sense (differential output voltage sensing)
Output voltage sense (differential output voltage sensing)
This is the enable pin of the device. The user must connect to this pin using a series resistor of at
least 15 kΩ. A low logic level on this pin disables the device and a high logic level on this pin
enables the device. Do not leave this pin unconnected.
EN
4
I
For stacked operation, interconnect EN pins of all stacked devices with a resistor to the supply
voltage or a GPIO of a processor. See 节9.3.17 for a detailed description.
VIN
GND
SW
5, 9
6, 8
7
P
GND
O
Power supply input. Connect the input capacitor as close as possible between VIN and GND.
Ground pin
This pin is the switch pin of the converter and is connected to the internal power MOSFETs.
Open-drain power-good output. Low impedance when not "power good," high impedance when
"power good." This pin can be left open or be tied to GND when not used in single device
operation.
In stacked operation, interconnect the PG pins of all stacked devices. Only the PG pin of the
primary converter in stacked operation is an open-drain output. For devices that are defined as
secondary converters in stacked mode, this pin is an input pin. See 节9.3.17 for a detailed
description.
PG
10
I/O
The device runs in power save mode when this pin is pulled low. If the pin is pulled high, the
device runs in forced-PWM mode. If unused, this pin can be left floating and an internal pulldown
resistor will pull it low. The mode pin can also be used to synchronize the device to an external
clock.
MODE/SYNC
11
I
I2C serial data pin. Do not leave floating. Connect a pullup resistor to a logic high level.
SDA
SCL
12
13
I/O
I/O
Connect to GND for secondary devices in stacked operation and for device variants without I2C.
I2C serial clock pin. Do not leave this pin floating. Connect a pullup resistor to a logic high level.
Connect this pin to GND for secondary devices in stacked operation and for device variants
without I2C.
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表7-1. Pin Functions (continued)
Pin
Type(1)
Description
Name
No.
Internal clock output pin for synchronization in stacked mode. Leave this pin floating for single
device operation. Connect this pin to the MODE/SYNC pin of the next device in the daisy-chain in
stacked operation. Do not use this pin to connect to a non-TPS6287x-Q1 device.
During start-up, this pin is used to identify if a device must operate as a secondary converter in
stacked operation. Connect a 47-kΩresistor from this pin to GND to define a secondary converter
in stacked operation. See 节9.3.17 for a detailed description.
SYNC_OUT
14
O
Start-up output voltage select pin. A resistor or short circuit to GND or VIN defines the selected
output voltage. See 节9.3.6.2.
VSEL
FSEL
15
16
—
—
—
Frequency select pin. A resistor or a short circuit to GND or VIN determines the free-running
switching frequency. See 节9.3.6.2.
The thermal pad must be soldered to GND to achieve an appropriate thermal resistance and for
mechanical stability.
Exposed Thermal Pad
(1) I = input, O = output, P = power, GND = ground
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8 Specifications
8.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
6.5
UNIT
VIN(4)
SW (DC)
VIN + 0.3
10
SW (AC, less than 10ns)(3)
Voltage(2)
VOSNS
3.8
V
–0.3
–0.3
–0.3
–0.3
–0.3
–1
SCL, SDA
5.5
FSEL, VSEL, EN, MODE/SYNC
6.5
GOSNS
0.3
Voltage(2)
Current
PG
6.5
SYNC_OUT
COMP
1
mA
1
–1
PG
5
TJ
Junction temperature
Storage temperature
150
150
°C
°C
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the GND pin.
(3) While switching.
(4) The voltage at the pin can exceed the 6.5 V absolute max condition for a short period of time, but must remain less than 8 V. VIN at 8
V for a 100ms duration is equivalent to approximately 8 hours of aging for the device at room temperature.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM) per AEC Q100-011
CDM ESD classification level C4A
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
2.7
6
5
VIN
Input voltage
V
SDA, SCL
3.35 V or
(VIN - 1.4
V)(1)
VOUT
Output voltage
0.4
V
TPS62870-Q1
TPS62871-Q1
TPS62872-Q1
TPS62873-Q1
6
9
IOUT
Output current
Inductance
A
12
15
110
55
330
330
L
nH
f
SW ≥2.25 MHz and VOUT ≤1.675 V
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8.3 Recommended Operating Conditions (continued)
Over operating temperature range (unless otherwise noted)
MIN
5
NOM
MAX
UNIT
Input capacitance (per
CIN
VIN
10
pin)(2)
µF
Output capacitance(2)
40
(3)
COUT
VSEL, FSEL
SYNC_OUT
VSEL, FSEL
100
20
CPAR
Parasitic capacitance
pF
Resistor tolerance
±2%
Operating junction
temperature
TJ
150
–40
(1) Whichever value is lower.
(2) Effective capacitance.
(3) The maximum recommended output capacitance depends on the specific operating conditions of an application. Output capacitance
values up to a few millifarad are typically possible, however.
8.4 Thermal Information
TPS6287x
THERMAL METRIC(1)
RXS (JEDEC)
RXS (EVM)
16 PINS
28
UNIT
16 PINS
43.2
19.2
7.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
N/A
N/A
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
1.5
ΨJT
7.7
9.3
ΨJB
RθJC(bot)
6.3
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
over operating junction temperature (TJ = –40 °C to 150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 3.3 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = high, IOUT = 0 mA, V(SW) = 0 V,
primary operation, device not switching,
TJ = 25 °C
Operating
Standby
1.75
3
mA
IQ
Supply current (VIN)
EN = low, V(SW) = 0 V, TJ = 25 °C
16.5
2.6
40
µA
V
Positive-going UVLO threshold voltage
(VIN)
VIT+
2.5
2.7
Negative-going UVLO threshold voltage
(VIN)
VIT–
Vhys
VIT+
2.4
90
2.5
2.6
V
mV
V
UVLO hysteresis voltage (VIN)
Positive-going OVLO threshold voltage
(VIN)
6.1
6.3
6.2
6.5
6.4
Negative-going OVLO threshold voltage
(VIN)
VIT–
6.0
V
Vhys
OVLO hysteresis voltage (VIN)
85
mV
V
VIT–
Negative-going power-on reset threshold
1.4
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8.5 Electrical Characteristics (continued)
over operating junction temperature (TJ = –40 °C to 150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 3.3 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
170
20
MAX
UNIT
°C
Thermal shutdown threshold temperature TJ rising
Thermal shutdown hysteresis
TSD
°C
Thermal warning threshold temperature
Thermal warning hysteresis
TJ rising
150
20
°C
TW
°C
CONTROL and INTERFACE
Positive-going input threshold voltage
(EN)
VIT+
0.97
1.0
0.9
1.03
0.93
V
Negative-going input threshold voltage
(EN)
VIT–
Vhys
IIH
0.87
95
V
Hysteresis voltage (EN)
mV
nA
VIH = VIN, internal pulldown resistor
disabled
High-level input current (EN)
200
VIL = 0 V, internal pulldown resistor
disabled
IIL
Low-level input current (EN)
nA
V
–200
High-level input voltage (SDA, SCL,
MODE/SYNC, VSEL, FSEL, SYNC_OUT)
VIH
VIL
0.8
Low-level input voltage (SDA, SCL,
MODE/SYNC, VSEL, FSEL, SYNC_OUT)
0.4
V
IOL = 3 mA
IOL = 9 mA
IOL = 5 mA
VOH = 3.3 V
VIL = 0 V
0.4
0.4
0.2
200
150
3
V
VOL
Low-level output voltage (SDA)
V
V
IOH
IIL
High-level output current (SDA, SCL)
Low-level input current (MODE/SYNC)
High-level input current (MODE/SYNC)
Low-level input current (SYNC_OUT)
High-level input current (SYNC_OUT)
nA
nA
µA
nA
nA
–150
–250
IIH
IIL
VIH = VIN
VIL = 0 V
IIH
VIH = 2 V
150
500
Measured from when EN goes high to
when device starts switching
SRVIN = 1 V/µs
td(EN)1
Enable delay time when EN tied to VIN
175
µs
µs
Enable delay time when VIN already
applied
Measured from when EN goes high to
when device starts switching
td(EN)2
100
0.35
0.7
1.4
2.8
0.5
1
0.65
1.3
2.6
5.2
ms
ms
ms
ms
µs
Measured from when device starts
switching to rising edge of PG
td(RAMP) Output voltage ramp time
2
4
Time to lock external frequency
50
Internal pullup resistance (VSEL, FSEL)
5.5
1.3
9
kΩ
Internal pulldown resistance (VSEL,
FSEL)
2.2
kΩ
Positive-going power good threshold
voltage (output undervoltage)
VT+
94
92
96
94
98 %VOUT
96 %VOUT
108 %VOUT
106 %VOUT
Negative-going power good threshold
voltage (output undervoltage)
VT–
Positive-going power good threshold
voltage (output overvoltage)
VT+
104
102
106
104
Negative-going power good threshold
voltage (output overvoltage)
VT–
VOL
Low-level output voltage (PG)
IOL = 1 mA
0.3
V
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8.5 Electrical Characteristics (continued)
over operating junction temperature (TJ = –40 °C to 150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 3.3 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VOH = 3.3 V
MIN
TYP
MAX
UNIT
IOH
VIH
High-level output current (PG)
200
nA
Device configured as a secondary device
in stacked operation
High-level input voltage (PG)
Low-level input voltage (PG)
High-level input current (PG)
Low-level input current (PG)
Deglitch time (PG)
0.8
V
V
Device configured as a secondary device
in stacked operation
VIL
IIH
0.4
1
Device configured as a secondary device
in stacked operation
µA
µA
µs
Device configured as a secondary device
in stacked operation
IIL
–1
High-to-low or low-to-high transition on
the PG pin
td(PG)
34
40
46
1
OUTPUT
VOUT
IIB
Output accuracy
%
µA
µA
mV
VIN ≥VOUT + 1.4 V
–1
–6
Input bias current (GOSNS)
Input bias current (VOSNS)
Input common-mode range (GOSNS)
V(GOSNS) = –100 mV to 100 mV
V(VOSNS) = 3.3 V, VIN = 6 V
IIB
6
VICR
100
–100
fSW = 1.5 MHz, PWM operation, VIN 3.3 V,
VOUT = 0.75 V
1.35
1.5
2.25
2.5
1.65
2.475
2.75
3.3
fSW = 2.25 MHz, PWM operation, VIN 3.3
V, VOUT = 0.75 V
2.025
2.25
2.7
fSW
Switching frequency (SW)
MHz
kHz
fSW = 2.5 MHz, PWM operation, VIN 3.3 V,
VOUT = 0.75 V
fSW = 3 MHz, PWM operation, VIN 3.3 V,
VOUT = 0.75 V
3
fsw/2048
±10%
fmod
Frequency of the spread-spectrum sweep
Switching frequency variation during
spread-spectrum operation
ΔfSW
Emulated current time constant
12.5
7
µs
τ
rDS(on)
High-side FET static on-state resistance VIN = 3.3 V
16
mΩ
mΩ
rDS(on)
Low-side FET static on-state resistance
High-side FET off-state current
Low-side FET off-state current
TPS62870-Q1
VIN = 3.3 V
4.1
9.4
VIN = 6 V, V(SW) = 0 V, TJ = 25 °C
VIN = 6 V, V(SW) = 6 V, TJ = 25 °C
–1
I(SW)(off)
µA
100
14
18
22
26
12
9
12
15
18
7.5
12
16
20
24
TPS62871-Q1
TPS62872-Q1
TPS62873-Q1
High-side FET forward
switch current limit, DC
ILIM
A
A
Low-side FET negative current limit, DC
8.6 I2C Interface Timing Characteristics
PARAMETER
TEST CONDITIONS
Standard mode
MIN
TYP
MAX
100
UNIT
fSCL
SCL clock frequency
Fast mode
400
kHz
Fast mode plus
Standard mode
Fast mode
1000
4
0.6
tHD; tSTA Hold time (repeated) START condition
µs
Fast mode plus
0.26
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8.6 I2C Interface Timing Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
4.7
1.3
0.5
4
TYP
MAX
UNIT
Standard mode
Fast mode
tLOW
LOW period of the SCL clock
µs
Fast mode plus
Standard mode
Fast mode
tHIGH
HIGH period of the SCL clock
0.6
0.26
4.7
0.6
0.26
0
µs
µs
µs
ns
ns
ns
µs
µs
pF
Fast mode plus
Standard mode
Fast mode
Setup time for a repeated START
condition
tSU; tSTA
Fast mode plus
Standard mode
Fast mode
3.45
0.9
tHD; tDAT Data hold time
tSU; tDAT Data setup time
0
Fast mode plus
Standard mode
Fast mode
0
250
100
50
Fast mode plus
Standard mode
Fast mode
1000
300
120
300
300
120
tr
Rise time of both SDA and SCL signals
20
Fast mode plus
Standard mode
Fast mode
tf
Fall time of both SDA and SCL signals
20×VDD/5.5V
Fast mode plus
Standard mode
Fast mode
20×VDD/5.5V
4
0.6
tSU; tSTO Setup time for STOP condition
Fast mode plus
Standard mode
Fast mode
0.26
4.7
Bus free time between a STOP and
START condition
tBUF
1.3
Fast mode plus
Standard mode
Fast mode
0.5
400
400
550
Cb
Capacitive load for each bus line
Fast mode plus
8.7 Timing Requirements
MIN
NOM
MAX
UNIT
Synchronization clock frequency range
(MODE/SYNC)
f(SYNC)
f(SYNC)
f(SYNC)
f(SYNC)
D(SYNC)
Nominal fSW = 1.5 MHz
Nominal fSW = 2.25 MHz
Nominal fSW = 2.5 MHz
Nominal fSW = 3.0 MHz
1.3
2.0
MHz
Synchronization clock frequency range
(MODE/SYNC)
1.8
2.0
2.7
3.0
MHz
MHz
MHz
Synchronization clock frequency range
(MODE/SYNC)
Synchronization clock frequency range
(MODE/SYNC)
2.5
3.3
Synchronization clock duty cycle range
(MODE/SYNC)
45%
55%
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8.8 Typical Characteristics
4m
50m
40m
30m
20m
10m
0
3m
2m
–40°C
25°C
85°C
105°C
125°C
150°C
–40°C
25°C
85°C
105°C
125°C
150°C
1m
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
Input Voltage (V)
VOUT = 0.75 V
MODE = Low
VOUT = 0.75 V
MODE = High
图8-1. Operating Supply Current (Power Save Mode)
图8-2. Operating Supply Current (Forced PWM)
2.235
60
TJ = –40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
2.230
2.225
2.220
2.215
2.210
2.205
50
40
30
20
10
0
VIN = 3.3 V
VIN = 5 V
-40
0
40
80
120
160
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Junction Temperature (°C)
Input Voltage (V)
ENABLE = Low
图8-4. Switching Frequency vs Temperature
图8-3. Quiescent Supply Current
3.5
3.25
3
2.75
2.5
2.25
2
VIN = 3.3 V
VIN = 5.5 V
1.75
1.5
0.4
0.6
0.8
1
1.2
1.4
1.6
Output Voltage (V)
图8-5. Maximum Switching Frequency vs VIN and VOUT
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9 Detailed Description
9.1 Overview
The TPS6287x-Q1 devices are synchronous step-down (buck) DC/DC converters. These devices use an
enhanced DCS control topology to achieve fast transient response while switching with a fixed frequency.
Together, with their low output voltage ripple, high DC accuracy, and differential remote sensing, these devices
are ideal for supplying the cores of modern high-performance processors.
The family of devices includes 6-A, 9-A, 12-A, and 15-A devices. To further increase the output current capability,
the user can combine multiple devices in a “stack”. For example, a stack of two TPS62873-Q1 devices have a
current capability of 30 A. Each device of a stack must have the same current rating to avoid that one device
enters current limit too early.
For each current rating, there are full-featured devices with an I2C interface and limited-featured devices without
an I2C interface (see the Device Options). The user can use a device variant without I2C in exactly the same way
as a device variant with I2C, except that:
• The user must connect the unused SCL and SDA pins to GND.
• The user must be aware of the (fixed) factory settings for parameters and functions that are programmable in
the I2C device variants.
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9.2 Functional Block Diagram
VIN
VIN
SW
Bias
Regulator
Gate Drive and Control
IHS
ILS
EN
GND
GND
Ramp and Slope
Compensation
PG
Device
Control
+
–
VOSNS
GOSNS
–
gm
+
FSEL
VSEL
Oscillator
COMP
SCL1
SDA1
Thermal
Shutdown
SYNCOUT
MODE/SYNC
1. In device variants without I2C the SDA and SCL pins are internally connected, but their functionality is disabled.
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9.3 Feature Description
9.3.1 Fixed-Frequency DCS Control Topology
图 9-1 shows a simplified block diagram of the fixed-frequency enhanced DCS control topology used in the
TPS6287x-Q1 devices. This topology is comprised of an inner emulated current loop, a middle direct feedback
loop, and an outer voltage-regulating loop.
VIN
–
+
ON
EN
R
S
Q
L
Gate
Driver
COUT
fsw
Control
Logic
Slope
Compensation
τaux
VOSNS
GOSNS
–
COMP
gm
RLOAD
+
RZ
CC2
CC
图9-1. Fixed-Frequency DCS Control Topology (Simplified)
9.3.2 Forced PWM and Power Save Modes
The device can control the inductor current in three different ways to regulate the output:
• Pulse-width modulation with continuous inductor current (PWM-CCM)
• Pulse-width modulation with discontinuous inductor current (PWM-DCM)
• Pulse-frequency modulation with discontinuous inductor current and pulse skipping (PFM-DCM)
During PWM-CCM operation, the device switches at a constant frequency and the inductor current is continuous
(see 图9-2). PWM operation achieves the lowest output voltage ripple and the best transient performance.
t1/fSW
t
0
Time
图9-2. Continuous Conduction Mode (PWM-CCM) Current Waveform
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During PWM-DCM operation, the device switches at a constant frequency and the inductor current is
discontinuous (see 图 9-3). In this mode, the device controls the peak inductor current to maintain the selected
switching frequency while still being able to regulate the output.
t1/fSW
t
0
Time
图9-3. Discontinuous Conduction Mode (PWM-DCM) Current Waveform
During PFM-DCM operation, the device keeps the peak inductor current constant (at a level corresponding to the
minimum on time of the converter) and skips pulses to regulate the output (see 图 9-4). The switching pulses
that occur during PFM-DCM operation are synchronized to the internal clock.
Minimum on-time
t1/fSW
t
t1/fSW
t
t1/fSWt
0
Time
Skipped Pulses
图9-4. Discontinuous Conduction Mode (PFM-DCM) Current Waveform
For very small output voltages, an absolute minimum on time of approximately 50 ns reduces the switching
frequency from the set value. 图8-5 shows the maximum switching frequency with 3.3-V and 5.5-V supplies.
Use 方程式1 to calculate the output current threshold at which the device enters PFM-DCM.
V
– V
2L
V
IN
IN
OUT
2
I
=
t
f
sw
(1)
OUT PFM
ON
V
OUT
图9-5 shows how this threshold typically varies with VIN and VOUT for a switching frequency of 2.25 MHz.
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1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VIN = 3.3 V
VIN = 5 V
fsw = 2.25 MHz
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Output Voltage (V)
图9-5. Output Current PFM-DCM Entry Threshold
The user can configure the device to use either forced PWM (FPWM) mode or power save mode (PSM):
• In forced PWM mode, the device uses PWM-CCM at all times.
• In power save mode, the device uses PWM-CCM at medium and high loads, PWM-DCM at low loads, and
PFM-DCM at very low loads. The transition between the different operating modes is seamless.
表 9-1 shows the function table of the MODE/SYNC pin and the FPWMEN bit in the CONTROL1 register, which
control the operating mode of the device.
表9-1. FPWM Mode and Power-Save Mode Selection
MODE/SYNC Pin
FPWMEN Bit
Operating Mode
Remark
Do not use in a stacked
configuration.
0
PSM
Low
1
X
X
FPWM
FPWM
FPWM
High
Sync Clock
备注
If spread-spectrum clocking is enabled, the device automatically operates in FPWM, regardless of the
state of FPWMEN bit in the CONTROL1 register (see 节9.3.9).
9.3.3 Precise Enable
The Enable (EN) pin is bidirectional and has two functions:
• As an input, EN enables and disables the DC/DC converter in the device.
• As an output, EN provides a SYSTEM_READY signal to other devices in a stacked configuration.
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+
–
EN
ENABLE
VIT(EN)
SYSTEM_READY
CONTROL3:SINGLE
图9-6. Enable Functional Block Diagram
Because there is an internal open-drain transistor connected to the EN pin, do not drive this pin directly from a
low-impedance source. Instead, use a resistor to limit the current flowing into the EN pin (see 节10).
When power is first applied to the VIN pin, the device pulls the EN pin low until it has loaded its default register
settings from nonvolatile memory and read the state of the VSEL, FSEL, and SYNCOUT pins. The device also
pulls EN low if a fault, such as thermal shutdown or overvoltage lockout, occurs. In stacked configurations, all
devices share a common enable signal, which means that the DC/DC converters in the stack cannot start to
switch until all devices in the stack have completed their initialization. Similarly, a fault in one or more devices in
the stack disables all converters in the stack (see 节9.3.17).
In standalone (nonstacked) applications, the user can disable the active pulldown of the EN pin if the user sets
SINGLE = 1 in the CONTROL3 register. Fault conditions have no effect on the EN pin when SINGLE = 1 (the EN
pin is always pulled down during device initialization). In stacked applications, ensure that SINGLE = 0.
When the internal SYSTEM_READY signal is low (that is, initialization is complete and there are no fault
conditions), the internal open-drain transistor is high impedance and the EN pin functions like a standard input. A
high level on the EN pin enables the DC/DC converter in the device. A low level disables the DC/DC converter
(the I2C interface is enabled as soon as the device has completed its initialization and is not affected by the state
of the internal ENABLE or SYSTEM_READY signals).
A low level on the EN pin forces the device into shutdown. During shutdown, the MOSFETs in the power stage
are off, the internal control circuitry is disabled, and the device consumes only 20 µA (typical).
The rising threshold voltage of the EN pin is 1.0 V and the falling threshold voltage is 0.9 V. The tolerance of the
threshold voltages is ±30 mV, which means that the user can use the EN pin to implement precise turn-on and
turn-off behavior.
When power is applied to the VIN pin, the toggling of the EN pin does not reset the loaded default register
settings.
9.3.4 Start-Up
When the voltage on the VIN pin exceeds the positive-going UVLO threshold, the device initializes as follows:
• The device pulls the EN pin low.
• The device enables the internal reference voltage.
• The device reads the state of the VSEL, FSEL, and SYNC_OUT pins.
• The device loads the default values into the device registers.
When initialization is complete, the device enables I2C communication and releases the EN pin. The external
circuitry controlling the EN pin now determines the behavior of the device:
• If the EN pin is low, the device is disabled. The user can write to and read from the device registers, but the
DC/DC converter does not operate.
• If the EN pin is high, the device is enabled. The user can write to and read from the device registers and,
after a short delay, the DC/DC converter starts to ramp up its output.
图9-7 shows the start-up sequence when the EN pin is pulled up to VIN.
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VIN
EN
VIT+(UVLO)
EN pin pulled
low internally
Device initialization
complete
VOUT
ttd(EN)1t
ttd(RAMP)t
PG
Undefined
td(PG)
图9-7. Start-Up Timing When EN is Pulled Up to VIN
图9-8 shows the start-up sequence when an external signal is connected to the EN pin.
VIN
VIT+(UVLO)
EN
VIT+(EN)
VOUT
ttd(EN)2
t
ttd(RAMP)t
Device initialization
complete
PG Undefined
td(PG)
图9-8. Start-Up Timing When an External Signal is Connected to the EN Pin
The SSTIME[1:0] bits in the CONTROL2 register select the duration of the soft-start ramp:
• td(RAMP) = 500 μs
• td(RAMP) = 1 ms (default)
• td(RAMP) = 2 ms
• td(RAMP) = 4 ms
The device ignores new values until the soft-start sequence is complete if the user programs the following when
the device soft-start sequence has already started:
• A new output voltage setpoint (VOUT[7:0])
• An output voltage range (VRANGE[1:0])
• Soft-start time (SSTIME[1:0]) settings
If the user change the value of VSET[7:0] during soft start, the device first ramps to the value that VSET[7:0] had
when the soft-start sequence began. Then, when soft start is complete, the device ramps up or down to the new
value.
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The device can start up into a prebiased output. In this case, only a portion of the internal voltage ramp is seen
externally (see 图9-9).
Final voltage
VOUT
Prebias voltage
ttd(RAMP)
t
图9-9. Start-Up into a Prebiased Output
Note that the device always operates in DCM during the start-up ramp, regardless of other configuration settings
or operating conditions.
9.3.5 Switching Frequency Selection
During device initialization, a resistor-to-digital converter in the device determines the state of the FSEL pin and
sets the switching frequency of the DC/DC converter according to 表9-2.
表9-2. Switching Frequency Options
FSEL Pin 1
Short to GND
6.2 kΩto GND
47 kΩto VIN
Short to VIN
Switching Frequency
1.5 MHz
2.25 MHz
2.5 MHz
3 MHz
1. For a reliable voltage setting, ensure there is no stray current path connected to the FSEL pin and that the
parasitic capacitance between the FSEL pin and GND is less than 100 pF.
图 9-10 shows a simplified block diagram of the R2D converter used to detect the state of the FSEL pin (an
identical circuit detects the state of the VSEL pin –see 节9.3.6.2).
VIN
S1
6.5 k
FSEL
VIL = < 0.4 V
VIH = > 0.8 V
1.6 k
S2
图9-10. FSEL R2D Converter Functional Block Diagram
Detection of the state of the FSEL pin works as follows:
To detect the most significant bit (MSB), the circuit opens S1 and S2, and the input buffer detects if a high or a
low level is connected to the FSEL pin.
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To detect the least significant bit (LSB):
• If the MSB was 0, the circuit closes S1. If the input buffer detects a high level, LSB = 1. If the circuit detects a
low level, LSB = 0.
• If the MSB was 1, the circuit closes S2. If the input buffer detects a low level, LSB = 0. If the circuit detects a
high level, LSB = 1.
9.3.6 Output Voltage Setting
9.3.6.1 Output Voltage Range
The device has four different voltage ranges. The VRANGE[1:0] bits in the CONTROL1 register control which
range is active (see 表 9-3). The default output voltage range after device initialization is 0.4 V to 1.675 V in 5-
mV steps.
表9-3. Voltage Ranges
VRANGE[1:0]
0b00
Voltage Range
0.4 V to 0.71875 V in 1.25-mV steps
0.4 V to 1.0375 V in 2.5-mV steps
0.4 V to 1.675 V in 5-mV steps
0.8 V to 3.35 V in 10-mV steps
0b01
0b10
0b11
Note that every change to the VRANGE[1:0] bits must be followed by a write to the VSET register, even if the
value of the VSET[7:0] bits does not change. This sequence is required for the device to start to use the new
voltage range.
Also note that the 0.8-V to 3.35-V range uses a 0.8-V reference and the other ranges use a 0.4-V reference.
Switching to and from the 0.8-V to 3.35-V range can therefore cause increased output voltage undershoot or
overshoot while the device switches its internal reference.
In device variants that do not have I2C, the output voltage range is factory-set to 0.4 V to 1.675 V.
9.3.6.2 Output Voltage Setpoint
Together with the selected range, the VSET[7:0] bits in the VSET register control the output voltage setpoint of
the device (see 表9-4).
表9-4. Start-Up Voltage Settings
VRANGE[1:0]
0b00
Output Voltage Setpoint
0.4 V + VSET[7:0] × 1.25 mV
0.4 V + VSET[7:0] × 2.5 mV
0.4 V + VSET[7:0] × 5 mV
0.8 V + VSET[7:0] × 10 mV
0b01
0b10
0b11
During initialization, the device reads the state of the VSEL pin and selects the default output voltage according
to 表9-5. Note that the VSEL pin also selects the I2C target address of the device (see 表9-10).
表9-5. Default Output Voltage Setpoints
VSEL Pin(1)
Device Number
VSET[7:0]
Output Voltage Setpoint
850 mV
TPS6287x-Q1
0x5a
TPS6287xY0-Q1
TPS6287xY1-Q1
TPS6287xY2-Q1
0x50
800 mV
0x14
500 mV
1800 mV
0x64
0x52
6.2 kΩto GND
TPS6287xY3-Q1
810 mV
TPS6287xN0-Q1
TPS6287xN1-Q1
TPS6287xN2-Q1
0x14
0x50
0x64
500 mV
800 mV
1800 mV
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表9-5. Default Output Voltage Setpoints (continued)
VSEL Pin(1)
Device Number
VSET[7:0]
Output Voltage Setpoint
Short Circuit to GND
0x46
750 mV
All, Except TPS6287xN2-Q1
Short Circuit to GND
0x4
TPS6287xN2-Q1
All, Except TPS6287XN2-Q1
TPS6287XN2-Q1
1500 mV
875 mV
1750 mV
1.0 V
Short Circuit to VIN
Short Circuit to VIN
0x5f
0x5f
TPS6287x-Q1
0x78
0x82
TPS6287xY0-Q1
1050
mV
TPS6287xY1-Q1
TPS6287xY2-Q1
0x50
0xFA
0x78
800 mV
3300 mV
1000 mV
47 kΩ to VIN
TPS6287xY3-Q1
TPS6287xN0-Q1
TPS6287xN1-Q1
TPS6287xN2-Q1
0x82
0x58
0xFA
1.050 V
840 mV
3300 mV
(1) For a reliable voltage setting, ensure there is no stray current path connected to the VSEL pin and that the parasitic capacitance
between the VSEL pin and GND is less than 100 pF.
If the user programs new output voltage setpoint (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start
time (SSTIME[1:0]) settings when the device has already begun its soft-start sequence, the device ignores the
new values until the soft-start sequence is complete. If the user changes the value of VSET[7:0] during soft start,
the device first ramps to the value that VSET[7:0] had when the soft-start sequence began. Then, when soft start
is complete, ramps up or down to the new value.
If the user changes VOUT[7:0], VRAMP[1:0], or SSTIME[1:0] while EN is low, the device uses the new values
the next time the user enables it.
During start-up, the output voltage ramps up to the target value set by the VSEL pin before ramping up or down
to any new value programmed to the device over the I2C interface.
9.3.6.3 Non-Default Output Voltage Setpoint
If none of the default voltage range or voltage setpoint combinations are suitable for the application, the user can
change these device settings through I2C before the user enables the device. Then, when the user pulls the EN
pin high, the device starts up with the desired start-up voltage.
Note that if the user changes the device settings through I2C while the device is ramping, the device ignores the
changes until the ramp is complete.
9.3.6.4 Dynamic Voltage Scaling
If the user changes the output voltage setpoint while the DC/DC converter is operating, the device ramps up or
down to the new voltage setting in a controlled way.
The VRAMP[1:0] bits in the CONTROL1 register sets the slew rate when the device ramps from one voltage to
another during DVS (see 表9-6).
表9-6. Dynamic Voltage Scaling Slew Rate
VRAMP[1:0]
0b00
DVS Slew Rate
10 mV/μs (0.5 μs/step)
5 mV/μs (1 μs/step)
1.25 mV/μs (5 μs/step)
0.5 mV/μs (10 μs/step)
0b01
0b10
0b11
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Note that ramping the output to a higher voltage requires additional output current, so that during DVS, the
converter must generate a total output current given by:
(2)
where
• IOUT is the total current the converter must generate while ramping to a higher voltage.
• IOUT(DC) is the DC load current.
• COUT is the total output capacitance.
• dVOUT/dt is the slew rate of the output voltage (programmable in the range 0.5 mV/µs to 10 mV/µs).
For correct operation, ensure that the total output current during DVS does not exceed the current limit of the
device.
9.3.7 Compensation (COMP)
The COMP pin is the connection point for an external compensation network. A series-connected resistor and
capacitor to GOSNS is sufficient for typical applications. The series-connected resistor also provides enough
scope to optimize the loop response for a wide range of operating conditions.
When using multiple devices in a stacked configuration, all devices share a common compensation network, and
the COMP pin makes sure there is equal current sharing between them (see 节9.3.17).
9.3.8 Mode Selection and Clock Synchronization (MODE/SYNC)
A high level on the MODE/SYNC pin selects forced PWM operation. A low level on the MODE/SYNC pin selects
power save operation, in which, the device automatically transitions between PWM and PFM, according to the
load conditions.
If the user applies a valid clock signal to the MODE/SYNC pin, the device synchronizes its switching cycles to
the external clock and automatically selects forced PWM operation.
The MODE/SYNC pin is logically ORed with the FPWMEN bit in the CONTROL1 register (see 表9-1).
When multiple devices are used together in a stacked configuration, the MODE/SYNC pin of the secondary
devices is the input for the clock signal (see 节9.3.17).
9.3.9 Spread Spectrum Clocking (SSC)
The device has a spread spectrum clocking function that can reduce electromagnetic interference (EMI). When
the SSC function is active, the device modulates the switching frequency to approximately ±10% the nominal
value. The frequency modulation has a triangular characteristic (see 图9-11).
Switching
Frequency
+10%
Nominal fSW
–10%
t2048/fSW
t
Time
图9-11. Spread Spectrum Clocking Behavior
To use the SSC function, make sure that:
• SSCEN = 1 in the CONTROL1 register.
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• Forced PWM operation is selected (MODE pin is high or FPWMEN = 1 in the CONTROL1 register).
• The device is not synchronized to an external clock.
To disable the SSC function, ensure that SCCEN = 0 in the CONTROL1 register.
To use the SSC function with multiple devices in a stacked configuration, ensure that the primary converter runs
from its internal oscillator and synchronize all secondary converters to the primary clock (see 图9-14).
9.3.10 Output Discharge
The device has an output discharge function that ensures a defined ramp down of the output voltage when the
device is disabled and keeps the output voltage close to 0 V while the device is off. The output discharge
function is enabled when DISCHEN = 1 in the CONTROL1 register. The output discharge function is enabled by
default.
If enabled, the device discharges the output under the following conditions:
• A low level is applied to the EN pin.
• SWEN = 0 in the CONTROL1 register.
• A thermal shutdown event occurs.
• A UVLO event occurs.
• An OVLO event occurs.
The output discharge function is not available until the user has enabled the device at least once after power up.
During power down, the device continues to discharge the output for as long as the internal supply voltage is
greater than approximately 1.8 V.
9.3.11 Undervoltage Lockout (UVLO)
The device has an undervoltage lockout function that disables the device if the supply voltage is too low for
correct operation. The negative-going threshold of the UVLO function is 2.5 V (typical). If the supply voltage
decreases below this value, the device stops switching and, if DISCHEN = 1 in the CONTROL1 register, turns on
the output discharge.
9.3.12 Overvoltage Lockout (OVLO)
The device has an overvoltage lockout function that disables the DC/DC converter if the supply voltage is too
high for correct operation. The positive-going threshold of the OVLO function is 6.3 V (typical). If the supply
voltage increases above this value, the device stops switching and, if DISCHEN = 1 in the CONTROL1 register,
turns on the output discharge.
The device automatically starts switching again – it begins a new soft-start sequence – when the supply
voltage falls below 6.2 V (typical).
9.3.13 Overcurrent Protection
9.3.13.1 Cycle-by-Cycle Current Limiting
If the peak inductor current increases above the high-side current limit threshold, the device turns off the high-
side switch and turns on the low-side switch to ramp down the inductor current. The device only turns on the
high-side switch again if the inductor current has decreased below the low-side current limit threshold.
Note that because of the propagation delay of the current limit comparator, the current limit threshold in practice
can be greater than the DC value specified in the Electrical Characteristics. The current limit in practice is given
by:
(3)
where:
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• IL is the inductor current.
• ILIMH is the high-side current limit threshold measured at DC.
• VIN is the input voltage.
• VOUT is the output voltage.
• L is the effective inductance at the peak current level.
• tpd is the propagation delay of the current limit comparator (typically 50 ns).
9.3.13.2 Hiccup Mode
To enable hiccup operation, ensure that HICCUPEN = 1 in the CONTROL1 register.
If hiccup operation is enabled and the high-side switch current exceeds the current limit threshold on 32
consecutive switching cycles, the device:
• Stops switching for 128 clock cycles, after which it automatically starts switching again (it starts a new soft-
start sequence)
• Sets the HICCUP bit in the STATUS register
• Pulls the PG pin low. The PG pin stays low until the overload condition goes away and the device can start up
correctly and regulate the output voltage. Note that power-good function has a deglitch circuit, which delays
the rising edge of the power-good signal by 40 µs (typical).
Hiccup operation continues in a repeating sequence of 32 cycles in current limit, followed by a pause of 128
cycles, followed by a soft-start attempt for as long as the output overload condition exists.
The device clears the HICCUP bit if the user reads the STATUS register when the overload condition has been
removed.
9.3.13.3 Current Limit Mode
To enable current limit mode, ensure that HICCUPEN = 0 in the CONTROL1 register.
When current limit operation is enabled, the device limits the high-side switch current cycle-by-cycle for as long
as the overload condition exists. If the device limits the high-side switch current for four or more consecutive
switching cycles, the device sets ILIM = 1 in the STATUS register.
The device clears the ILIM bit if the user reads the STATUS register when the overload condition no longer exits.
9.3.14 Power Good (PG)
The power good (PG) pin is bidirectional and has two functions:
• In a standalone configuration and in the primary device of a stacked configuration, the PG pin is an open-
drain output that indicates the status of the converter or stack.
• In a secondary device of a stacked configuration, the PG pin is an input that indicates when the soft-start
sequence is complete and all converters in the stack can change from DCM switching to CCM switching.
9.3.14.1 Standalone or Primary Device Behavior
The primary purpose of the PG pin is to indicate if the output voltage is in regulation, but it also indicates if the
device is in thermal shutdown or disabled. 表 9-7 summarizes the behavior of the PG pin in a standalone or
primary device.
表9-7. Power-Good Function Table
VIN
EN
X
VOUT
Soft Start
PGBLNKDVS
TJ
X
PG
Undefined
Low
2 V > VIN
X
X
X
X
X
X
X
X
V
IT(UVLO) ≥VIN ≥2 V
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表9-7. Power-Good Function Table (continued)
VIN
EN
VOUT
Soft Start
PGBLNKDVS
TJ
X
PG
Low
Low
low
L
X
X
X
X
0
X
Active
X
VOUT > VT(PGOV)
or
X
VIN > VIT(UVLO)
1
H
Inactive
X
TJ < TSD
Hi-Z
< VT(PGUV) > VOUT
(and DVS is active)
VT(PGOV) > VOUT > VT(PGUV)
X
X
X
TJ < TSD
TJ > TSD
Hi-Z
Low
图 9-12 shows a functional block diagram of the power-good function in a standalone or primary device. A
window comparator monitors the output voltage, and the output of the comparator goes high if the output voltage
is either less than 95% (typical) or greater than 105% (typical) of the nominal output voltage. The output of the
window comparator is deglitched – the typical deglitch time is 40 µs – and then used to drive the open-drain
PG pin.
CONTROL1:HICCUPEN
To converter
control logic
Hiccup
Control
HICCUP
ILIM
STATUS
Register
4 Consecutive
Pulses
Detection
Current
I(SW)
Comparator
PBOV
PBUV
Soft-Start Complete
PG
40-µs
Deglitch
Window
Comparator
VOUT
Blanking
Thermal Shutdown
95% VOUT
105% VOUT
VIN < VIT–(UVLO)
V(EN) < VIT(EN)
DVS Active
CONTROL3:PGBLNKDVS
图9-12. Power-Good Functional Block Diagram (Standalone or Primary Device)
During DVS activity, when the DC/DC converter transitions from one output voltage setting to another, the output
voltage can temporarily exceed the limits of the window comparator and pull the PG pin low. The device has a
feature to disable this behavior. If PGBLNKDVS = 1 in the CONTROL3 register, the device ignores the output of
the power-good window comparator while DVS is active.
Note that the PG pin is always low, regardless of the output of the window comparator, when:
• The device is in thermal shutdown.
• The device is disabled.
• The device is in undervoltage lockout.
• The device is in soft start.
9.3.14.2 Secondary Device Behavior
图 9-13 shows a functional block diagram of the power-good function in a secondary device. During initialization,
the device presets FF1 and FF2, which pulls down the PG pin and forces the device to operate in DCM. When
the device completes its soft start, it resets FF2, which turns off Q1. However, in a stacked configuration, all
devices share the same PG signal, and therefore the PG pin stays low until all devices in the stack have
completed their soft start. When that happens, FF1 is reset and the converters operate in CCM.
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FF1
Input
Buffer
FORCE DCM
Latch
PG
VIL = < 0.4 V
VIH = > 0.8 V
SECONDARY DEVICE
DETECTED
Q1
SOFT START
COMPLETE
Latch
FF2
图9-13. Power-Good Functional Block Diagram (Secondary Device)
9.3.15 Remote Sense
The device has two pins, VOSNS and GOSNS, to remotely sense the output voltage. Remote sensing lets the
converter sense the output voltage directly at the point-of-load and increases the accuracy of the output voltage
regulation.
9.3.16 Thermal Warning and Shutdown
The device has a two-level overtemperature detection function.
If the junction temperature rises above the thermal warning threshold of 150°C (typical), the device sets the
TWARN bit in the STATUS register. The device clears the TWARN bit if the user reads the STATUS register
when the junction temperature is below the TWARN threshold of 130°C (typical).
If the junction temperature rises above the thermal shutdown threshold of 170°C (typical), the device:
• Stops switching
• Pulls down the EN pin (if SINGLE = 0 in the CONTROL3 register)
• Enables the output discharge (if DISCHEN = 1 in the CONTROL1 register)
• Sets the TSHUT bit in the STATUS register
• Pulls the PG pin low
If the junction temperature falls below the thermal shutdown threshold of 150°C (typical), the device:
• Starts switching again, starting with a new soft-start sequence
• Sets the EN pin to high impedance
• Sets the PG pin to high-impedance
The device clears the TSHUT bit if the user reads the STATUS register when the junction temperature is below
the TSHUT threshold of 150°C (typical).
In a stacked configuration, in which all devices share a common enable signal, a thermal shutdown condition in
one device disables the entire stack. When the hot device cools down, the whole stack automatically starts
switching again.
9.3.17 Stacked Operation
The user can connect multiple devices in parallel in what is known as a "stack"; for example, to increase output
current capability or reduce device junction temperature. A stack comprises one primary device and one or more
secondary devices. During initialization, each device monitors its SYNC_OUT pin to determine if must operate
as a primary device or a secondary device:
• If there is a 47-kΩresistor between the SYNC_OUT pin and ground, the device operates as a secondary
device.
• If the SYNC_OUT pin is high impedance, the device operates as a primary device.
图9-14 shows the recommended interconnections in a stack of two TPS6287x-Q1 devices.
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Primary Device
CLOAD
100 nH
VIN
2.7 V to 6 V
VIN
VIN
SW
COUT
CIN
VIO
REN
MODE/SYNC
Load
EN
VOSNS
GOSNS
SDA
SCL
I2C
RCOMP
VSEL
FSEL
10 pF
CCOMP
RVSEL RFSEL
COMP
PG
SYNC_OUT GND
GND
Secondary Device
100 nH
VIN
VIN
SW
COUT
CIN
MODE/SYNC
EN
VOSNS
GOSNS
SDA
SCL
VSEL
VIO
10 pF
FSEL
RFSEL
RPG
COMP
PG
1 k
PG
SYNC_OUT GND
GND
10 pF
47 k
图9-14. Two TPS6287x-Q1 Devices in a Stacked Configuration
The key points to note are:
• All the devices in the stack share a common enable signal, which must be pulled up with a resistance of at
least 15 kΩ.
• All the devices in the stack share a common power-good signal.
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• All the devices in the stack share a common compensation signal.
• All secondary devices must connect a 47-kΩresistor between the SYNC_OUT pin and ground.
• The remote sense pins (VOSNS and GOSNS) of each device must be connected (do not leave these pins
floating).
• Each device must be configured for the same switching frequency.
• The primary device must be configured for forced PWM operation (secondary devices are automatically
configured for forced PWM operation).
• A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.
• Only the VSEL pin of the primary device is used to set the default output voltage. The VSEL pin of secondary
devices is not used and must be connected to ground.
• The SDA and SCL pins of secondary devices are not used and must be connected to ground.
• A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase
offset of approximately 140° relative to the adjacent devices in the daisy-chain. To daisy-chain the clocking
signal, connect the SYNC_OUT pin of the primary device to the MODE/SYNC pin of the first secondary
device. Connect the SYNC_OUT pin of the first secondary device to the MODE/SYNC pin of the second
secondary device. Continue this connection scheme for all devices in the stack, to daisy-chain them together.
• Hiccup overcurrent protection must not be used in a stacked configuration.
In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see 节 9.3.3).
Each device in the stack can pull its EN pin low during device start-up or when a fault occurs. Thus, the stack is
only enabled when all devices have completed their start-up sequence and are fault-free. A fault in any one
device disables the whole stack for as long as the fault condition exists.
During start-up, the primary converter pulls the COMP pin low for as long as the enable signal
(SYSTEM_READY) is low. When the enable signal goes high, the primary device actively controls the COMP pin
and all converters in the stack follow the COMP voltage. During start-up, each device in the stack pulls its PG pin
low while it initializes. When initialization is complete, each secondary device in the stack sets its PG pin to a
high impedance and the primary device alone controls the state of the PG signal. The PG pin goes high when
the stack has completed its start-up ramp and the output voltage is within specification. The secondary
converters in the stack detect the rising edge of the power-good signal and switch from DCM operation to CCM
operation. After the stack has successfully started up, the primary device controls the power-good signal in the
normal way. In a stacked configuration, there are some faults that only affect individual devices, and other faults
that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal
shutdown or undervoltage lockout event in one device disables all devices through the shared enable
(SYSTEM_READY) signal.
Functionality During Stacked Operation
Some device features are not available during stacked operation, or are only available in the primary converter.
表9-8 summarizes the available functionality during stacked operation.
表9-8. Functionality During Stacked Operation
Function
UVLO
Primary Device
Secondary Device
Remark
Yes
Yes
Yes
Yes
Yes
Yes
Common enable signal
Common enable signal
Individual
OVLO
OCP –Current Limit
Do not use during stacked
operation.
No
Yes
No
Yes
No
No
No
OCP –Hiccup OCP
Thermal Shutdown
Common enable signal
Primary device only
Primary device only
Power-Good (Window
Comparator)
Yes
I2C Interface
Yes
Voltage loop controlled by primary
device only
DVS
Through I2C
Daisy-chained from primary device
to secondary devices
SSC
Through I2C
No
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表9-8. Functionality During Stacked Operation (continued)
Function
SYNC
Primary Device
Secondary Device
Remark
Synchronization clock applied to
primary device
Yes
No
Yes
No
Precise Enable
Output Discharge
Only binary enable
Always enabled in secondary
devices
Yes
Yes
Fault Handling During Stacked Operation
In a stacked configuration, there are some faults that only affect individual devices and other faults that affect all
devices. For example, if one device enters current limit, only that device is affected. A thermal shutdown or
undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY)
signal. 表9-9 summarizes the fault handling of the TPS6287x-Q1 devices during stacked operation.
表9-9. Fault Handling During Stacked Operation
Fault Condition
UVLO
Device Response
Enable signal pulled low
Enable signal remains high
System Response
New soft start
OVLO
Thermal shutdown
Current limit
Error amplifier clamped
9.4 Device Functional Modes
9.4.1 Power-On Reset
The device operates in POR mode when the supply voltage is less than the POR threshold, 1.4 V (typical).
In POR mode, no functions are available and the content of the device registers is not valid.
The device leaves POR mode and enters UVLO mode when the supply voltage increases above the POR
threshold.
9.4.2 Undervoltage Lockout
The device operates in UVLO mode when the supply voltage is between the POR and UVLO thresholds.
If the device enters UVLO mode from POR mode, no functions are available. If the device enters UVLO mode
from standby mode, the output discharge function is available. The content of the device registers is valid in
UVLO mode.
The device leaves UVLO mode and enters POR mode when the supply voltage decreases below the POR
threshold. The device leaves UVLO mode and enters standby mode when the supply voltage increases above
the UVLO threshold.
9.4.3 Standby
The device operates in standby mode when the supply voltage is greater than the UVLO threshold (and the
device has completed its initialization) and any of the following conditions is true:
• A low level is applied to the EN pin.
• SWEN = 0 in the CONTROL1 register.
• The device junction temperature is greater than the thermal shutdown threshold.
• The supply voltage is greater than the OVLO threshold.
The device initializes for 400 µs (typical) after the supply voltage increases above the UVLO threshold voltage
following a device power-on reset. If the supply voltage decreases below the UVLO threshold but not below the
POR threshold, the device does not reinitialize when the supply voltage increases again. During initialization, the
device reads the state of the FSEL, VSEL, and SYNC_OUT pins.
The following functions are available in standby mode:
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• I2C interface
• Output discharge
• Power good
The device leaves standby mode and enters UVLO mode when the supply voltage decreases below the UVLO
threshold. The device leaves standby mode and enters on mode when all of the following conditions are true:
• A high-level is applied to the EN pin.
• SWEN = 1 in the CONTROL1 register.
• The device junction temperature is below the thermal shutdown threshold.
• The supply voltage is below the OVLO threshold.
9.4.4 On
The device operates in on mode when the supply voltage is greater than the UVLO threshold and all of the
following conditions are true:
• A high-level is applied to the EN pin.
• SWEN = 1 in the CONTROL1 register.
• The device junction temperature is below the thermal shutdown threshold.
• The supply voltage is below the OVLO threshold.
All functions are available in on mode.
The device leaves on mode and enters UVLO mode when the supply voltage decreases below the UVLO
threshold. The device leaves on mode and enters standby mode when any of the following conditions is true:
• A low level is applied to the EN pin.
• SWEN = 0 in the CONTROL1 register.
• The device junction temperature is greater than the thermal shutdown threshold.
• The supply voltage is greater than the OVLO threshold.
9.5 Programming
9.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification and User Manual, Revision 6, 4 April 2014). The bus consists of a data line (SDA) and a clock line
(SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All I2C-compatible
devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A controller, usually a microcontroller
or a digital signal processor, controls the bus. The controller is responsible for generating the SCL signal and
device addresses. The controller also generates specific conditions that indicate the START and STOP of data
transfer. A target receives data, transmits data, or both on the bus under control of the controller.
The TPS6287x-Q1 device operates as a target and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The
interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values
depending on the instantaneous application requirements. Register contents remain intact as long as the input
voltage remains above 1.4 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The device supports 7-bit addressing; general call addresses are not supported.
The state of the VSEL pin during power up defines the I2C target address of the device (see 表 9-10). Note that
the VSEL pin also sets the default start-up voltage of the device (see 表9-4).
表9-10. I2C Interface Target Address Selection
VSEL Pin
I2C Target Address (1)
0x40 or 0x30
6.2 kΩto GND
Short Circuit to GND
Short Circuit to VIN
0x41 or 0x31
0x42 or 0x32
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表9-10. I2C Interface Target Address Selection (continued)
VSEL Pin
I2C Target Address (1)
0x43 or 0x33
47 kΩto VIN
(1) Available I2C address. Refer to the 节6
TI recommends that the I2C controller initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pullup voltages to ensure reset of the I2C engine.
9.5.2 Standard, Fast, Fast Mode Plus Protocol
The controller initiates a data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 9-15. All I2C-compatible devices must
recognize a start condition.
DATA
CLK
S
P
START
STOP
Condition
Condition
图9-15. START and STOP Conditions
The controller then generates the SCL pulses, and transmits the 7-bit address and the read and write direction
bit R/W on the SDA line. During all transmissions, the controller makes sure that data is valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse (see 图 9-16). All
devices recognize the address sent by the controller and compare the address to their internal fixed addresses.
Only the target with a matching address generates an acknowledge (see 图 9-17) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows that
a communication link with a target has been established.
DATA
CLK
Data line stable;
data valid
Change of
data allowed
图9-16. Bit Transfer on the Serial Interface
The controller generates further SCL cycles to either transmit data to the target (R/W bit 0) or receive data from
the target (R/W bit 1). In either case, the target must acknowledge the data sent by the controller. So an
acknowledge signal can either be generated by the controller or by the target, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see 图 9-15). This stop condition releases the bus and stops the
communication link with the addressed target. All I2C-compatible devices must recognize the stop condition.
Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition
followed by a matching address.
Attempting to read data from register addresses not listed in this section will result in 0x00 being read out.
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Data Output by
Transmitter
Not Acknowledge
Acknowledge
Data Output
by Receiver
SCL from
Controller
1
2
8
9
S
START
Clock pulse for
Condition
acknowledgment
图9-17. Acknowledge on the I2C Bus
Recognize START or
REPEATED START
condition
Recognize STOP or
REPEATED START
condition
Generate ACKNOWLEDGE
signal
P
SDA
SCL
MSB
acknowledgement
signal from Target
acknowledgement
signal from receiver
Sr
1
2
7
8
9
1
2
3 to 8
9
S or Sr
Sr or P
ACK
ACK
START or
repeated START
condition
byte complete,
interrupt within target
clock line held low while
interrupts are serviced
STOP or
repeated START
condition
图9-18. Bus Protocol
9.5.3 I2C Update Sequence
The following are required for a single update:
• A start condition
• A valid I2C address
• A register address byte
• A data byte
After the receipt of each byte, the receiving device acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the target. The target performs an update on the falling
edge of the acknowledge signal that follows the LSB byte.
1
7
1
1
8
1
8
1
1
S
Target Address
R/W
A
Register Address
A
Data
A/A
P
"0" Write
From Controller to Target
From Target to Controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
图9-19. “Write”Data Transfer Format in Standard, Fast, Fast Plus Modes
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1
7
1
1
8
1
1
8
1
1
8
1
1
S
Target Address
R/W
A
Register Address
A
Sr
Target Address
R/W
A
Data
A/A
P
"0" Write
"1" Read
From Controller to Target
From Target to Controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
图9-20. “Read”Data Transfer Format in Standard, Fast, Fast Plus Modes
9.5.4 I2C Register Reset
The I2C registers can be reset by:
• Pulling the input voltage below 1.4 V (typical).
• Setting the RESET bit in the CONTROL register. When RESET = 1, all registers are reset to their default
values and a new start-up begins immediately. After td(EN), you can program the I2C registers again.
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9.6 Register Map
表 9-11 lists the device registers. Consider all register offset addresses not listed in 表 9-11 as reserved
locations. Do not modify the register contents.
表9-11. Device Registers
Address
Acronym
VSET
Register Name
Output Voltage Setpoint
Control 1
Section
Go
0h
1h
2h
3h
4h
CONTROL1
CONTROL2
CONTROL3
STATUS
Go
Control 2
Go
Control 3
Go
Status
Go
Complex bit access types are encoded to fit into small table cells. 表 9-12 shows the codes that are used for
access types in this section.
表9-12. Device Access Type Codes
Access Type
Code
R
Description
Read Type
R
Read
Write Type
W
W
Write
Reset or Default Value
- n
Value after reset or the default value
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9.6.1 VSET Register (Address = 0h) [Reset = X]
VSET is shown in 图9-21 and described in 表9-13.
Return to the Summary Table.
This register controls the output voltage setpoint.
图9-21. VSET Register
7
6
5
4
3
2
1
0
VSET
R/W-X
表9-13. VSET Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
VSET
R/W
X
Output voltage setpoint (see the range-setting bits in the CONTROL2
register.)
Range 1: Output voltage setpoint = 0.4 V + VSET[7:0] × 1.25 mV
Range 2: Output voltage setpoint = 0.4 V + VSET[7:0] × 2.5 mV
Range 3: Output voltage setpoint = 0.4 V + VSET[7:0] × 5 mV
Range 4: Output voltage setpoint = 0.8 V + VSET[7:0] × 10 mV
The state of the VSEL pin during power up determines the reset
value.
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9.6.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah]
CONTROL1 is shown in 图9-22 and described in 表9-14.
Return to the Summary Table.
This register controls various device configuration options.
图9-22. CONTROL1 Register
7
6
5
4
3
2
1
0
RESET
R/W-0b
SSCEN
R/W-0b
SWEN
R/W-1b
FPWMEN
R/W-0b
DISCHEN
R/W-1b
HICCUPEN
R/W-0b
VRAMP
R/W-10b
表9-14. CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0b
Reset device
0b = No effect
1b = Resets all registers to their default values
Reading this bit always returns 0.
6
5
4
SSCEN
SWEN
R/W
R/W
R/W
0b
1b
0b
Spread spectrum clocking enable
0b = SSC operation disabled
1b = SSC operation enabled
Software enable
0b = Switching disabled (register values retained)
1b = Switching enabled (without the enable delay)
FPWMEN
Forced PWM enable
0b = Power-save operation enabled
1b = Forced-PWM operation enabled
This bit is logically ORed with the MODE/SYNC pin. If a high level or
a synchronization clock is applied to the MODE/SYNC pin, the
device operates in forced-PWM, regardless of the state of this bit.
3
2
DISCHEN
R/W
R/W
1b
0b
Output discharge enable
0b = Output discharge disabled
1b = Output discharge enabled
HICCUPEN
Hiccup operation enable
0b = Hiccup operation disabled
1b = Hiccup operation enabled. Do not enable hiccup operation
during stacked operation.
1-0
VRAMP
R/W
10b
Output voltage ramp speed when changing from one output voltage
setting to another
00b = 10 mV/µs
01b = 5 mV/µs
10b = 1.25 mV/µs
11b = 0.5 mV/µs
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9.6.3 CONTROL2 Register (Address = 2h) [Reset = 9h]
CONTROL2 is shown in 图9-23 and described in 表9-15.
Return to the Summary Table.
This register controls various device configuration options.
图9-23. CONTROL2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
VRANGE
R/W-10b
SSTIME
R/W-01b
表9-15. CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000b
Reserved for future use. For compatibility with future device variants,
program these bits to 0.
3-2
VRANGE
R/W
R/W
10b
01b
Output voltage range
00b = 0.4 V to 0.71875 V in 1.25-mV steps
01b = 0.4 V to 1.0375 V in 2.5-mV steps
10b = 0.4 V to 1.675 V in 5-mV steps
11b = 0.8 V to 3.35 V in 10-mV steps
1-0
SSTIME
Soft-start ramp time
00b = 0.5 ms
01b = 1 ms
10b = 2 ms
11b = 4 ms
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9.6.4 CONTROL3 Register (Address = 3h) [Reset = 0h]
CONTROL3 is shown in 图9-24 and described in 表9-16.
Return to the Summary Table.
This register controls various device configuration options.
图9-24. CONTROL3 Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
SINGLE
R/W-0b
PGBLNKDVS
R/W-0b
表9-16. CONTROL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000b
Reserved for future use. For compatibility with future device variants,
program these bits to 0.
1
SINGLE
R/W
R/W
0b
0b
Single operation. This bit controls the internal EN pulldown and
SYNCOUT functions.
0b = EN pin pulldown and SYNCOUT enabled
1b = EN pin pulldown and SYNCOUT disabled. Do not use during
stacked operation.
0
PGBLNKDVS
Power-good blanking during DVS
0b = PG pin reflects the output of the window comparator.
1b = PG pin is high impedance during DVS.
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9.6.5 STATUS Register (Address = 4h) [Reset = 2h]
STATUS is shown in 图9-25 and described in 表9-17.
Return to the Summary Table.
This register returns the device status flags.
图9-25. STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
HICCUP
R-0b
ILIM
R-0b
TWARN
R-0b
TSHUT
R-0b
PBUV
R-1b
PBOV
R-0b
表9-17. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
00b
Reserved for future use. For compatibility with future device variants,
ignore these bits.
5
HICCUP
R
R
R
R
R
0b
0b
0b
0b
1b
Hiccup. This bit reports whether a hiccup event occurred since the
last time the STATUS register was read.
0b = No hiccup event occurred
1b = A hiccup event occurred
4
3
2
1
ILIM
Current limit. This bit reports whether an current limit event occurred
since the last time the STATUS register was read.
0b = No current limit event occurred
1b = An current limit event occurred
TWARN
TSHUT
PBUV
Thermal warning. This bit reports whether a thermal warning event
occurred since the last time the STATUS register was read.
0b = No thermal warning event occurred
1b = A thermal warning event occurred
Thermal shutdown. This bit reports whether a thermal shutdown
event occurred since the last time the STATUS register was read.
0b = No thermal shutdown event occurred
1b = A thermal shutdown event occurred
Power-bad undervoltage. This bit reports whether a power-bad event
(output voltage too low) occurred since the last time the STATUS
register was read.
0b = No power-bad undervoltage event occurred
1b = A power-bad undervoltage event occurred
0
PBOV
R
0b
Power-bad overvoltage. This bit reports whether a power-bad event
(output voltage too high) occurred since the last time the STATUS
register was read.
0b = No power-bad overvoltage event occurred
1b = A power-bad overvoltage event occurred
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The following section discusses selection of the external components to complete the power supply design for
typical a application.
10.2 Typical Application
110 nH ±20%
0.75 V
VIN
3.3 V
VIN
VIN
SW
COUT
CIN
VIO
20 k
MODE/SYNC
Load
EN
VOSNS
GOSNS
SDA
SCL
I2C
RZ
VSEL
FSEL
3.3 V
CC2
6.2 k
CC
10 k
1 k
COMP
PG
PG
SYNC_OUT GND
GND
10 pF
图10-1. Typical Application Schematic
10.2.1 Design Requirements
表10-1 lists the operating parameters for this application example.
表10-1. Design Parameters
Symbol
Parameter
Value
3.3 V
VIN
Input voltage
VOUT
TOLVOUT
TOLDC
ΔIOUT
tt
Output voltage
0.75 V
±3.3%
±1%
Output voltage tolerance allowed by the application
Output voltage tolerance of the TPS6287x-Q1 (DC accuracy)
Output current load step
±7.5 A
Load step transition time
1 μs
2.25 MHz
110 nH
±20%
fSW
Switching frequency
L
Inductance
TOLIND
gm
Inductor tolerance
Error amplifier transconductance
Internal timing parameter
1.5 mS
12.5 μs
±30%
τ
TOLτ
Tolerance of the internal timing parameter
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表10-1. Design Parameters (continued)
Symbol
Parameter
Ratio of switching frequency to converter bandwidth (must be ≥4)
Number of phases
Value
kBW
4
1
Nɸ
Preliminary Calculations
The maximum allowable deviation of the power supply is ±3.3%. The DC accuracy of the TPS6287x-Q1 is
specified as ±1%, therefore, the maximum output voltage variation during a transient is given by:
∆ V
= ± V
× 3.3% – 1% = ± 17.25 mV
OUT
(4)
OUT
10.2.2 Detailed Design Procedure
The following subsections describe how to calculate the external components required to meet the specified
transient requirements of a given application. The calculations include the worst-case variation of components
and use the RMS method to combine the variation of uncorrelated parameters.
10.2.2.1 Selecting the Inductor
The TPS6287x-Q1 devices have been optimized for inductors in the range 50 nH to 300 nH. If the transient
response of the converter is limited by the slew rate of the current in the inductor, using a smaller inductor can
improve performance. However, the output ripple current increases as the value of the inductor decreases, and
higher output current ripple generates higher output voltage ripple, which adds to the transient overshoot or
undershoot. The optimal configuration for a given application is always a trade-off between a number of
parameters. TI recommends a starting value of 110 nH for typical applications.
The peak-to-peak inductor current ripple is given by:
V
V
– V
OUT
IN
OUT
sw
I
=
=
(5)
(6)
L PP
L PP
V
Nɸ × L × f
IN
0.75
3.3
3.3 – 0.75
I
= 2.342 A
6
–9
1 × 110 × 10 × 2.25 × 10
表 10-2 lists a number of inductors suitable for use with this application. This list is not exhaustive and other
inductors from other manufacturers can also be suitable.
表10-2. List of Recommended Inductors
Current Rating
(ISAT at 25°C)
24 A
Dimensions
Inductance
DC Resistance
Part Number(1)
(L × W × H)
92 nH
100 nH
110 nH
110 nH
55 nH
4 × 4 × 1.2 mm
Coilcraft, XEL4012-920NE
Coilcraft, XEL4030-101ME
Coilcraft, XGL4020-111ME
TDK, CLT32-R11
5.2 mΩ(typical)
1.5 mΩ(typical)
1.4 mΩ(typical)
1.9 mΩ(typical)
1.0 mΩ(typical)
3.0 mΩ(typical)
1.9 mΩ(typical)
0.8 mΩ(typical)
30 A
4 × 4 × 3.2 mm
29 A
4 × 4 × 2.1 mm
29 A
3.2 × 2.5 × 2.5 mm
3.2 × 2.5 × 2.5 mm
3.2 × 2.5 × 2.5 mm
4.2 × 4.0 × 2.1 mm
5.45 × 5.25 × 2.8 mm
39.5 A
17.0 A
25 A
TDK, CLT32-55N
110 nH
100 nH
100 nH
Cyntec, VCTA32252E-R11MS6
Cyntec, VCHA042A-R10MS62M
Cyntec, VCHW053T-R10NMS5
44 A
(1) See the Third-Party Products Disclaimer.
10.2.2.2 Selecting the Input Capacitors
As with all buck converters, the input current of the TPS6287x-Q1 devices is discontinuous. The input capacitors
provide a low-impedance energy source for the device, and their value, type, and location are critical for correct
operation. TI recommends low-ESR multilayer ceramic capacitors for best performance. In practice, the total
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input capacitance is typically comprised of a combination of different capacitors, in which larger capacitors
provide the decoupling at lower frequencies and smaller capacitors provide the decoupling at higher frequencies.
The TPS6287x-Q1 devices feature a butterfly layout with two pairs of VIN and GND pins on opposite sides of the
package. This allows the input capacitors to be placed symmetrically on the PCB so that the electromagnetic
fields generated cancel each other out, thereby reducing EMI.
The duty cycle of the converter is given by:
V
OUT
D =
(7)
η × V
IN
where
• VIN is the input voltage.
• VOUT is the output voltage.
• ηis the efficiency.
0.75
0.9 × 3.3
D =
= 0.253
(8)
(9)
The value of input capacitance needed to meet the input voltage ripple requirements is given by:
D × 1 − D × I
OUT
C
=
IN
V
× f
IN PP
sw
where
• D is the duty cycle.
• fsw is the switching frequency.
• L is the inductance.
• IOUT is the output current.
100mV is used as the input voltage ripple target.
0.253 × 1 − 0.253 × 11.3
C
=
= 9.5 μF
(10)
IN
6
0.1 × 2.25 × 10
The value of CIN calculated with 方程式 9 is the effective capacitance after all derating, tolerance, and aging
effects have been considered. 5 µF effective capacitance per input pin is required. TI recommends multilayer
ceramic capacitors with an X7R dielectric (or similar) for CIN, and these capacitors must be placed as close to
the VIN and GND pins as possible to minimize the loop area.
表10-3 lists a number of capacitors suitable for this application. This list is not exhaustive and other capacitors
from other manufacturers can also be suitable.
表10-3. List of Recommended Input Capacitors
Dimensions
Capacitance
Voltage Rating
Manufacturer, Part Number(1)
mm (Inch)
1005 (0402)
1005 (0402)
2012 (0805)
470 nF ±10%
470 nF ±10%
10 μF ±10%
10 μF ±10%
22 μF ±10%
22 μF ±20%
10 V
10 V
10 V
Murata, GCM155C71A474KE36D
TDK, CGA2B3X7S1A474K050BB
Murata, GCM21BR71A106KE22L
2012 (0805)
3216 (1206)
3216 (1206)
10 V
10 V
10 V
TDK, CGA4J3X7S1A106K125AB
Murata, GCM31CR71A226KE02L
TDK, CGA5L1X7S1A226M160AC
(1) See the Third-Party Products Disclaimer.
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10.2.2.3 Selecting the Compensation Resistor
Use 方程式11 to calculate the recommended value of compensation resistor, RZ:
I
L PP
2
L
Nɸ
π × ∆ I
OUT
+
×
1
2
2
R =
– 1 1 + TOL
+ TOL
τ
(11)
(12)
Z
IND
g
4 × τ × ∆ V
m
OUT
–9
1
2.342
2
–6
110 × 10
π × 7.5 +
×
1
2
2
R =
– 1 1 + 20% + 30% = 2.244 kΩ
–3
Z
–3
1.5 × 10
4 × 12.5 × 10 × 17.25 × 10
Rounding up, the closest standard value from the E24 series is 2.4 kΩ.
10.2.2.4 Selecting the Output Capacitors
In practice, the total output capacitance is typically comprised of a combination of different capacitors, in which
larger capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at
higher frequencies. The value, type, and location of the output capacitors are critical for correct operation. TI
recommends low-ESR multilayer ceramic capacitors with an X7R dielectric (or similar) for best performance.
The TPS6287x-Q1 devices feature a butterfly layout with two GND pins on opposite sides of the package. This
allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields
generated cancel each other out, thereby reducing EMI.
The transient response of the converter is limited by one of two criteria:
• The slew rate of the current through the inductor, in which case, the feedback loop of the converter saturates.
• The maximum allowed ratio of converter bandwidth to switching frequency, in which the converter remains in
regulation (that is, its loop does not saturate). TI recommends a minimum ratio of four for typical applications.
Which of the above criteria applies in any given application depends on the operating conditions and component
values used. Therefore, TI recommends that the user calculate the output capacitance for both cases, and select
the higher of the two values.
If the converter remains in regulation, the minimum output required capacitance is given by:
τ × 1 + g × R
m
Z
2
2
2
C
=
=
1 + TOL + TOL
+ TOL
(13)
(14)
OUT min reg
OUT min reg
τ
IND
fSW
f
L
SW
4
2 × π ×
×
Nɸ
–6
–3
1 + 1.5 × 10 × 2.4 × 10
3
12.5 × 10
×
2
2
2
C
1 + 30% + 20% + 10% = 203.2 μF
–9
6
110 × 10
1
2.25 × 10
4
–9
× 10
2 × π ×
×
If the converter loop saturates, the minimum output capacitance is given by:
2
I
L PP
2
L
Nɸ
×
∆ I +
OUT
∆ I
× t
t
1
OUT
2
C
=
=
–
1 + TOL
(15)
(16)
OUT min sat
OUT min sat
IND
∆ V
2 × V
OUT
OUT
–9
2
110 × 10
1
2.342
2
×
7.5 +
–6
1
7.5 × 1 × 10
2
C
–
1 + 20% = 122.7 μF
–3
2 × 0.75
17.25 × 10
In this case, choose COUT(min) = 203 µF as the larger of the two values for the output capacitance.
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When calculating worst-case component values, use the value calculated above as the minimum output
capacitance required. For ceramic capacitors, the maximum capacitance when considering tolerance, DC bias,
temperature, and aging effects is typically two times the minimum capacitance. In this case, the maximum
capacitance COUT(max) is 406 μF.
表10-4. List of Recommended Output Capacitors
Dimensions
Capacitance
Voltage Rating
Manufacturer, Part Number(1)
mm (Inch)
2012 (0805)
2012 (0805)
3216 (1206)
2012 (1210)
3225 (1210)
3216 (1210)
6.3 V
6.3 V
4 V
TDK, CGA4J1X7T0J226M125AC
Murata, GCM31CR71A226KE02
TDK, CGA5L1X7T0G476M160AC
Murata, GCM32ER70J476ME19
TDK, CGA6P1X7T0G107M250AC
Murata, GRT32EC70J107ME13
22 μF ±20%
22 μF ±10%
47 μF ±20%
47 μF ±20%
100 μF ±20%
100 μF ±20%
6.3 V
4 V
6.3 V
(1) See the Third-Party Products Disclaimer.
10.2.2.5 Selecting the Compensation Capacitor, CC
First, use 方程式17 to calculate the bandwidth of the inner loop:
τ
BW
=
(17)
INNER
L
Nɸ
2π ×
× C
OUT max
–6
12.5 × 10
BW
=
= 89 kHz
(18)
(19)
INNER
–9
110 × 10
1
–6
× 203.2 × 10
2π ×
Next, calculate the product of gmRZ:
–3
3
g
× R = 1.5 × 10 × 2.4 × 10 = 3.6
Z
m
If gmRZ > than 1, use 方程式 20 to calculate the recommended value of CC. If gmRZ < 1, use 方程式 22 to
calculate the recommended value of CC.
2
C =
(20)
(21)
C
2
π × BW
× g × R
m
INNER
Z
2
C =
= 0.828 nF
C
2
3
3
–3
π × 89 × 10 × 1.5 × 10
× 2.4 × 10
The closest standard value from the E12 series is 0.82 nF.
2 × g
m
C =
(22)
C
π × BW
INNER
10.2.2.6 Selecting the Compensation Capacitor, CC2
The compensation capacitor, CC2, is an optional capacitor that TI recommends the user include to bypass high-
frequency noise away from the COMP pin. The value of this capacitor is not critical; 10-pF or 22-pF capacitors
are suitable for typical applications.
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10.2.3 Application Curves
100
90
80
70
60
50
40
30
20
0.405
0.404
0.403
0.402
0.401
0.400
0.399
0.398
0.397
0.396
0.395
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V
VIN = 5 V
10
0
0
0
0
2
2
2
4
6
8
10
12
14 15
0
0
0
2
2
2
4
6
8
10
12
14 15
Output Current (A)
Output Current (A)
VOUT = 0.4 V
VOUT = 0.4 V
图10-3. Load Regulation
图10-2. Efficiency
100
90
80
70
60
50
40
30
20
10
0
0.505
0.504
0.503
0.502
0.501
0.500
0.499
0.498
0.497
0.496
0.495
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V
VIN = 5 V
4
6
8
10
12
14 15
4
6
8
10
12
14 15
Output Current (A)
Output Current (A)
VOUT = 0.5 V
VOUT = 0.5 V
图10-5. Load Regulation
图10-4. Efficiency
100
90
80
70
60
50
40
30
20
10
0
0.755
0.754
0.753
0.752
0.751
0.750
0.749
0.748
0.747
0.746
0.745
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V
VIN = 5 V
4
6
8
10
12
14 15
4
6
8
10
12
14 15
Output Current (A)
Output Current (A)
VOUT = 0.75 V
VOUT = 0.75 V
图10-7. Load Regulation
图10-6. Efficiency
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10.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
0.880
0.879
0.878
0.877
0.876
0.875
0.874
0.873
0.872
VIN = 3.3 V
VIN = 5 V
0.871
0.870
VIN = 3.3 V
VIN = 5 V
0
2
4
6
8
10
12
14 15
0
2
4
6
8
10
12
14 15
Output Current (A)
Output Current (A)
VOUT = 0.875 V
VOUT = 0.875 V
图10-9. Load Regulation
图10-8. Efficiency
100
90
80
70
60
50
40
30
20
10
0
1.055
1.054
1.053
1.052
1.051
1.050
1.049
1.048
1.047
1.046
1.045
VIN = 3.3 V
VIN = 5 V
VIN = 3.3 V
VIN = 5 V
0
2
4
6
8
10
12
14 15
0
2
4
6
8
10
12
14 15
Output Current (A)
Output Current (A)
VOUT = 1.05 V
VOUT = 1.05 V
图10-11. Load Regulation
图10-10. Efficiency
1.0100
1.0075
1.0050
1.0025
1.0000
0.9975
0.9950
0.9925
0.9900
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
IOUT = 10 A
图10-13. Line Transient Response
图10-12. Line Regulation
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10.2.3 Application Curves (continued)
IOUT = 2 A
图10-15. PWM-CCM Operation
CH1 = 50 mV/A
ΔIOUT = 7.5 A
图10-14. Load Transient Response
IOUT = 750 mA
IOUT = 75 mA
图10-16. PWM-DCM Operation
图10-17. PFM Operation
0
-20
SSC Off
SSC On
-40
-60
-80
-100
100k
1M
10M
Frequency(Hz)
FSEL = 2.25 MHz
f(SYNC) = 2 MHz
Load = 0.75 Ω
VOUT = 1.6 V
IOUT = 6 A
图10-19. Synchronization to an External Clock
图10-18. Spread Spectrum Operation
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10.2.3 Application Curves (continued)
Load = 0.75 Ω
Load = 7.5 Ω
图10-20. Start-Up Using the EN Pin
图10-21. Shutdown Using the EN Pin (Discharge Enabled)
Load = 7.5 Ω
图10-23. Current Limit (Hiccup)
图10-22. Shutdown (Discharge Enabled)
10.3 Best Design Practices
INCORRECT
CORRECT
TPS6287x-Q1
TPS6287x-Q1
2.7 V to 6 V
2.7 V to 6 V
VIN
15 kΩ
EN
INCORRECT
CORRECT
TPS6287x-Q1
TPS6287x-Q1
2.7 V to 6 V
2.7 V to 6 V
VIN
15 k
ENABLE
ENABLE
EN
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10.4 Power Supply Recommendations
The TPS6287x-Q1 family has no special requirements for its input power supply. The output current rating of the
input power supply must be rated according to the supply voltage and current requirements of the TPS6287x-
Q1.
10.5 Layout
10.5.1 Layout Guidelines
Achieving the performance the TPS6287x-Q1 devices are capable of requires proper PDN and PCB design. TI
therefore recommends the user perform a power integrity analysis on their design. There are a number of
commercially available power integrity software tools, and the user can use these tools to model the effects on
performance of the PCB layout and passive components.
In addition to the use of power integrity tools, TI recommends the following basic principles:
• Place the input capacitors close to the VIN and GND pins. Position the input capacitors in order of increasing
size, starting with the smallest capacitors closest to the VIN and GND pins. Use an identical layout for both
VIN-GND pin pairs of the package, to gain maximum benefit from the butterfly configuration.
• Place the inductor close to the device and keep the SW node small.
• Connect the exposed thermal pad and the GND pins of the device together. Use multiple thermal vias to
connect the exposed thermal pad of the device to one or more ground planes (TI's EVM uses nine 150-µm
thermal vias).
• Use multiple power and ground planes.
• Route the VOSNS and GOSNS remote sense lines as a differential pair and connect them to the lowest-
impedance point of the PDN. If the desired connection point is not the lowest impedance point of the PDN,
optimize the PDN until it is. Do not route the VOSNS and GOSNS close to any of the switch nodes.
• Connect the compensation components between VOSNS and GOSNS. Do not connect the compensation
components directly to power ground.
• If possible, distribute the output capacitors evenly between the TPS6287x-Q1 device and the point-of-load,
rather than placing them altogether in one place.
• Use multiple vias to connect each capacitor pad to the power and ground planes (TI's EVM typically uses four
vias per pad).
• Use plenty of stitching vias to ensure a low impedance connection between different power and ground
planes.
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10.5.2 Layout Example
图 10-24 shows the top layer of one of the evaluation modules for this device. It demonstrates the practical
implementation of the PCB layout principles previously listed. The user can find a complete set drawings of all
the layers used in this PCB in the evaluation module's user guide.
GND
VIN
COUT
CIN
L
CIN
COUT
VIN
图10-24. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62870N0QWRXSRQ1
TPS62870QWRXSRQ1
TPS62870Y0QWRXSRQ1
TPS62870Y1QWRXSRQ1
TPS62870Y2QWRXSRQ1
TPS62870Y3QWRXSRQ1
TPS62871QWRXSRQ1
TPS62871Y1QWRXSRQ1
TPS62872N0QWRXSRQ1
TPS62872QWRXSRQ1
TPS62872Y1QWRXSRQ1
TPS62873QWRXSRQ1
TPS62873Y1QWRXSRQ1
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
ACTIVE VQFN-FCRLF
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
16
16
16
16
16
16
16
16
16
16
16
16
16
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
870N0B
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
870B
870Y0B
870Y1B
870Y2B
870Y3B
871B
871Y1B
872N0B
872B
872Y1B
873B
873Y1B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2023
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62872-Q1, TPS62873-Q1 :
Catalog : TPS62872, TPS62873
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62870N0QWRXSRQ1 VQFN-
FCRLF
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
16
16
16
16
16
16
16
16
16
3000
3000
3000
3000
3000
3000
3000
3000
3000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
TPS62870QWRXSRQ1 VQFN-
FCRLF
TPS62870Y0QWRXSRQ1 VQFN-
FCRLF
TPS62870Y1QWRXSRQ1 VQFN-
FCRLF
TPS62870Y2QWRXSRQ1 VQFN-
FCRLF
TPS62870Y3QWRXSRQ1 VQFN-
FCRLF
TPS62871QWRXSRQ1 VQFN-
FCRLF
TPS62871Y1QWRXSRQ1 VQFN-
FCRLF
TPS62872N0QWRXSRQ1 VQFN-
FCRLF
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62872QWRXSRQ1 VQFN-
FCRLF
RXS
RXS
RXS
RXS
16
16
16
16
3000
3000
3000
3000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
2.8
2.8
2.8
2.8
3.8
3.8
3.8
3.8
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
TPS62872Y1QWRXSRQ1 VQFN-
FCRLF
TPS62873QWRXSRQ1 VQFN-
FCRLF
TPS62873Y1QWRXSRQ1 VQFN-
FCRLF
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62870N0QWRXSRQ1
TPS62870QWRXSRQ1
TPS62870Y0QWRXSRQ1
TPS62870Y1QWRXSRQ1
TPS62870Y2QWRXSRQ1
TPS62870Y3QWRXSRQ1
TPS62871QWRXSRQ1
TPS62871Y1QWRXSRQ1
TPS62872N0QWRXSRQ1
TPS62872QWRXSRQ1
TPS62872Y1QWRXSRQ1
TPS62873QWRXSRQ1
TPS62873Y1QWRXSRQ1
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
VQFN-FCRLF
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
RXS
16
16
16
16
16
16
16
16
16
16
16
16
16
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
338.0
338.0
338.0
338.0
338.0
338.0
338.0
338.0
338.0
338.0
338.0
338.0
338.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
355.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
Pack Materials-Page 3
PACKAGE OUTLINE
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RXS0016A
2.65
2.45
B
A
PIN 1 INDEX AREA
3.65
3.45
0.1 MIN
(0.1)
SECTION A-A
TYPICAL
1.05
0.95
C
SEATING PLANE
0.08
C
0.00
-0.01
2X
2
1.25±0.1
(0.2) TYP
3X 0.275
SYMM
℄
7
8
6
0.2 MIN.
2.25±0.1
2X
SYMM ℄
17
3
0.5
11X
0.3
A
A
13
PIN 1 ID
1
(45° X 0.35)
16
20X 0.5
24X (0.18)
0.3
0.2
16X
0.1
C
A
B
0.05
C
4226093/E 09/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RXS0016A
(2.35)
2X (2)
(0.4)
20X
(0.5)
16
(R 0.05) TYP
13
1
11X (0.6)
(1.675)
(0.9)
11X (0.25)
2X (0.45)
17
(2.25)
SYMM
℄
2X (3)
2X (0.45)
3X (0.9)
(1.97)
(0.275)
6
7
8
(Ø 0.15) TYP
SYMM
℄
(0.6)
(0.25)
(0.2)
2X (0.4)
2X (0.6)
(1.25)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
PADS 6, 7 & 8
PADS 1-5 & 9-17
SOLDER MASK DETAILS
4226093/E 09/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RXS0016A
2.35
2X (2)
20X (0.5)
16
(R 0.05) TYP
13
1
11X (0.6)
(1.675)
2X (1)
11X (0.25)
17
SYMM
2X (3)
℄
(0.2)
(0.6)
(1.97)
6
8
7
(0.25)
SYMM
(0.6)
℄
2X (0.6)
2X (1.17)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 15X
4226093/E 09/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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