TPS62876-Q1 [TI]
汽车类 2.7V 至 6V 输入、25A 可堆叠同步降压转换器;
| 型号： | TPS62876-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2.7V 至 6V 输入、25A 可堆叠同步降压转换器 转换器 |
| 文件： | 总71页 (文件大小：3505K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62876-Q1
ZHCSLO0 –APRIL 2023
TPS6287x-Q1 具有I2C 接口的2.7V 至6V 输入、15A、20A、25A 和30A 汽车类快
速瞬态同步降压转换器
在省电模式下运行以充分提高效率，也可以在强制
PWM 模式下运行以实现出色瞬态性能和超低输出电压
纹波。
1 特性
• 符合面向汽车应用的AEC-Q100 标准
– 器件温度等级1：-40°C 至125°C TA
– -40°C 至150°C 的结温范围
• 提供功能安全型
可选的遥感功能可更大限度地提高负载点的电压调节，
并且该器件可在整个输出电压范围内实现 ±0.8% 的直
流电压精度。
– 可帮助进行功能安全系统设计的文档
• 输入电压范围：2.7V 至6V
• 引脚对引脚兼容器件系列：15A、20A、25A 和
30A
开关频率可通过 FSEL 引脚选择，可设置为 1.5MHz、
2.25MHz、2.5MHz 或 3MHz，也可与频率范围相同的
外部时钟同步。
I2C 兼容接口提供多种控制、监控和警告功能，例如电
压监控和温度相关警告。可快速调整输出电压，使负载
功耗适应性能需求。通过 VSEL 引脚，默认启动电压
可实现电阻可选。
• 0.4V 至1.675V 的3 个可选输出电压范围
– 0.4V 至0.71875V、步长为1.25mV
– 0.4V 至1.0375V，步长为2.5mV
– 0.4V 至1.675V，步长为5mV
• 输出电压精度：±0.8%
• 内部电源MOSFET：2.6mΩ和1.5mΩ
• 可调软启动
• 外部补偿
• 可通过VSEL 引脚选择启动输出电压
• 可通过FSEL 引脚选择1.5MHz、2.25MHz、
2.5MHz 或3MHz 开关频率
器件信息
封装(1)
器件型号
TPS62874-Q1 (2)
TPS62875-Q1 (2)
TPS62876-Q1
电流额定值
15A
20 A
RZV（VQFN，24）
4.05mm × 3.05mm
25 A
TPS62877-Q1 (2)
30 A
• 强制PWM 或省电模式运行
• 通过外部电阻器或I2C 选择启动输出电压
• 与I2C 兼容的接口频率高达3.4MHz
• 旨在提高输出电流能力的可选堆叠操作
• 差分遥感
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 产品预发布。
TPS6287x-Q1
VIN
L
VOUT
VIN
VIN
SW
COUT
CIN
• 热预警和热关断
• 输出放电
REN
VOSNS
MODE/SYNC
LOAD
GOSNS
EN
RZ CC
• 可选展频时钟
• 具有窗口比较器的电源正常输出
COMP
AGND
FSEL
RFSEL
CC2
VI/O
VI/O
RPG
2 应用
VSEL
PG
RVSEL
SYNC_OUT
AGND
• ADAS 摄像头、ADAS 传感器融合
• 环视ECU
• 混合和可重新配置仪表组
• 音响主机、远程信息处理控制单元
SCL
SDA
GND
GND
简化版原理图
3 说明
TPS62874-Q1 、TPS62875-Q1 、TPS62876-Q1 和
TPS62877-Q1 是具有 I2C 接口和差分遥感的引脚对引
脚 15A、20A、25A 和 30A 同步直流/直流降压转换器
系列。所有器件都具有高效率且易于使用。低阻电源开
关可在高温环境下支持高达30A 的持续输出电流。
这些器件可在堆叠模式下运行，以提供更高的输出电流
或将功耗分散到多个器件上。
TPS6287x-Q1 系列实现了增强型 DCS 控制方案，该
方案支持具有固定频率运行的快速瞬变响应。器件可以
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Table of Contents
8.6 Device Registers.......................................................37
9 Application and Implementation..................................43
9.1 Application Information............................................. 43
9.2 Typical Application.................................................... 43
9.3 Application Using Two TPS62876-Q1 in a
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings - Q100................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................7
6.6 I2C Interface Timing Characteristics..........................11
6.7 Typical Characteristics..............................................13
7 Parameter Measurement Information..........................14
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................32
8.5 Programming............................................................ 33
Stacked Configuration.................................................52
9.4 Application Using Three TPS62876-Q1 in a
Stacked Configuration.................................................57
9.5 Best Design Practices...............................................61
9.6 Power Supply Recommendations.............................62
9.7 Layout....................................................................... 62
10 Device and Documentation Support..........................64
10.1 接收文档更新通知................................................... 64
10.2 支持资源..................................................................64
10.3 Trademarks.............................................................64
10.4 静电放电警告.......................................................... 64
10.5 术语表..................................................................... 64
11 Mechanical, Packaging, and Orderable
Information.................................................................... 65
11.1 Tape and Reel Information......................................65
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
April 2023
*
Initial release.
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Device Options
SOFT-
START
TIME
OUTPUT
CURRENT
VSEL SETTING FOR START-UP
VOLTAGE AND I2C ADDRESS
TRANSIENT
ASYNC MODE
DEVICE NUMBER
SSC
TPS62874QWRZVRQ1(1)
TPS62875QWRZVRQ1(1)
TPS62876QWRZVRQ1
15 A
20 A
25 A
30 A
25 A
off
off
off
off
off
off
off
off
off
on
VSEL with 6.2 kΩto GND: 0.80 V, 0x44
VSEL shorted to GND: 0.75 V, 0x45
VSEL shorted to VIN: 0.875 V, 0x46
VSEL with 47 kΩto VIN: 0.58 V, 0x47
1 ms
TPS62877QWRZVRQ1(1)
TPS6287680QWRZVRQ1(1)
(1) Product preview
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
5 Pin Configuration and Functions
TOP VIEW
BOTTOM VIEW
22
21
21
22
24
24
23
23
1
VOSNS
EN
20
19
SCL
SDA
VOSNS
EN
1
2
3
SCL
SDA
20
2
19
18
MODE/
SYNC
MODE/
SYNC
3
FSEL
VSEL
VIN
FSEL
VSEL
VIN
18
17
16
15
4
5
SYNC_OUT
4
5
SYNC_OUT
17
16
15
VIN
VIN
VIN
6
7
VIN
VIN
VIN
6
7
GND
GND
GND
14
13
GND
GND
14
13
GND
GND
8
8
GND
SW
12
SW
11
SW
10
SW
9
SW
9
SW
10
SW
11
SW
12
图5-1. RZV Package 24 Pin VQFN
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
VOSNS
I
Output voltage sense (differential output voltage sensing).
This pin is the enable pin of the device. Connect to this pin using a series resistor of at least
15 kΩ. A logic low level on this pin disables the device, and a logic high level on the pin
enables the device. Do not leave this pin unconnected.
2
EN
I
For stacked operation interconnect EN pins of all stacked devices with a resistor to the
supply voltage or a GPIO of a processor. See Stacked Operation for a detailed description.
Frequency select pin. A resistor or a short circuit to GND or VIN determines the switching
frequency if not externally synchronized. See 节8.3.6 for the frequency options.
3
4
FSEL
VSEL
VIN
I
I
Start-up output voltage set pin. A resistor or short circuit to GND or VIN defines the selected
output voltage.
Power supply input. Connect the input capacitor as close as possible between pin VIN and
GND.
5, 6, 15, 16
P
7, 8,
13, 14
GND
SW
GND
O
Ground pin
9, 10, 11, 12
This is the switch pin of the converter and is connected to the internal Power MOSFETs.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
4
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
Internal clock output pin for synchronization in stacked mode. Leave this pin floating for
single device operation. Connect this pin to the MODE/SYNC pin of the successing device in
the daisy-chain in stacked operation. Do not use this pin to connect to a non-TPS6287x-Q1
device.
During start-up, this pin is used to identify if a device must operate as a secondary converter
in stacked operation. Connect a 47-kΩresistor from this pin to GND to define a secondary
converter in stacked operation. See Stacked Operation for a detailed description.
17
SYNCOUT
O
The device runs in Power-Save mode when this pin is pulled low. If the pin is pulled high, the
device runs in Forced-PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external clock.
18
19
20
MODE/SYNC
SDA
I
I2C serial data pin. Do not leave this pin floating. Connect a pullup to logic high level.
Connect to GND for secondary devices in stacked operation.
I/O
I/O
I2C serial clock pin. Do not leave this pin floating. Connect a pullup resistor to a logic high
level.
SCL
Connect to GND for secondary devices in stacked operation.
Open drain power good output. Low impedance when not "power good", high impedance
when "power good". This pin can be left open or be tied to GND when not used in single
device operation.
In stacked operation interconnect the PG pins of all stacked devices. Only the PG pin of the
primary converter in stacked operation is an open drain output. For devices that are defined
as secondary converters in stacked mode the pin is an input pin. See Stacked Operation for
a detailed description.
21
PG
I/O
22
23
24
AGND
COMP
GOSNS
GND
Analog Ground. Connect to GND.
Device compensation input. A resistor and capacitor from this pin to AGND define the
compensation of the control loop.
In stacked operation connect the COMP pins of all stacked devices together and connect a
resistor and capacitor between the common COMP node and AGND.
–
I
Output ground sense (differential output voltage sensing)
Exposed
The thermal pads must be soldered to GND to achieve an appropriate thermal resistance
and for mechanical stability.
-
Thermal Pads
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–3
MAX
6.5
UNIT
V
VIN(4)
SW (DC)
VIN + 0.3
VIN
V
Voltage(2)
COMP
V
SW (AC, less than 10ns)(3)
10
V
VOSNS
1.8
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
Voltage(2)
Voltage(2)
Voltage((2))
Voltage(2)
Voltage(2)
Tstg
SCL, SDA
5.5
V
SYNC_OUT
2
V
PG
6.5
V
FSEL, VSEL, EN, MODE/SYNC((4))
GOSNS
6.5
V
0.3
V
Storage temperature
150
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal
(3) While switching
(4) The voltage at the pin can exceed the 6.5 V absolute max condition for a short period of time, but must remain less than 8 V. VIN at 8
V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature.
6.2 ESD Ratings - Q100
VALUE
UNIT
Human body model (HBM), per AEC
Q100-002 (1)
HBM ESD classification level 2
Electrostatic
discharge
V(ESD)
±2000
V
Charged device model (CDM) per AEC
Q100-011
CDM ESD classification level C5
Electrostatic
discharge
V(ESD)
±750
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage range
Output voltage range
2.7
6
V
1.675 V or
(VIN - 1.5
V)((1))
VOUT
0.4
V
Voltage
L
Nominal pull-up voltage on pins SDA and SCL
Effective inductance for fSW = 1.5 MHz
Effective inductance for fSW = 2.25 MHz, 2.5 MHz and 3 MHz
Effective input capacitance per power input pin
Effective output capacitance
1.2
100
40
5
200
200
V
150
100
22
nH
nH
µF
µF
pF
pF
kΩ
L
CIN
10
COUT
CPAR
CPAR
REN
47
470
100
20
Parasitic capacitance on FSEL, VSEL pin
Parasitic capacitance on SYNC_OUT pin
Pull-up resistance on EN pin
15
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
6
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.3 Recommended Operating Conditions (continued)
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
RVSEL
RFSEL
,
,
,
Resistance on VSEL, VSEL to GND if not directly tied to GND or VIN
Resistance on VSEL, VSEL to VIN if not directly tied to GND or VIN
6.2
kΩ
RVSEL
RFSEL
47
kΩ
RVSEL
RFSEL
Resistor tolerance on VSEL, FSEL
Sink current at PG pin
± 2%
ISINK_PG
TJ
0
1
mA
°C
(2)
Operating junction temperature
150
–40
(1) Whatever VOUT value is lower
(2) Operating lifetime is derated at junction temperatures greater than 125 °C.
6.4 Thermal Information
TPS6287x-Q1
TPS6287x-Q1
THERMAL METRIC(1)
RZV (JEDEC)
RZV (EVM)
UNIT
24 PINS
34.7
14.9
6.5
24 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
28
-
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
-
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
-
ΨJT
YJB
6.5
-
RθJC(bot)
4.8
-
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating junction temperature (TJ = –40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = High, IOUT = 0 mA, device not
switching; MODE = Low;
CONTROL3:SINGLE = 0
IQ
Quiescent current
4.2
3.8
mA
mA
EN = High, IOUT = 0 mA, device not
switching; MODE = Low;
CONTROL3:SINGLE = 1
IQ
Quiescent current
Shutdown current
2.1
EN = Low, V(SW) = 0 V, max value at TJ =
125 °C
ISD
15
2.6
2.5
450
2.7
2.6
µA
V
Positive-going UVLO threshold voltage
(VIN)
VIT+
2.5
Negative-going UVLO threshold voltage
(VIN)
VIT-
2.4
80
V
mV
V
Vhys
VIT+
UVLO hysteresis voltage (VIN)
Positive-going OVLO threshold voltage
(VIN)
6.1
6.3
6.2
6.5
6.4
Negative-going OVLO threshold voltage
(VIN)
VIT-
6.0
80
V
Vhys
OVLO hysteresis voltage (VIN)
mV
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
over operating junction temperature (TJ = –40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Negative-going power-on reset threshold
voltage (VIN)
VIT-(POR)
1.4
V
Thermal shutdown threshold temperature TJ rising
Thermal shutdown hysteresis
170
20
°C
°C
°C
°C
TSD
Thermal warning threshold temperature
Thermal warning hysteresis
TJ rising
150
20
TW
CONTROL and INTERFACE
Positive-going input threshold voltage
(EN)
VIT+
0.97
1.0
0.9
1.03
0.93
V
Negative-going input threshold voltage
(EN)
VIT-
0.87
95
V
Vhys
R(EN)
IIH
IIL
Hysteresis voltage (EN)
mV
kΩ
Only active during startup in stacked
operation.
Input resistance to GND (EN)
1.4
2
3
3
VIH = VIN, internal pulldown resistor
disabled
High-level input current (EN)
Low-level input current (EN)
µA
nA
VIL = 0 V, internal pulldown resistor
disabled
–200
High-level input voltage (MODE/SYNC,
VSEL, FSEL, SYNC_OUT, PG)
VIH
VIH
VIL
VIL
RIN
0.8
V
V
High-level input voltage (SDA, SCL)
0.95
Low-level input voltage (MODE/SYNC,
VSEL, FSEL, SYNC_OUT, PG)
0.4
0.5
4
V
Low-level input voltage (SDA, SCL)
V
Input resistance to GND on pins MODE/
SYNC, EN and PG
2
3
MΩ
VOL
VOL
ILKG
IIL
Low-level output voltage (SDA)
IOL = 9 mA
IOL = 5 mA
VOH = 3.3 V
VIL = 0 V
0.4
0.2
200
100
3
V
V
Low-level output voltage (SDA)
Input leakage current into SDA, SCL
Low-level input current (MODE/SYNC)
High-level input current (MODE/SYNC)
Low-level input current (SYNC_OUT)
High-level input current (SYNC_OUT)
Low-level output voltage (SYNC_OUT)
High-level output voltage (SYNC_OUT)
nA
nA
µA
nA
nA
V
–100
–230
IIH
VIH = VIN
IIL
VIL = 0 V
IIH
VIH = 2 V
110
0.3
2.1
VOL
VOH
IOL = 1 mA
IOH = 0.1 mA
1.3
V
Measured from when EN goes high to
when device starts switching, SRVIN = 1
V/µs
td(EN)1
Enable delay time when EN tied to VIN
200
600
µs
Enable delay time when VIN already
applied
Measured from when EN goes high to
when device starts switching
td(EN)2
40
0.5
0.77
1
100
0.65
1.0
µs
ms
ms
ms
ms
Output voltage ramp time for
CONTROL2[1:0] = 00
0.35
0.54
0.7
Output voltage ramp time for
CONTROL2[1:0] = 01
Measured from when device starts
switching to rising edge of PG
td(Ramp)
Output voltage ramp time for
CONTROL2[1:0] = 10, default
1.3
Output voltage ramp time for
CONTROL2[1:0] = 11
1.4
2
2.6
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
8
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
over operating junction temperature (TJ = –40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronization clock frequency range
(MODE/SYNC)
f(SW)nom = 1.5 MHz, D(MODE/SYNC)
45%...55%
=
f(SYNC)
1.2
1.8
MHz
Synchronization clock frequency range
(MODE/SYNC)
f(SW)nom = 2.25 MHz, D(MODE/SYNC)
45%...55%
=
1.8
2
2.7
3.0
3.3
55
MHz
MHz
MHz
%
Synchronization clock frequency range
(MODE/SYNC)
f(SW)nom = 2.5 MHz, D(MODE/SYNC)
45%...55%
=
Synchronization clock frequency range
(MODE/SYNC)
f(SW)nom = 3 MHz, D(MODE/SYNC)
45%...55%
=
f(SYNC)
2.4
45
D(MODE/ Duty cycle of synchronization clock
frequency (MODE/SYNC)
)
SYNC
Phase shift at SYNC_OUT with reference CONTROL2:SYNCH_OUT_PHASE =
to internal CLK or external CLK 0b0
120
°
Phase shift at SYNC_OUT with reference CONTROL2:SYNCH_OUT_PHASE =
180
50
°
to internal CLK or external CLK
0b1
Time to lock to external frequency
µs
kΩ
Resistance on FSEL, VSEL to GND if not
tied to GND directly
6.2
Resistance on FSEL, VSEL to VIN if not
tied to VIN directly
47
96
kΩ
%
%
%
%
Positive-going power good threshold
voltage (output undervoltage)
VT+(UVP)
VT-(UVP)
VT+(OVP)
VT-(OVP)
94
92
98
96
Negative-going power good threshold
voltage (output undervoltage)
94
Positive-going power good threshold
voltage (output overvoltage)
104
102
106
108
106
Negative-going power good threshold
voltage (output overvoltage)
104
VOL
IOH
Low-level output voltage (PG)
High-level output current (PG)
IOL = 1 mA
VOH = 5 V
0.012
0.3
3
V
µA
Device configured as secondary device in
stacked operation
IIH
IIL
High-level input current (PG)
Low-level input current (PG)
Deglitch time (PG)
3
µA
µA
µs
Device configured as secondary device in
stacked operation
–1
High-to-low or low-to-high transition on
the PG pin
td(PG)
34
40
46
OUTPUT
VOUT
VIN ≥VOUT + 1.6 V, droop compensation
disabled
Output voltage accuracy
0.8
%
–0.8
–3
Output voltage change from no current to
rated current
droop compensation enabled
±12
mV
ΔVOUT
Accuracy of droop compensation voltage device in forced PWM mode
3
mV
Line regulation
0.02
%/V
IOUT = 15 A, VIN ≥VOUT + 1.6 V
EN = High; V(GOSNS) = –100 mV to 100
IIB
Input bias current (GOSNS)
3
µA
µA
mV
–60
V(VOSNS) = 1.675 V, VIN = 6 V, droop
compensation disabled
IIB
IIB
Input bias current (VOSNS)
5.5
–5.5
V(VOSNS) = 1.675 V, VIN = 6 V, droop
compensation enabled
Input bias current (VOSNS)
13.2
100
µA
–13.2
–100
VICR
Input common-mode range (GOSNS)
mV
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
over operating junction temperature (TJ = –40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25
°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
OUT ≤1 V
MIN
TYP
2.7
MAX
9.2
UNIT
RDIS
Output discharge resistance
V
Ω
fSW = 1.5 MHz, PWM operation
fSW = 2.25 MHz, PWM operation
fSW = 2.5 MHz, PWM operation
fSW = 3 MHz, PWM operation
1.35
2.025
2.25
2.7
1.5
1.65
2.475
2.75
3.3
MHz
MHz
MHz
MHz
kHz
2.25
2.5
fSW
Switching frequency (SW)
Modulation frequency
3
fSSC
fsw/2048
Switching frequency variation during
spread spectrum operation
fSW–
10%
fSW+10%
ΔfSW
gm
Transconductance of OTA on COMP pin
Emulated current time constant
1.5
12.5
3.4
mS
µs
11.87
13.2
6.4
τ
RDS(ON) High-side FET static on-resistance
RDS(ON) Low-side FET static on-resistance
VIN = 3.3 V
VIN = 3.3 V
mΩ
mΩ
1.9
3.6
SW pin current when HS-FET and LS-
FET are off
I(SW)(off)
VIN = 6 V; V(SW) = 0 V, TJ = 25 °C
VIN = 6 V; V(SW) = 6 V, TJ = 25 °C
V(SW) = 0.4 V, current into SW pin
TPS62874-Q1(1)
0.1
130
3000
26
µA
µA
µA
A
–1.5
SW pin current when HS-FET and LS-
FET are off
60
SW pin current when HS-FET and LS-
FET are off
11
22.5
28.5
34
High-side FET forward switch current
limit, DC
19
24
High-side FET forward switch current
limit, DC
TPS62875-Q1(1)
32
A
ILIM
High-side FET forward switch current
limit, DC
TPS62876-Q1
29
39
A
High-side FET forward switch current
limit, DC
TPS62877-Q1(1)
34
39
44
A
Low-side FET forward switch current limit,
ILIM
DC
TPS62874-Q1(1)
15
20
24
A
Low-side FET forward switch current limit,
ILIM
DC
TPS62875-Q1(1)
20
24.5
29
29
A
Low-side FET forward switch current limit,
ILIM
DC
TPS62876-Q1
24.5
29.5
33
A
Low-side FET forward switch current limit,
ILIM
DC
TPS62877-Q1(1)
33
38
A
ILIM
Low-side FET negative current limit, DC
Minimum on-time of HS FET
A
–10
45
ton, min
ton, min
toff, min
VIN = 3.3 V
53
44
ns
ns
ns
%
Minimum on-time of HS FET
VIN = 5 V
35
Minimum off-time of HS FET
VIN = 5 V
70
100
Maximum duty cycle of power stage
for TPS62877-Q1 only(1)
45
(1) Product preview
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
10
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.6 I2C Interface Timing Characteristics
PARAMETER
TEST CONDITIONS
Standard mode
MIN
TYP
MAX
100
400
1
UNIT
kHz
Fast mode
kHz
Fast mode plus
MHz
High-speed mode (write operation), CB –
100 pF max
3.4
3.4
1.7
1.7
MHz
MHz
MHz
MHz
fSCL
SCL clock frequency
High-speed mode (read operation), CB –
100 pF max
High-speed mode (write operation), CB –
400 pF max
High-speed mode (read operation), CB –
400 pF max
Standard mode
4
0.6
0.26
0.16
4.7
1.3
0.5
0.16
0.32
4
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
Fast mode
tHD, tSTA Hold time (repeated) START condition
Fast mode plus
High-speed mode
Standard mode
Fast mode
Fast mode plus
tLOW
LOW period of the SCL clock
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
Fast mode
0.6
0.26
0.06
0.12
4.7
0.6
0.26
0.16
250
100
50
Fast mode plus
tHIGH
HIGH period of the SCL clock
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
Fast mode
Setup time for a repeated START
condition
tSU, tSTA
Fast mode plus
High-speed mode
Standard mode
Fast mode
tSU, tDAT Data setup time
Fast mode plus
High-speed mode
10
Standard mode
0
3.45
0.9
Fast mode
0
Fast mode plus
0
tHD, tDAT Data hold time
0
70
150
1000
300
120
40
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
0
Fast mode
20
Fast mode plus
tRCL
Rise time of both SDA and SCL signals
10
20
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
80
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.6 I2C Interface Timing Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Standard mode
300
ns
20 x
VDD/5.5
V
Fast mode
300
ns
ns
tFCL
Fall time of both SDA and SCL signals (1)
20 x
VDD/5.5
V
Fast mode plus
120
10
20
40
80
ns
ns
µs
µs
µs
µs
pF
pF
pF
pF
µs
µs
µs
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
4
Fast mode
0.6
0.26
0.16
tSU, tSTO Setup time of STOP Condition
Fast mode plus
High-Speed mode
Standard mode
400
400
550
400
Fast mode
CB
Capacitive load for SDA and SCL
Fast mode plus
High-Speed mode
Standard mode
4.7
1.3
0.5
Bus free time between a STOP and a
START condition
tBUF
Fast mode
Fast mode plus
(1) VDD is the pull-up voltage of SDA and SCL
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
12
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
6.7 Typical Characteristics
7
4
3.8
3.6
3.4
3.2
3
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
6.5
6
5.5
5
2.8
2.6
2.4
2.2
2
4.5
4
3.5
3
1.8
1.6
1.4
1.2
1
2.5
2
1.5
1
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
D002
D002
图6-1. RDS(ON) of High Side Switch
图6-2. RDS(ON) of Low Side Switch
70
65
60
55
50
45
40
35
30
25
20
15
10
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
D002
D002
图6-4. Quiescent Current vs Temperature
图6-3. Shutdown Current vs Temperature
2.3
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
VIN = 3.3 V
2.28
2.26
2.24
2.22
2.2
VIN = 5.0 V
2.18
2.16
2.14
2.12
2.1
V
IN = 5 V
1.7
1.5
VIN = 3.3 V
-40 -20
0
20
40
60
80 100 120 140
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Junction Temperature (°C)
Output Voltage (V)
D002
D002
图6-6. Switching Frequency vs Temperature
图6-5. Maximum Switching Frequency vs Output
Voltage
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
7 Parameter Measurement Information
TPS6287x-Q1
VIN
L
VOUT
VIN
VIN
SW
COUT
CIN
REN
VOSNS
MODE/SYNC
LOAD
GOSNS
EN
RZ CC
COMP
AGND
FSEL
RFSEL
CC2
VI/O
VI/O
RPG
VSEL
PG
RVSEL
SYNC_OUT
AGND
SCL
SDA
GND
GND
图7-1. Measurement Setup for TPS6287x-Q1
表7-1. List of Components
Description
Reference
Manufacturer
Texas Instruments
Vishay
IC
L
TPS62877QWRZVRQ1
IHSR2525CZ-56nH
6 × 10 µF / 10 V; GCM21BR71A106KE22L
+ 2 × 4.7 µF / 10 V; LMK107BJ475MAHT
Murata,
Taiyo Yuden
CIN
2 × 22 µF / 10 V; GCM31CR71A226KE02L
+ 8 × 47 µF / 6.3 V; GCM32ER70J476ME19L
COUT
Murata
+ 3 × 100 µF / 6.3 V;
GRT32ER60J107NE13L
CC
RZ
1 nF
any
any
any
3.6 kΩ
4.7 pF
CC2
REN
any
any
22 kΩ
RFSEL
0 kΩto GND
6.2 kΩ
RVSEL
RPG
any
any
or 47 kΩor 0 kΩ
100 kΩ
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
14
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS6287x-Q1 devices are automotive-qualified synchronous step-down (buck) DC/DC converters. These
devices use an enhanced DCS-control scheme that combines fast transient response with fixed frequency
operation, which, together with their low output voltage ripple, high DC accuracy and differential remote sensing
makes them designed for supplying the cores of modern high-performance processors.
The three devices in this family are identical except for their current rating:
• The TPS62874-Q1 is a 15-A rated device
• The TPS62875-Q1 is a 20-A rated device
• The TPS62876-Q1 is a 25-A rated device
• The TPS62877-Q1 is a 30-A rated device
To further increase the output current capability, combine multiple devices in a “stack”. For example, a stack
of two TPS62875-Q1 devices has a current capability of 40 A.
The TPS6287x-Q1 devices have a built-in I2C-compatible interface to control and monitor their operation. If the
I2C-compatible interface is not used, connect the SCL and SDA pins to GND.
8.2 Functional Block Diagram
VIN
SW
VIN
VIN
SW
SW
SW
Bias
Regulator
Gate Drive and Control
VIN
EN
IHS
ILS
GND
GND
PG
GND
GND
Ramp and Slope
Compensation
Device
Control
+
–
–
VOSNS
GOSNS
gm
MODE/SYNC
+
VREF
Oscillator
COMP
FSEL
VSEL
SCL
AGND
SYNC_OUT
Thermal
Shutdown
SDA
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.3 Feature Description
8.3.1 Fixed-Frequency DCS-Control Topology
图 8-1 shows a simplified block diagram of the fixed-frequency DCS-control topology used in the TPS6287x-Q1
devices. This topology comprises an inner emulated current loop and an outer voltage-regulating loop.
VIN
–
+
ON
EN
R
S
Q
L
Gate
Driver
COUT
fsw
Control
Logic
τaux
Slope
Compensation
AGND
VOSNS
GOSNS
–
+
COMP
gm
RLOAD
RZ
CC2
CC
AGND
AGND
图8-1. Fixed-Frequency DCS-Control Topology (Simplified)
8.3.2 Forced-PWM and Power-Save Modes
The device can control the inductor current in three different ways to regulate the output:
• Pulse-width modulation with continuous inductor current (PWM-CCM)
• Pulse-width modulation with discontinuous inductor current (PWM-DCM)
• Pulse-frequency modulation with discontinuous inductor current and pulse skipping (PFM-CCM)
During PWM-CCM operation, the device switches at a constant frequency and the inductor current is continuous
(see 图8-2). PWM operation achieves the lowest output voltage ripple and the best transient performance.
t1/fSW
t
0
Time
图8-2. Continuous Conduction Mode (CCM) Current Waveform
During PWM-DCM operation the device switches at a constant frequency and the inductor current is
discontinuous (see 图 8-3). In this mode the device controls the peak inductor current to maintain the selected
switching frequency while still being able to regulate the output.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
16
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
t1/fSW
t
0
Time
图8-3. Discontinuous Conduction Mode (DCM) Waveform
During PFM-DCM operation the device keeps the peak inductor current constant (at a level corresponding to the
minimum on-time of the converter) and skips pulses in order to regulate the output (see 图 8-3). The switching
pulses that occur during PFM-DCM operation are synchronized to the internal clock.
Minimum on-time
t1/fSW
t
t1/fSW
t
t1/fSWt
0
Time
Skipped Pulses
图8-4. Discontinuous Conduction Mode (PFM-DCM) Current Waveform
You can use 方程式1 to calculate the output current threshold at which the device enters PFM-DCM:
V
– V
2L
V
IN
IN
OUT
2
I
=
t
f
sw
(1)
OUT PFM
ON
V
OUT
图8-5 shows how this threshold typically varies with VIN and VOUT for a switching frequency of 2.25 MHz.
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VIN = 5 V
VIN = 3.3 V
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Output Voltage (V)
D002
图8-5. Output Current PFM-DCM Entry Threshold for fSW = 2.25 MHz
You can configure the device to use either Forced-PWM (FPWM) mode or Power-Save Mode (PSM):
• In Forced-PWM mode the device uses PWM-CCM at all times
• In Power-Save Mode the device uses PWM-CCM at medium and high loads, PWM-DCM at low loads, and
PFM-DCM at very low loads. Transition between the different operating modes is seamless.
表 8-1 shows the function table of the MODE/SYNC pin and the FPWMEN bit in the CONTROL1 register, which
control the operating mode of the device.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表8-1. FPWM Mode and Power-Save Mode Selection
MODE/SYNC Pin
FPWMEN Bit
Operating Mode
Remark
Low
0
PSM
Do not use in a stacked
configuration
1
X
X
FPWM
FPWM
FPWM
High
Sync Clock
8.3.3 Transient Asynchronous Mode (optional)
The TPS6287x-Q1 has a transient asynchronous mode that helps to minimize the output voltage overshoot
during a load release. When the high side FET is turned off, the decay in inductor current is mainly determined
by the output voltage as there is little voltage drop over the low side FET. For very low output voltages the
current decays slowly so the output voltage overshoot is typically larger than the undershoot during a load step.
Asynchronous mode turns off the low side FET for 6 switching cycles so the inductor current decays through the
body diode. This adds extra voltage across the inductor so the current decays quicker and the output voltage
overshoot is lower.
8.3.4 Precise Enable
The Enable (EN) pin is bidirectional, and has two functions:
• As an input, it enables and disables the DC/DC converter in the device
• As an output, it provides a SYSTEM_READY signal to other devices in a stacked configuration
+
–
EN
ENABLE
VIT(EN)
SYSTEM_READY
CONTROL3:SINGLE
图8-6. Enable Functional Block Diagram
Because there is an internal open-drain transistor connected to the EN pin, do not drive this pin directly from a
low-impedance source. Instead, use a resistor to limit the current flowing into the EN pin (see 节9.1).
When power is first applied to the VIN pin, the device pulls the EN pin low until it has loaded its default register
settings from nonvolatile memory and read the state of the VSEL, FSEL and SYNC_OUT pins. The device also
pulls EN low if a fault such as thermal shutdown or overvoltage lockout occurs. In a stacked configuration all
devices share a common enable signal, which means that the DC/DC converters in the stack cannot start to
switch until all devices in the stack have completed their initialization. Similarly, a fault in one or more devices in
the stack disables all converters in the stack (see 节8.3.18).
In stand-alone (non-stacked) applications, you can disable the active pulldown of the EN pin if you set SINGLE =
1 in the CONTROL3 register. Fault conditions have no effect on the EN pin when SINGLE = 1. (Note that the EN
pin is always pulled down during device initialization.) In stacked applications, make sure that SINGLE = 0.
When the internal SYSTEM_READY signal is low (that is, initialization is complete and there are no fault
conditions), the internal open-drain transistor is high impedance and the EN pin functions like a standard input: A
high level on the EN pin enables the DC/DC converter in the device and a low level disables it. (The I2C interface
is enabled as soon as the device has completed its initialization and is not affected by the state of the internal
ENABLE or SYSTEM_READY signals.)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
18
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
A low level on the EN pin forces the device into shutdown. During shutdown, the MOSFETs in the power stage
are off, the internal control circuitry is disabled, and the device consumes only 20 µA (typical).
The rising threshold voltage of the EN pin is 1.0 V and the falling threshold voltage is 0.9 V. The tolerance of the
threshold voltages is ±30 mV, which means that you can use the EN pin to implement precise turn-on and turn-
off behavior.
8.3.5 Start-Up
When the voltage on the VIN pin exceeds the positive-going UVLO threshold, the device initializes as follows:
• It pulls the EN pin low
• It enables the internal reference voltage
• It reads the state of the VSEL, FSEL and SYNC_OUT pins
• It loads the default values into the device registers
When initialization is complete, the device enables I2C communication and releases the EN pin. The external
circuitry controlling the EN pin now determines the behavior of the device:
• If the EN pin is low, the device is disabled: you can write to and read from the device registers, but the DC/DC
converter does not operate.
• If the EN pin is high, the device is enabled: you can write to and read from the device registers and, after a
short delay from EN pin going high, the DC/DC converter starts to ramp up its output.
图8-7 shows the start-up sequence when the EN pin is pulled up to VIN.
VIN
EN
VIT+(UVLO)
EN pin pulled
low internally
Device initialization
complete
VOUT
ttd(EN)1t
ttd(RAMP)t
PG
Undefined
td(PG)
图8-7. Start-Up Timing When EN is Pulled Up to VIN
图8-8 shows the start-up sequence when an external signal is connected to the EN pin.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
VIN
EN
VIT+(UVLO)
VIT+(EN)
VOUT
ttd(EN)2
t
ttd(RAMP)t
Device initialization
complete
PG Undefined
td(PG)
图8-8. Start-Up Timing When an External Signal is Connected to the EN Pin
The SSTIME[1:0] bits in the CONTROL2 register select the duration of the soft-start ramp:
• td(RAMP) = 500 μs
• td(RAMP) = 770 μs
• td(RAMP) = 1 ms (default)
• td(RAMP) = 2 ms
If you program new output voltage setpoint (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start time
(SSTIME[1:0]) settings when the device has already begun its soft-start sequence, the device ignores the new
values until the soft-start sequence is complete. For example, if you change the value of VSET[7:0] during soft-
start, the device first ramps to the value that VSET[7:0] had when the soft-start sequence began and then, when
soft-start is complete, ramps up or down to the new value.
The device can start up into a prebiased output. In this case, only a portion of of the internal voltage ramp is
seen externally (see 图8-9).
Final voltage
VOUT
Prebias voltage
ttd(RAMP)
t
图8-9. Start-Up into a Prebiased Output
Note that the device always operates in DCM/PFM allowed during the start-up ramp, regardless of other
configuration settings or operating conditions.
8.3.6 Switching Frequency Selection
During device initialization, a resistor-to-digital converter in the device determines the state of the FSEL pin and
sets the switching frequency of the DC/DC converter according to 表8-2.
表8-2. Switching Frequency Options
Resistor at FSEL (1%)
6.2 kΩto GND
Short to GND
Switching Frequency
1.5 MHz
2.25 MHz
Short to VIN
2.5 MHz
Copyright © 2023 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表8-2. Switching Frequency Options (continued)
Resistor at FSEL (1%)
47 kΩto VIN
Switching Frequency
3 MHz
图 8-10 shows a simplified block diagram of the R2D converter used to detect the state of the FSEL pin. (An
identical circuit detects the state of the VSEL pin –see 表8-5.)
VIN
S1
6.5 k
FSEL
VIL = < 0.4 V
VIH = > 0.8 V
1.6 k
S2
图8-10. FSEL R2D Converter Functional Block Diagram
Detection of the state of the FSEL pin works as follows:
To detect the most significant bit (MSB), the circuit opens S1 and S2, and the input buffer detects if a high or a
low level is connected to the FSEL pin.
To detect the least significant bit (LSB):
• If the MSB was 0, the circuit closes S1. If the input buffer detects a high level, the LSB = 1; if the circuit
detects a low level, the LSB = 0.
• If the MSB was 1, the circuit closes S2. If the input buffer detects a low level, the LSB = 0; if the circuit detects
a high level, the LSB = 1.
The propagation delay of the current-sensing comparator limits the minimum on-time of the device. In practice,
this means that the maximum switching frequency the device can support decreases with small duty cycles. 图
6-5 shows the practical operating range of the device with 3.3-V and 5-V supplies.
8.3.7 Output Voltage Setting
8.3.7.1 Output Voltage Range
The device has three different voltage ranges. The VRANGE[1:0] bits in the CONTROL1 register control which
range is active (see 表 8-3). The default output voltage range after device initialization is 0.4 V to 1.675 V in 5-
mV steps.
表8-3. Voltage Ranges
VRANGE[1:0]
0b00
Voltage Range
0.4 V to 0.71875 V in 1.25-mV steps
0.4 V to 1.0375 V in 2.5-mV steps
0b01
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表8-3. Voltage Ranges (continued)
VRANGE[1:0]
0b10
Voltage Range
0.4 V to 1.675 V in 5-mV steps
0.4 V to 1.675 V in 5-mV steps
0b11
Note that every change to the VRANGE[1:0] bits must be followed by a write to the VSET register – even if the
value of the VSET[7:0] bits does not change. This sequence is necessary for the device to start to use the new
voltage range.
8.3.7.2 Output Voltage Setpoint
Together with the selected range, the VSET[7:0] bits in the VSET register control the output voltage setpoint of
the device (see 表8-4).
表8-4. Start-Up Voltage Settings
VRANGE[1:0]
0b00
Output Voltage Setpoint
0.4 V + VSET[7:0] × 1.25 mV
0.4 V + VSET[7:0] × 2.5 mV
0.4 V + VSET[7:0] × 5 mV
0.4 V + VSET[7:0] × 5 mV
0b01
0b10 (default)
0b11
During initialization, the device reads the state of the VSEL pin and selects the default output voltage according
to 表8-5. Note that the VSEL pin also selects the I2C target address of the device (see below).
表8-5. Default Output Voltage Setpoints
VSEL Pin1
VSET[7:0]
Output Voltage Setpoint
800 mV
I2C Device Address
0x50
6.2 kΩto GND
Short-Circuit to GND
Short-Circuit to VIN
0x44
0x45
0x46
0x47
0x46
750 mV
0x5F
875 mV
0x24
47 kΩ to VIN
580 mV
If you program new output voltage setpoint (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start time
(SSTIME[1:0]) settings when the device has already begun its soft-start sequence, the device ignores the new
values until the soft-start sequence is complete. For example, if you change the value of VSET[7:0] during soft-
start, the device first ramps to the value that VSET[7:0] had when the soft-start sequence began and then, when
soft-start is complete, ramps up or down to the new value.
If you change VOUT[7:0], VRAMP[1:0], or SSTIME[1:0] while EN is low, the device uses the new values the next
time you enable it.
During start-up the output voltage ramps up to the target value set by the VSEL pin before ramping up or down
to any new value programmed to the device over the I2C interface.
8.3.7.3 Non-Default Output Voltage Setpoint
If none of the default voltage range / voltage setpoint combinations is suitable for your application, you can you
change these device settings via I2C before you enable the device. Then, when you pull the EN pin high, the
device starts up with the desired start-up voltage.
Note that if you change the device settings via I2C while the device is ramping, the device ignores the changes
until the ramp is complete.
1
For reliable voltage setting, make sure that there is no stray current path connected to the VSEL pin and that the parasitic capacitance
between the VSEL pin and GND is less than 30 pF.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
22
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.3.7.4 Dynamic Voltage Scaling
If you change the output voltage setpoint while the DC/DC converter is operating, the device ramps up or down
to the new voltage setting in a controlled way.
The VRAMP[1:0] bits in the CONTROL1 register set the slew rate when the device ramps from one voltage to
another during DVS (see 表8-6).
表8-6. Dynamic Voltage Scaling Slew Rate
VRAMP[1:0]
0b00
DVS Slew Rate
10 mV/μs
0b01
5 mV/μs
0b10 (default)
0b11
1.25 mV/μs
0.5 mV/μs
Note that ramping the output to a higher voltage requires additional output current, so that during DVS the
converter must generate a total output current given by:
(2)
where:
• IOUT is the total current the converter must generate while ramping to a higher voltage
• IOUT(DC) is the DC load current
• COUT is the total output capacitance
• dVOUT/dt is the slew rate of the output voltage (programmable in the range 0.5 mV/µs to 10 mV/µs)
For correct operation, make sure that the total output current during DVS does not exceed the current limit of the
device.
8.3.7.5 Droop Compensation
Droop Compensation scales the nominal output voltage based on the output current. This is done such that the
output voltage is set to a higher value with no output current and to a lower value than the nominal value with the
maximum output current. Droop Compensation therefore provides a higher margin during a load transient and
helps to keep the output voltage within a certain tolerance band in case of a heavy load step or at load release
or allows to use a lower output capacitance. The voltage scaling is absolute instead of relative. The voltage
scaling vs output current depends on the output current version of TPS6287x-Q1 based on the rated output
current of 15 A, 20 A, 25 A and 30 A, respectively. The behavior is shown in the graph Voltage Scaling with
Output Current. Droop compensation is disabled by default and can be enabled by bit CONTROL3:DROOPEN.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Output
Voltage
+12 mV
Nominal
Output
Voltage
0 A
50% of
rated
output
current
Rated
output
current
Output Current
-12 mV
图8-11. Voltage Scaling with Output Current
8.3.8 Compensation (COMP)
The COMP pin is the connection point for an external compensation network. A series-connected resistor and
capacitor to GND is sufficient for typical applications and provides enough scope to optimize the loop response
for a wide range of operating conditions.
When using multiple devices in a stacked configuration, all devices share a common compensation network, and
the COMP pin ensures equal current sharing between them (see 节8.3.18).
8.3.9 Mode Selection / Clock Synchronization (MODE/SYNC)
A high level on the MODE/SYNC pin selects forced-PWM operation. A low level on the MODE/SYNC pin selects
power-save operation, in which the device automatically transitions between PWM and PFM, according to the
load conditions.
If you apply a valid clock signal to the MODE/SYNC pin, the device synchronizes its switching cycles to the
external clock and automatically selects forced-PWM operation.
The MODE/SYNC pin is logically ORed with the FPWMEN bit in the CONTROL1 register (see 表8-1).
When multiple devices are used together in a stacked configuration the MODE/SYNC pin of the secondary
devices is the input for the clock signal (see 节8.3.18).
8.3.10 Spread Spectrum Clocking (SSC)
The device has a spread spectrum clocking function that can reduce electromagnetic interference (EMI). When
the SSC function is active, the device modulates the switching frequency ±10% about the nominal value. The
frequency modulation has a triangular characteristic (see 图8-12).
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
24
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Switching
Frequency
+10%
Nominal fSW
–10%
t2048/fSW
t
Time
图8-12. Spread Spectrum Clocking Behavior
To use the SSC function, make sure that:
• SSCEN = 1 in the CONTROL1 register
• Forced-PWM operation is selected (MODE pin is high or FPWMEN = 1 in the CONTROL1 register)
• The device is not synchronized to an external clock
To disable the SSC function, make sure that SCCEN = 0 in the CONTROL1 register.
To use the SSC function with multiple devices in a stacked configuration, make sure that the primary converter
runs from its internal oscillator and synchronize all secondary converters to the primary clock (see 图8-16).
8.3.11 Output Discharge
The device has an output discharge function which ensures a defined ramp down of the output voltage when the
device is disabled and keeps the output voltage close to 0 V while the device is off. The output discharge
function is enabled when DISCHEN = 1 in the CONTROL1 register. The output discharge function is enabled by
default.
If enabled, the device discharges the output under the following conditions:
• A low level is applied to the EN pin
• SWEN = 0 in the CONTROL1 register
• A thermal shutdown event occurs
• An UVLO event occurs
• An OVLO event occurs
The output discharge function is not available until you have enabled the device at least once after power up.
During power-down, the device continues to discharge the output for as long as the supply voltage is greater
than approximately 1.8 V.
8.3.12 Undervoltage Lockout (UVLO)
The TPS6287x-Q1 has an undervoltage lockout function that disables the device if the supply voltage is too low
for correct operation. The negative-going threshold of the UVLO function is 2.5 V (typical). If the supply voltage
decreases below this value, the device stops switching and, if DISCHEN = 1 in the CONTROL1 register, turns on
the output discharge.
8.3.13 Overvoltage Lockout (OVLO)
The TPS6287x-Q1 has an overvoltage lockout function that disables the DC/DC converter if the supply voltage is
too high for correct operation. The positive-going threshold of the OVLO function is 6.3 V (typical). If the supply
voltage increases above this value, the device stops switching and, if DISCHEN = 1 in the CONTROL1 register,
turns on the output discharge.
The device automatically starts switching again – it begins a new soft-start sequence – when the supply
voltage falls below 6.2 V (typical).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.3.14 Overcurrent Protection
8.3.14.1 Cycle-by-Cycle Current Limiting
If the peak inductor current increases above the high-side current limit threshold, the device turns off the high-
side switch and turns on the low-side switch to ramp down the inductor current. The device only turns on the
high-side switch again if the inductor current has decreased below the low-side current limit threshold.
Note that because of the propagation delay of the current limit comparator, the current limit threshold in practice
can be greater than the DC value specified in the Electrical Characteristics. The current limit in practice is given
by:
(3)
where:
• IL is the peak inductor current
• ILIMH is the high-side current limit threshold measured at DC
• VIN is the input voltage
• VOUT is the output voltage
• L is the effective inductance at the peak current level
• tpd is the propagation delay of the current limit comparator (typically 50 ns)
8.3.14.2 Hiccup Mode
To enable hiccup operation, make sure that HICCUPEN = 1 in the CONTROL1 register. The HICCUP function is
disabled by default.
If hiccup operation is enabled and the high-side switch current exceeds the current limit threshold on 32
consecutive switching cycles, the device:
• Stops switching for 128 µs, after which it automatically starts switching again (it starts a new soft-start
sequence)
• Sets the HICCUP bit in the STATUS register
• Pulls the PG pin low. The PG pin stays low until the overload condition goes away and the device can start up
correctly and regulate the output voltage. Note that power-good function has a deglitch circuit, which delays
the rising edge of the power-good signal by 40 µs (typical).
Hiccup operation continues – in a repeating sequence of 32 cycles in current limit, followed by a pause of 128
µs, followed by a soft-start attempt –for as long as the output overload condition exists.
The device clears the HICCUP bit if you read the STATUS register when the overload condition has been
removed.
8.3.14.3 Current-Limit Mode
To enable current-limit mode, make sure that HICCUPEN = 0 in the CONTROL1 register.
When current limit operation is enabled the device limits the high-side switch current cycle-by-cycle for as long
as the overload condition exists. If the device limits the high-side switch current for four or more consecutive
switching cycles it sets ILIM = 1 in the STATUS register.
The device clears the ILIM bit if you read the STATUS register when the overload condition no longer exits.
8.3.15 Power Good (PG)
The Power-Good (PG) pin is bidirectional and has two functions:
• In a standalone configuration, and in the primary device of a stacked configuration, the PG pin is an open-
drain output that indicates the status of the converter or stack.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
26
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
• In a secondary device of a stacked configuration, the PG pin is an input that indicates when the soft-start
sequence is complete and all converters in the stack can change from DCM switching to CCM switching.
VT+(OVP)
OVP
VT+(OVP)-VHYS
VO
VT-(UVP)+VHYS
UVP
VT-(UVP)
de-glitch me td(PG)
de-glitch me td(PG)
PG
图8-13. PG Timing
8.3.15.1 Standalone / Primary Device Behavior
The primary purpose of the PG pin is to indicate if the output voltage is in regulation, but it also indicates if the
device is in thermal shutdown or disabled. 表 8-7 summarizes the behavior of the PG pin in a stand-alone or
primary device.
表8-7. Power-Good Function Table
PGBLNKDVS
AND DVS_active
VIN
EN
VOUT
Soft Start
TJ
PG
2 V > VIN
X
X
L
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
Undefined
Low
V
IT(UVLO) ≥VIN ≥2 V
X
Low
Active
Low
VOUT > VT(OVP)
or
low
VIN > VIT(UVLO)
Inactive
1
TJ < TSD
Hi-Z
VT(UVP) > VOUT
H
VT(OVP) > VOUT > VT(UVP)
X
X
X
TJ < TSD
TJ > TSD
X
Hi-Z
Low
Low
X
X
X
X
VIN > VIT(OVLO)
图 8-14 shows a functional block diagram of the power-good function in a stand-alone or primary device. A
window comparator monitors the output voltage, and the output of the comparator goes high if the output voltage
is either less than 95% (typical) or greater than 105% (typical) of the nominal output voltage. The output of the
window comparator is deglitched – the typical deglitch time is 40 µs – and then used to drive the open-drain
PG pin.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
CONTROL1:HICCUPEN
To converter
control logic
Hiccup
Control
PBOV
PBUV
STATUS
Register
4 Consecutive
Pulses
Detection
Current
Comparator
ISW
ILIM
HICCUP
Soft-Start Complete
PG
40-µs
Deglitch
VIN > VIT(OVLO)
Window
Comparator
VOUT
Blanking
Thermal Shutdown
VIN < VIT(UVLO)
95% VOUT
105% VOUT
VEN < VIT(EN)
DVS Active
CONTROL3:PGBLNKDVS
图8-14. Power-Good Functional Block Diagram (Standalone / Primary Device)
During DVS activity, when the DC/DC converter transitions from one output voltage setting to another, the output
voltage can temporarily exceed the limits of the window comparator and pull the PG pin low. The device has a
feature to disable this behavior: if PGBLNKDVS = 1 in the CONTROL3 register, the device ignores the output of
the power-good window comparator while DVS is active.
Note that the PG pin is always low –regardless of the output of the window comparator –when:
• The device is in thermal shutdown
• The device is disabled
• The device is in undervoltage lockout
• The device is in overvoltage lockout
• The device is in soft start
• The device is in HICCUP mode
8.3.15.2 Secondary Device Behavior
图 8-15 shows a functional block diagram of the power-good function in a secondary device. During initialization,
the device presets FF1 and FF2, which pulls down the PG pin and forces the device to operate in DCM. When
the device completes its soft start, it resets FF2, which turns off Q1. However, in a stacked configuration all
devices share the same PG signal, and therefore the PG pin stays low until all devices in the stack have
completed their soft start. When that happens, FF1 is reset and the converters operate in CCM. FF1 and FF2
are pre-set such that DCM is allowed each time the converter is disabled, either by the EN pin, EN bit, thermal
shutdown or UVLO.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
28
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
FF1
Input
Buffer
FORCE DCM
Latch
PG
VIL = < 0.4 V
VIH = > 0.8 V
SECONDARY DEVICE
DETECTED
Q1
SOFT START
COMPLETE
Latch
FF2
图8-15. Power-Good Functional Block Diagram (Secondary Device)
8.3.16 Remote Sense
The device has two pins, VOSNS and GOSNS, to remotely sense the output voltage. Remote sensing lets the
converter sense the output voltage directly at the point-of-load and increases the accuracy of the output voltage
regulation.
In a stacked configuration, you must connect the VOSNS and GOSNS of the primary device directly at the point-
of-load. For the secondary devices, you can connect the VOSNS and GOSNS pins to the local output capacitor
or both pins to AGND (see 节8.3.18).
8.3.17 Thermal Warning and Shutdown
The device has a two-level overtemperature detection function.
If the junction temperature rises above the thermal warning threshold of 150 °C (typical), the device sets the
TWARN bit in the STATUS register. The device clears the TWARN bit if you read the STATUS register when the
junction temperature is below the TWARN threshold of 130 °C (typical).
If the junction temperature rises above the thermal shutdown threshold of 170 °C (typical), the device:
• Stops switching
• Pulls down the EN pin (if SINGLE = 0 in the CONTROL3 register)
• Enables the output discharge (if DISCHEN = 1 in the CONTROL1 register)
• Sets the TSHUT bit in the STATUS register
• Pulls the PG pin low
If the junction temperature falls below the thermal shutdown threshold of 150 °C (typical), the device:
• Starts switching again, starting with a new soft-start sequence
• Sets the EN pin to high impedance
• Sets the PG pin to high-impedance
The device clears the TSHUT bit if you read the STATUS register when the junction temperature is below the
TSHUT threshold of 150 °C (typical).
In a stacked configuration, in which all devices share a common enable signal, a thermal shutdown condition in
one device disables the entire stack. When the hot device cools down, the whole stack automatically starts
switching again.
8.3.18 Stacked Operation
You can connect multiple TPS6287x-Q1 devices in parallel in what is known as a "stack"; for example, to
increase output current capability or reduce device junction temperature. A stack comprises one primary device
and one or more secondary devices. During initialization, each device monitors its SYNCOUT pin to determine if
it must operate as a primary device or a secondary device:
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
• If there is a 47-kΩresistor between the SYNCOUT pin and ground, the device operates as a secondary
device
• If the SYNCOUT pin is high impedance, the device operates as a primary device
图8-16 shows the recommended interconnections in a stack of two TPS6287x-Q1 devices.
TPS6287x-Q1
(Primary Device)
CLOAD
100 nH
VIN
2.7 V to 6 V
VIN
VIN
SW
COUT
CIN
VIO
REN
MODE/SYNC
Load
EN
VOSNS
GOSNS
SDA
SCL
I2C
AGND
RZ
VSEL
FSEL
VIO
CC2
CC
RVSEL RFSEL
RPG
COMP
PG
PG
SYNC_OUT
AGND
GND
GND
TPS6287x-Q1
(Secondary Device)
100 nH
VIN
VIN
SW
COUT
CIN
MODE/SYNC
VOSNS
GOSNS
EN
SDA
SCL
VSEL
FSEL
RFSEL
COMP
PG
SYNC_OUT
AGND
GND
GND
47 k
图8-16. Two TPS6287x-Q1 Devices in a Stacked Configuration
The key points to note are:
• All the devices in the stack share a common enable signal, which must be pulled up with a resistance of at
least 15 kΩ.
• All the devices in the stack share a common power-good signal.
• All the devices in the stack share a common compensation signal.
• The remote sense pins (VOSNS and GOSNS) of each device must be connected (do not leave these pins
floating).
• VOSNS and GOSNS of the primary device must be connected to the capacitor at the load
• VOSNS and GOSNS of the secondary devices can either be connected to the output capacitor at the device
or alternatively both pins can be tied to AGND.
• Each device must be configured for the same switching frequency.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
30
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
• The primary device must be configured for forced-PWM operation (secondary devices are automatically
configured for forced-PWM operation).
• A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.
• Only the VSEL pin of the primary device is used to set the default output voltage. The VSEL pin of secondary
devices is not used and must be connected to ground.
• The SDA and SCL pins of secondary devices are not used and must be connected to ground.
• A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase
offset of approximately 120° relative to the adjacent devices in the daisy-chain. To daisy-chain the clocking
signal, connect the SYNCOUT pin of the primary device to the MODE/SYNC pin of the first secondary device.
Connect the SYNCOUT pin of the first secondary device to the MODE/SYNC pin of the second secondary
device. Continue this connection scheme for all devices in the stack, to daisy-chain them together.
• Hiccup overcurrent protection must not be used in a stacked configuration.
In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see 节 8.3.4).
Each device in the stack can pull its EN pin low during device start-up or when a fault occurs. Thus, the stack is
only enabled when all devices have completed their start-up sequence and are fault-free. A fault in any one
device disables the whole stack for as long as the fault condition exists.
During start-up, the primary device pulls the COMP pin low for as long as the enable signal (SYSTEM_READY)
is low. When the enable signal goes high, the primary device actively controls the COMP pin and all devices in
the stack follow the COMP voltage. During start-up, each device in the stack pulls its PG pin low while it
initializes. When initialization is complete, each secondary device in the stack sets its PG pin to a high
impedance and the primary device alone controls the state of the PG signal. The PG pin goes high when the
stack has completed its start-up ramp and the output voltage is within specification. The secondary devices in
the stack detect the rising edge of the power-good signal and switch from DCM operation to CCM operation.
After the stack has successfully started up, the primary device controls the power-good signal in the normal way.
In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all
devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or
undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY)
signal.
Functionality During Stacked Operation
Some device features are not available during stacked operation, or are only available in the primary converter.
表8-8 summarizes the available functionality during stacked operation.
表8-8. Functionality During Stacked Operation
Function
Primary Device
Secondary Device
Remark
UVLO
Yes
Yes
Common enable signal
OVLO
Yes
Yes
Yes
Yes
Common enable signal
Individual
OCP –Current Limit
Do not use during stacked
operation
No
Yes
No
Yes
No
No
No
OCP –Hiccup OCP
Thermal Shutdown
Common enable signal
Primary device only
Primary device only
Power-Good (Window
Comparator)
Yes
I2C Interface
Yes
Voltage loop controlled by
primary device only
DVS
Via I2C
Daisy-chained from primary
device to secondary devices
SSC
Via I2C
No
Synchronization clock applied to
primary device
SYNC
Yes
No
Yes
No
Precise Enable
Only binary enable
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表8-8. Functionality During Stacked Operation (continued)
Function
Primary Device
Secondary Device
Remark
Always enabled in secondary
devices
Output Discharge
Yes
Yes
Fault Handling During Stacked Operation
In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all
devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or
undervoltage lockout event in one device disables all devices via the shared enable (SYSTEM_READY) signal.
表8-9 summarizes the fault handling of the TPS6287x-Q1 devices during stacked operation.
表8-9. Fault Handling During Stacked Operation
Fault Condition
UVLO
Device Response
Enable signal pulled low
Enable signal remains high
System Response
New soft start
OVLO
Thermal Shutdown
Current Limit
Error amplifier clamped
SYNC_OUT and power-stage switch to
internal oscillator
System active but switching frequency is not
synchronized if clk to a secondary device fails
External CLK applied to MODE/SYNC fails
8.4 Device Functional Modes
8.4.1 Power-On Reset
The device operates in POR mode when the supply voltage is less than the POR threshold.
In POR mode no functions are available and the content of the device registers is not valid.
The device leaves POR mode and enters UVLO mode when the supply voltage increases above the POR
threshold.
8.4.2 Undervoltage Lockout
The device operates in UVLO mode when the supply voltage is between the POR and UVLO thresholds.
If the device enters UVLO mode from POR mode, no functions are available. If the device enters UVLO mode
from Standby mode, the output discharge function is available. The content of the device registers is valid in
UVLO mode.
The device leaves UVLO mode and enters POR mode when the supply voltage decreases below the POR
threshold. The device leaves UVLO mode and enters Standby mode when the supply voltage increases above
the UVLO threshold.
8.4.3 Standby
The device operates in standby mode when the supply voltage is greater than the UVLO threshold (and the
device has completed its initialization2) and any of the following conditions is true:
• A low level is applied to the EN pin.
• SWEN = 0 in the CONTROL1 register.
• The device junction temperature is greater than the thermal shutdown threshold.
• The supply voltage is greater than the OVLO threshold.
The following functions are available in standby mode:
2
The device initializes for 400 µs (typical) after the supply voltage increases above the UVLO threshold voltage following a device
power-on reset (f the supply voltage decreases below the UVLO threshold but not below the POR threshold, the device does not
reinitialize when the supply voltage increases again). During initialization the device reads the state of the VSEL, FSEL, and
SYNC_OUT pins.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
32
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
• I2C interface
• Output discharge
• Power good
The device leaves standby mode and enters UVLO mode when the supply voltage decreases below the UVLO
threshold. The device leaves standby mode and enters on mode when all of the following conditions are true:
• A high-level is applied to the EN pin.
• SWEN = 1 in the CONTROL1 register.
• The device junction temperature is below the thermal shutdown threshold.
• The supply voltage is below the OVLO threshold.
8.4.4 On
The device operates in On mode when the supply voltage is greater than the UVLO threshold and all of the
following conditions are true:
• A high-level is applied to the EN pin
• SWEN = 1 in the CONTROL1 register
• The device junction temperature is below the thermal shutdown threshold
• The supply voltage is below the OVLO threshold
All functions are available in On mode.
The device leaves On mode and enters UVLO mode when the supply voltage decreases below the UVLO
threshold. The device leaves On mode and enters the Standby mode when any of the following conditions is
true:
• A low level is applied to the EN pin
• SWEN = 0 in the CONTROL1 register
• The device junction temperature is greater than the thermal shutdown threshold
• The supply voltage is greater than the OVLO threshold
8.5 Programming
8.5.1 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification and User´s Manual, Revision 6, 4 April 2014). The bus consists of a data line (SDA) and a clock
line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C
compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A controller, usually a
microcontroller or a digital signal processor, controls the bus. The controller is responsible for generating the
SCL signal and device addresses. The controller also generates specific conditions that indicate the START and
STOP of data transfer. A target receives or transmits data on the bus under control of the controller.
The TPS6287x-Q1 device operates as a target and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps) and fast mode plus (1 Mbps). The
interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values
depending on the instantaneous application requirements. Register contents remain intact as long as the input
voltage remains above 1.4V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-
mode in this document. The device supports 7-bit addressing; general call addresses are not supported. The
device 7-bt address is selected by the status of pin VSEL (see 表8-5).
The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-mode.
TI recommends that the I2C controller initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pull-up voltages to ensure reset of the I2C engine.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
The controller initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 8-17. All I2C-compatible devices must
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图8-17. START and STOP Conditions
The controller then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the controller ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see 图 8-18). All devices
recognize the address sent by the primary device and compare it to their internal fixed addresses. Only the
target with a matching address generates an acknowledge (see 图 8-19) by pulling the SDA line low during the
entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows that the
communication link with a target has been established.
DATA
CLK
Data line stable
Change
data valid
of data
allowed
图8-18. Bit Transfer on the Serial Interface
The controller generates further SCL cycles to either transmit data to the target (write comand; R/W = 0) or
receive data from the target (read command; R/W = 1). In either case, the receiver needs to acknowledge the
data sent by the transmitter. So an acknowledge signal can either be generated by the controller or by the target,
depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit
acknowledge can continue as long as necessary.
To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see 图 8-17). This releases the bus and stops the communication link with the
addressed target. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL from
1
2
8
9
Controller
S
Clock Pulse for
START
Acknowledgement
Condition
图8-19. Acknowledge on the I2C Bus
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
34
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Recognize START or
REPEATED START
condition
Recognize STOP or
REPEATED START
condition
Generate ACKNOWLEDGE
signal
P
SDA
MSB
acknowledgement
signal from Target
acknowledgement
signal from receiver
Sr
SCL
1
2
7
8
9
1
2
3 to 8
9
S or Sr
Sr or P
ACK
ACK
START or
repeated START
condition
byte complete,
interrupt within target
clock line held low while
interrupts are serviced
STOP or
repeated START
condition
图8-20. Bus Protocol
8.5.3 HS-Mode Protocol
The controller generates a start condition followed by a valid serial byte containing HS controller code
00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to
acknowledge the HS controller code, but all devices must recognize it and switch their internal setting to support
3.4 Mbps operation.
The controller then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the target devices to support the F/S-mode. Instead of using a stop condition, repeated start
conditions must be used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
8.5.4 I2C Update Sequence
This requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update.
After the receipt of each byte, device acknowledges by pulling the SDA line low during the high period of a single
clock pulse. A valid I2C address selects the device. The device performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8
1
7
1
1
8
1
1
1
S
Device Address
R/W
A
Register Address
A
Data
A/A
P
“0” Write
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
From Controller to Target
From Target to Controller
S
= START condition
Sr = REPEATED START condition
= STOP condition
P
图8-21. : “Write”Data Transfer Format in Standard-, Fast, Fast-Plus Modes
8
1
7
1
1
8
1
1
7
1
1
1
1
S
Device Address
R/W
A
Register Address
A
Sr
Device Address
R/W
A
Data
A
P
“0” Write
“1” Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
From Controller to Target
From Target to Controller
S
= START condition
Sr = REPEATED START condition
= STOP condition
P
图8-22. “Read”Data Transfer Format in Standard-, Fast, Fast-Plus Modes
F/S Mode
HS Mode
8
F/S Mode
8
1
8
1
1
7
1
1
1
1
1
S
HS-Code
A
Sr
Device Address
R/W
A
Register Address
A
Data
A/A
P
(n x Bytes + Acknowledge)
HS Mode continues
Device Address
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
From Controller to Target
From Target to Controller
Sr
S
= START condition
Sr = REPEATED START condition
= STOP condition
P
图8-23. Data Transfer Format in HS-Mode
8.5.5 I2C Register Reset
The I2C registers can be reset by:
• pulling the input voltage below 1.4 V (typ).
• or setting the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new startup is begun immediately. After tDelay, the I2C registers can be programmed again.
8.5.6 Dynamic Voltage Scaling (DVS)
To optimize the power consumption of the system, the output voltage of the TPS6287x-Q1 can be adapted
during operation based on the actual power requirement of the load.
The device starts up into the default output voltage selected through the external VSEL pin or the settings in the
VSET register. The output voltage can be dynamically adapted via the I2C interface by writing the new target
output voltage to the VSET register. The output voltage then increases or decrease to the desired value with the
voltage ramp speed defined in the CONTROL1 register.
Switching between different output voltage ranges
TPS6287x-Q1 devices offer three different output voltages ranges as defined in the CONTROL2 register. To
change the output voltage range of TPS6287x-Q1, first step to the closest output voltage value within the
currently used range, then change the VRANGE bit in the CONTROL2 register to the next VRANGE seting. After
that set the target output voltage in the VSET register.
Note that a change in the output voltage range always must be followed by writing to the VSET Register, even
though the output voltage does not change. The code in the VSET register must be updated to the correct value
in the new range.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
36
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.6 Device Registers
表 8-10 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in 表
8-10 must be considered as reserved locations and the register contents must not be modified.
表8-10. DEVICE Registers
Address
Acronym
VSET
Register Name
Output Voltage Setpoint
Control 1
Section
Go
0h
1h
2h
3h
4h
CONTROL1
CONTROL2
CONTROL3
STATUS
Go
Control 2
Go
Control 3
Go
Status
Go
Complex bit access types are encoded to fit into small table cells. 表 8-11 shows the codes that are used for
access types in this section.
表8-11. Device Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.6.1 VSET Register (Address = 0h) [Reset = X]
VSET is shown in 图8-24 and described in 表8-12.
Return to the Summary Table.
This register controls the output voltage setpoint
图8-24. VSET Register
7
6
5
4
3
2
1
0
VSET
R/W-X
表8-12. VSET Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
VSET
R/W
X
Output voltage setpoint (see also the range-setting bits in the
CONTROL2 register).
Range 1: Output voltage setpoint = 0.4 V + VSET[7:0] × 1.25 mV
Range 2: Output voltage setpoint = 0.4 V + VSET[7:0] × 2.5 mV
Range 3: Output voltage setpoint = 0.4 V + VSET[7:0] × 5 mV
The state of the VSEL pin during power up determines the reset
value.
Copyright © 2023 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.6.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah]
CONTROL1 is shown in 图8-25 and described in 表8-13.
Return to the Summary Table.
This register controls various device configuration options
图8-25. CONTROL1 Register
7
6
5
4
3
2
1
0
VRAMP
RESET
R/W-0b
SSCEN
R/W-0b
SWEN
R/W-1b
FPWMEN
R/W-0b
DISCHEN
R/W-1b
HICCUPEN
R/W-0b
R/W-10b
表8-13. CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0b
Reset device.
0b = No effect
1b = The device is powered down, the pin status is read and all
registers are reset to their default value. The device is then powered
up again starting with a soft-start cycle.
Reading this bit always returns 0.
6
5
4
SSCEN
SWEN
R/W
R/W
R/W
0b
1b
0b
Spread spectrum clocking enable.
0b = SSC operation disabled
1b = SSC operation enabled
Software enable.
0b = Switching disabled (register values retained)
1b = Switching enabled (without the enable delay)
FPWMEN
Forced-PWM enable.
0b = Power-save operation enabled
1b = Forced-PWM operation enabled
This bit is logically ORed with the MODE/SYNC pin: If a high level or
a synchronization clock is applied to the the MODE/SYNC pin, the
device operates in Forced-PWM, regardless of the state of this bit.
3
2
DISCHEN
R/W
R/W
1b
0b
Output discharge enable.
0b = Output discharge disabled.
1b = Output discharge enabled.
HICCUPEN
Hiccup operation enable.
0b = Hiccup operation disabled
1b = Hiccup operation enabled. Do not enable Hiccup operation
during stacked operation
1-0
VRAMP
R/W
10b
Output voltage ramp speed when changing from one output voltage
setting to another.
00b = 10 mV/µs
01b = 5 mV/µs
10b = 1.25 mV/µs
11b = 0.5 mV/µs
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.6.3 CONTROL2 Register (Address = 2h) [Reset = 0Ah]
CONTROL2 is shown in 图8-26 and described in 表8-14.
Return to the Summary Table.
This register controls various device configuration options
图8-26. CONTROL2 Register
7
6
5
4
3
2
1
0
RESERVED
SYNC_OUT_P
HASE
VRANGE
R/W-10b
SSTIME
R/W-10b
R/W-000b
R/W-0b
表8-14. CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000b
Reserved for future use. To ensure compatibility with future device
variants, program these bits to 0.
4
SYNC_OUT_PHASE
R/W
R/W
R/W
0b
Phase shift of SYNC_OUT with reference to internal clk or external
clk applied at MODE/SYNC.
0b = SYNC_OUT is phase shifted by 120°
1b = SYNC_OUT is phase shifted by 180° The phase relation of
180° is only valid from the primary to the first secondary converter.
3-2
1-0
VRANGE
SSTIME
10b
10b
Output voltage range.
00b = 0.4 V to 0.71875 V in 1.25-mV steps
01b = 0.4 V to 1.0375 V in 2.5-mV steps
10b = 0.4 V to 1.675 V in 5-mV steps
11b = 0.4 V to 1.675 V in 5-mV steps
Soft-start ramp time.
00b = 0.5 ms
01b = 0.77 ms
10b = 1 ms
11b = 2 ms
Copyright © 2023 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.6.4 CONTROL3 Register (Address = 3h) [Reset = 00h]
CONTROL3 is shown in 图8-27 and described in 表8-15.
Return to the Summary Table.
This register controls various device configuration options
图8-27. CONTROL3 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-00000b
DROOPEN
R/W-0b
SINGLE
R/W-0b
PGBLNKDVS
R/W-0b
表8-15. CONTROL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000b
Reserved for future use. To ensure compatibility with future device
variants, program these bits to 0.
2
DROOPEN
R/W
R/W
0b
0b
Droop compensation enable
0b = droop compensation disabled
1b = droop compensation enabled
1
0
SINGLE
Single operation. This bit controls the internal EN pulldown and
SYNCOUT functions.
0b = EN pin pulldown and SYNCOUT enabled
1b = EN pin pulldown and SYNCOUT disabled. Do not set during
stacked operation
PGBLNKDVS
R/W
0b
Power-good blanking during DVS.
0b = PG pin reflects the output of the window comparator
1b = PG pin is high impedance during DVS
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
8.6.5 STATUS Register (Address = 4h) [Reset = 00h]
STATUS is shown in 图8-28 and described in 表8-16.
Return to the Summary Table.
This register returns the device status flags
图8-28. STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W-00b
HICCUP
R/W-0b
ILIM
TWARN
R/W-0b
TSHUT
R/W-0b
PBUV
R/W-0b
PBOV
R/W-0b
R/W-0b
表8-16. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00b
Reserved for future use. To ensure compatibility with future device
variants, ignore these bits.
5
HICCUP
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
Hiccup. This bit reports whether a hiccup event occurred since the
last time the STATUS register was read.
0b = No hiccup event occured
1b = A hiccup event occurred
4
3
2
1
ILIM
Current limit. This bit reports whether an current limit event occurred
since the last time the STATUS register was read.
0b = No current limit event occured
1b = An current limit event occurred
TWARN
TSHUT
PBUV
Thermal warning. This bit reports whether a thermal warning event
occurred since the last time the STATUS register was read.
0b = No thermal warning event occurred
1b = A thermal warning event occurred
Thermal shutdown. This bit reports whether a thermal shutdown
event occurred since the last time the STATUS register was read.
0b = No thermal shutdown event occurred
1b = A thermal shutdown event occurred
Power-bad undervoltage. This bit reports whether a power-bad event
(output voltage too low) occurred since the last time the STATUS
register was read.
0b = No power-bad undervoltage event occurred
1b = A power-bad undervoltage event occurred
0
PBOV
R/W
0b
Power-bad overvoltage. This bit reports whether a power-bad event
(output voltage too high) occurred since the last time the STATUS
register was read.
0b = No power-bad overvoltage event occurred
1b = A power-bad overvoltage event occurred
Copyright © 2023 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The following section discusses selection of the external components to complete the power supply design for a
typical application.
9.2 Typical Application
TPS6287x-Q1
CLOAD
L1
VOUT
VIN
VIO
VIN
VIN
SW
COUT
CIN
MODE/SYNC
REN
Load
RSDA
EN
VOSNS
GOSNS
RSCL
SDA
SCL
I2C
AGND
RZ
VSEL
FSEL
VIO
CC2
CC
RPG
COMP
PG
PG
SYNC_OUT
AGND
GND
GND
图9-1. Typical Application Schematic
9.2.1 Design Requirements
表9-1 lists the operating parameters for this application example.
表9-1. Design Parameters
SYMBOL
PARAMETER
VALUE
3.3 V
VIN
VOUT
TOLVOUT
TOLDC
ΔIOUT
tr
Input voltage
Output voltage
0.75 V
±3.3%
±0.8%
±7.5 A
Output voltage tolerance allowed by the application
Output voltage tolerance of the TPS6287x-Q1 (DC accuracy)
Output current load step
Load step rise time
1 μs
1 μs
tf
Load step fall time
fSW
Switching frequency
2.25 MHz
80nH
L
Inductance
gm
Error amplifier transconductance
Internal timing parameter
1.5 mS
12.5 μs
τ
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表9-1. Design Parameters (continued)
SYMBOL
kBW
PARAMETER
VALUE
4
Ratio of switching frequency to converter bandwidth (must be ≥4)
Ratio of minimum to maximum output capacitance (typically 2)
Pullup resistor on power-good output
kCOUT
2
RPG
10 kΩ
22 kΩ
680 Ω
REN
Pullup resistor on enable
RSCL, RSDA
Pullup resistors on SDA and SCL
Preliminary Calculations
With a total allowable output voltage tolerance of ±3.3% and a maximum DC error of ±0.8%, the allowable output
voltage tolerance during a load step is given by:
∆ V
∆ V
= ±V
× TOL
– TOL
DC
(4)
(5)
OUT
OUT
OUT
VOUT
= ± 0.75 × 0.033 – 0.008 = ± 18.75 mV
9.2.2 Detailed Design Procedure
The following subsections describe how to calculate the external components required to meet the specified
transient requirements of a given application. The calculations include the worst-case variation of components
and use the RMS method to combine the variation of uncorrelated parameters.
9.2.2.1 Inductor Selection
The TPS6287x-Q1 devices have been optimized for inductors in the the range 42 nH to 200 nH. If the transient
response of the converter is limited by the slew rate of the current in the inductor, using a smaller inductor can
improve performance. However, the output ripple current increases as the value of the inductor decreases, and
higher output current ripple generates higher output voltage ripple, which adds to the transient over- or
undershoot. The optimum configuration for a given application is a trade-off between a number of parameters.
We recommend a starting value of 60 nH to 80 nH for typical applications.
The inductor ripple current is given by:
V
V
– V
OUT IN OUT
I
=
=
(6)
(7)
L PP
L PP
V
L × f
IN
sw
0.75
3.3
3.3 – 0.75
–9
I
A = 3.22 A
6
80 × 10 × 2.25 × 10
表9-2 lists a number of inductors suitable for use with this application. This list is not exhaustive, however, and
other inductors from other manufacturers may also be suitable.
表9-2. Typical Inductors
DC
DIMENSIONS
[LxWxH] mm
PART NUMBER
INDUCTANCE [µH] CURRENT [A]
Notes
MANUFACTURER
RESISTANCE
0.056 µH
IHSR2525CZ-5A
XEL4030-101ME
45
22
6.65 × 6.65 × 3
4 × 4 × 3.2
Vishay
0.38 mΩ
1.5 mΩ
For f ≥2.25 MHz
For f ≥1.5 MHz
0.10 µH, ±20%
Coilcraft
744302010
0.105 µH
0.16 µH
30
25
7 × 7 × 4.8
Wurth
0.235 mΩ
For f ≥1.5 MHz
XGL5030-161ME
5.3 × 5.5 × 3
Coilcraft
1.3 mΩ
For f ≥1.5 MHz
For f ≥2.25 MHz
0.22 mΩ
744300006
CLT32-55N
CLT32-42N
0.06 µH
0.055 µH
0.042 µH
37
28
28
8.64 × 6.35 × 4.5
2.5 × 3.2 × 2.5
2.5 × 3.2 × 2.5
Wurth
TDK
1 mΩ
1 mΩ
For f ≥2.25 MHz
For f ≥2.25 MHz
TDK
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
44
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表9-2. Typical Inductors (continued)
DC
DIMENSIONS
[LxWxH] mm
PART NUMBER
INDUCTANCE [µH] CURRENT [A]
Notes
MANUFACTURER
RESISTANCE
HPL505032F1060MRD3
P
0.06 µH
0.08 µH
34
34
5 × 5 × 3.2
5 × 5 × 3.2
TDK
TDK
0.7 mΩ
For f ≥2.25 MHz
For f ≥2.25 MHz
HPL505028F080MRD3P
0.8 mΩ
9.2.2.2 Selecting the Input Capacitors
As with all buck converters, the input current of the TPS6287x-Q1 devices is discontinuous. The input capacitors
provide a low-impedance energy source for the device, and their value, type, and location are critical for correct
operation. TI recommends low-ESR multilayer ceramic capacitors for best performance. In practice, the total
input capacitance typically comprises a combination of different capacitors, in which larger capacitors provide the
decoupling at lower frequencies and smaller capacitors provide the decoupling at higher frequencies.
The TPS6287x-Q1 devices feature a butterfly layout with two VIN pin pairs on opposite sides of the package.
This allows the input capacitors to be placed symmetrically on the PCB such that the electromagnetic fields
generated cancel each other out, thereby reducing EMI.
The duty cycle of the converter is given by:
V
OUT
D =
(8)
η × V
IN
where:
• VIN is the input voltage
• VOUT is the output voltage
• ηis the effciency
0.75
0.9 × 3.3
D =
= 0.253
(9)
The value of input capacitance needed to meet the input voltage ripple requirements is given by:
D × 1 − D × I
OUT
C
=
(10)
IN
V
× f
IN PP
sw
where:
• D is the duty cycle
• fsw is the switching frequency
• VIN(PP) is the input voltage ripple
• IOUT is the output current
0.253 × 1 − 0.253 × 11.3
C
=
F = 9.5 μF
(11)
IN
6
0.1 × 2.25 × 10
The value of CIN calculated with 方程式 10 is the effective capacitance after all derating, tolerance, and ageing
effects have been considered. We recommend multilayer ceramic capacitors with an X7R dielectric (or similar)
for CIN, and these capacitors must be placed as close to the VIN and GND pins as possible, so as to minimize
the loop area.
表9-3 lists a number of capacitors suitable for this application. This list is not exhaustive, however, and other
capacitors from other manufacturers may also be suitable.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表9-3. List of Recommended Input Capacitors
DIMENSIONS
CAPACITANCE
VOLTAGE RATING
MANUFACTURER, PART NUMBER
mm (inch)
1005 (0402)
1005 (0402)
2012 (0805)
470 nF ±10%
470 nF ±10%
10 μF ±10%
10 μF ±10%
22 μF ±10%
22 μF ±20%
10 V
10 V
10 V
Murata, GCM155C71A474KE36D
TDK, CGA2B3X7S1A474K050BB
Murata, GCM21BR71A106KE22L
2012 (0805)
3216 (1206)
3216 (1206)
10 V
10 V
10 V
TDK, CGA4J3X7S1A106K125AB
Murata, GCM31CR71A226KE02L
TDK, CGA5L1X7S1A226M160AC
9.2.2.3 Selecting the Compensation Resistor
Use 方程式12 to calculate the recommended value of compensation resistor RZ:
π × ∆ I
OUT
× L
1
R =
1 + TOL
(12)
Z
IND
g
4 × τ × ∆ V
m
OUT
–9
1
π × 7.5 × 80 × 10
–6
R =
1 + 0.2 Ω = 1.95 kΩ
(13)
Z
–3
–3
1.5 × 10
4 × 12.5 × 10 × 18.75 × 10
Rounding up, the closest standard value from the E24 series is 2.0 kΩ.
9.2.2.4 Selecting the Output Capacitors
In practice, the total output capacitance typically comprises a combination of different capacitors, in which larger
capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at higher
frequencies. The value, type, and location of the output capacitors are critical for correct operation. TI
recommends low-ESR multilayer ceramic capacitors with an X7R dielectric (or similar) for best performance.
The TPS6287x-Q1 devices feature a butterfly layout with two GND pins on opposite sides of the package. This
allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields
generated cancel each other out, thereby reducing EMI.
The transient response of the converter is defined by one of two criteria:
• The loop bandwidth, which must be at least 4 times smaller than the switching frequency.
• The slew rate of the current through the inductor and the output capacitance.
In typical low-output-voltage application, this is limited by the value of the output voltage and the inductors.
Which of the above criteria applies in any given application depends on the operating conditions and component
values used. We therefore recommend calculating the output capacitance for both cases, and selecting the
higher of the two values.
If the converter remains in regulation, the minimum output capacitance required is given by:
τ × g × R
m
Z
2
2
C
=
=
1 + TOL
+ TOL
fSW
(14)
(15)
OUT min reg
OUT min reg
IND
f
SW
2 × π × L ×
4
−6
12.5 × 10
−3
3
× 1.5 × 10
× 2 . 0 × 10
2
2
C
1 + 20% + 10% F = 162 μF
6
2.25 × 10
−9
2 × π × 80 × 10
×
4
If the converter loop saturates, the minimum output capacitance is given by:
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
46
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
2
I
L PP
2
L × ∆ I
OUT
+
∆ I
× t
t
1
OUT
2
C
C
=
=
–
1 + TOL
(16)
(17)
OUT min sat
IND
∆ V
2 × V
OUT
OUT
2
–
3.22
2
–9
80 × 10 × 7.5 +
2 × 0.75
–6
1
7.5 × 1 × 10
2
1 + 20% F = 43 μF
OUT min sat
–3
18.75 × 10
In this case, choose COUT(min) = 162 µF, as the larger of the two values, for the output capacitance.
When calculating worst-case component values, use the value calculated above as the minimum output
capacitance required. For ceramic capacitors, the nominal capacitance when considering tolerance, DC bias,
temperature, and aging effects is typically two times the minimum capacitance. In this case the nominal
capacitance is thus 324 μF.
表9-4. List of Recommended Output Capacitors
DIMENSIONS
CAPACITANCE
VOLTAGE RATING
MANUFACTURER, PART NUMBER
mm (inch)
2012 (0805)
2012 (0805)
3216 (1206)
2012 (0805)
3225 (1210)
3216 (1210)
6.3 V
6.3 V
4 V
TDK, CGA4J1X7T0J226M125AC
Murata, GCM31CR71A226KE02
TDK, CGA5L1X7T0G476M160AC
Murata, GCM32ER70J476ME19
TDK, CGA6P1X7T0G107M250AC
Murata, GRT32EC70J107ME13
22 μF ±20%
22 μF ±10%
47 μF ±20%
47 μF ±20%
100 μF ±20%
100 μF ±20%
6.3 V
4 V
6.3 V
9.2.2.5 Selecting the Compensation Capacitor CC
First, use 方程式18 to calculate the bandwidth of the loop:
τ × g × R
m
Z
BW =
BW =
(18)
(19)
2 × π × L × C
× k
COUT
OUT, min
−6
−3
3
12.5 × 10
× 1.5 × 10
× 2 × 10
= 230kHz
−9
−6
2 × π × 80 × 10
× 162 × 10
× 2
Use 方程式20 to calculate the recommended value of CC.
k
BW
C =
(20)
(21)
C
2 × π × BW × R
Z
4
C =
= 1.38 nF
3
C
3
2 × π × 230 × 10 × 2 × 10
The closest standard value from the E12 series is 1.5 nF.
9.2.2.6 Selecting the Compensation Capacitor CC2
The compensation capacitor CC2 is an optional capacitor that we recommend you include to bypass high-
frequency noise from the COMP pin. The value of this capacitor is not critical; 10-pF or 22-pF capacitors are
suitable for typical applications.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9.2.3 Application Curves
0.5865
0.585
90
85
80
75
70
65
60
0.5835
0.582
0.5805
0.579
0.5775
0.576
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
0.5745
0.573
0.5715
0
5
10
15
20
25
30
Output Current (A)
0
5
10
15
20
25
30
D002
Output Current (A)
D002
VOUT = 0.58 V
PWM; droop
disabled
TA = 25°C
VOUT = 0.58 V
PWM
TA = 25°C
图9-2. Efficiency Versus Output Current
图9-3. Output Voltage Versus Output Current
0.592
0.59
95
90
85
80
75
0.588
0.586
0.584
0.582
0.58
0.578
0.576
0.574
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
0.572
0.57
70
65
0.568
0.566
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Current (A)
D002
Output Current (A)
D002
VOUT = 0.58 V
PWM; TPS62877
droop enabled
TA = 25°C
VOUT = 0.75 V
PWM
TA = 25°C
图9-5. Efficiency Versus Output Current
图9-4. Output Voltage Versus Output Current
Copyright © 2023 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
0.7575
0.756
0.7545
0.753
0.7515
0.75
0.762
0.76
0.758
0.756
0.754
0.752
0.75
0.748
0.746
0.744
0.742
0.74
0.7485
0.747
0.7455
0.744
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
0.738
0.736
0.7425
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Current (A)
Output Current (A)
D002
D002
VOUT = 0.75 V
PWM; droop
disabled
TA = 25°C
VOUT = 0.75 V
PWM; TPS62877
droop enabled
TA = 25°C
图9-6. Output Voltage Versus Output Current
图9-7. Output Voltage Versus Output Current
0.808
0.807
0.806
0.805
0.804
0.803
0.802
0.801
0.8
0.799
0.798
0.797
0.796
0.795
0.794
0.793
0.792
95
90
85
80
75
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
70
65
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Current (A)
D002
Output Current (A)
D002
VOUT = 0.8 V
PWM; droop
disabled
TA = 25°C
VOUT = 0.8 V
PWM
TA = 25°C
图9-8. Efficiency Versus Output Current
图9-9. Output Voltage Versus Output Current
0.8125
0.81
95
90
85
80
75
0.8075
0.805
0.8025
0.8
0.7975
0.795
0.7925
0.79
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
V
V
IN = 2.7 V
IN = 3.3 V
VIN = 4.0 V
70
65
V
V
IN = 5.0 V
IN = 6.0 V
0.7875
0
5
10
15
20
25
30
Output Current (A)
0
5
10
15
20
25
30
D002
Output Current (A)
D002
VOUT = 0.8 V
PWM; TPS62877
droop enabled
TA = 25°C
VOUT = 1.0 V
PWM
TA = 25°C
图9-11. Efficiency Versus Output Current
图9-10. Output Voltage Versus Output Current
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
1.0125
1.01
1.01
1.008
1.006
1.004
1.002
1
1.0075
1.005
1.0025
1
0.9975
0.995
0.9925
0.99
0.998
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
0.996
0.994
0.992
0.99
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
0.9875
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Current (A)
Output Current (A)
D002
D002
VOUT = 1.0 V
PWM; TPS62877
droop enabled
TA = 25°C
VOUT = 1.0 V
PWM; droop
disabled
TA = 25°C
图9-13. Output Voltage Versus Output Current
图9-12. Output Voltage Versus Output Current
VOUT = 0.75 V
VIN = 5 V
PWM
TA = 25°C
VOUT = 0.75 V
VIN = 5 V
PWM
TA = 25°C
RLOAD = 66mΩ
RLOAD = 66mΩ
图9-14. Start-Up Timing
图9-15. Output Voltage Ripple
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
50
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
VOUT = 0.75 V
VIN = 5 V
PWM, TPS62874
droop disabled
TA = 25°C
VOUT = 0.75 V
VIN = 5 V
PWM, TPS62874
droop enabled
TA = 25°C
Iout = 3.8A to 11.3A to 3.8A
Iout = 3.8A to 11.3A to 3.8A
图9-16. Load Transient Response
图9-17. Load Transient Response
VOUT = 0.75 V
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
IOUT = 11.3 A
图9-18. Line Transient Response
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9.3 Application Using Two TPS62876-Q1 in a Stacked Configuration
TPS62876-Q1
(Primary Device)
CLOAD
L
VIN
2.7 V to 6 V
VIN
VIN
SW
COUT
CIN
VIO
REN
MODE/SYNC
Load
EN
VOSNS
GOSNS
SDA
SCL
I2C
VIO
RZ
AGND
COMP
PG
CC
VSEL
FSEL
CC2
RPG
RVSEL
RFSEL
PG
AGND
GND
GND
SYNC_OUT
TPS62876-Q1
(Secondary Device)
L
VIN
VIN
SW
MODE/SYNC
CIN
COUT
GOSNS
VOSNS
EN
SDA
SCL
VSEL
COMP
PG
FSEL
RFSEL
AGND
GND
GND
SYNC_OUT
47 k
图9-19. Stacking Two Devices
9.3.1 Design Requirements For Two Stacked Devices
表9-5 lists the operating parameters for this application example.
表9-5. Design Parameters
SYMBOL
PARAMETER
VALUE
VIN
Input voltage
3.3 V
0.8 V
±4%
VOUT
TOLVOUT
TOLDC
ΔIOUT
tr
Output voltage
Output voltage tolerance allowed by the application
Output voltage tolerance of the TPS62876-Q1 -Q1 (DC accuracy)
Output current load step
±0.8%
±24 A
Load step rise time
1 μs
1 μs
tf
Load step fall time
fSW
Switching frequency
2.25 MHz
56 nH
1.5 ms
12.5 μs
4
L
Inductance
gm
Error amplifier transconductance
Internal timing parameter
τ
kBW
Ratio of switching frequency to converter bandwidth (must be ≥4)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
52
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表9-5. Design Parameters (continued)
SYMBOL
PARAMETER
VALUE
2
NΦ
kCOUT
RPG
Number of phases (number of stacked devices)
Ratio of minimum to maximum output capacitance (typically 2)
Pullup resistor on power-good output
Pullup resistor on enable
2
10 kΩ
22 kΩ
680 Ω
REN
RSCL, RSDA
Pullup resistors on SDA and SCL
Preliminary Calculations
With a total allowable output voltage tolerance of ±4% and a maximum DC error of ±0.8%, the allowable output
voltage tolerance during a load step is given by:
∆ V
∆ V
= ±V
× TOL
– TOL
DC
(22)
(23)
OUT
OUT
OUT
VOUT
= ± 0.8 × 0.04 – 0.008 = ± 25 . 6 mV
9.3.2 Detailed Design Procedure
9.3.2.1 Selecting the Compensation Resistor
The calculation for a stack of two converters is similar to the single device expect that the parameter "number of
phases" NΦ is added to the equations. Use 方程式 24 to calculate the recommended value of compensation
resistor RZ:
π × ∆ I
OUT
× L
1
R =
1 + TOL
(24)
(25)
Z
IND
g
4 × τ × N × ∆ V
m
ϕ
OUT
–9
1
π × 24 × 56 × 10
–6
R =
1 + 0.2 Ω = 1.32 kΩ
Z
–3
–3
1.5 × 10
4 × 12.5 × 10 × 2 × 25.6 × 10
Rounding up, the closest standard value from the E24 series is 1.5 kΩ.
9.3.2.2 Selecting the Output Capacitors
If the converter remains in regulation, the minimum output capacitance required is given by:
τ × g × R
m
Z
f
2
2
C
=
=
1 + TOL
+ TOL
fSW
(26)
(27)
OUT min reg
IND
L
SW
4
2 × π ×
×
N
ϕ
−6
−3
3
12.5 × 10
× 1.5 × 10
× 1 . 5 × 10
2
2
C
1 + 20% + 10% F = 350 μF
OUT min reg
−9
6
56 × 10
2
2.25 × 10
2 × π ×
×
4
If the converter loop saturates, the minimum output capacitance is given by:
2
I
L PP
2
L
×
∆ I +
OUT
N
∆ I
× t
t
ϕ
1
OUT
2
C
=
–
1 + TOL
(28)
OUT min sat
IND
∆ V
2 × V
OUT
OUT
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
–9
2
56 × 10
2
2 . 4
2
× 24 +
–6
1
24 × 1 × 10
2
C
=
–
1 + 20% F = − 90 μF
(29)
OUT min sat
–3
2 × 0.8
25.6 × 10
In this case, choose COUT(min) = 350 µF, as the larger of the two values, for the output capacitance.
When calculating worst-case component values, use the value calculated above as the minimum output
capacitance required. For ceramic capacitors, the nominal capacitance when considering tolerance, DC bias,
temperature, and aging effects is typically two times the minimum capacitance. In this case the nominal
capacitance is thus 700 μF.
9.3.2.3 Selecting the Compensation Capacitor CC
τ × g × R
m
Z
BW =
BW =
(30)
(31)
L
N
2 × π ×
× C
× k
COUT
OUT, min
∅
−6
12.5 × 10
−3
3
× 1.5 × 10
× 1.5 × 10
= 230kHz
−9
56 × 10
2
−6
2 × π ×
× 350 × 10
× 2
Next, calculate CC:
k
BW
2 × π × BW × R
C =
(32)
(33)
C
Z
4
C =
= 1.85 nF
3
C
3
2 × π × 230 × 10 × 1.5 × 10
The closest standard value from the E12 series is 2.2 nF.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
54
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9.3.3 Application Curves for Two Stacked Devices
0.808
0.807
0.806
0.805
0.804
0.803
0.802
0.801
0.8
0.799
0.798
0.797
0.796
0.795
0.794
0.793
0.792
95
90
85
80
75
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
70
65
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Current (A)
D002
Output Current (A)
D002
VOUT = 0.8 V
PWM
TA = 25°C
VOUT = 0.8 V
PWM
TA = 25°C
图9-21. Output Voltage Versus Output Current
图9-20. Efficiency Versus Output Current
VOUT = 0.8 V
VIN = 5 V
PWM
TA = 25°C
VOUT = 0.8 V
VIN = 5 V
PWM
TA = 25°C
RLOAD = 20 mΩ
RLOAD = 20 mΩ
图9-22. Start-Up Timing
图9-23. Output Voltage Ripple
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
VOUT = 0.8 V
VIN = 5 V
PWM; TPS62876
droop disabled
TA = 25°C
VOUT = 0.8 V
VIN = 5 V
PWM; TPS62876
droop enabled
TA = 25°C
Iout = 15 A to 40 A to 15 A
Iout = 15 A to 40 A to 15 A
图9-24. Load Transient Response
图9-25. Load Transient Response
VOUT = 0.8 V
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
IOUT = 40 A
图9-26. Line Transient Response
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
56
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9.4 Application Using Three TPS62876-Q1 in a Stacked Configuration
TPS62876-Q1
(Primary Device)
CLOAD
L
VIN
2.7 V to 6 V
VIN
VIN
SW
COUT
CIN
VIO
REN
MODE/SYNC
Load
EN
VOSNS
GOSNS
SDA
SCL
I2C
VIO
RZ
AGND
COMP
PG
CC
VSEL
FSEL
CC2
RPG
RVSEL
RFSEL
PG
AGND
GND
GND
SYNC_OUT
TPS62876-Q1
(Secondary Device)
L
VIN
VIN
SW
MODE/SYNC
CIN
COUT
GOSNS
VOSNS
EN
SDA
SCL
VSEL
COMP
PG
FSEL
RFSEL
AGND
GND
GND
SYNC_OUT
47 k
TPS62876-Q1
(Secondary Device)
L
VIN
VIN
SW
CIN
MODE/SYNC
COUT
GOSNS
VOSNS
EN
SDA
SCL
VSEL
COMP
PG
FSEL
RFSEL
AGND
GND
GND
SYNC_OUT
47 k
图9-27. Stacking Three Devices
9.4.1 Design Requirements For Three Stacked Devices
表9-6 lists the operating parameters for this application example.
表9-6. Design Parameters
SYMBOL
PARAMETER
VALUE
3.3 V
VIN
Input voltage
VOUT
Output voltage
0.875 V
±3%
TOLVOUT
TOLDC
Output voltage tolerance allowed by the application
Output voltage tolerance of the TPS62876-Q1 -Q1 (DC accuracy)
±0.8%
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
表9-6. Design Parameters (continued)
SYMBOL
PARAMETER
VALUE
Output current load step
±46 A
ΔIOUT
tr
tf
Load step rise time
1 μs
1 μs
2.25 MHz
56 nH
1.5 ms
12.5 μs
4
Load step fall time
fSW
Switching frequency
Inductance
L
gm
Error amplifier transconductance
Internal timing parameter
τ
kBW
NΦ
Ratio of switching frequency to converter bandwidth (must be ≥4)
Number of phases (number of stacked devices)
Ratio of minimum to maximum output capacitance (typically 2)
Pullup resistor on power good output
3
kCOUT
RPG
REN
RSCL, RSDA
2
10 kΩ
22 kΩ
680 Ω
Pullup resistor on enable
Pullup resistors on SDA and SCL
Preliminary Calculations
With a total allowable output voltage tolerance of ±3% and a maximum DC error of ±0.8%, the allowable output
voltage tolerance during a load step is given by:
∆ V
∆ V
= ±V
× TOL
– TOL
DC
(34)
(35)
OUT
OUT
OUT
VOUT
= ± 0.875 × 0.03 – 0.008 = ± 19.25 mV
9.4.2 Detailed Design Procedure
9.4.2.1 Selecting the Compensation Resistor
The calculation for a stack of two converters is similar to the single device expect that the parameter "number of
phases" NΦ is added to the equations. Use 方程式 36 to calculate the recommended value of compensation
resistor RZ:
π × ∆ I
OUT
× L
1
R =
1 + TOL
(36)
(37)
Z
IND
g
4 × τ × N × ∆ V
m
ϕ
OUT
–9
1
π × 46 × 56 × 10
–6
R =
1 + 0.2 Ω = 2.29 kΩ
Z
–3
–3
1.5 × 10
4 × 12.5 × 10 × 3 × 19.25 × 10
Rounding up, the closest standard value from the E24 series is 2.4 kΩ.
9.4.2.2 Selecting the Output Capacitors
If the converter remains in regulation, the minimum output capacitance required is given by:
τ × g × R
m
Z
f
2
IND
2
C
=
1 + TOL
+ TOL
fSW
(38)
OUT min reg
L
SW
4
2 × π ×
×
N
ϕ
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
58
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
−6
−3
3
12.5 × 10
× 1.5 × 10
× 2 . 4 × 10
6
2
2
C
=
1 + 20% + 10% F = 838 μF
(39)
OUT min reg
−9
56 × 10
3
2.25 × 10
4
2 × π ×
×
If the converter loop saturates, the minimum output capacitance is given by:
2
I
L PP
2
L
×
∆ I +
OUT
N
∆ I
× t
t
ϕ
1
OUT
2
C
C
=
=
–
1 + TOL
(40)
(41)
OUT min sat
IND
∆ V
2 × V
OUT
OUT
–9
2
56 × 10
3
2 . 4
2
× 46 +
–6
1
46 × 1 × 10
2
–
1 + 20% F = 25.7 μF
OUT min sat
–3
2 × 0.875
19.25 × 10
In this case, choose COUT(min) = 838 µF, as the larger of the two values, for the output capacitance.
When calculating worst-case component values, use the value calculated above as the minimum output
capacitance required. For ceramic capacitors, the nominal capacitance when considering tolerance, DC bias,
temperature, and aging effects is typically two times the minimum capacitance. In this case the nominal
capacitance is thus 1640 μF.
9.4.2.3 Selecting the Compensation Capacitor CC
τ × g × R
m
Z
BW =
BW =
(42)
(43)
L
N
2 × π ×
× C
× k
COUT
OUT, min
∅
−6
12.5 × 10
−3
3
× 1.5 × 10
× 1.5 × 10
= 143kHz
−9
56 × 10
3
−6
2 × π ×
× 838 × 10
× 2
Next, calculate CC:
k
BW
2 × π × BW × R
C =
(44)
(45)
C
Z
4
C =
= 1.85 nF
3
C
3
2 × π × 143 × 10 × 2.4 × 10
The closest standard value from the E12 series is 2.2 nF.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9.4.3 Application Curves for Three Stacked Devices
0.884
0.882
0.88
95
90
85
80
75
0.878
0.876
0.874
0.872
0.87
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
V
V
V
V
V
IN = 2.7 V
IN = 3.3 V
IN = 4.0 V
IN = 5.0 V
IN = 6.0 V
70
65
0.868
0.866
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Output Current (A)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Output Current (A)
D002
D002
VOUT = 0.875 V
PWM
TA = 25°C
VOUT = 0.875 V
PWM
TA = 25°C
图9-29. Output Voltage Versus Output Current
图9-28. Efficiency Versus Output Current
VOUT = 0.875 V
VIN = 5 V
PWM
TA = 25°C
VOUT = 0.875 V
VIN = 5 V
PWM
TA = 25°C
RLOAD = 14 mΩ
RLOAD = 14 mΩ
图9-30. Start-Up Timing
图9-31. Output Voltage Ripple
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
60
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
VOUT = 0.875 V
VIN = 5 V
PWM; TPS62876
droop disabled
TA = 25°C
VOUT = 0.875 V
VIN = 5 V
PWM; TPS62876
droop enabled
TA = 25°C
Iout = 17 A to 63 A to 17 A
Iout = 17 A to 63 A to 17 A
图9-32. Load Transient Response
图9-33. Load Transient Response
VOUT = 0.875 V
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
IOUT = 63 A
图9-34. Line Transient Response
9.5 Best Design Practices
INCORRECT
CORRECT
TPS6287x-Q1
TPS6287x-Q1
2.7 V to 6 V
2.7 V to 6 V
15 kΩ
VIN
EN
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
INCORRECT
CORRECT
TPS6287x-Q1
TPS6287x-Q1
2.7 V to 6 V
2.7 V to 6 V
15 k
VIN
EN
ENABLE
ENABLE
9.6 Power Supply Recommendations
The TPS6287x-Q1 device family has no special requirements for input power supply. The input power supply
output current must be rated according to the supply voltage, output voltage, and output current of the
TPS6287x-Q1.
9.7 Layout
Achieving the performance the TPS6287x-Q1 devices are capable of requires proper PDN and PCB design. TI
therefore recommends the user perform a power integrity analysis on their design. There are a number of
commercially available power integrity software tools, and the user can use these tools to model the effects on
performance of the PCB layout and passive components.
In addition to the use of power integrity tools, TI recommends the following basic principles:
• Place the input capacitors close to the VIN and GND pins. Position the input capacitors in order of increasing
size, starting with the smallest capacitors closest to the VIN and GND pins. Use an identical layout for both
VIN-GND pin pairs of the package, to gain maximum benefit from the butterfly configuration.
• Place the inductor close to the device and keep the SW node small.
• Connect the exposed thermal pad and the GND pins of the device together. Use multiple thermal vias to
connect the exposed thermal pad of the device to one or more ground planes (TI's EVM uses nine 150-µm
thermal vias).
• Use multiple power and ground planes.
• Route the VOSNS and GOSNS remote sense lines on the primary device as a differential pair and connect
them to the lowest-impedance point of the PDN. If the desired connection point is not the lowest impedance
point of the PDN, optimize the PDN until it is. Do not route the VOSNS and GOSNS close to any of the switch
nodes.
• Connect the compensation components between COMP and AGND. Do not connect the compensation
components directly to power ground.
• If possible, distribute the output capacitors evenly between the TPS6287x-Q1 device and the point-of-load,
rather than placing them altogether in one place.
• Use multiple vias to connect each capacitor pad to the power and ground planes (TI's EVM typically uses four
vias per pad).
• Use plenty of stitching vias to ensure a low impedance connection between different power and ground
planes.
9.7.1 Layout Guidelines
图 9-35 shows the top layer of one of the evaluation modules for this device. the figure demonstrates the
practical implementation of the PCB layout principles previously listed. The user can find a complete set
drawings of all the layers used in this PCB in the evaluation module user's guide SLVUCL6.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
62
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
9.7.2 Layout Example
图9-35. TPS62876-Q1 EVM top layer
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
I2C™ is a trademark of NXP Semiconductors.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
64
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
WQFN_FC
RLF
XPS62876QWRZVRQ1
RZV
24
3000
330
12.4
3.30
4.40
0.80
8.0
12.0
Q1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
RZV 24
SPQ
Length (mm) Width (mm)
338.0 355.0
Height (mm)
XPS62876QWRZVRQ1
WQFN_FCRLF
3000
50.0
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
66
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSFU1
68
Submit Document Feedback
Product Folder Links: TPS62876-Q1
TPS62876-Q1
ZHCSLO0 –APRIL 2023
www.ti.com.cn
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TPS62876-Q1
English Data Sheet: SLVSFU1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XPS62876QWRZVRQ1
ACTIVE WQFN-FCRLF
RZV
24
3000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS62903QRYTRQ1
Automotive, 3-V to 18-V, 3-A low-IQ synchronous buck converter with 165°C junction temperature | RYT | 9 | -40 to 165
TI
TPS62912
TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation
TI
TPS62912RPUR
TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation
TI
TPS62913
TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation
TI
TPS62913RPUR
TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation
TI
©2020 ICPDF网 联系我们和版权申明