TPS629211QDRLRQ1 [TI]
采用 SOT-583 封装的汽车类 3V 至 10V、1A、高效率、低 IQ 同步降压转换器 | DRL | 8 | -40 to 150;
| 型号： | TPS629211QDRLRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-583 封装的汽车类 3V 至 10V、1A、高效率、低 IQ 同步降压转换器 | DRL | 8 | -40 to 150 转换器 |
| 文件： | 总58页 (文件大小：2026K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS629211-Q1
ZHCSO00A –MARCH 2022 –REVISED MARCH 2023
TPS629211-Q1 1A、3V 至10V 汽车类低IQ 降压转换器
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准：
• 高级驾驶辅助系统(ADAS)
• 汽车信息娱乐系统与仪表组
• 汽车车身电子装置和照明
• 混合动力、电动和动力总成系统
– –40°C 至150°C 的工作结温范围
– 器件HBM ESD 分类等级2
– CDM ESD 分级等级C4B
• 提供功能安全
3 说明
– 有助于进行功能安全系统设计的文档
• 高效率DCS-Control 拓扑
符合汽车标准的 TPS629211-Q1 器件是高效、小巧、
高度灵活且易于使用的同步降压直流/直流转换器。3V
至 10V 的宽输入电压范围支持各种由 9V、5V 或 3.3V
电源轨或者单节或多节锂离子电池供电的系统。可将
TPS629211-Q1 配置为以强制 PWM 模式或可变频率
（自动 PFM）模式在 2.5 MHz 或 1 MHz 频率下运
行。在自动 PFM 模式下，器件在轻负载时自动转换为
省电模式，以保持高效率。此外，借助 4µA 的低典型
静态电流，可在极小的负载下实现高效率。TI 的自动
效率增强 (AEE) 模式可根据输入和输出电压自动调整
开关频率，从而无需使用不同的电感器即可在整个工作
范围内保持高转换效率。除选择开关频率的行为之外，
MODE/S-CONF 输入引脚还可用于在外部和内部反馈
分压器和启用/禁用输出电压放电功能的不同组合之间
进行选择。在内部反馈配置中，FB/VSET 引脚和GND
之间的电阻器可用于在 18 种不同的输出电压选项之间
进行选择（请参阅表8-2）。
– 内部补偿
– 无缝PWM/PFM 转换
• 4 µA（典型值）低静态电流
• 输出电流高达1A
• 250mΩ高侧/85mΩ低侧RDSON
• ±1% 的输出电压精度
• 可配置的输出电压选项：
– 0.6V 至5.5V VFB 外部分压器：
– VSET 内部分压器：
• 18 个电压选项（0.4V 至5.5V）
• 通过MODE/S-CONF 引脚提高了灵活性
– 2.5 MHz 或1.0 MHz 开关频率
– 具有动态模式更改选项的强制PWM 或自动
(PFM) 省电模式
– 输出放电开/关
• 无需外部自举电容器
• 过流和过热保护
• 100% 占空比模式
• 精密使能输入
• 电源正常状态输出
封装信息
封装(1)
封装尺寸（标称值）
器件型号
1.60mm × 2.10mm
（包括引脚）
DRL（SOT-5X3，
8）
TPS629211-Q1
• 与TPS629210-Q1、TPS629206-Q1 和
TPS629203-Q1 器件引脚对引脚兼容
• 0.5mm 间距、8 引脚SOT-5X3 封装
1.60mm × 2.10mm
（包括引脚）
DYC（SOT-5X3，
8）
TPS629211-Q1
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
90
80
70
60
50
40
30
20
VIN
3 V to 10 V
VOUT
0.4 V to 5.5 V
2.2 µH
VIN
EN
SW
22
F
4.7
F
VOS
FB/
VSET
MODE/
S-CONF
PG
VIN = 6V
VIN = 9V
10
0
GND
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
效率与输出电流间的关系（频率为2.5MHz，
VOUT = 3.3V，自动PFM/PWM）
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGD0
TPS629211-Q1
ZHCSO00A –MARCH 2022 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 20
9.3 System Examples..................................................... 42
9.4 Power Supply Recommendations.............................43
9.5 Layout....................................................................... 44
10 Device and Documentation Support..........................46
10.1 Device Support....................................................... 46
10.2 Documentation Support.......................................... 46
10.3 接收文档更新通知................................................... 46
10.4 支持资源..................................................................46
10.5 Trademarks.............................................................46
10.6 静电放电警告.......................................................... 47
10.7 术语表..................................................................... 47
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Thermal Information - DYC Package..........................6
7.6 Electrical Characteristics.............................................6
7.7 Typical Characteristics................................................8
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
Information.................................................................... 47
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2022) to Revision A (March 2023)
Page
• 添加了 DYC 封装................................................................................................................................................1
• Added the DYC package.................................................................................................................................... 3
• Added the DYC package.................................................................................................................................... 3
• Added the DYC package.................................................................................................................................. 44
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGD0
2
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5 Device Comparison Table
Operating
Temperature
Range
Switching
Frequency
Package
Options
Device Number
Output Current
Input Voltage
3 V –17 V
3 V –10 V
PWM Mode
VO Adjust
TPS629203-Q1
TPS629206-Q1
TPS629210-Q1
0 A –0.3 A
0 A –0.6 A
0 A –1 A
Selectable auto
PWM/PFM or
forced PWM
Externally
programmable or
18 internal options
DRL
Selectable 1-MHz
or 2.5-MHz options
–40°C to 150°C
–40°C to 150°C
DRL and DYC
Selectable auto
PWM/PFM or
forced PWM
Externally
Selectable 1-MHz
or 2.5-MHz options
TPS629211-Q1
programmable or DRL and DYC
18 internal options
0 A –1 A
6 Pin Configuration and Functions
/
F
E
N
D
D
O
N
I
N
C
N
-
MO
G
E
V
S
8
7
6
5
4
1
2
3
/
T
B
S
G
P
E
F
W
S
O
V
S
图6-1. TPS629211-Q1 8-Pin DRL SOT-5X3 Pinout (TOP)
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ZHCSO00A –MARCH 2022 –REVISED MARCH 2023
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8
1
7
2
6
3
5
4
图6-2. TPS629211-Q1 8-Pin DYC SOT-5X3 Pinout (TOP)
表6-1. Pin Functions
Pin
I/O
Description
Name
NO.
Dependent upon device configuration (see 节8.3.1)
•
•
FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
FB/VSET
1
I
VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage
according to 表8-2.
PG
2
3
4
5
O
I
Open-drain power-good output
VOS
SW
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
Switch pin of the converter. Connected to the internal power switches
Ground pin
GND
Power supply input. Make sure the input capacitor is connected as close as possible between
the VIN pin and GND.
VIN
EN
6
7
8
I
I
I
Enable/disable pin including a threshold comparator. Connect to logic low to disable the device.
Pull high to enable the device. Do not leave this pin unconnected.
Device mode selection (auto PFM/PWM or forced PWM operation) and Smart-CONFIG pin.
Connect a resistor to configure the device according to 表8-1.
MODE/S-CONF
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-3.0
-0.3
MAX
UNIT
V
Voltage(2)
Voltage(2)
Voltage(2)
Voltage(2)
Current
Tstg
VIN, EN, PG, MODE/S-CONF
SW((3))
12
VIN + 0.3
V
SW (AC, less than 10ns)(3)
17
6
V
FB/VSET, VOS
V
PG
10
mA
°C
Storage temperature
-65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
±2000
V
Charged device model (CDM), per AEC
Q100-011CDM ESD classification level C4B
±750
V
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
3.0
0.4
3
NOM
MAX
10
UNIT
V
VI
Input voltage range
VO
Output voltage range
Effective input capacitance
Effective output capacitance(1)
Output inductance(2)
Output current
5.5
V
CI
4.7
22
µF
µF
µH
A
CO
L
10
100
4.7(4)
1
1.0(3)
2.2
IOUT
ISINK_PG
TJ
0
Sink current at PG-Pin
Junction temperature (5)
1
mA
°C
-40
150
(1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitor.
(2) Nominal inductance value.
(3) Not recommended for 1 MHz operation
(4) Larger values of inductance may be used to reduce the ripple current, but they may have a negative impact on efficiency and the
overall transient response.
(5) Operating lifetime is derated at junction temperatures greater than 150°C.
7.4 Thermal Information
TPS629211-Q1
THERMAL METRIC((1))
SOT583 8-Pin (DRL)
JEDEC PCB TPS6292xx EVM
UNIT
RθJA
Junction-to-ambient thermal resistance
120
60
°C/W
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UNIT
TPS629211-Q1
THERMAL METRIC((1))
SOT583 8-Pin (DRL)
JEDEC PCB
TPS6292xx EVM
RθJC(top)
RθJB
ΨJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
45
25
1
n/a
n/a
n/a
n/a
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information - DYC Package
TPS629211-Q1
THERMAL METRIC(1)
SOT583 8-Pin (DYC)
JEDEC PCB TPS6292xx DYC EVM
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
105
45
22
1
55
°C/W
°C/W
°C/W
°C/W
°C/W
n/a
n/a
n/a
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
18
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Electrical Characteristics
VI = 3 V to 10 V, TJ = -40 °C to +150 °C , Typical values at VI = 6 V and TA = 25 °C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Operating Quiescent Current, (Power
Save Mode)
IQ
Iout = 0 mA, device not switching
4
5
µA
Operating Quiescent Current (PWM
Mode)
VIN = 6V, VOUT=1.2V; Iout = 0 mA,
device switching
IQ;PWM
ISD
VUVLO
VUVLO
mA
Shutdown current into VIN pin
Under Voltage Lock-Out
EN = 0 V
VIN rising
VIN falling
0.25
2.95
2.75
200
3
3.0
µA
V
2.85
2.65
Under Voltage Lock-Out
2.85
V
Under Voltage Lock-Out Hysteresis
mV
CONTROL & INTERFACE
ILKG
EN Input leakage current
EN=VIN
3
300
nA
V
High-Level Input Voltage at MODE/S-
CONF Pin
VIH;MODE
1.0
Low-level input voltage at MODE/
S_CONF Pin
VIL;MODE
0.15
V
VIH
VIL
High-level input voltage at EN-Pin
Low-level input voltage at EN-Pin
0.97
0.87
93%
89%
1.0
0.9
1.03
0.93
99%
96%
V
V
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
hysteresis
96%
93%
3%
32
VPG
Power good threshold
VPG_HYS
tPG,DLY
tPG,DLY
VPG,OL
Power good threshold hysteresis
Power good delay time
µs
Power good pull down resistance
Low-level output voltage at PG pin
10
Ω
ISINK = 1 mA
0.1
V
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English Data Sheet: SLVSGD0
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7.6 Electrical Characteristics (continued)
VI = 3 V to 10 V, TJ = -40 °C to +150 °C , Typical values at VI = 6 V and TA = 25 °C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPG,LKG
Input leakage current into PG pin
VPG = 5 V
0.01
1
µA
POWER SWITCHES
High-side FET on resistance
250
85
RDS;ON
mΩ
Low-side FET on resistance
High-side FET current limit
Low-side FET current limit
Low-side FET sink current limit
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Switching frequency
1.5
1.3
0.8
1.8
1.6
1
2.1
1.9
1.2
A
A
A
ILIM
ILIM;SINK
TSD
TJ rising
170
20
°C
TJ falling
fSW
2.5-MHz selection (FPWM Mode)
1.0-MHz selection (FPWM Mode)
2.5
1.0
40
MHz
MHz
ns
fSW
Switching frequency
TON(MIN)
ILKG;SW
OUTPUT
Minimum On-time
Leakage current into SW-Pin
EN = 0V, VSW = VOS = 5.5V
0.1
5
µA
VSET Configuration selected, 0°C ≤
TJ ≤85°C
VO
VO
Output Voltage Regulation
Output Voltage Regulation
-1%
+1%
VSET Configuration selected, -40°C ≤
TJ ≤150°C (DRL Package)
-1.4%
+1.1%
VSET Configuration selected, VOUT
≤3.8V, -40°C ≤TJ ≤150°C
(DYC Package)
VO
VO
Output Voltage Regulation
Output Voltage Regulation
-1.4%
-1.6%
+1.1%
+1.1%
VSET Configuration selected,
VOUT ≥5.0V, -40°C ≤TJ ≤150°C
(DYC Package)
VFB
VFB
Feedback Regulation Voltage
Feedback Voltage Regulation
Adjustable Configuration selected
0.6
V
-0.75%
-1.2%
+0.75%
+0.75%
100
FB-Option selected, 0°C ≤TJ ≤85°C
FB-Option selected, -40°C ≤TJ ≤
150°C
VFB
IFB
Feedback Voltage Regulation
Input leakage current into FB pin
Adjustable configuration, VFB = 0.6 V
1
nA
µs
IO = 0 mA, time from EN rising edge
until start switching, External FB
Configuration selected
Start-up delay time
Start-up delay time
700
1500
1800
Tdelay
IO = 0 mA, time from EN rising edge
until start switching, VSET
Configuration selected
1000
µs
IO = 0 mA after Tdelay, from 1st
switching pulse until target VO
TSS
Soft-Start time
600
7.5
700
20
µs
Discharge = ON - Option Selected, EN
= LOW,
RDISCH
Active Discharge Resistance
Ω
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7.7 Typical Characteristics
10
9
8
7
6
5
4
3
2
1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图7-2. Typical Shutdown Current vs Temperature
Measured with the device not switching
图7-1. Typical Quiescent Current vs Temperature
0.2
Vin = 3V
Vin = 6V
Vin = 9V
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
VOUT = 5.0 V
图7-3. Output Voltage Accuracy –External Feedback
图7-4. Output Voltage Accuracy –VSET Selected
3.315
1.81
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
3.312
1.808
1.806
1.804
1.802
1.8
3.309
3.306
3.303
3.3
3.297
3.294
3.291
3.288
3.285
1.798
1.796
1.794
1.792
1.79
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
VOUT = 3.3 V
VOUT = 1.8 V
图7-5. Output Voltage Accuracy –VSET Selected
图7-6. Output Voltage Accuracy –VSET Selected
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7.7 Typical Characteristics (continued)
1.206
1.204
1.202
1.2
0.603
0.602
0.601
0.6
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
1.198
1.196
1.194
1.192
1.19
0.599
0.598
0.597
0.596
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
VOUT = 1.2 V
VOUT = 0.6 V
图7-7. Output Voltage Accuracy –VSET Selected
2.8
图7-8. Output Voltage Accuracy –VSET Selected
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
0.99
0.98
0.97
0.96
0.95
0.94
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
1.9
1.8
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Fsw = 1.0 MHz
FPWM
Temperature (C)
FSW = 2.5 MHz
FPWM
VOUT = 1.2 V
IOUT = 0 A
VOUT = 1.2 V
IOUT = 0 A
图7-10. Switching Frequency vs Temperature
图7-9. Switching Frequency vs Temperature
475
450
425
400
375
350
325
300
275
250
225
200
175
160
150
140
130
120
110
100
90
80
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
70
60
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图7-11. High-Side RDSON vs Temperature
图7-12. Low-Side RDSON vs Temperature
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7.7 Typical Characteristics (continued)
1.85
1.84
1.83
1.82
1.81
1.8
1.65
1.64
1.63
1.62
1.61
1.6
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.5
Vin = 3V
Vin = 6V
Vin = 9V
1.79
1.78
1.77
1.76
1.75
Vin = 3V
Vin = 6V
Vin = 9V
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图7-14. Low-Side ILIM vs Temperature
图7-13. High-Side ILIM vs Temperature
1.03
1.02
1.01
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
Vin = 3V
Vin = 6V
Vin = 9V
-40 -20
0
20
40
60
80 100 120 140 160
图7-16. VIN UVLO Thresholds vs Temperature
Temperature (C)
图7-15. Low-Side INEG vs Temperature
1.005
1.004
1.003
1.002
1.001
1
0.9
0.899
0.898
0.897
0.896
0.895
0.894
0.893
0.892
0.891
0.89
0.999
0.998
0.997
0.996
0.995
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图7-17. Precision Enable Threshold vs Temperature
图7-18. Precision Enable Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The TPS629211-Q1 synchronous switched mode power converter is based on DCS-Control (Direct Control with
Seamless Transition into power save mode), an advanced regulation topology that combines the advantages of
hysteretic, voltage mode, and current mode control. This control loop takes information about output voltage
changes and feeds it directly to a fast comparator stage. and sets the switching frequency, which is constant for
steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate
DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves
fast and stable operation with small external components and low-ESR capacitors.
8.2 Functional Block Diagram
VIN
PG
VI
Ref
1.0 V
–
+
HS Limit
EN
VO
Internal/External
Divider
Device Control
and Logic
Power Control
FB/VSET
SW
Power Save Mode
Forced PWM
100% Mode
Resistor-to-
Digital
Gate
Driver
Smart-Enable
Ref-System
VFB
UVLO
Start-up Handling
Smart-CONFIG
PG-Control
Thermal Shutdown
Resistor-to-
Digital
MODE/
S-CONF
LS Limit
MODE Detection
VO
Direct
Control
VI
VOS
TON timer
VFB
–
VO
+
Device
Control
VREF
DCS-Control
GND
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8.3 Feature Description
8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
The MODE/S-CONF pin is an input with two functions, which can be used to customize the device behavior in
two ways:
• Select the device mode (forced PWM or auto PFM/PWM operation) traditionally with a HIGH or LOW level.
• Select the device configuration (switching frequency, internal and external feedback, output discharge, and
PFM/PWM mode) by connecting a single resistor to this pin.
The device interprets this pin during its start-up sequence after the internal OTP readout and before it starts
switching in soft start. If the device reads a HIGH or LOW level, dynamic mode change is active and PFM/PWM
mode can be changed during operation. If the device reads a resistor value, there is no further interpretation
during operation and the device mode or other configurations cannot be changed afterward.
EN & UVLO
Precise
Enable
detection
PG -> High
Switching
Operation
OTP
Readout
S-CONF
Readout
VSET
Readout
Softstart
Resistor-to-Digitial
readout &
interpretation
No interpretation of
MODE/S-CONF or VSET
MODE-Pin toggling detection
VOUT
图8-1. Interpretation of S-CONF and VSET Flow
表8-1. Smart-CONFIG Setting Table
Dynamic
Mode
Change
M ODE/S-CONF Level Or
Resistor Value [Ω] (1)
FB/VSET
Pin
Output
Discharge
#
FSW (MHz)
Mode (Auto Or Forced PWM)
Setting Options by Level
1
2
GND
HIGH (> 1.8 V)
Setting Options by Resistor
7.50 k
external FB
external FB
up to 2.5(2)
2.5
yes
yes
Auto PFM/PWM with AEE
Forced PWM
Active
3
4
external FB
external FB
external FB
external FB
external FB
external FB
VSET
up to 2.5(2)
no
no
Auto PFM/PWM with AEE
Forced PWM
9.31 k
2.5
5
11.50 k
1
yes
yes
no
Auto PFM/PWM
Forced PWM
6
14.30 k
1
7
17.80 k
1
Auto PFM/PWM
Forced PWM
8
22.10 k
1
no
9
27.40 k
up to 2.5(2)
yes
yes
no
Auto PFM/PWM with AEE
Forced PWM
not active
10
11
12
13
14
15
16
34.00 k
VSET
2.5
42.20 k
VSET
up to 2.5(2)
Auto PFM/PWM with AEE
Forced PWM
52.30 k
VSET
2.5
1
no
64.90 k
VSET
yes
yes
no
Auto PFM/PWM
Forced PWM
80.60 k
VSET
1
100.00 k
VSET
1
Auto PFM/PWM
Forced PWM
124.00 k
VSET
1
no
(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C
(2) FSW varies based on VIN and VOUT. See 节8.4.3 for more details.
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8.3.2 Adjustable VO Operation (External Voltage Divider)
If the device is configured to operate in classical adjustable VO operation, the FB/VSET pin is used as the
feedback pin and must sense VO through an external divider network. 图8-2 shows the typical schematic for this
configuration.
VIN
3 V to 10 V
VOUT
0.6 V to 5.5 V
2.2 µH
VIN
EN
SW
22 F
4.7 F
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
图8-2. Adjustable VO Operation Schematic
8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/S-
CONF readout (see 图 8-3). There is no further interpretation of the VSET pin during operation and the output
voltage cannot be changed afterward without toggling the EN pin.
图 8-3 shows the typical schematic for this configuration, where VO is directly sensed at the VOS pin of the
device. VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by
an external resistor connected between VSET and GND (see 表8-2).
VIN
3 V to 10 V
VOUT
0.4 V to 5.5 V
2.2 µH
VIN
EN
SW
22 F
4.7 F
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
图8-3. Selectable VO Operation Schematic
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表8-2. VSET Selection Table
Resistor Value [Ω](1)
VSET #
Target VO [V]
1
2
GND
1.2
0.4
0.6
0.8
0.85
1.0
1.1
1.25
1.3
1.35
1.8
1.9
2.5
3.8
5.0
5.1
5.5
3.3
4.87 k
3
6.04 k
4
7.50 k
5
9.31 k
6
11.50 k
7
14.30 k
8
17.80 k
9
22.10 k
10
11
12
13
14
15
16
17
18
27.40 k
34.00 k
42.20 k
52.30 k
64.90 k
80.60 k
100.00 k
124.00 k
249.00 k or larger/open
(1) E96 Resistor Series, 1% accuracy, temperature coefficient
better or equal to ±200 ppm/°C
8.3.4 Smart Enable with Precise Threshold
The voltage applied at the EN pin of the TPS629211-Q1 is compared to a fixed threshold rising voltage. This
allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to
achieve a power-up delay.
The precise enable input allows the use of a user-programmable undervoltage lockout by adding a resistor
divider to the input of the EN pin.
The enable input threshold for a falling edge is lower than the rising edge threshold. The TPS629211-Q1 starts
operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must
not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side
and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.
An internal resistor pulls the EN pin to GND and avoids the pin to be floating. This prevents an uncontrolled start-
up of the device in case the EN pin cannot be driven to a low level safely. With EN low, the device is in shutdown
mode. The device is turned on with EN set to a high level. The pulldown control circuit disconnects the pulldown
resistor on the EN pin after the internal control logic and the reference have been powered up. With EN set to a
low level, the device enters shutdown mode and the pulldown resistor is activated again.
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8.3.5 Power Good (PG)
The TPS629211-Q1 has a built-in power-good (PG) feature to indicate whether the output voltage has reached
its target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG
pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage
level. PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN
must remain present for the PG pin to stay low.
If the power-good output is not used, it is recommended to tie to GND or leave open.
表8-3. Power-Good Indicator Functional Table
Logic Signals
PG Status
VI
EN Pin
Thermal Shutdown
VO
VO on target
High Impedance
LOW
No
HIGH
VO < target
VVIN > UVLO
Yes
x
x
x
x
x
LOW
LOW
LOW
1.8 V < VVIN < UVLO
VI < 1.8 V
x
x
x
LOW
x
Undefined
8.3.6 Output Discharge Function
The purpose of the discharge function is to make sure there is a defined down-ramp of the output voltage when
the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output
discharge feature is only active after the TPS629211-Q1 has been enabled at least after since the supply voltage
was applied. The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as
soon as the device is disabled (EN pin = low), in thermal shutdown, or in undervoltage lockout. The minimum
supply voltage required for the discharge function to remain active typically is 2 V.
8.3.7 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
8.3.8 Current Limit and Short Circuit Protection
The TPS629211-Q1 is protected against overload and short circuit events. If the inductor current exceeds the
current limit, ILIM_HS, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased below
the low-side current limit threshold, ILIM_LS
.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given in 方程式1.
V
L
L
I
= I
+
× t
pd
(1)
peak typ
LIMH
where:
• ILIMH is the static current limit as specified in the electrical characteristics.
• L is the effective inductance at the peak current.
• VL is the voltage across the inductor (VIN –VOUT).
• tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
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V
− V
L
IN
OUT
I
= I
+
× 50ns
(2)
peak typ
LIMH
The TPS629211-Q1 also includes a low-side negative current limit (ILIM:SINK) to protect against excessive
negative currents that can occur in forced PMW mode under heavy to light load transient conditions. If the
negative current in the low-side switch exceeds the ILIM:SINK threshold, the low-side switch is disabled. Both the
low-side and high-side switches remain off until an internal timer re-enables the high-side switch based on the
selected PWM switching frequency.
CAUTION
TI recommends that the inductor be sized such that the inductor ripple current, ΔIL (see 方程式 9),
does not exceed 1.6 A to avoid the potential for continuous operation of the negative current limit
with no output load (IO = 0 A).
8.3.9 Thermal Shutdown
The junction temperature of the device, TJ, is monitored by an internal temperature sensor. If TJ rises and
exceeds the thermal shutdown threshold, TSD, the device shuts down. Both the high-side and low-side power
FETs are turned off and PG goes low. When TJ decreases below the hysteresis, the converter resumes normal
operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A
shutdown or restart is only triggered during a switching cycle. See 节8.4.2.
8.4 Device Functional Modes
8.4.1 Forced Pulse Width Modulation (PWM) Operation
The TPS629211-Q1 has two operating modes: forced PWM mode discussed in this section and auto PFM/PWM
mode as discussed in 节8.4.2.
With the MODE/S-CONF pin set to forced PWM mode, the device operates with pulse width modulation in
continuous conduction mode (CCM) with a nominal switching frequency of either 1.0 MHz or 2.5 MHz. The
frequency variation in PWM is controlled and depends on VIN, VOUT, and the inductance. The on time in forced
PWM mode is given by 方程式3.
V
OUT
1
T
=
×
(3)
ON
V
f
IN
SW
For very small output voltages, an absolute minimum on time of aproximately 40 ns is kept to limit switching
losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high.
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8.4.2 Power Save Mode Operation (Auto PFM/PWM)
When the MODE/S-CONF pin is configured for auto PFM/PWM mode, power save mode is allowed. The device
operates in PWM mode as long the output current is higher than half the ripple current of the inductor. To
maintain high efficiency at light loads, the device enters power save mode at the boundary to discontinuous
conduction mode (DCM). This happens if the output current becomes smaller than half the ripple current of the
inductor. Power save mode is entered seamlessly to make sure there is high efficiency in light-load operation.
The device remains in power save mode as long as the inductor current is discontinuous.
In power save mode, the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of power save mode is seamless in both directions.
The TPS629211-Q1 adjusts the on time (TON) in power save mode, depending on the input voltage and the
output voltage to maintain highest efficiency. The on time in steady-state operation can be estimated as:
With the MODE/S-CONF pin set to 1.0-MHz operation:
V
OUT
T
µs =
(4)
(5)
(6)
ON
V
IN
With the MODE/S-CONF pin set to 2.5-MHz operation:
V
IN
T
ns = 100 ×
V
ON
− V
IN
OUT
Using TON, the typical peak inductor current in power save mode is approximated by:
V
− V
L
IN
OUT
ILPSM
=
× T
ON
peak
The output voltage ripple in power save mode is given by 方程式7:
2
L × V
IN
1
− V
1
∆ V =
+
+
(7)
200 × C
V
V
IN
OUT
OUT
备注
When VIN decreases to typically 15% above VOUT, the device does not enter power save mode
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 AEE (Automatic Efficiency Enhancement)
When the MODE/S-CONF pin is configured for auto PFM/PWM with AEE mode, the TPS629211-Q1 provides
the highest efficiency over the entire input voltage and output voltage range by automatically adjusting the
switching frequency of the converter (see 方程式 8). To keep the efficiency high over the entire duty cycle range,
the switching frequency is adjusted while maintaining the ripple current amplitudes. This feature compensates for
the very small duty cycles of high VIN to low VOUT conversions, which can limit the control range in other
topologies.
V
− V
OUT
IN
F
MHz = 10 × V
×
(8)
SW
OUT
2
V
IN
Traditionally, the efficiency of a switched mode converter decreases if VOUT decreases, VIN increases, or both.
By decreasing the switching losses at lower VOUT values or higher VIN values, the AEE feature provides an
efficiency enhancement across various duty cycles, especially for the lower VOUT values, where fixed frequency
converters suffer from a significant efficiency drop. Furthermore, when used with the recommended 2.2-μH
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inductor, the ripple current amplitudes remains low enough to deliver the full output current without reaching
current limit across the entire range of input and output voltages (see 图8-4).
By using the same TON configuration (see 方程式 9) across the entire load range in AEE mode, the inductor
ripple current in AEE mode becomes effectively independent of the output voltage and can be approximated by
方程式9:
V
− V
L
V
V
IN
OUT
IN
L μH
∆ I mA = T
×
= 0.1 ×
(9)
L
ON
500
450
400
350
300
250
200
150
100
50
0
3
3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Input Voltage (V)
Fsw = 2.5 MHz
Auto PFM/PWM with AEE
L = 2.2 μH
图8-4. Typical Inductor Ripple Current Versus Input Voltage in AEE Mode
The TPS629211-Q1 operates in AEE mode as long as the output current is higher than half the ripple current of
the inductor. To maintain high efficiency at light loads, the device enters power save mode at the boundary to
discontinuous mode (DCM), which happens when the output current becomes smaller than half the inductor
ripple current.
8.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operated in PWM mode is given in 方程式10.
V
OUT
D =
(10)
V
IN
The duty cycle increases as the input voltage comes close to the output voltage and the off time of the high-side
switch gets smaller. When the minimum off time of typically 80 ns is reached, the TPS629211-Q1 scales down its
switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch on
continuously as long as the output voltage is below the internal set point. This allows the conversion of small
input to output voltage differences. For example, getting the longest operation time of battery-powered
applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
V
= V
+ I
× R
+ R
L
(11)
IN MIN
OUT
OUT
DS ON
where:
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• IOUT is the output current.
• RDS(on) is the on-state resistance of the high-side FET.
• RL is the DC resistance of the inductor used.
8.4.5 Starting into a Prebiased Load
The TPS629211-Q1 is capable of starting into a prebiased output. The device only starts switching when the
internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPS629211-Q1 does not start switching unless the voltage at the
feedback pin drops to the target. Performance is the same for devices configured for VSET operation (internal
feedback), however, the switching is delayed until the soft-start ramp reaches the internal feedback voltage.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers must validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS629211-Q1 device is a highly efficient, small, and highly-flexible synchronous step-down DC-DC
converter that is easy to use. A wide input voltage range of 3 V to 10 V supports a wide variety of inputs like 9-V
supply rails, single-cell or dual-cell Li-Ion, and 5-V or 3.3-V rails.
9.2 Typical Application
VIN
3 V to 10 V
VOUT
0.6 V to 5.5 V
2.2 µH
VIN
EN
SW
22
F
4.7
F
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
图9-1. Typical Application Setup
表9-1. List of Components
Reference
Description
Manufacturer
IC
L1
C1
10-V, 1-A Step-Down Converter
2.2-µH inductor
TPS629211-Q1; Texas Instruments
XGL3530-222; Coilcraft
4.7 µF, 25 V, Ceramic, 1206
22 µF, 6.3 V, Ceramic, 0805
CGA5L1X7R1E475K160AC, TDK
GCM21BD70J226ME36L, MuRata
C2
R1
R2
R3
Standard 1% metal film
Standard 1% metal film
Standard 1% metal film
Depending on VOUT; see 节9.2.2.2.
Depending on VOUT; see 节9.2.2.2.
Depending on device setting, see 节8.3.1.
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9.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS629211-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
The output voltage of the TPS629211-Q1 is adjustable and can be programmed for output voltages from 0.6 V to
5.5 V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of
the output voltage is set by the selection of the resistor divider from 表 9-2. TI recommends to size R2 to be less
than 300 kΩ to allow for a feedback current of at least 2 μA. Lower resistor values are recommended for
highest accuracy and most robust design.
VOUT
VFB
R = R ×
− 1
(12)
1
2
where
• VFB is 0.6 V.
表9-2. Setting the Output Voltage
Nominal Output Voltage
R1
R2
Exact Output Voltage
0.804 V
1.200 V
1.500 V
1.803 V
2.502 V
3.311 V
4.995 V
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5 V
51 kΩ
150 kΩ
130 kΩ
100 kΩ
237 kΩ
165 kΩ
137 kΩ
84.5 kΩ
130 kΩ
150 kΩ
475 kΩ
523 kΩ
619 kΩ
619 kΩ
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the control
loop of the device. The TPS629211-Q1 is optimized to work within a range of external components.
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9.2.2.3.1 Output Filter and Loop Stability
The TPS629211-Q1 is internally compensated to be stable with a range of LC filter combinations. The LC output
filters inductance and capacitance have to be considered together, creating a double pole, responsible for the
corner frequency of the converter using 方程式13.
1
f
=
(13)
LC
2π L × C
表 9-3 can be used to simplify the output filter component selection. The values in 表 9-3 are nominal values,
and the effective capacitance was considered to be +20% and –50%. Different values can work, but care has to
be taken on the loop stability which is affected. More information on the sizing of the LC filter of a DCS-Control
regulator can be found in the Optimizing the TPS62130/40/50/60 Output Filter Application Note.
表9-3. Recommended LC Output Filter Combinations
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
1 µH (3) (4)
1.5 µH
(2)
√
√
√
√
(2)
√
√
√
√
√
√
√
(1)
(2)
2.2 µH
√
√
√
3.3 µH
√
√
√
√
√
(2)
4.7 µH
√
(1) This LC combination is the standard value and recommended for most applications.
(2) Output capacitance must have an ESR of ≥10 mΩfor stable operation. See 节9.3.1.
(3) Not recommended for 1-MHz operation
(4) At full load, ILpeak can exceed ILIM_HS at higher input or output voltages.
Although the TPS629211-Q1 is stable without the pole and zero being in a particular location, an external
feedforward capacitor can also be added to adjust their location based on the specific needs of the application.
This can provide better performance in power save mode, improved transient response, or both.
A more detailed discussion on the optimization for stability versus transient response can be found in the
Optimizing Transient Response of Internally Compensated DC-DC Converters Application Note and
Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family Application Note.
9.2.2.3.2 Inductor Selection
The TPS629211-Q1 is designed for a nominal 2.2-µH inductor. Larger values can be used to achieve a lower
inductor current ripple but they can have a negative impact on efficiency and transient response. Smaller values
than 2.2 µH cause larger inductor current ripple, which cause larger negative inductor currents in forced PWM
mode and higher peak currents at full load. Therefore, they are not recommended at larger voltages across the
inductor as it is the case for high input voltages and low output voltages. With low output current in forced PWM
mode, this causes a larger negative inductor current peak that can exceed the negative current limit. At low or no
output current and small inductor values, the output voltage can therefore not be regulated any more. More
detailed information on further LC combinations can be found in the Optimizing the TPS62130/40/50/60 Output
Filter Application Note.
The inductor selection is affected by several effects like the following:
• Inductor ripple current
• Output ripple voltage
• PWM-to-PFM transition point
• Efficiency
In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). 方
程式14 calculates the maximum inductor current.
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∆ I
V
L MAX
2
I
= I
+
(14)
(15)
L MAX
OUT MAX
V
OUT
1 −
IN MAX
∆ I
= V
×
L MAX
OUT
L
× f
MIN
SW
where:
• IL(max) is the maximum inductor current.
• ΔIL is the peak-to-peak inductor ripple current.
• L(min) is the minimum effective inductor value.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to add a margin of approximately 20%. A larger inductor value
is also useful to get lower ripple current, but increases the transient response time and size as well. The
following inductors have been used with the TPS629211-Q1 and are recommended for use:
表9-4. List of Inductors
Dimensions
Type
Inductance [µH]
Current [A](1)
Manufacturer
DCR [mΩ]
[L×W×H] mm
2.5 × 2.0 × 1.2
3.5 × 3.2 × 3
4 × 4 × 2.1
DFE252012PD-2R2M(2)
XGL3530-222ME
XGL4020-222ME
XGL3530-332ME
XGL4020-472ME
2.2 µH, ±20%
2.2 μH, ±20%
2.2 µH, ±20%
3.3 μH, ±20%
4.7 µH, ±20%
84
20
2.8
4.0
6.2
3.3
4.1
muRata
Coilcraft
Coilcraft
Coilcraft
Coilcraft
19.5
33
3.5 × 3.2 × 3
4 × 4 × 2.1
43
(1) ISAT at 30% drop
(2) For smaller size solutions that do not require maximum efficiency at the full output current
The inductor value also determines the load current at which power save mode is entered:
1
2
I
=
× ∆ I
(16)
Load PSM
L
9.2.2.3.3 Capacitor Selection
9.2.2.3.3.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS629211-Q1 allows the use
of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, TI recommends to use X7R or X5R dielectric. Using a higher value has
advantages like smaller voltage ripple and a tighter DC output accuracy in power save mode (see Optimizing the
TPS62130/40/50/60 Output Filter Application Note for more information).
In power save mode, the output voltage ripple depends on the following:
• Output capacitance
• ESR
• ESL
• Peak inductor current
Using ceramic capacitors provides small ESR, ESL, and low ripple.
The output capacitor must be as close as possible to the device, and TI recommends to have the VOS signal
and feedback resistors (if used) must be connected to the positive terminal of the output capacitor.
For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance has to
be observed.
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9.2.2.3.3.2 Input Capacitor
For most applications, 4.7-µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
must be placed as close as possible to the VIN and GND pins.
表9-5. List of Capacitors
Type
Nominal Capacitance [µF]
Voltage Rating [V]
Size
Manufacturer
TDK
CGA5L1X7R1E475K160AC
CGA5L1X7R1E106K160AC
4.7
10
25
25
1206(1)
1206(1)
TDK
(1) Smaller (0805 or 0603) options may be used and are available from various manufacturers.
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9.2.3 Application Curves
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 7V
VIN = 9V
VIN = 7V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 5.0 V
Fsw = 2.5 MHz
VOUT = 5.0 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-3. Efficiency vs Output Current
图9-2. Efficiency vs Output Current
3.5
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
3
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
6
6.5
7
7.5
8
8.5
9
9.5
10
6
6.5
7
7.5
8
8.5
9
9.5
10
Input Voltage (V)
Input Voltage (V)
VOUT = 5.0 V
Fsw = 2.5 MHz
VOUT = 5.0 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-4. Switching Frequency vs Input Voltage
图9-5. Switching Frequency vs Input Voltage
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9.2.3 Application Curves (continued)
0.45
0.4
0.21
0.2
VIN = 7V
VIN = 9V
0.35
0.3
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.25
0.2
0.15
0.1
0.05
0
VIN = 7V
VIN = 9V
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
Iout (A)
VOUT = 5.0 V
Fsw = 2.5 MHz
L = 2.2 μH
VOUT = 5.0 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
Auto PFM/PWM
图9-6. Output Voltage vs Output Current
图9-7. Output Voltage vs Output Current
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
VIN = 7V
VIN = 9V
VIN = 7V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 5.0 V
Fsw = 1.0 MHz
VOUT = 5.0 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-8. Efficiency vs Output Current
图9-9. Efficiency vs Output Current
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9.2.3 Application Curves (continued)
2
1.75
1.5
1.25
1
1.12
1.11
1.1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
0.75
0.5
0.25
0
6
6.5
7
7.5
8
8.5
9
9.5
10
6
6.5
7
7.5
8
8.5
9
9.5
10
Input Voltage (V)
Input Voltage (V)
VOUT = 5.0 V
Fsw = 1.0 MHz
VOUT = 5.0 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-10. Switching Frequency vs Input Voltage
0.6
图9-11. Switching Frequency vs Input Voltage
0.04
VIN = 7V
VIN = 9V
0.55
0.5
0.035
0.03
0.45
0.4
0.025
0.02
0.35
0.3
0.015
0.01
0.25
0.2
0.005
0
0.15
0.1
-0.005
-0.01
-0.015
-0.02
0.05
0
VIN = 7V
VIN = 9V
-0.05
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 5.0 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
VOUT = 5.0 V
Fsw = 1.0 MHz
Auto PFM/PWM
图9-12. Output Voltage vs Output Current
L = 3.3 μH
图9-13. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 6V
VIN = 9V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 3.3 V
Fsw = 2.5 MHz
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-14. Efficiency vs Output Current
图9-15. Efficiency vs Output Current
3.5
3
2.75
2.5
3
2.5
2
2.25
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.75
1.5
0.5
0
4
5
6
7
8
9
10
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
VOUT = 3.3 V
Fsw = 2.5 MHz
L = 2.2 μH
Auto PFM/PWM
图9-17. Switching Frequency vs Input Voltage
图9-16. Switching Frequency vs Input Voltage
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9.2.3 Application Curves (continued)
0.4
0.35
0.3
0.085
0.08
VIN = 6V
VIN = 9V
0.075
0.07
0.25
0.2
0.065
0.06
0.15
0.1
0.055
0.05
0.05
0
0.045
0.04
-0.05
-0.1
-0.15
-0.2
0.035
0.03
VIN = 6V
VIN = 9V
0.025
0.02
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
VOUT = 3.3 V
Fsw = 2.5 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-19. Output Voltage vs Output Current
图9-18. Output Voltage vs Output Current
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
VIN = 6V
VIN = 9V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 3.3 V
Fsw = 1.0 MHz
VOUT = 3.3 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-20. Efficiency vs Output Current
图9-21. Efficiency vs Output Current
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9.2.3 Application Curves (continued)
2
1.75
1.5
1.25
1
1.2
1.15
1.1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.05
1
0.75
0.5
0.25
0
0.95
4
5
6
7
8
9
10
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V
Fsw = 1.0 MHz
VOUT = 3.3 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-22. Switching Frequency vs Input Voltage
0.65
图9-23. Switching Frequency vs Input Voltage
0.06
VIN = 6V
VIN = 9V
0.6
0.55
0.5
0.055
0.05
0.45
0.4
0.045
0.04
0.35
0.3
0.035
0.03
0.25
0.2
0.15
0.1
0.025
0.02
0.05
0
VIN = 6V
VIN = 9V
0.015
-0.05
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 3.3 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 3.3 V
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
L = 3.3 μH
图9-25. Output Voltage vs Output Current
图9-24. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.8 V
Fsw = 2.5 MHz
VOUT = 1.8 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-26. Efficiency vs Output Current
图9-27. Efficiency vs Output Current
4
3.1
3
3.5
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
0
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 1.8 V
Fsw = 2.5 MHz
VOUT = 1.8 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-28. Switching Frequency vs Input Voltage
图9-29. Switching Frequency vs Input Voltage
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9.2.3 Application Curves (continued)
0.5
0.45
0.4
0.16
0.15
0.14
0.13
0.12
0.11
0.1
VIN = 3V
VIN = 6V
VIN = 9V
0.35
0.3
0.25
0.2
0.15
0.1
0.09
0.08
0.07
0.06
0.05
0.05
0
VIN = 3V
VIN = 6V
VIN = 9V
-0.05
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
Iout (A)
VOUT = 1.8 V
Fsw = 2.5 MHz
L = 2.2 μH
VOUT = 1.8 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
Auto PFM/PWM
图9-30. Output Voltage vs Output Current
图9-31. Output Voltage vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.8 V
Fsw = 1.0 MHz
VOUT = 1.8 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-32. Efficiency vs Output Current
图9-33. Efficiency vs Output Current
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9.2.3 Application Curves (continued)
1.5
1.25
1.2
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.25
1
1.15
1.1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.75
0.5
0.25
0
1.05
1
0.95
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 1.8 V
Fsw = 1.0 MHz
VOUT = 1.8 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-34. Switching Frequency vs Input Voltage
0.5
图9-35. Switching Frequency vs Input Voltage
0.025
VIN = 3V
VIN = 6V
VIN = 9V
0.02
0.015
0.01
0.45
0.4
0.35
0.3
0.005
0
0.25
0.2
-0.005
-0.01
-0.015
-0.02
-0.025
-0.03
-0.035
0.15
0.1
0.05
0
VIN = 3V
VIN = 6V
VIN = 9V
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 1.8 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
VOUT = 1.8 V
Fsw = 1.0 MHz
Auto PFM/PWM
图9-36. Output Voltage vs Output Current
L = 3.3 μH
图9-37. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.2 V
Fsw = 2.5 MHz
VOUT = 1.2 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-38. Efficiency vs Output Current
图9-39. Efficiency vs Output Current
4
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
3.5
3
2.5
2
1.5
1
0.5
0
3
4
5
6
7
8
9
10
Input Voltage (V)
VOUT = 1.2 V
Fsw = 2.5 MHz
VOUT = 1.2 V
Fsw = 2.5 MHz
Forced PWM
图9-41. Switching Frequency vs Input Voltage
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-40. Switching Frequency vs Input Voltage
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9.2.3 Application Curves (continued)
0.7
0.65
0.6
0.16
0.14
0.12
0.1
VIN = 3V
VIN = 6V
VIN = 9V
0.55
0.5
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
VIN = 3V
VIN = 6V
VIN = 9V
0.05
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
Iout (A)
VOUT = 1.2 V
Fsw = 2.5 MHz
VOUT = 1.2 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-42. Output Voltage vs Output Current
图9-43. Output Voltage vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 1.2 V
Fsw = 1.0 MHz
VOUT = 1.2 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-44. Efficiency vs Output Current
图9-45. Efficiency vs Output Current
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9.2.3 Application Curves (continued)
1.4
1.3
1.25
1.2
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.2
1
1.15
1.1
0.8
0.6
0.4
0.2
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.05
1
3
4
5
6
7
8
9
10
3
3.8
4.6
5.4
6.2
7
7.8
8.6
9.4 10
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
VOUT = 1.2 V
Fsw = 1.0 MHz
L = 3.3 μH
Auto PFM/PWM
图9-47. Switching Frequency vs Input Voltage
0.06
图9-46. Switching Frequency vs Input Voltage
0.3
0.25
0.2
VIN = 3V
VIN = 6V
VIN = 9V
0.04
0.02
0
0.15
0.1
-0.02
-0.04
-0.06
-0.08
0.05
0
VIN = 3V
VIN = 6V
VIN = 9V
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
Iout (A)
VOUT = 1.2 V
Fsw = 1.0 MHz
Auto PFM/PWM
VOUT = 1.2 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
图9-48. Output Voltage vs Output Current
图9-49. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 0.6 V
Fsw = 2.5 MHz
VOUT = 0.6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-50. Efficiency vs Output Current
图9-51. Efficiency vs Output Current
3
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
0
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 0.6 V
Fsw = 2.5 MHz
VOUT = 0.6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-52. Switching Frequency vs Input Voltage
图9-53. Switching Frequency vs Input Voltage
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9.2.3 Application Curves (continued)
1.25
1
0.125
0.1
VIN = 3V
VIN = 6V
VIN = 9V
0.075
0.05
0.75
0.5
0.025
0
-0.025
-0.05
-0.075
-0.1
0.25
0
VIN = 3V
VIN = 6V
VIN = 9V
-0.25
-0.5
-0.125
-0.15
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
VOUT = 0.6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
VOUT = 0.6 V
Fsw = 2.5 MHz
L = 2.2 μH
Auto PFM/PWM
图9-55. Output Voltage vs Output Current
图9-54. Output Voltage vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
1E-5
0.0001
0.001
Iout (A)
0.01
0.1 0.2 0.5 1
0.01
0.02 0.03 0.050.07 0.1
Iout (A)
0.2 0.3
0.5 0.7
1
VOUT = 0.6 V
Fsw = 1.0 MHz
VOUT = 0.6 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
Auto PFM/PWM
图9-56. Efficiency vs Output Current
图9-57. Efficiency vs Output Current
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9.2.3 Application Curves (continued)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.5
1.45
1.4
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
0.9
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 0.6 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
VOUT = 0.6 V
Fsw = 1.0 MHz
L = 3.3 μH
Auto PFM/PWM
图9-59. Switching Frequency vs Input Voltage
图9-58. Switching Frequency vs Input Voltage
0.4
0.5
VIN = 3V
VIN = 6V
VIN = 9V
VIN = 3V
VIN = 6V
VIN = 9V
0.45
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Iout (A)
Iout (A)
VOUT = 0.6 V
Fsw = 1.0 MHz
Auto PFM/PWM
图9-60. Output Voltage vs Output Current
VOUT = 0.6 V
Fsw = 1.0 MHz
Forced PWM
L = 3.3 μH
L = 3.3 μH
图9-61. Output Voltage vs Output Current
VIN = 6 V
Fsw = 2.5 MHz
VIN = 6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
VOUT = 3.3 V
IO = 0 A
Auto PFM/PWM
VOUT = 3.3 V
IO = 1 A
图9-62. Start-Up Timing
图9-63. Start-Up Timing
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9.2.3 Application Curves (continued)
VIN = 6 V
Fsw = 2.5 MHz
Auto PFM/PWM
VIN = 6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
VOUT = 3.3 V
IO = 0 A
VOUT = 3.3 V
IO = 0 A
图9-65. Shutdown Timing with Output Discharge Enabled
图9-64. Start-Up into Prebiased Output
VIN = 6 V
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
VIN = 6 V
Fsw = 2.5 MHz
L = 2.2 μH
L = 2.2 μH
IO = 1 A
VOUT = 3.3 V
IO = 0 A to 0.5 A
Auto PFM/PWM
图9-66. Shutdown Timing with Output Discharge Disabled
图9-67. Load Transient Response
VIN = 6 V
Fsw = 2.5 MHz
L = 2.2 μH
VIN = 6 V
VOUT = 3.3 V
Fsw = 2.5 MHz
Auto PFM/PWM
L = 2.2 μH
VOUT = 3.3 V
IO = 0.5 A to 1 A
Auto PFM/PWM
IO = 0 A
图9-68. Load Transient Response
图9-69. Output Voltage Ripple
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9.2.3 Application Curves (continued)
VIN = 6 V
Fsw = 2.5 MHz
VIN = 6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
VOUT = 3.3 V
IO = 1 A
Auto PFM/PWM
VOUT = 3.3 V
IO = 1 A
图9-70. Output Voltage Ripple
图9-71. Output Voltage Ripple
VIN = 6 V
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
VIN = 6 V
VOUT = 3.3 V
Fsw = 2.5 MHz
L = 3.3 μH
L = 2.2 μH
IO = 1 A
IO = 1 A
Auto PFM/PWM
图9-72. Output Voltage Ripple
图9-73. Input Voltage Ripple
40
35
30
25
20
15
10
5
240
210
180
150
120
90
60
30
0
0
-5
-30
-60
-90
-120
-150
-10
-15
-20
-25
-30
Gain
Phase
-180
1000 2000
5000 10000
100000
Frequency (Hz)
1000000
VIN = 6 V
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
VIN = 6 V
Fsw = 2.5 MHz
Forced PWM
L = 2.2 μH
IO = 1 A
VOUT = 0.6 V
IO = 1 A
图9-74. Input Voltage Ripple
图9-75. Bode Plot
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9.3 System Examples
9.3.1 Powering Multiple Loads
In applications where the TPS629211-Q1 is used to power multiple load circuits, it is possible that the total
capacitance on the output is very large. To properly regulate the output voltage, there must be an appropriate AC
signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output voltage ripple
sufficiently high on the VOS pin. With low-ESR ceramic capacitors, the output voltage ripple can get very low, so
it is not recommended to use a large capacitance directly on the output of the device. If there are several load
circuits with their associated input capacitor on a PCB, these loads are typically distributed across the board.
This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for proper
regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n × CIN in 图 9-76
was 32 × 47 μF of ceramic X7R capacitors.
Load1
Rtrace
CIN
VOUT
0.4 V to 5.5 V
VIN
3 V to 10 V
L1
TPS629211-Q1
VIN
SW
Load2
Rtrace
C2
22
EN
VOS
CIN
F
C1
4.7
F
FB/
VSET
R2
MODE/
S-CONF
PG
R1
GND
Loadn
Rtrace
CIN
图9-76. Multiple Loads Example
9.3.2 Inverting Buck-Boost (IBB)
The must generate negative voltage rails for electronic designs is a common challenge. The wide 3-V to 10-V
input voltage range of the TPS629211-Q1 makes it ideal for an inverting buck-boost (IBB) circuit, where the
output voltage is inverted or negative with respect to ground.
The circuit operation in the IBB topology differs from that in the traditional buck topology. Though the
components are connected the same as with a traditional buck converter, the output voltage terminals are
reversed. See 图9-77 and 图9-78.
The maximum input voltage that can be applied to an IBB converter is less than the maximum voltage that can
be applied to the TPS629211-Q1 in a typical buck configuration. This is because the ground pin of the IC is
connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, and not
VIN to ground. Thus, the input voltage range of the TPS629211-Q1 in an IBB configuration becomes 3 V to 10 V
+ VOUT, where VOUT is a negative value.
The output voltage range is the same as when configured as a buck converter, but only negative. Thus, the
output voltage for a TPS629211-Q1 in an IBB configuration can be set between –0.4 V and –5.5 V.
The maximum output current for the TPS629211-Q1 in an IBB topology is normally lower than a traditional buck
configuration due to the average inductor current being higher in an IBB configuration. Traditionally, lower input
or (more negative) output voltages results in a lower maximum output current. However, using a larger inductor
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value or the higher 2.5-MHz frequency setting can be used to recover some or all of this lost maximum current
capability.
When implementing an IBB design, it is important to understand that the IC ground is tied to the negative voltage
rail, and in turn, the electrical characteristics of the TPS629211-Q1 device are referenced to this rail. During
power up, as there is no charge in the output capacitor, the IC GND pin (and VOUT) are effectively 0 V, thus
parameters such as the VIN UVLO and EN thresholds are the same as in a typical buck configuration. However,
after the output voltage is in regulation, due to the negative voltage on the IC GND pin, the device traditionally
continues to operate below what can appear to be the normal UVLO/EN falling thresholds relative to the system
ground. Thus, special care must be taken if the user is using the dynamic mode change feature on the MODE
pin of the TPS629211-Q1 or driving the EN pin from an upstream microcontroller as the high and low thresholds
are relative to the negative rail and not the system ground.
More information on using a DCS regulator in an IBB configuration can be found in the Description
Compensating the Current Mode Boost Control Loop Application Note and Using the TPS6215x in an Inverting
Buck-Boost Topology Application Note.
TPS6292xx
2.2 µH
VIN
VIN
SW
22
F
10
F
EN
VOS
FB/
VSET
MODE/
S-CONF
PG
VOUT
GND
-0.6 V to -5.5 V
图9-77. IBB Example with Adjustable Feedback
TPS6292xx
2.2 µH
VIN
VIN
SW
22
F
10
F
EN
VOS
FB/
VSET
MODE/
S-CONF
PG
GND
VOUT
-0.4 V to -5.5 V
图9-78. IBB Example with Internal Feedback
9.4 Power Supply Recommendations
The power supply to the TPS629211-Q1 must have a current rating according to the supply voltage, output
voltage, and output current of the TPS629211-Q1.
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English Data Sheet: SLVSGD0
TPS629211-Q1
ZHCSO00A –MARCH 2022 –REVISED MARCH 2023
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9.5 Layout
9.5.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more so at high switching
frequencies. Therefore, the PCB layout of the TPS629211-Q1 demands careful attention to make sure proper
operation and to get the performance specified. A poor layout can lead to issues like the following:
• Poor regulation (both line and load)
• Stability and accuracy weaknesses
• Increased EMI radiation
• Noise sensitivity
See 图 9-79 for the recommended layout of the TPS629211-Q1, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin of the
TPS629211-Q1.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an
alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS must be connected with short wires and not nearby high dv/dt signals (for
example, SW). As they carry information about the output voltage, they also must be connected as close as
possible to the actual output voltage (at the output capacitor). The FB resistors, R1 and R2, must be kept close
to the IC and connect directly to those pins and the system ground plane. The same applies for the S-CONFIG/
MODE and VSET programming resistors.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread
the heat through the PCB.
In case any of the digital inputs (EN or S-CONF/MODE pins) must be tied to the input supply voltage at VIN, the
connection must be made directly at the input capacitor as indicated in the schematics.
The recommended layout is implemented on the EVM and shown in the TPS629211-Q1EVM User's Guide.
9.5.2 Layout Example
GND
VOUT
GND
VIN
SW
VOS
PG
EN
FB
S-CONFIG
VIN
图9-79. TPS629211-Q1 Layout
9.5.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
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heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
The following are basic approaches for enhancing thermal performance:
• Improving the power dissipation capability of the PCB design (for example, increasing copper thickness,
thermal vias, number of layers)
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs Application Note and Semiconductor and IC Package Thermal Metrics
Application Note.
The TPS629211-Q1 is designed for a maximum operating junction temperature (TJ) of 150°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the
size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal
resistance. To get an improved thermal behavior, TI recommends to use top layer metal to connect the device
with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved
thermal performance. Additionally, the DYC package option (see 图6-2) with extended leads can also be used to
further reduce the thermal resistance of a design.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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Product Folder Links: TPS629211-Q1
English Data Sheet: SLVSGD0
TPS629211-Q1
ZHCSO00A –MARCH 2022 –REVISED MARCH 2023
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS629211-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Note
• Texas Instruments, TPS629211-Q1EVM User's Guide
• Texas Instruments, Description Compensating the Current Mode Boost Control Loop Application Note
• Texas Instruments, Using the TPS6215x in an Inverting Buck-Boost Topology Application Note
• Texas Instruments, Optimizing the TPS62130/40/50/60 Output Filter Application Note
• Texas Instruments, Optimizing Transient Response of Internally Compensated DC-DC Converters Application
Note
• Texas Instruments, Description Compensating the Current Mode Boost Control Loop Application Note
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGD0
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所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS629211QDRLRQ1
TPS629211QDYCRQ1
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
DRL
DYC
8
8
4000 RoHS & Green
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
T211
T11Q
Samples
Samples
Call TI | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS629211QDRLRQ1 SOT-5X3
DRL
8
4000
180.0
8.4
2.75
1.9
0.8
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-5X3 DRL
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS629211QDRLRQ1
8
4000
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DYC0008A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
1.3
1.1
0.05
TYP
0.00
B
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.375
0.225
5
4
SYMM
1
8
0.27
0.17
8X
0.3
8X
0.1
0.1
C A B
0.75
0.55
8X
0.05
4226548/B 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DYC0008A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.85)
8X (0.4)
SYMM
8
1
8X (0.22)
8X (0.3)
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.15)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4226548/B 12/2021
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DYC0008A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.85)
8X (0.4)
SYMM
8
8X (0.22)
1
8X (0.3)
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.15)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4226548/B 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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采用 SOT583 封装的 Out-of-Audio 式、3.8V 至 30V、3A、200kHz 至 2.2MHz 同步降压转换器 | DRL | 8 | -40 to 150
TI
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