TPS62933 [TI]
TPS62933 3.8-V to 30-V, 3-A Synchronous Buck Converter in SOT583 Package;型号: | TPS62933 |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS62933 3.8-V to 30-V, 3-A Synchronous Buck Converter in SOT583 Package |
文件: | 总47页 (文件大小:4142K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS62933
SLUSEA4A – JUNE 2021 – REVISED DECEMBER 2021
TPS62933 3.8-V to 30-V, 3-A Synchronous Buck Converter in SOT583 Package
1 Features
3 Description
•
Configured for a wide range of applications
– Input voltage range: 3.8 V to 30 V
– Output voltage range: 0.8 V to 22 V
– 3-A continuous output current
– 0.8V ± 1% reference voltage (25°C)
– Operating junction temperature: –40°C to
150°C
– Integrated 76-mΩ and 32-mΩ MOSFETs
– Ultra-low quiescent current: 12 μA (typical)
– Low shutdown current: 2 μA (typical)
– Maximum 98% duty cycle operation
– Precision EN threshold
Ease of use and small solution size
– Peak current control mode with internal
compensation
– Pulse frequency modulation for high light-load
efficiency
The TPS62933 is a high-efficiency, easy-to-use
synchronous buck converter with a wide input voltage
range of 3.8 V to 30 V, and supports up to 3-A
continuous output current and 0.8-V to 22-V output
voltage.
The device employs fixed-frequency peak current
control mode for fast transient response and good
line and load regulation. The optimized internal
loop compensation eliminates external compensation
components over a wide range of output voltage
and operation frequency. Pulse frequency modulation
(PFM) mode maximizes the light load efficiency.
The ULQ (ultra low quiescent) feature is extremely
beneficial for long battery life time in low-power
operation. The switching frequency can be set by the
configuration of the RT pin in the range of 200 kHz
to 2.2 MHz, which allows the user to optimize system
efficiency, solution size, and bandwidth. The soft-start
time can be adjusted by the external capacitor at the
SS pin, which can minimize the inrush current when
driving large capacitive load. This device also has
frequency spread spectrum feature, which helps with
lowering down EMI noise.
•
– Adjustable soft-start time
– Selectable frequency: 200 kHz to 2.2 MHz
– EMI friendly with Frequency Spread Spectrum
– Support start-up with pre-biased output
– Cycle-by-cycle OC limit for both high-side and
low-side MOSFETs
– Non-latched protections for OTP, OCP, OVP,
UVP, and UVLO
– 1.6-mm × 2.1-mm SOT583 package
Create a custom design using the TPS62933 with
the WEBENCH Power Designer
The device provides complete protections including
OTP, OVP, UVLO, cycle-by-cycle OC limit, and UVP
with hiccup mode. This device is in a small SOT583
(1.6-mm × 2.1-mm) package with 0.5-mm pin pitch,
and has an optimized pinout for easy PCB layout and
promotes good EMI performance.
•
2 Applications
•
•
•
•
•
Building automation, appliances, industrial PC
Multifunction printers, enterprise projectors
Portable electronics, connected peripherals
Smart speakers, monitors
Distributed power systems with 5-V, 12-V, 19-V,
24-V input
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
TPS62933
SOT583 (8)
1.60 mm × 2.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN
VIN
GND
EN
BST
SW
FB
CBST
CIN
L
90
VOUT
RFBT
80
VEN
COUT
RFBB
70
SS
RT
60
VOUT=3.3V
VOUT=5V
VOUT=12V
Simplified Schematic
50
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2 3
Efficiency, VIN = 24 V, fSW = 500 kHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62933
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SLUSEA4A – JUNE 2021 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................24
9.1 Application Information............................................. 24
9.2 Typical Application.................................................... 24
9.3 What to Do and What Not to Do............................... 34
10 Power Supply Recommendations..............................35
11 Layout...........................................................................36
11.1 Layout Guidelines .................................................. 36
11.2 Layout Example...................................................... 37
12 Device and Documentation Support..........................38
12.1 Device Support....................................................... 38
12.2 Receiving Notification of Documentation Updates..38
12.3 Support Resources................................................. 38
12.4 Trademarks.............................................................38
12.5 Electrostatic Discharge Caution..............................38
12.6 Glossary..................................................................38
13 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (December 2021)
Page
•
Changed document status from Advance Information to Production Data.........................................................1
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5 Device Comparison Table
PART NUMBER
PFM OR FCCM OR OOA SS OR PG PIN
STATUS
OUTPUT CURRENT
TPS62933
PFM
PFM
SS
SS
Released
3 A
2 A
TPS62932
To be released
TPS62933F
TPS62933O
TPS62933P
3 A
3 A
3 A
FCCM
OOA
PFM
SS
PG
PG
To be released
To be released
To be released
6 Pin Configuration and Functions
RT
EN
FB
1
2
8
7
6
5
SS
BST
SW
VIN 3
4
GND
Figure 6-1. 8-Pin SOT583 DRL Package (Top View)
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Frequency programming input. Float for 500 kHz, tie to GND for 1.2 MHz, or connect to an
RT timing resistor. See Section 8.3.5 for details.
RT
1
A
A
P
Enable input to converter. Driving EN high or leaving this pin floating enables the converter.
An external resistor divider can be used to implement an adjustable VIN UVLO function.
EN
2
3
Supply input terminal to internal LDO and high-side FET. Input bypass capacitors must be
directly connected to this pin and GND.
VIN
Ground terminal. Connected to the source of the low-side FET as well as the ground
terminal for the controller circuit. Connect to system ground and the ground side of CIN
and COUT. The path to CIN must be as short as possible.
GND
4
G
Switching output of the convertor. Internally connected to the source of the high-side FET
and drain of the low-side FET. Connect to power inductor.
SW
5
6
P
P
Bootstrap capacitor connection for high-side FET driver. Connect a high-quality, 100-nF
ceramic capacitor from this pin to the SW pin.
BST
Soft-start and tracking input. An external capacitor connected to this pin sets the internal
voltage reference rising time. See Section 8.3.7 for details. A minimum 6.8-nF ceramic
capacitor must be connected at this pin, which sets the minimum soft-start time to
approximately 1 ms. Do not float.
SS
FB
7
8
A
A
Output feedback input. Connect FB to the tap of an external resistor divider from the output
to GND to set output voltage.
(1) A = Analog, P = Power, G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C , unless otherwise noted(1)
MIN
–0.3
–0.3
–0.3
–0.3
–3
MAX
UNIT
VIN
32
Input voltage
EN
6
6
FB
SW, DC
32
SW, transient < 10 ns
33
V
BST
–0.3
–0.3
–0.3
–0.3
–40
–65
SW + 6
6
Output voltage
BST–SW
SS
6
RT
6
TJ
Operating junction temperature(2)
150
150
°C
Tstg
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Operating at junction temperatures greater than 150°C, although possible, degrades the lifetime of the device.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted(1)
MIN
NOM
MAX
UNIT
VIN
Input voltage EN
FB
3.8
30
–0.1
–0.1
0.8
5.5
5.5
VOUT
22
V
SW, DC
–0.1
–3
30
Output voltage SW, transient < 10 ns
32
BST
–0.1
–0.1
0
SW + 5.5
5.5
BST-SW
Ouput current IOUT
3
A
Temperature Operating junction temperature, TJ
–40
150
°C
(1) The Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For compliant specifications, see the Electrical Characteristics.
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7.4 Thermal Information
TPS62933
THERMAL METRIC(1)
DRL (SOT583), 8 PINS
UNIT
JEDEC(2)
EVM(3)
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
112.2
29.1
19.3
1.6
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
N/A
N/A
Junction-to-top characterization parameter
Junction-to-board characterization parameter
N/A
ΨJB
19.2
N/A
Junction-to-ambient thermal resistance on official
EVM board
RθJA_EVM
N/A
60.2
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were simulated on a standard JEDEC board. They do not represent the performance obtained in an actual application.
(3) The real RθJA on TPS62933EVM is about 60.2°C/W, test condition: VIN = 24 V, VOUT = 5 V, IOUT = 3 A, TA = 25°C.
7.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it. TJ = –40°C to +150°C, VIN = 3.8 V to 30 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY (VIN PIN)
VIN
Operation input voltage
3.8
30
V
µA
µA
V
IQ
Nonswitching quiescent current
Shutdown supply current
EN = 5 V, VFB = 0.85 V
12
ISHDN
VEN = 0 V
2
Rising threshold
Falling threshold
Hysteresis
3.4
3.1
3.6
3.3
300
3.8
3.5
Input undervoltage lockout
thresholds
VIN_UVLO
V
mV
ENABLE (EN PIN)
VEN_RISE Enable threshold
VEN_FALL
Rising enable threshold
Falling disable threshold
1.21
1.17
1.28
V
V
Disable threshold
1.1
Ip
Ih
EN pullup current
VEN = 1.0 V
VEN = 1.5 V
0.7
1.4
µA
µA
EN pullup hysteresis current
VOLTAGE REFERENCE (FB PIN)
TJ = 25°C
792
788
784
800
800
800
808
812
816
0.15
mV
mV
mV
μA
VFB
FB voltage
TJ = 0°C to 85°C
TJ = –40°C to 150°C
VFB = 0.8 V
IFB
Input leakage current
INTEGRATED POWER MOSFETS
RDSON_HS High-side MOSFET on-resistance TJ = 25°C, VBST – SW = 5 V
RDSON_LS
CURRENT LIMIT
76
32
mΩ
mΩ
Low-side MOSFET on-resistance
TJ = 25°C
IHS_LIMIT
ILS_LIMIT
IPEAK_MIN
High-side MOSFET current limit
TPS62933
TPS62933
TPS62933
4.2
2.9
5
5.8
4.5
A
A
A
Low-side MOSFET current limit
Minimum peak inductor current
3.8
0.75
SOFT START (SS PIN)
ISS
Soft-start charge current
4.5
5.5
6.5
μA
OSCILLATOR FREQUENCY (RT PIN)
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The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it. TJ = –40°C to +150°C, VIN = 3.8 V to 30 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RT = Floating
450
500
550
RT = GND
1000
1200
310
2100
70
1350
fSW
Switching center frequency
kHz
RT = 71.5 kΩ
RT = 9.09 kΩ
(1)
tON_MIN
Minimum ON pulse width
Minimum OFF pulse width
Maximum ON pulse width
ns
ns
μs
(1)
(1)
tOFF_MIN
tON_MAX
140
7
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
OVP detect (L→H)
112%
115%
5%
118%
VOVP
Output OVP threshold
Hysteresis
VUVP
Output UVP threshold
UVP detect (H→L)
65%
UV hiccup ON time before entering
hiccup mode after soft start ends
thiccup_ON
256
μs
S
10.5 ×
tSS
thiccup_OFF
UV hiccup OFF time before restart
THERMAL SHUTDOWN
(1)
TSHDN
Thermal shutdown threshold
Shutdown temperature
Hysteresis
165
30
°C
°C
(1)
THYS
SPREAD SPECTRUM FREQUENCY
fSW
128
/
fm
Modulation frequency
kHz
fspread
Internal spread oscillator frequency
±6%
(1) Not production tested, ensured by design.
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7.6 Typical Characteristics
TJ = –40°C to 150°C, VIN = 12 V, unless otherwise noted.
18
17
16
15
14
13
12
11
10
5
4
3
2
1
0
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-1. Quiescent Current vs Junction
Temperature
Figure 7-2. Shutdown Current vs Junction
Temperature
140
50
45
40
35
30
25
20
120
100
80
60
40
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-3. High-Side RDSON vs Junction
Temperature
Figure 7-4. Low-Side RDSON vs Junction
Temperature
820
815
810
805
800
795
790
785
780
1.35
1.3
1.25
1.2
1.15
1.1
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-5. Feedback Voltage vs Junction
Temperature
Figure 7-6. Enable Threshold vs Junction
Temperature
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1.3
1.25
1.2
3.65
3.6
3.55
3.5
1.15
1.1
3.45
1.05
3.4
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-7. Disable Threshold vs Junction
Temperature
Figure 7-8. VIN UVLO Rising Threshold vs Junction
Temperature
3.5
600
575
550
525
500
475
450
425
400
3.45
3.4
3.35
3.3
3.25
3.2
3.15
3.1
-40 -20
0
20
40
60
80 100 120 140 160
-40
0
40
80
120
160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-9. VIN UVLO Falling Threshold vs Junction Figure 7-10. Switching Frequency (RT Floating) vs
Temperature Junction Temperature
5.2
5.15
5.1
4
3.9
3.8
3.7
3.6
3.5
3.4
5.05
5
4.95
4.9
4.85
4.8
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-11. High-Side Current Limit vs Junction
Temperature
Figure 7-12. Low-Side Current Limit vs Junction
Temperature
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117
66
65
64
63
116
115
114
113
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-13. OVP Threshold vs Junction
Temperature
Figure 7-14. UVP Threshold vs Junction
Temperature
5.8
5.7
5.6
5.5
5.4
5.3
100
95
90
85
80
75
70
65
60
55
50
Vin=6V
Vin=12V
Vin=19V
Vin=24V
-40 -20
0
20
40
60
80 100 120 140 160
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2 3
Junction Temperature (°C)
Figure 7-15. Soft-Start Charge Current vs Junction Figure 7-16. Efficiency, VOUT = 3.3 V, fSW = 500 kHz,
Temperature
L = 4.7 µH
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
Vin=6V
Vin=12V
Vin=19V
Vin=24V
Vin=19V
Vin=24V
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2
3
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2 3
Figure 7-17. Efficiency, VOUT = 3.3 V, fSW = 1200
kHz, L = 2.2 µH
Figure 7-18. Efficiency, VOUT = 12 V , fSW = 500 kHz,
L = 12 µH
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1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Vin=6V
Vin=6V
Vin=12V
Vin=19V
Vin=24V
Vin=12V
Vin=19V
Vin=24V
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2
3
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2 3
Figure 7-19. Load Regulation, VOUT = 3.3 V, fSW
500 kHz
=
Figure 7-20. Load Regulation, VOUT = 3.3 V, fSW
1200 kHz
=
1
0.8
0.6
0.4
0.2
0
1
Iout=0A
Iout=0.03A
Iout=0.3A
Iout=1.5A
Iout=3A
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
Vin=19V
Vin=24V
-0.8
-1
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2
3
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
Vin (V)
Figure 7-21. Load Regulation, VOUT = 12 V, fSW
500 kHz
=
Figure 7-22. Line Regulation, VOUT = 3.3 V, fSW
500 kHz
=
1
600
Iout=0A
Iout=0.03A
Iout=0.3A
Iout=1.5A
Iout=3A
Vin=6V
Vin=12V
Vin=19V
Vin=24V
Vin=30V
0.8
0.6
0.4
0.2
0
500
400
300
200
100
0
-0.2
-0.4
-0.6
-0.8
-1
12
14
16
18
20
22
24
26
28
30
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2 3
Vin (V)
Figure 7-23. Line Regulation, VOUT = 12 V, fSW = 500 Figure 7-24. Switching Frequency vs Load Current,
kHz
VOUT = 3.3 V, fSW = 500 kHz (RT Floating)
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1400
1200
1000
800
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1400
1200
1000
800
600
400
200
0
Vin=6V
Vin=12V
Vin=19V
Vin=24V
Vin=30V
600
400
200
fSW=500kHz
fSW=1200kHz
0
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2 3
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Vin (V)
Figure 7-25. Switching Frequency vs Load Current,
VOUT = 3.3 V, fSW = 1200 kHz (RT to GND)
Figure 7-26. Switching Frequency vs VIN, VOUT
3.3 V, IOUT = 3 A
=
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8 Detailed Description
8.1 Overview
The TPS62933 is a 30-V, 3-A, synchronous buck (step-down) converter with two integrated n-channel
MOSFETs. It employs fixed-frequency peak current control mode for fast transient response and good line and
load regulation. With the optimized internal loop compensation, the device eliminates the external compensation
components over a wide range of output voltage and switching frequency.
The integrated 76-mΩ and 32-mΩ MOSFETs allow for high-efficiency power supply designs with continuous
output currents up to 3 A. The feedback reference voltage is designed at 0.8 V. The output voltage can be
stepped down from 0.8 V to 22 V. It is ideally suited for systems powered from 5-V, 12-V, 19-V, and 24-V
power-bus rails.
The TPS62933 has been designed for safe monotonic start-up into pre-biased loads. The default start-up is at
VIN equal to 3.8 V. After the device is enabled, the output rises smoothly from 0 V to its regulated voltage. The
total operating current is 12 μA (typical) when not switching under no load. When the device is disabled, the
supply current is approximately 2 µA (typical). The pulse frequency modulation (PFM) mode maximizes the light
load efficiency. These features are extremely beneficial for long battery life time in low-power operation.
The EN pin has an internal pullup current that can be used to adjust the input voltage undervoltage lockout
(UVLO) with two external resistors. In addition, the EN pin can be floating for the device to operate with the
internal pullup current.
The switching frequency can be set by the configuration of the RT pin in the range of 200 kHz to 2.2 MHz, which
allows for efficiency and solution size optimization when selecting the output filter components. This device also
has frequency spread spectrum feature which helps with lowering down EMI noise.
The SS (soft start/tracking) pin is used to minimize inrush current when driving capacitative load. A small value
capacitor or resistor divider is connected to the SS pin for soft-start time setting or voltage tracking.
The device has the on-time extension function with a maximum on time of 7 μs (typical). During the low dropout
operation, the high-side MOSFET can turn on up to 7 μs, then the high-side MOSFET turns off and the low-side
MOSFET turns on with a minimum off time of 140 ns (typical). It supports the maximum 98% duty cycle.
The device reduces the external component count by integrating the bootstrap circuit. The bias voltage for the
integrated high-side MOSFET is supplied by a capacitor between the BST and SW pins. A UVLO circuit monitors
the bootstrap capacitor voltage VBST-SW. When it falls below a preset threshold of 2.5 V (typical), the SW pin is
pulled low to recharge the bootstrap capacitor.
Cycle-by-cycle current limiting on the high-side MOSFET protects the device in overload situations and is
enhanced by a low-side sourcing current limit, which prevents current runaway. The TPS62933 provides output
undervoltage protection (UVP) when the regulated output voltage is lower than 65% of the nominal voltage
due to overcurrent being triggered, about 256-μs (typical) deglitch time later, both the high-side and low-side
MOSFET turn off, the device steps into hiccup mode.
The device minimizes excessive output overvoltage transient by taking advantage of the overvoltage
comparator. When the regulated output voltage is greater than 115% of the nominal voltage, the overvoltage
comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output
voltage is lower than 110%.
Thermal shutdown disables the device when the die temperature, TJ, exceeds 165°C and enables the device
again after TJ decreases below the hysteresis amount of 30°C.
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8.2 Functional Block Diagram
EN
VCC
Enable
LDO
VIN
ISS
Precision
Enable
BST
HSI Sense
SS
REF
EA
FB
RC
CC
TSD
UVLO
PWM CONTROL LOGIC
PFM
Detector
SW
Slope
Comp
Ton_min/Toff_min
Detector
Freq
Foldback
HICCUP
Detector
Zero
Cross
LSI Sense
Oscillator
FB
GND
RT
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8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode
The following operation description of the TPS62933 refers to the functional block diagram and to the waveforms
in Figure 8-1. The TPS62933 is a synchronous buck converter with integrated high-side (HS) and low-side (LS)
MOSFETs (synchronous rectifier). The TPS62933 supplies a regulated output voltage by turning on the HS
and LS NMOS switches with controlled duty cycle. During high-side switch on time, the SW pin voltage swings
up to approximately VIN, and the inductor current, iL, increases with linear slope (VIN – VOUT) / L. When the
HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot–through dead time.
Inductor current discharges through the low-side switch with a slope of –VOUT / L. The control parameter of a
buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch on time and TSW is
the switching period. The converter control loop maintains a constant output voltage by adjusting the duty cycle
D. In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
VSW
VIN
D = tON/ TSW
tON
tOFF
t
0
TSW
iL
ILPK
IOUT
∆iL
t
0
Figure 8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The TPS62933 employs the fixed-frequency peak current mode control. A voltage feedback loop is used to
get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The
peak inductor current is sensed from the HS switch and compared to the peak current threshold to control
the on time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The converter operates with fixed switching frequency at normal load condition. At light-load
condition, the TPS62933 operates in PFM mode to maintain high efficiency.
8.3.2 Pulse Frequency Modulation
The TPS62933 is designed to operate in pulse frequency modulation (PFM) mode at light load currents to boost
light load efficiency.
When the load current is lower than half of the peak-to-peak inductor current in CCM, the TPS62933 operates
in discontinuous conduction mode (DCM). In DCM operation, the low-side switch is turned off when the inductor
current drops to approximately 0 A to improve efficiency. Both switching losses and conduction losses are
reduced in DCM, compared to forced CCM operation at light load.
At even lighter current load, pulse frequency modulation (PFM) mode is activated to maintain high-efficiency
operation. When either the minimum high-side switch on time tON_MIN or the minimum peak inductor current
IPEAK_MIN (typically 750 mA) is reached, the switching frequency decreases to maintain regulation. In PFM mode,
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the switching frequency is decreased by the control loop to maintain output voltage regulation when load current
reduces. Switching loss is further reduced in PFM operation due to less frequent switching actions. Since the
integrated current comparator catches the peak inductor current only, the average load current entering PFM
mode varies with the applications and external output LC filters.
In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to
the load. The duration of the burst depends on how long it takes the feedback voltage catches VREF. The
periodicity of these bursts is adjusted to regulate the output, while zero current crossing detection turns off the
low-side MOSFET to maximize efficiency. This mode provides high light-load efficiency by reducing the amount
of input supply current required to regulate the output voltage at small loads. This trades off very good light-load
efficiency for larger output voltage ripple and variable switching frequency.
8.3.3 Voltage Reference
The internal reference voltage VREF is designed at typical 0.8 V, the negative feedback system of converter
produces a precise ±2% feedback voltage VFB over full temperature by scaling the output of a temperature
stable internal bandgap circuit.
8.3.4 Output Voltage Setting
A precision 0.8-V reference voltage, VREF, is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from the output voltage to the FB pin.
It is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
bottom-side resistor, RFBB, for the desired divider current and use Equation 1 to calculate the top-side resistor,
R
FBT. Lower RFBB increases the divider current and reduces efficiency at very light load. Larger RFBB makes
the FB voltage more susceptible to noise, so the larger RFBB value requires more carefully designed feedback
path on the PCB. Setting RFBB = 10 kΩ and RFBT in the range of 10 kΩ to 300 kΩ is recommended for most
applications.
The tolerance and temperature variation of the resistor dividers affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
Figure 8-2. Output Voltage Setting
VOUT - VREF
RFBT
=
× RFBB
VREF
(1)
where
•
•
VREF = 0.8 V, the internal reference voltage
RFBB = 10 kΩ is recommended
8.3.5 Switching Frequency Selection
The switching frequency is set by the condition of the RT input. The condition of this input is detected when the
device is first enabled. Once the converter is running, the switching frequency selection is fixed and cannot be
changed until the next power-on cycle or EN toggle. Table 8-1 shows the selection programming. In adjustable
frequency mode, the switching frequency can be set between 200 kHz and 2200 kHz by proper selection of RT
resistor. See Equation 2.
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(2)
where
•
•
RT = the value of RT timing resistor in kΩ
fSW = the switching frequency in kHz
Table 8-1. RT Pin Resistor Settings
RT PIN
Floating
GND
RESISTANCE
SWITCHING FREQUENCY
> 280 kΩ
500 kHz
1200 kHz
< 1 kΩ
RT to GND
8.9 kΩ to 111 kΩ
200 kHz to 2200 kHz
Figure 8-3 indicates the required resistor value for RT to set a desired switching frequency.
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
8
18 28 38 48 58 68 78 88 98 108 118
RT (kohm)
Figure 8-3. Switching Frequency Versus RT
There are four cases where the switching frequency does not conform to the condition set by the RT pin:
•
•
•
•
Light load operation (PFM mode)
Low dropout operation
Minimum on-time operation
Current limit tripped
Under all of these cases, the switching frequency folds back, meaning it is less than that programmed by the RT
pin. During these conditions, the output voltage remains in regulation, except for current limit operation.
8.3.6 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage exceeds the enable
threshold voltage, VEN_RISE, the TPS62933 begins operation. If the EN pin voltage is pulled below the disable
threshold voltage, VEN_FALL, the converter stops switching and enters shutdown mode.
The EN pin has an internal pullup current source, which allows the user to float the EN pin to enable the device.
If an application requires control of the EN pin, use open-drain or open-collector or GPIO output logic to interface
with the pin.
The TPS62933 implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN_UVLO threshold. The internal VIN_UVLO threshold has a
hysteresis of typical 300 mV. If an application requires a higher UVLO threshold on the VIN pin, the EN pin can
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be configured as shown in Figure 8-4. When using the external UVLO function, setting the hysteresis at a value
greater than 500 mV is recommended.
The EN pin has a small pullup current, Ip, which sets the default state of the EN pin to enable when no external
components are connected. The pullup hysteresis current Ih is used to control the hysteresis voltage for the
UVLO function when the EN pin voltage crosses the enable threshold. Use Equation 3 and Equation 4 to
calculate the values of R1 and R2 for a specified UVLO threshold. Once R1, R2 are settled down, the VEN can
be calculated by Equation 5, which must be lower than 5.5 V with max VIN.
VIN
Device
R1
R2
Ip
Ih
EN
Figure 8-4. Adjustable VIN Undervoltage Lockout
(3)
(4)
(5)
R1 ì VEN_FALL
R2 =
VSTOP - VEN_FALL + R ì I +I
1
p
h
R ì V +R ìR ì I +I
(
)
2
IN
1
2
p
h
VEN
=
R1+R2
where
•
•
•
•
•
•
Ip = 0.7 µA
Ih = 1.4 µA
VEN_FALL = 1.17 V
VEN_RISE = 1.21 V
VSTART = input voltage enabling the device
VSTOP = input voltage disabling the device
8.3.7 External Soft Start and Pre-Biased Soft Start
The SS pin is used to minimize inrush current when driving capacitative load. The TPS62933 device uses
the lower voltage of the internal voltage reference, VREF, or the SS pin voltage as the reference voltage and
regulates the output accordingly. A capacitor on the SS pin to ground implements a soft-start time. The device
has an internal pullup current source that charges the external soft-start capacitor. Use Equation 6 to calculate
the soft time (tSS, 0% to 100%) and soft-start capacitor (CSS).
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CSS ì VREF
ISS
tSS
=
(6)
where
•
•
VREF = 0.8 V, the internal reference voltage
ISS = 5.5 µA (typical), the internal pullup current
If the output capacitor is pre-biased at start-up, the device initiates switching and starts ramping up only after
the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
A resistor divider is connected to the SS pin can implement voltage tracking of other power rail.
8.3.8 Minimum On Time, Minimum Off Time, and Frequency Foldback
Minimum on time (tON_MIN) is the smallest duration of time that the high-side switch can be on. tON_MIN is typical
70 ns in the TPS62933. Minimum off time (tOFF_MIN) is the smallest duration that the high-side switch can be
off. tOFF_MIN is typical 140 ns. In CCM operation, tON_MIN and tOFF_MIN limit the voltage conversion range without
switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is:
DMIN = tON_MIN × fSW
(7)
The maximum duty cycle without frequency foldback allowed is:
DMAX = 1 F tOFF _MIN × fSW
(8)
Given a required output voltage, the maximum VIN without frequency foldback is:
VOUT
V
=
IN_MAX
fSW × tON_MIN
(9)
The minimum VIN without frequency foldback is:
VOUT
V
IN_MIN
=
1 F fSW × tOFF _MIN
(10)
In TPS62933, a frequency foldback scheme is employed once tON_MIN or tOFF_MIN is triggered, which can extend
the maximum duty cycle or lower the minimum duty cycle.
The on time decreases while VIN voltage increases. Once the on time decreases to tON_MIN, the switching
frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in
regulation according to Equation 7.
The frequency foldback scheme also works once larger duty cycle is needed under low VIN condition. The
frequency decreases once the device hits its tOFF_MIN, which extends the maximum duty cycle according to
Equation 8. Wide range of frequency foldback allows the TPS62933 output voltage to stay in regulation with a
much lower supply voltage VIN, which allows a lower effective dropout.
With frequency foldback, VIN_MAX is raised, and VIN_MIN is lowered by decreased fSW
.
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1300
1200
1100
1000
900
1500
1250
1000
750
500
250
0
800
700
Iout=1.5A
Iout=3A
600
Iout=3A
Iout=1.5A
500
12
14
16
18
20
22
24
26
28
30
4
5
6
7
8
9
10
11
12
Vin (V)
Vin (V)
Figure 8-5. Frequency Foldback at TON_MIN, VOUT
1.8 V, fSW = 1200 kHz
=
Figure 8-6. Frequency Foldback at TOFF_MIN, VOUT
5 V, fSW = 1200 kHz
=
8.3.9 Frequency Spread Spectrum
In order to reduce EMI, the TPS62933 introduces frequency spread spectrum. The jittering span is typically
Δfc = ±6% of the switching frequency with the modulation frequency of fm = fSW/128. The purpose of spread
spectrum is to eliminate peak emissions at specific frequencies by spreading emissions across a wider range
of frequencies than a part with fixed frequency operation. Figure 8-7 shows the frequency spread spectrum
modulation. Figure 8-8 shows the energy is spread out at the center frequency fc.
fmax = fc * (1 + 6%)
Center Frequency fc
fmin = fc * (1 - 6%)
Modulation Frequency fm = fsw/128
Figure 8-7. Frequency Spread Spectrum Diagram
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Energy
fm
Frequency
fc
Figure 8-8. Energy Versus Frequency
8.3.10 Overvoltage Protection
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.
The OVP feature minimizes the overshoot by comparing the FB pin voltage to the OVP threshold. If the FB pin
voltage is greater than the OVP threshold of 115%, the high-side MOSFET is turned off, which prevents current
from flowing to the output and minimizes output overshoot. When the FB pin voltage drops lower than the OVP
threshold minus hysteresis, the high-side MOSFET is allowed to turn on at the next clock cycle. This function is
non-latch operation.
8.3.11 Overcurrent and Undervoltage Protection
The TPS62933 incorporates both peak and valley inductor current limits to provide protection to the device from
overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current
run-away during short circuits on the output, while both peak and valley limits work together to limit the maximum
output current of the converter. Hiccup mode is also incorporated for sustained short circuits.
The high-side switch current is sensed when it is turned on after a set blanking time (tON_MIN), the peak current
of high-side switch is limited by the peak current threshold, IHS_LIMIT. The current going through low-side switch
is also sensed and monitored. When the low-side switch turns on, the inductor current begins to ramp down.
As the device is overloaded, a point is reached where the valley of the inductor current cannot reach below
ILS_LIMIT before the next clock cycle, then the low-side switch is kept on until the inductor current ramps below
the valley current threshold, ILS_LIMIT, then the low-side switch is turned off and the high-side switch is turned
on after a dead time. When this occurs, the valley current limit control skips that cycle, causing the switching
frequency to drop. Further overload causes the switching frequency to continue to drop, but the output voltage
remains in regulation. As the overload is increased, both the inductor current ripple and peak current increase
until the high-side current limit, IHS_LIMIT, is reached. When this limit is tripped, the switch duty cycle is reduced
and the output voltage falls out of regulation. This represents the maximum output current from the converter
and is given approximately by Equation 11. The output voltage and switching frequency continue to drop as the
device moves deeper into overload while the output current remains at approximately IOMAX. There is another
situation, if the inductor ripple current is large, the high-side current limit can be tripped before the low-side limit
is reached. In this case, Equation 12 gives the approximate maximum output current.
IHS _LIMIT +ILS _LIMIT
IOMAX
ö
2
(11)
(12)
(V -VOUT
)
VOUT
IN
IOMAX ö IHS _LIMIT
-
ì
2ìL ì fSW
V
IN
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Furthermore, if a severe overload or short circuit causes the FB voltage to fall below VUVP threshold, 65% of the
VREF, and triggering current limit, and the condition occurs for more than the hiccup ON time (typical 256 μs), the
converter enters hiccup mode. In this mode, the device stops switching for hiccup off time, 10.5 × tSS, and then
goes to a normal restart with soft-start time. If the overload or short-circuit condition remains, the device runs
in current limit and then shuts down again. This cycle repeats as long as the overload or short-circuit condition
persists. This mode of operation reduces the temperature rise of the device during a sustained overload or short
circuit condition on the output. Once the output short is removed, the output voltage recovers normally to the
regulated value.
8.3.12 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 165°C
(typical), the device goes into thermal shut down, both the high-side and low-side power FETs are turned off.
When TJ decreases below the hysteresis amount of 30°C (typical), the converter resumes normal operation,
beginning with a soft start.
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8.4 Device Functional Modes
8.4.1 Modes Overview
The TPS62933 moves between CCM, DCM, and PFM mode as the load changes. Depending on the load
current, the TPS62933 will be in one of below modes:
•
•
•
Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple.
Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation.
Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load.
8.4.2 Heavy Load Operation
The TPS62933 operates in continuous conduction mode (CCM) when the load current is higher than half of
the peak-to-peak inductor current. In CCM operation, the output voltage is regulated by switching at a constant
frequency and modulating the duty cycle to control the power to the load. This provides excellent line and
load regulation and minimum output voltage ripple, and the maximum continuous output current of 3 A can be
supplied by the TPS62933.
8.4.3 Light Load Operation (PFM Version)
For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
device operates in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In DCM
operation, the LS switch is turned off when the inductor current drops to ILS_ZC (150 mA typical) to improve
efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced CCM operation
at light load.
At even lighter current load, pulse frequency modulation (PFM) mode is activated to maintain high efficiency
operation. When either the minimum ON time, tON_MIN, or the minimum peak inductor current, IPEAK_MIN, (750
mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode, switching
frequency is decreased by the control loop to maintain output voltage regulation when load current reduces.
Switching loss is further reduced in PFM operation due to less frequent switching actions. The output current
for mode change depends on the input voltage, inductor value, and the programmed switching frequency. For
applications where the switching frequency must be known for a given condition, the transition between PFM
and CCM must be carefully tested before the design is finalized.
8.4.4 Dropout Operation
The dropout performance of any buck converter is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage level
approaches the output voltage, the off time of the high-side MOSFET starts to approach the minimum value.
Beyond this point, the switching frequency becomes erratic and the output voltage can fall out of regulation. To
avoid this problem, the TPS62933 automatically reduces the switching frequency (on-time extension function) to
increase the effective duty cycle and maintain in regulation until the switching frequency reach to the lowest limit
of about 140 kHz, the period is equal to (tON_MAX + tOFF_MIN) (7.14-μS typical). In this condition, the difference
voltage between VIN and VOUT is defined as dropout voltage. The typical overall dropout characteristics can be
found as Figure 8-9.
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5.5
5
4.5
4
3.5
3
Io=0.5A
Io=3A
4
4.5
5
5.5
6
6.5
7
7.5
8
Vin (V)
Figure 8-9. Overall Dropout Characteristic, VOUT = 5 V
8.4.5 Minimum On-Time Operation
Every switching converter has a minimum controllable on time dictated by the inherent delays and blanking
times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the TPS62933 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage
at the maximum input voltage. Use Equation 13 to find an estimate for the approximate input voltage for a given
output voltage before frequency foldback occurs. The values of tON_MIN and ƒSW can be found in Section 7.5.
VOUT
VIN ≤
tON_MIN × fSW
(13)
As the input voltage is increased, the switch on time (duty-cycle) reduces to regulate the output voltage. When
the on time reaches the minimum on time, tON_MIN, the switching frequency drops while the on time remains
fixed.
8.4.6 Shutdown Mode
The EN pin provides electrical ON and OFF control for the device. When VEN is below typical 1.1 V, the
TPS62933 is in shutdown mode. The device also employs VIN UVLO protection. If VIN voltage is below their
respective UVLO level, the converter is turned off too.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS62933 is a highly integrated, synchronous, step-down, DC-DC converter. This device is used to convert
a higher DC input voltage to a lower DC output voltage, with a maximum output current of 3 A.
9.2 Typical Application
The application schematic of Figure 9-1 was developed to meet the requirements of the device. This circuit is
available as the TPS62933EVM evaluation module. The design procedure is given in this section.
L1
VOUT = 5V/3A
VOUT
C5
R4
0
U1
VIN
BST
VIN = 5.5V to 30V
VIN
6.8uH
VIN
EN
3
2
7
1
6
5
8
4
100nF
BST
SW
C6
C7
C8
SW
FB
22uF
22uF
100nF
EN
SS
C1
C2
C3
R6
GND
10µF
10µF
100nF
JP1
SS
FB
3
2
1
53.6k
GND
RT
GND
RT
GND
R1
C9
R5
GND
511k
R7
TPS62933DRLR
DNP
C4
10.2k
49.9
10pF
1
2
33nF
JP2
R2
88.7k
R3
0
GND
GND
GND
GND
GND
Figure 9-1. TPS62933 5-V Output, 3-A Reference Design
9.2.1 Design Requirements
Table 9-1 shows the design parameters for this application.
Table 9-1. Design Parameters
PARAMETER
Input voltage
CONDITIONS
MIN
TYP
MAX
UNIT
VIN
5.5
24
5
30
V
V
A
V
VOUT
IOUT
Output voltage
Output current rating
Transient response
3
ΔVOUT
Load step from 0.5 A→2.5
A→0.5 A, 0.8-A/μS slew rate
±5% ×
VOUT
VIN(ripple)
VOUT(ripple)
FSW
Input ripple voltage
400
30
500
5
mV
mV
kHz
mS
V
Output ripple voltage
Switching frequency
RT = floating
CSS = 33 nF
tSS
Soft-start time
VSTART
VSTOP
TA
Start input voltage (Rising VIN)
Stop input voltage (Falling VIN)
Ambient temperature
8
7
V
25
°C
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9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
To create a custom design using the TPS62933 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%
tolerance or better divider resistors. Referring to the application schematic of Figure 9-1, start with 10.2 kΩ for
R7 and use Equation 14 to calculate R6 = 53.6 kΩ. To improve efficiency at light loads, consider using larger
value resistors. If the values are too high, the converter is more susceptible to noise and voltage errors from the
FB input leakage current are noticeable.
VOUT - VREF
VREF
R6 =
ìR7
(14)
Table 9-2 shows the recommended components value for common output voltages.
9.2.2.3 Choosing Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Higher switching frequency allows the use of smaller inductors and output capacitors, and hence, a more
compact design. However, lower switching frequency implies reduced switching losses and usually results in
higher system efficiency, so the 500-kHz switching frequency was chosen for this example, remove the jumper
on JP2 and leave RT pin floating.
Please note the switching frequency is also limited by the following as mentioned in Section 8.3.8:
•
•
•
•
Minimum on time of the integrated power switch
Input voltage
Output voltage
Frequency shift limitation
9.2.2.4 Soft-Start Capacitor Selection
The large CSS can reduce inrush current when driving large capacitive load, here chooses 33 nF for C4 which
sets the soft start time tSS to approximately 5 mS.
In addition, the SS pin cannot be floated, a minimum 6.8-nF capacitor must be connected at this pin.
9.2.2.5 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BST to SW pins for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor C5 must have a
16-V or higher voltage rating.
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In addition, Adding one BST resistor R4 to reduce the spike voltage on the SW node, the resistance smaller than
10 Ω is recommended to be used between BST to the bootstrap capacitor.
9.2.2.6 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2.
R1 is connected between VIN and the EN pin of the TPS62933 and R2 is connected between EN and GND.
The UVLO has two thresholds: one for power up when the input voltage is rising and one for power down
or brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching when the input voltage increases above 8 V (VSTART). After the converter starts switching, it should
continue to do so until the input voltage falls below 7 V (VSTOP). Equation 3 and Equation 4 can be used
to calculate the values for the upper and lower resistor values. For the stop voltages specified, the nearest
standard resistor value for R1 is 511 kΩ and for R2 is 80.7 kΩ.
9.2.2.7 Output Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL, which can be calculated by Equation 15.
VOUT
V
F VOUT
IN_MAX
¿IL =
×
V
L × fSW
IN_MAX
(15)
Usually, define K coefficient represents the amount of inductor ripple current relative to the maximum output
current of the device, a reasonable value of K should be 20% to 60%, experience shows that the best value of
K is 40%. Since the ripple current increases with the input voltage, the maximum input voltage is always used to
calculate the minimum inductance L. Use Equation 16 to calculate the minimum value of the output inductor.
(V -VOUT
)
VOUT
IN
L =
ì
fSW ìK ìIOUT _MAX
V
IN
(16)
where
K = Ripple ratio of the inductor current (ΔIL / IOUT_MAX
•
)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low
of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full
load can be falsely triggered. It also generates more inductor core loss since the current ripple is larger. Larger
inductor current ripple also implies larger output voltage ripple with the same output capacitors.
After inductance L is determined, the maximum inductor peak current and RMS current can be calculated by
Equation 17 and Equation 18.
¿IL
IL_PEAK = IOUT
+
2
(17)
2
¿IL
2
¨
IOUT
IL_RMS
=
+
12
(18)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit,
IHS_LIMIT (see Section 7.5). This ensures that the inductor does not saturate even during a short circuit on
the output. When the inductor core material saturates, the inductance falls to a very low value, causing the
inductor current to rise very rapidly. Although the valley current limit, ILS_LIMIT, is designed to reduce the risk of
current runaway, a saturated inductor can cause the current to rise to high values very rapidly, this can lead to
component damage, so do not allow the inductor to saturate. In any case, the inductor saturation current must
not be less than the maximum peak inductor current at full load.
For this design example, choose the following values:
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•
•
•
•
K = 0.4
VIN_MAX = 30 V
fSW = 500 kHz
IOUT_MAX = 3 A
The inductor value is calculated to be 6.94 μH. Choose the nearest standard value of 6.8 μH. This gives a new K
value of 0.408. The max IHS_LIMIT is 5.8 A, the calculated peak current is 3.61 A, and the calculated RMS current
is 3.02 A. The chosen inductor is a Würth Elektronik, 74439346068, 6.8 μH, which has a saturation current rating
of 10 A and a RMS current rating of 6.5 A.
The maximum inductance is limited by the minimum current ripple required for the peak current mode control
to perform correctly. To avoid subharmonic oscillation, as a rule-of-thumb, the minimum inductor ripple current
should be no less than about 10% of the device maximum rated current (3 A) under nominal conditions.
9.2.2.8 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output
capacitance as possible to keep cost and size down. The output capacitance, COUT, should be chosen with care
since it directly affects the following specification:
•
•
•
Steady state output voltage ripple
Loop stability
Output voltage overshoot and undershoot during load current transient
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple
going through the Equivalent Series Resistance (ESR) of the output capacitors:
¿VOUT _ESR = ¿IL × ESR = K × IOUT × ESR
(19)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
¿IL
K × IOUT
¿VOUT _C
=
=
8 × fSW × COUT 8 × fSW × COUT
(20)
K is the ripple ratio of the inductor current (ΔIL / IOUT_MAX). The two components in the voltage ripple are not in
phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.
Output capacitance is usually limited by the load transient requirements rather than the output voltage ripple
if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a
large load step happens, output capacitors provide the required charge before the inductor current can slew up
to the appropriate level. The control loop of the converter usually needs eight or more clock cycles to regulate
the inductor current equal to the new load level. The output capacitance must be large enough to supply the
current difference for about eight clock cycles to maintain the output voltage within the specified range. Equation
21 shows the minimum output capacitance needed for specified VOUT overshoot and undershoot.
K2
»
ÿ
Ÿ
DIOUT
fSW ì DVOUT ìK
COUT
í
ì (1-D)ì(1+ K) +
(2 -D)
…
12
…
Ÿ
⁄
(21)
where
•
•
•
D = VOUT / VIN, duty cycle of steady state
ΔVOUT = Output voltage change
ΔIOUT = Output current change
For this design example, the target output ripple is 30 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 30 mV and
choose K = 0.4. Equation 19 yields ESR no larger than 25 mΩ and Equation 20 yields COUT no smaller
than 10 μF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT < 5% × VOUT
= 250 mV for an output current step of ΔIOUT = 1.5 A. COUT is calculated to be no smaller than 25 μF
by Equation 21. In summary, the most stringent criterion for the output capacitor is 25 μF. Considering the
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ceramic capacitor has DC bias de-rating, it can be achieved with a bank of 2 × 22-μF, 35-V, ceramic capacitor
C3216X5R1V226M160AC in the 1206 case size.
More output capacitors can be used to improve the load transient response. Ceramic capacitors can easily meet
the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor can be placed in parallel
with the ceramics to build up the required value of capacitance. When using a mixture of aluminum and ceramic
capacitors, use the minimum recommended value of ceramics and add aluminum electrolytic capacitors as
needed.
The recommendations given in Table 9-2 provide typical and minimum values of output capacitance for the
given conditions. These values are the effective figures. If the minimum values are to be used, the design must
be tested over all of the expected application conditions, including input voltage, output current, and ambient
temperature. This testing must include both bode plot and load transient assessments. The maximum value of
total output capacitance can be referred to the application note (COUT selection and CFF selection) in Technical
documentation. Large values of output capacitance can adversely affect the start-up behavior of the converter as
well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full
load and loop stability must be performed.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF
to 100 nF can help reduce spikes on the output caused by inductor and board parasitics.
Table 9-2 shows the recommended LC combination.
Table 9-2. Recommended LC Combination
TYPICAL EFFECTIVE COUT MINIMUM EFFECTIVE
VOUT(V) fSW (kHz) RTOP(kΩ) RDOWN(kΩ) TYPICAL INDUCTOR L (μH)
(μF)
COUT (μF)
500
1200
500
4.7
2.2
6.8
3.3
12
40
15
10
10
10
10
3.3
31.3
10.0
30
20
5
52.5
10.0
10.0
1200
500
20
12
140.0
15
9.2.2.9 Input Capacitor Selection
The TPS62933 device requires an input decoupling capacitor and, depending on the application, a bulk input
capacitor. The typical recommended value for the decoupling capacitor is 10 μF, and an additional 0.1-µF
capacitor from the VIN pin to ground is recommended to provide high frequency filtering.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. X5R and X7R ceramic dielectrics are recommended because they have a high capacitance-to-volume
ratio and are fairly stable over temperature. The capacitor must also be selected with the DC bias taken into
account. The effective capacitance value decreases as the DC bias increases.
The capacitor voltage rating needs to be greater than the maximum input voltage. The capacitor must also have
a ripple current rating greater than the maximum input current ripple of the TPS62933. The input ripple current
can be calculated using Equation 22.
V
IN_MIN - VOUT
VOUT
ICIN_RMS = IOUT
ì
ì
V
V
IN_MIN
IN_MIN
(22)
For this example design, two TDK CGA5L1X7R1H106K160AC (10-μF, 50-V, 1206, X7R) capacitors have been
selected. The effective capacitance under input voltage of 24 V for each one is 3.45 μF. The input capacitance
value determines the input ripple voltage of the converter. The input voltage ripple can be calculated using
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Equation 23. Using the design example values, IOUT_MAX = 3 A, CIN_EFF = 2 × 3.45 = 6.9 μF, and fSW = 500 kHz,
yields an input voltage ripple of 222 mV and a RMS input ripple current of 1.22 A.
IOUT _MAX ì0.25
DV
=
+ (IOUT _MAX ìRESR _MAX )
IN
CIN ì fSW
(23)
where
•
RESR_MAX = maximum series resistance of the input capacitor. It is approximately 1.5 mΩ of two capacitors in
paralleled.
9.2.2.10 Feedforward Capacitor CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values
of RFBT in combination with the parasitic capacitance at the FB pin can create a small signal pole that interferes
with the loop stability. A CFF helps mitigate this effect. Use lower values to determine if any advantage is gained
by the use of a CFF capacitor.
The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor
Application Report is helpful when experimenting with a feedforward capacitor.
For this example design, a 10-pF capacitor C9 can be mounted to boost load transient performance.
9.2.2.11 Maximum Ambient Temperature
As with any power conversion device, the TPS62933 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the following:
•
•
•
•
Ambient temperature
Power loss
Effective thermal resistance, RθJA, of the device
PCB combination
The maximum internal die temperature for the TPS62933 must be limited to 150°C. This establishes a limit on
the maximum device power dissipation and, therefore, the load current. Equation 24 shows the relationships
between the important parameters. It is easy to see that larger ambient temperatures (TA) and larger values
of RθJA reduce the maximum available output current. The converter efficiency can be estimated by using
the curves provided in this data sheet. Note that these curves include the power loss in the inductor. If the
desired operating conditions cannot be found in one of the curves, then interpolation can be used to estimate
the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the
efficiency can be measured directly. The correct value of RθJA is more difficult to estimate. As stated in the
Semiconductor and IC Package Thermal Metrics Application Report, the value of RθJA given in the Thermal
Information table is not valid for design purposes and must not be used to estimate the thermal performance of
the application. The values reported in that table were measured under a specific set of conditions that are rarely
obtained in an actual application. The data given for RθJC(bott) and ΨJT can be useful when determining thermal
performance. See the Semiconductor and IC Package Thermal Metrics Application Report for more information
and the resources given at the end of this section.
(TJ-TA )
RqJA
h
1
IOUT _MAX
=
ì
ì
1- h VOUT
(24)
where
ŋ = efficiency
The effective RθJA is a critical parameter and depends on many factors such as the following:
Power dissipation
•
•
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•
•
•
•
•
Air temperature/flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement
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9.2.3 Application Curves
VIN = 24 V, VOUT = 5 V, L1= 6.8 µH, COUT = 44 µF, TA = 25°C (unless otherwise noted)
100
95
90
85
80
75
70
65
60
55
50
1
0.8
0.6
0.4
0.2
0
Vin=6V
Vin=12V
Vin=19V
Vin=24V
-0.2
-0.4
-0.6
-0.8
-1
Vin=6V
Vin=12V
Vin=19V
Vin=24V
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2
3
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2
3
Figure 9-2. Efficiency
Figure 9-3. Load Regulation
1
0.8
0.6
0.4
0.2
0
600
550
500
450
400
350
300
250
200
150
100
50
Vin=6V
Vin=12V
Vin=19V
Vin=24V
Vin=30V
-0.2
-0.4
-0.6
-0.8
-1
Iout=0A
Iout=0.03A
Iout=0.3A
Iout=1.5A
Iout=3A
0
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
Vin (V)
0.001
0.005
0.02 0.05 0.1 0.2
I-Load (A)
0.5
1
2
3
Figure 9-4. Line Regulation
Figure 9-5. Switching Frequency vs Load Current
90
60
30
0
300
200
100
0
-30
-60
-90
-100
-200
Mag (dB)
Phase (deg)
-300
100 200 5001000
10000
100000
1000000
Figure 9-7. Case Temperature, VIN = 24 V, IOUT = 3
A, fSW = 500 kHz
Frequency (Hz)
Figure 9-6. Loop Frequency Response, IOUT = 3 A,
BW = 49.4 kHz, PM = 57°, GM = –12 dB
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VIN = 10V/div
VOUT = 2V/div
VIN = 10V/div
VOUT = 2V/div
SS = 2V/div
IL = 2A/div
SS = 2V/div
IL = 2A/div
4mS/div
4mS/div
Figure 9-8. Start-Up Relative to VIN, IOUT = 3 A
Figure 9-9. Shutdown Relative to VIN, IOUT = 3 A
EN = 2V/div
EN = 2V/div
VOUT = 2V/div
VOUT = 2V/div
SS = 2V/div
IL = 2A/div
SS = 2V/div
IL = 2A/div
2mS/div
2mS/div
Figure 9-10. Start-Up Through EN, IOUT = 3 A
Figure 9-11. Shutdown Through EN, IOUT = 3 A
VOUT = 20mV/div (AC coupled)
VOUT = 20mV/div (AC coupled)
IL = 500mA/div
IL = 500mA/div
4mS/div
4uS/div
Figure 9-12. Steady State, IOUT = 0 A
Figure 9-13. Steady State, IOUT = 0.1 A
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VOUT = 20mV/div (AC coupled)
VOUT = 20mV/div (AC coupled)
IL = 500mA/div
IL = 500mA/div
2uS/div
2uS/div
Figure 9-14. Steady State, IOUT = 0.5 A
Figure 9-15. Steady State, IOUT = 1 A
VOUT = 20mV/div (AC coupled)
VOUT = 20mV/div (AC coupled)
IL = 1A/div
IL = 1A/div
2uS/div
2uS/div
Figure 9-17. Steady State, IOUT = 3 A
Figure 9-16. Steady State, IOUT = 2 A
VOUT = 200mV/div (AC coupled)
VOUT = 200mV/div (AC coupled)
IOUT = 2A/div
IOUT = 2A/div
100uS/div
100uS/div
Figure 9-19. Load Transient Response, 1 to 3 A,
Slew Rate = 0.8 A/μS
Figure 9-18. Load Transient Response, 0.5 to 2.5 A,
Slew Rate = 0.8 A/μS
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VIN = 10V/div
VOUT = 2V/div
VIN = 10V/div
VOUT = 2V/div
SS = 2V/div
IL = 2A/div
SS = 2V/div
IL = 2A/div
20mS/div
20mS/div
Figure 9-20. VOUT Hard Short Protection
Figure 9-21. VOUT Hard Short Recovery
9.3 What to Do and What Not to Do
•
•
•
•
•
•
Do not exceed the Absolute Maximum Ratings.
Do not exceed the Recommended Operating Conditions.
Do not exceed the ESD Ratings.
Do not allow the SS pin floating.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Do not use the value of RθJA given in the Thermal Information table to design your application. See Section
9.2.2.11.
•
•
Follow all the guidelines and suggestions found in this data sheet before committing the design to production.
TI application engineers are ready to help critique your design and PCB layout to help make your project a
success.
Use a 100-nF capacitor connected directly to the VIN and GND pins of the device. See Section 9.2.2.9 for
details.
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10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 3.8 V and 30 V. This input
supply must be well regulated and compatible with the limits found in the specifications of this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded converter. The
average input current can be estimated with Equation 25.
VOUT ìIOUT
I
=
IN
V ì h
IN
(25)
where
ŋ = efficiency
•
If the converter is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to
the converter. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient
is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause
the converter to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the converter and use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 μF to 100 μF is usually sufficient to provide input damping and help
hold the input voltage steady during large load transients.
It is recommended that the input supply must not be allowed to fall below the output voltage by more than
0.3 V. Under such conditions, the output capacitors discharges through the body diode of the high-side power
MOSFET. The resulting current can cause unpredictable behavior, and in extreme cases, possible device
damage. If the application allows for this possibility, then use a Schottky diode from VIN to VOUT to provide a
path around the converter for this current.
In some cases, a transient voltage suppressor (TVS) is used on the input of converters. One class of this
device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the converter, the output capacitors discharges through the device, as mentioned above.
Sometimes, for other system considerations, an input filter is used in front of the converter. This can lead to
instability as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success with Conducted EMI from DCDC Converters User's Guide provides helpful suggestions when designing
an input filter for any switching converter.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout
can disrupt the operation of a good schematic design. Even if the converter regulates correctly, bad PCB layout
can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the
EMI performance of the converter is dependent on the PCB layout to a great extent. In a buck converter, the
most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 11-1.
This loop carries large transient currents that can cause large transient voltages when reacting with the trace
inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this,
the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic
inductance.
TI recommends a 2-layer board with 2-oz copper thickness of top and bottom layer, and proper layout provides
low current conduction impedance, proper shielding, and lower thermal resistance. Figure 11-2 and Figure 11-3
show the recommended layouts for the critical components of the TPS62933.
•
•
Inductor, input/output capacitors, and the IC should be placed on the same layer.
The input/output capacitors should be placed as close as possible to the IC. The VIN and GND traces should
be as wide as possible and provide sufficient vias on them to minimize trace impedance. The wide areas are
also of advantage from the view point of heat dissipation.
•
A 0.1-µF ceramic decoupling capacitor or several should be placed as close as possible to VIN and GND pins
which is key to EMI reduction.
•
•
Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
BST capacitor and resistor should be placed close to BST pin and SW node, > 10-mil width trace is
recommended to reduce the parasitic inductance.
•
The feedback divider should be placed as close as possible to the FB pin, > 10-mil width trace is
recommended for heat dissipation. A separate VOUT trace should be connected to the upper feedback
resistor, the voltage feedback loop should be placed away from the high-voltage switching trace, and
preferably has ground shield.
•
SS capacitor and RT resistor should be placed close to the IC and routed with minimal lengths of trace, >
10-mil width trace is recommended for heat dissipation.
VIN
KEEP
CIN
CURRENT
LOOP
SW
SMALL
GND
Figure 11-1. Current Loop With Fast Edges
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11.2 Layout Example
Figure 11-2. TPS62933 Top Layout Example
Figure 11-3. TPS62933 Bottom Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62933 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62933DRLR
XTPS62933DRLR
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
DRL
DRL
8
8
4000 RoHS & Green
4000 TBD
Call TI
Level-1-260C-UNLIM
Call TI
-40 to 150
-40 to 150
2933
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62933DRLR
SOT-5X3
DRL
8
4000
180.0
8.4
2.75
1.9
0.8
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-5X3 DRL
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS62933DRLR
8
4000
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/D 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/D 11/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/D 11/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号:
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采用 SOT583 封装的 Out-of-Audio 式、3.8V 至 30V、3A、200kHz 至 2.2MHz 同步降压转换器 | DRL | 8 | -40 to 150
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