TPS62993QRYTRQ1 [TI]
3V 至 10V、3A、低 IQ 汽车类同步降压转换器 | RYT | 9 | -40 to 125;
| 型号： | TPS62993QRYTRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3V 至 10V、3A、低 IQ 汽车类同步降压转换器 | RYT | 9 | -40 to 125 转换器 |
| 文件： | 总57页 (文件大小：2464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
TPS62993-Q1 结温为+165°C TJ 的3V 至10V，3A 汽车类低IQ 降压转换器
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准：
• ADAS
• 车身电子装置和照明
• 信息娱乐系统与仪表组
• 混合动力、电动和动力总成系统
– 温度等级1：–40°C 至+125°C，TA
– 器件HBM ESD 分类等级2
– CDM ESD 分级等级C4B
• 提供功能安全
3 说明
– 可提供用于功能安全系统设计的文档
• 扩展TJ 范围：至高达165°C
• 高效率DCS-Control 拓扑
TPS62993-Q1 是一款高效、小巧、灵活且易用的同步
降压直流/直流转换器。2.5MHz 或1.0MHz 的可选开关
频率支持使用小型电感器，并提供快速瞬态响应。该器
– RDS(ON)：62mΩ高侧，22mΩ低侧
– 无缝PWM/PFM 转换
– 内部补偿
件在整个运行温度范围内支持 ±1.5% 的高 VOUT
精
度，并通过 DCS-Control 拓扑提高负载瞬态性能。3V
至 10V 的宽输入电压范围支持各种标称输入，例如 9V
电源轨、单节或多节锂离子电池、5V 或 3.3V 电源
轨。
• 4µA 低IQ（典型值）
• 高达3A 的持续输出电流
• 整个温度范围内的输出电压精度为±1.5%
• 可配置的输出电压选项：
TPS62993-Q1 可在轻负载时自动进入省电模式（如果
选择了自动 PFM 或 PWM）以保持高效率。此外，为
了在非常小的负载下提供高效率，该器件具有 4µA 的
低典型静态电流。AEE（如果启用）可在 VIN、VOUT
和负载电流范围内提供高效率。该器件包含一个
MODE/Smart-CONF 输入，用来设置内部和外部分压
器、开关频率、输出电压放电和自动省电模式或强制
PWM 操作。
– 0.6V 至5.5V VFB 外部分压器
– VSET 内部分压器
• 16 个电压选项（0.4V 至5.5V）
• 通过MODE/S-CONF 引脚提高了灵活性
– 2.5 MHz 或1.0 MHz 开关频率
– 具有动态模式更改选项的强制PWM 或自动
PFM（省电模式）
封装信息
封装(1)
– 输出放电开和关
封装尺寸（标称值）
• 无需外部自举电容器
• 过流和过热保护
器件型号
TPS62993-Q1
RYT (VQFN, 9)
2.20mm × 2.00mm
• 100% 占空比模式
• 精密使能输入
• 可调软启动和跟踪
• 电源正常状态输出
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 针对单层布线的引脚排列进行了优化
• 可湿性2.2mm × 2.0mm VQFN 封装，间距为
0.5mm
• 借助TPS62993-Q1 并使用WEBENCH® Power
Designer 创建定制设计方案
VIN
3 V to 10 V
100
90
80
70
60
50
40
30
20
VOUT
0.6 V to 5.5 V
TPS6299x-Q1
1
H
VIN
SW
EN
VOS
C2
C1
10
R1
R2
22
F
F
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
GND
Vin = 6V
Vin = 9V
10
0
简化原理图
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
效率与输出电流间的关系（3.3 VO，2.5MHz，1μH，
自动PFM 或PWM）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGV5
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
9 Application and Implementation..................................24
9.1 Application Information............................................. 24
9.2 Typical Application with Adjustable Output Voltage.. 24
9.3 Typical Application with Selectable VOUT using
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................8
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................21
VSET ..........................................................................35
9.4 System Examples..................................................... 43
9.5 Power Supply Recommendations.............................47
9.6 Layout....................................................................... 47
10 Device and Documentation Support..........................49
10.1 Device Support....................................................... 49
10.2 Documentation Support.......................................... 49
10.3 接收文档更新通知................................................... 49
10.4 支持资源..................................................................49
10.5 Trademarks.............................................................49
10.6 静电放电警告.......................................................... 50
10.7 术语表..................................................................... 50
11 Mechanical, Packaging, and Orderable
Information.................................................................... 50
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2022) to Revision A (March 2023)
Page
• Corrected 图9-59 ............................................................................................................................................ 38
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGV5
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5 Device Comparison Table
Operating
Temperature
Range
Device Number
Output Current
Input Voltage
Switching Frequency
PWM Mode
VO Adjust
Externally
programmable or 16
internal options
TPS62993-Q1
TPS62992-Q1
0 A –3 A
0 A –2 A
Selectable 1-MHz or Selectable auto PFM/PWM
3 V –10 V
–40°C to 165°C
–40°C to 165°C
2.5-MHz options
or forced PWM
TPS62903-Q1
TPS62902-Q1
TPS62901-Q1
TPS62903
0 A –3 A
0 A –2 A
0 A –1 A
0 A –0.3 A
0 A –2 A
0 A –1 A
0 A –3 A
Externally
programmable or 16
internal options
Selectable 1-MHz or Selectable auto PFM/PWM
3 V –18 V
3 V –18 V
2.5-MHz options
or forced PWM
Externally
programmable or 16
internal options
TPS62902
–40°C to 125°C
–55°C to 165°C
Selectable 1-MHz or Selectable auto PFM/PWM
2.5-MHz options
or forced PWM
TPS62901
TPS62903E
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ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
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6 Pin Configuration and Functions
GND
4
VOS
SW
PG
3
2
EN
5
6
VIN
1
7
8
9
图6-1. 9-Pin RYT VQFN Package (Top View, Device Pins Face Down)
表6-1. Pin Functions
Pin
Type(1)
Description
Name
Number
Open-drain power-good output. High = VOUT is ready. Low = VOUT is below nominal regulation.
This pin requires a pullup resistor.
PG
1
O
Switch pin of the converter and is connected to the internal power switches. Connect the inductor
between SW and the output capacitor.
SW
2
—
VOS
GND
3
4
I
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
Ground pin. This pin must be connected directly to the common ground plane.
—
Enable input pin. Connect to logic low to disable the device. Pull high to enable the device. Do not
leave this pin unconnected.
EN
5
6
I
I
Power supply input pin. Ensure the input capacitor is connected as close as possible between the
VIN and GND pins.
VIN
Device mode selection (auto PFM/PWM or forced PWM operation) and SmartConfig pin. Connect
high, low, or to a resistor to configure the device according to 表8-1. Do not leave this pin
unconnected.
MODE/
S-CONF
7
8
I
I
Soft start and tracking pin. An external capacitor connected from this pin to GND defines the rise
time for the internal reference voltage. The pin can also be used as an input for tracking and
sequencing. The pin can be left floating for the fastest ramp-up time.
SS/TR
Depends on device configuration (see 节8.3.1.)
•
•
FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage
according to 表8-2.
FB/VSET
9
I
(1) O = output, I = input
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English Data Sheet: SLVSGV5
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3.0
–0.3
–55
–65
MAX
12
UNIT
V
Voltage((2))
Voltage(2)
Voltage((2))
Voltage(2)
TJ
VIN, EN, PG, MODE/S-CONF
SW ((3))
VIN + 0.3
17
V
SW (AC, less than 10ns)((3))
FB/VSET, SS/TR, VOS
Junction temperature
Storage temperature
V
6
V
165
°C
°C
Tstg
165
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC-Q100-002 HBM ESD Classification Level 2,
all pins((1))
V(ESD) Electrostatic discharge
V(ESD) Electrostatic discharge
±2000
V
All pins
±500
±750
Charged device model (CDM), per AEC-Q100-011
CDM ESD Classification level C4B.
V
Corner pins (3, 4, 7, and 9)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
3.0
0.4
3
NOM
MAX
10
UNIT
VI
Input voltage range
V
V
VO
Output voltage range
5.5
CI
Effective input capacitance
Effective output capacitance (2.5MHz selection)(1)
Effective output capacitance (1MHz selection)(1)
Output inductance(2)
10
22
µF
µF
µF
µH
A
CO
CO
L
10
10
1
100 (1)
100 (1)
4.7(3)
3
22
2.2
IOUT
ISINK_PG
TJ
Output current
0
Sink current at PG-Pin
1
mA
°C
Junction temperature (4)
-40
165
(1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitor.
(2) Nominal inductance value.
(3) Larger values of inductance may be used to reduce the ripple current, but they may have a negative impact on efficiency and the
overvall transient responce.
(4) Operating lifetime is derated at junction temperatures greater than 165°C.
7.4 Thermal Information
VQFN (RYT)
THERMAL METRIC((1))
UNIT
JEDEC PCB
TPS6299xEVM-xxx
73.5
RθJA
Junction-to-ambient thermal resistance
97.2
°C/W
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UNIT
7.4 Thermal Information (continued)
VQFN (RYT)
TPS6299xEVM-xxx
THERMAL METRIC((1))
JEDEC PCB
RθJC(top)
RθJB
ΨJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
74.4
25
N/A
N/A
4.3
28
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.7
24.7
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VI = 3 V to 10 V, TJ = -40C °C to +165°C, Typical values at VI = 6V and TA = 25 °C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Operating Quiescent Current (Power
Save Mode)
IQ
Iout = 0 mA device not switching
4
8
µA
Operating Quiescent Current (PWM
Mode)
VIN= 6V, VOUT=1.2V; Iout = 0 mA,
device switching
IQ;PWM
ISD
VUVLO
VUVLO
mA
Shutdown current into VIN pin
Under Voltage Lock-Out
EN = 0 V,
VIN rising,
VIN falling
0.27
2.925
2.79
3.5
3.0
µA
V
2.85
2.71
Under Voltage Lock-Out
2.87
V
Under Voltage Lock-Out Hysteresis
130
mV
CONTROL & INTERFACE
ILKG
EN Input leakage current
EN = 5V
10
310
nA
V
High-Level Input Voltage at MODE/S-
CONF Pin
VIH;MODE
1.0
Low-Level Input Voltage at MODE/S-
CONF Pin
VIL;MODE
0.15
185
V
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
High-level input voltage at EN-Pin
Low-level input voltage at EN-Pin
TJ rising
TJ falling
168
175
12.5
1.0
TSD
°C
VIH
VIL
0.97
0.820
93%
1.03
0.880
99%
96%
6%
V
V
0.850
96%
92%
3.5%
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
VPG
Power good fthreshold
88%
VPG_HYS
VPG,OL
IPG,LKG
tPG,DLY
Power good threshold hysteresis
Low-level output voltage at PG pin
Input leakage current into PG pin
Power good delay time
1.5%
ISINK = 1 mA
0.4
V
VPG = 5 V,
25
32
550
nA
µs
VFB rising and falling
Maximum Capacitance connected to
VSET pin
CSET
30
pF
POWER SWITCHES
ILKG;SW Leakage current into SW-Pin
EN = 0V, VSW = VOS = 5.5V, TJ up to
150°C
2
7
µA
High-side FET on resistance
Low-side FET on resistance
High-side FET current limit
Low-side FET current limit
Low-side FET sink current limit
VIN > 4 V, ISW = 500 mA
VIN > 4 V, ISW = 500 mA
62
22
111
41
5
RDS;ON
mΩ
ILIM
4
3.8
1.3
4.4
4.3
1.7
A
A
A
ILIM
4.8
2.5
ILIM;SINK
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGV5
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7.5 Electrical Characteristics (continued)
VI = 3 V to 10 V, TJ = -40C °C to +165°C, Typical values at VI = 6V and TA = 25 °C unless otherwise noted
PARAMETER
Switching frequency
Minimum On-time
Switching frequency
TEST CONDITIONS
MIN
TYP
2.5
30
MAX
UNIT
MHz
ns
fSW
2.5-MHz selection
TON(MIN)
fSW
1.0-MHz selection
1.0
MHz
OUTPUT
VSET Configuration selected, TJ =
25°C
VO
Output Voltage Regulation
+1%
–1%
VO
Output Voltage Regulation
VSET Configuration selected
Adjustable Configuration selected
FB-Option selected. TJ = 25 °C.
FB-Option selected
+1.5%
–1.5%
VFB
VFB
VFB
IFB
Feedback Regulation Voltage
Feedback Voltage Regulation
Feedback Voltage Regulation
Input leakage current into FB pin
0.6
V
+0.6%
+1.25%
70
–0.6%
–1.25%
Adjustable configuration, VFB = 0.6 V
1
nA
µs
IO = 0 mA, time from EN=HIGH until
start switching, Adjustable
Configuration selected
Start-up delay time
Start-up delay time
600
1400
1850
Tdelay
IO = 0 mA, time from EN=HIGH until
start switching, VSET Configuration
selected. The typical value is based on
the first option of VSET configuration.
650
150
µs
IO = 0 mA after Tdelay, from 1st
switching pulse until target VO ,
Css=Open
TSS
Soft-Start time
µs
ISS
SS/TR source current
2.25
2.5
0.75
±8
2.75
30
µA
Tracking Gain, Adjustable
Configuration
VFB/VSS/TR
VFB/VSS/TR
RDISCH
Tracking Gain tolerance
mV
Discharge = ON - Option Selected, EN
= LOW
Active Discharge Resistance
7.5
Ω
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7.6 Typical Characteristics
16
6
5.5
5
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
14
12
10
8
4.5
4
3.5
3
2.5
2
6
1.5
1
4
2
0.5
0
0
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
图7-2. Shutdown Current vs Temperature
Measured with the device not switching
图7-1. Quiescent Current vs Temperature
0.603
0.602
0.601
0.6
5.02
5.015
5.01
5.005
5
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 6V
Vin = 9V
0.599
0.598
0.597
0.596
0.595
0.594
4.995
4.99
4.985
4.98
4.975
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
图7-3. Feedback Voltage Accuracy - External Feedback
图7-4. Output Voltage Accuracy - VSET Selected
Selected
3.32
2.506
Vin = 6V
Vin = 9V
3.315
3.31
2.504
2.502
2.5
3.305
3.3
2.498
2.496
2.494
2.492
2.49
3.295
3.29
3.285
3.28
Vin = 3V
Vin = 6V
Vin = 9V
3.275
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
VOUT = 3.3 V
VOUT = 2.5 V
图7-5. Output Voltage Accuracy - VSET Selected
图7-6. Output Voltage Accuracy - VSET Selected
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English Data Sheet: SLVSGV5
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7.6 Typical Characteristics (continued)
1.81
1.808
1.806
1.804
1.802
1.8
1.206
1.205
1.204
1.203
1.202
1.201
1.2
Vin = 3V
Vin = 6V
Vin = 9V
1.199
1.198
1.197
1.196
1.195
1.194
1.798
1.796
1.794
1.792
1.79
Vin = 3V
Vin = 6V
Vin = 9V
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
VOUT = 1.8 V
VOUT = 1.2 V
图7-7. Output Voltage Accuracy - VSET Selected
图7-8. Output Voltage Accuracy - VSET Selected
0.602
0.76
0.6015
0.601
0.6005
0.6
0.7575
0.755
0.7525
0.75
0.5995
0.599
0.5985
0.598
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.7475
0.745
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
图7-10. Tracking Voltage Gain vs Temperature
VOUT = 0.6 V
图7-9. Output Voltage Accuracy - VSET Selected
1.1
3
1.075
1.05
1.025
1
2.8
2.6
2.4
2.2
2
0.975
0.95
0.925
0.9
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
FSW = 1.0 MHz
FPWM
Temperature (C)
FSW = 2.5 MHz
FPWM
VOUT = 1.2 V
IOUT = 0 A
VOUT = 1.2 V
IOUT = 0 A
图7-12. Switching Frequency vs Temperature
图7-11. Switching Frequency vs Temperature
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7.6 Typical Characteristics (continued)
125
115
105
95
50
45
40
35
30
25
20
15
10
5
85
75
65
55
45
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
35
25
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
图7-13. High Side RDSON vs Temperature
图7-14. Low Side RDSON vs Temperature
4.6
Vin = 3V
Vin = 6V
Vin = 9V
4.575
4.55
4.525
4.5
4.475
4.45
4.425
4.4
4.375
4.35
4.325
4.3
-40
-10
20
50
80
110
140
170
Temperature (C)
图7-15. High Side ILIM vs Temperature
图7-16. Low Side ILIM vs Temperature
1.9
1.85
1.8
2.75
2.7
2.65
2.6
2.55
2.5
1.75
1.7
2.45
2.4
2.35
2.3
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
1.65
1.6
2.25
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
图7-17. Negative ILIM vs Temperature
图7-18. Soft Start Current vs Temperature
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7.6 Typical Characteristics (continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
3
2.975
2.95
2.925
2.9
2.875
2.85
2.825
2.8
2.775
2.75
2.725
2.7
Vin Rising
Vin Falling
PG Rising
PG Falling
2.675
2.65
87
86
-40
-40
-10
20
50
80
110
140
170
-10
20
50
80
110
140
170
Temperature (C)
Temeraturee (C)
图7-20. VVIN UVLO Thresholds vs Temperature
VVIN = 6 V
图7-19. Power Good Thresholds vs Temperature
1.01
0.855
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
0.854
0.853
0.852
0.851
0.85
0.849
0.848
0.847
0.846
0.845
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
-40
-10
20
50
80
110
140
170
-40
-10
20
50
80
110
140
170
Temperature (C)
Temperature (C)
图7-21. Percise EN Threshold vs Temperature
图7-22. Percise EN Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The TPS62993-Q1 synchronous switched mode power converters are based on DCS-Control (Direct Control
with Seamless Transition into power save mode). DCS-Control is an advanced regulation topology that
combines the advantages of hysteretic, voltage mode, and current mode control. This control loop takes
information about output voltage changes and feeds the information directly to a fast comparator stage. DCS-
Control sets the switching frequency, which is constant for steady-state operating conditions, and provides
immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is
used. The internally compensated regulation network achieves fast and stable operation with small external
components and low-ESR capacitors.
8.2 Functional Block Diagram
VIN
PG
VI
Ref
1.0V
–
+
HS Limit
EN
VO
Internal/External
Divider
FB / VSET
SW
Power Control
Resistor-to-Digital
Device Control
and Logic
Gate
Driver
Power Save Mode
Forced PWM
VFB
Smart-Enable
Ref-System
100% Mode
UVLO
SS/TR
Start-up Handling
Smart-CONFIG
PG-Control
Thermal Shutdown
Resistor-to-Digital
MODE Detection
MODE / S-CONF
LS Limit
VO
Direct
VI
VOS
Control
TON timer
VFB
–
+
VO
Device
Control
DCS-Control
VREF
GND
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8.3 Feature Description
8.3.1 Mode Selection and Device Configuration MODE/S-CONF
With MODE/S-CONF (SmartConfig), this device features an input with two functions. This pin can be used to
customize the device behavior in two ways:
• Select the device mode (Forced PWM or Auto PFM /PWM with AEE operation) with a HIGH-level or LOW-
level.
• Select the device configuration (switching frequency, internal or external feedback, output discharge, and
auto PFM/PWM mode) by connecting a single resistor to the MODE/S-CONF pin.
The TPS62993-Q1 interprets this pin during the start-up sequence after the internal OTP readout and before the
device starts switching in soft start (see 图 8-1). If the device reads a HIGH-level or LOW-level, the dynamic
mode change is active and auto PFM/PWM or FPWM mode can be changed during operation. If the TPS62993-
Q1 reads a resistor value, the device is configured according to the resistance value in 表 8-1 and there is no
further interpretation during operation and device mode or other configurations can only be changed by power
cycling or disabling the device.
备注
The MODE/S-CONF pin must not be left floating. Connect the pin high, low, or to a resistor to
configure the device according to 表8-1.
EN and UVLO
Precise
Enable
detec on
PG -> High
Switching
Opera on
OTP
Readout
S-CONF
Readout
VSET
Readout
So start
Resistor-to-Digi al
readout and
interpreta on
No interpreta on of
MODE/S-CONF or VSET
MODE-Pin toggling detec on
VOUT
图8-1. Interpretation of S-CONF and VSET Flow
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表8-1. SmartConfig Setting Table
FB/VSET
Pin
Output
Discharge
Mode (Auto Or Forced
PWM)
Dynamic Mode
Change
Level Or Resistor Value [Ω]
#
FSW (MHz)
(1)
Setting Options by Level
Auto PFM/PWM with
AEE
1
2
GND
External FB
External FB
2.5(2)
2.5
yes
yes
Active
HIGH (> VIH_MODE
)
Forced PWM
Setting Options by Resistor
Auto PFM/PWM with
AEE
3
7.15 k
External FB
2.5(2)
no
4
5
6
7
8
8.87 k
11.0 k
13.7 k
16.9 k
21.0 k
External FB
External FB
External FB
External FB
External FB
2.5
1
no
yes
yes
no
Forced PWM
Auto PFM/PWM
Forced PWM
1
1
Auto PFM/PWM
Forced PWM
1
no
Auto PFM/PWM with
AEE
9
26.1 k
32.4 k
40.2 k
VSET
VSET
VSET
2.5(2)
2.5
yes
yes
no
Not active
10
11
Forced PWM
Auto PFM/PWM with
AEE
2.5(2)
12
13
14
15
16
49.9 k
61.9 k
76.8 k
95.3 k
118 k
VSET
VSET
VSET
VSET
VSET
2.5
1
no
yes
yes
no
Forced PWM
Auto PFM/PWM
Forced PWM
1
1
Auto PFM/PWM
Forced PWM
1
no
(1) E96 resistor series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C
(2) FSW varies based on VIN and VOUT. See 节8.4.3 for more details.
8.3.2 Adjustable VO Operation (External Voltage Divider)
The TPS62993-Q1 can be programmed by the MODE/S-CONF pin to operating in a classical configuration
where the FB/VSET pin is used as the feedback pin, sensing VO through an external resistive divider. The
TPS62993-Q1 can also be programmed to 1 of 16 different fixed output voltages (see 节8.3.3).
If the device is configured to operate in the classical adjustable VO operation, the FB/VSET pin is used as the
feedback pin and must sense VO through an external divider network. 图8-2 shows the typical schematic for this
configuration.
VIN
3 V to 10 V
VOUT
0.6 V to 5.5 V
TPS6299x-Q1
1 H
VIN
SW
EN
VOS
C2
22 F
C1
10 F
R1
R2
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
GND
图8-2. Adjustable VO Operation Schematic
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8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
If the device is configured to VSET operation, VO is sensed only through the VOS pin by an internal resistor
divider. The target VO is programmed by an external resistor (RVSET) connected between the VSET pin and
GND. 图8-3 shows the typical schematic for this configuration.
CAUTION
The MODE/S-CONF pin must not be configured for external feedback operation (see 表 8-1) if only
RVSET (R2 as shown in 图 8-3) is populated. This causes the output voltage to become unregulated
and can damage to the device or surrounding circuitry.
VIN
VOUT
0.4 V to 5.5 V
TPS6299x-Q
3 V to 10 V
1 H
VIN
SW
EN
VOS
C2
22 F
C1
10 F
FB/
VSET
SS/TR
R2
MODE/
S-CONF
PG
R3
C3
GND
图8-3. Selectable VO Operation Schematic
表8-2. VSET Selection Table
Level Or Resistor Value [Ω] (1)
#
1
2
3
4
5
6
7
8
9
Target VO [V]
GND
4.64 k
1.2
0.4
5.76 k
0.6
7.15 k
0.8
8.87 k
1.0
11.0 k
1.1
13.7 k
1.3
16.9 k
1.35
1.8
21.0 k
10
26.1 k
1.9
11
12
13
14
15
16
40.2 k
2.5
61.9 k
3.8
76.8 k
5.0
95.3 k
1.25
5.5
118.0 k
249.00 k or larger/Open
3.3
(1) E96 resistor series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C
8.3.4 Soft Start and Tracking (SS/TR)
With the SS/TR pin, the user can adjust the soft-start behavior or track an external voltage source (see 节
8.3.4.1 for operation details).
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The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and makes sure there is a controlled output voltage rise time. The soft-start circuitry also prevents
unwanted voltage drops from high impedance power sources or batteries. When EN is set high to start
operation, the device starts switching after the start-up delay, while the internal reference, and hence VO, rises
with a slope controlled by the 2.5μA (typical) ISS current source and an external capacitor connected to the
SS/TR pin and the 2.5μA (typical) ISS current source.
备注
Shorting or pulling the SS/TR pin LOW externally prevents the device from switching as this sets the
internal reference voltage to 0 V.
备注
Leaving the SS/TR pin unconnected provides the fastest start-up response, but this can result in some
output voltage overshoot depending on the Vout value, load current, and external component sizes.
Adding or increasing the soft-start capacitor (CSS) minimizes or removes the voltage overshoot.
If the device is set to shut down (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor
pulls the SS/TR pin down to make sure there is a proper low level. Returning from those states causes a new
start-up sequence as set by the SS/TR connection.
8.3.4.1 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the
Electrical Characteristics.
备注
In forced PWM (FPWM) mode the output voltage increases and decreases with any changes in the
tracking voltage, but in auto PFM (power save) mode, the output voltage only decreases based on the
load current.
ISS
SS/TR
to VREF
图8-4. Tracking Operation Simplified Schematic
VFB = 0.75 x VSS/TR
(1)
When the SS/TR pin voltage is above 0.8 V, the internal voltage is clamped and the device goes to normal
regulation. This action works for rising and falling tracking voltages with the same behavior, as long as the input
voltage is inside the recommended operating conditions. For decreasing the SS/TR pin voltage in PFM mode,
the device does not sink current from the output. The resulting decrease of the output voltage can therefore be
slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin, which is 6 V. The SS/TR pin is internally connected with a resistor to
GND when EN = 0.
If the input voltage drops below undervoltage lockout, the output voltage goes to zero, independent of the
tracking voltage. 图 8-5 shows how to connect devices to get ratiometric and simultaneous sequencing by using
the tracking function. See 节9.4.3 in the systems examples.
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Device 1
L1
TPS629xx-Q1
VOUT1
VIN
VIN
SW
EN
VOS
R1
R2
22 μF
10 μF
FB/
VSET
SS/TR
MODE/
S-CONF
PG
GND
CSS
R3
Device 2
L2
TPS629xx-Q1
VOUT2
VIN
SW
EN
VOS
22 μF
R7
R8
10 μF
R4
R5
FB/
VSET
SS/TR
MODE/
S-CONF
PG
GND
R6
图8-5. Schematic for Ratiometric and Simultaneous Start-Up
The resistive divider of R7 and R8 can be used to change the ramp rate of VOUT2 to be faster, slower, or the
same as VOUT1.
A sequential start-up is achieved by connecting the PG pin of VOUT of device 1 to the EN pin of device 2. PG
requires a pullup resistor. Ratiometric start-up sequence happens if both supplies are sharing the same soft-start
capacitor. 方程式 18 gives the soft-start time, though the SS/TR current has to be doubled. Details about these
and other tracking and sequencing circuits are found in the Sequencing and Tracking With the TPS621-Family
and TPS821-Family application report.
备注
If the voltage at the FB pin is below its typical value of 0.6 V, the output voltage accuracy can have a
wider tolerance than specified. The current of 2.5 µA out of the SS/TR pin also has an influence on the
tracking function, especially for high resistive external voltage dividers on the SS/TR pin.
8.3.5 Smart Enable with Precise Threshold
The voltage applied at the enable pin of the TPS62993-Q1 is compared to a fixed threshold rising voltage. This
allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to
achieve a power-up delay.
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The precise enable input allows the user to program the undervoltage lockout by adding a resistor divider to the
input of the EN pin.
The enable input threshold for a falling edge is lower than the rising edge threshold. The TPS62993-Q1 starts
operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must
not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side
and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.
An internal resistor pulls the EN pin to GND when the device is disabled and avoids the pin to be floating (after
the device is enabled, the pulldown is removed). This prevents an uncontrolled start-up of the device in case the
EN pin cannot be driven to a low level safely. With EN low, the device is in shutdown mode. The device is turned
on with EN set to a high level. The pulldown control circuit disconnects the pulldown resistor on the EN pin after
the internal control logic and the reference have been powered up. With EN set to a low level, the device enters
shutdown mode and the pulldown resistor is activated again.
8.3.6 Power Good (PG)
The TPS62993-Q1 has a built-in power-good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is
an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.
PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN must
remain present for the PG pin to stay low.
If the power-good output is not used, TI recommends to tie to GND or leave it open.
表8-3. Power Good Indicator Functional Table
Logic Signals
PG Status
VIN
EN Pin
Thermal Shutdown
VOUT
VOUT on target
High Impedance
LOW
No
HIGH
VOUT < target
VIN > UVLO
Yes
×
×
×
×
×
LOW
LOW
LOW
1.8 V< VIN < UVLO
VIN < 1.8 V
×
×
×
LOW
×
Undefined
备注
For prebiased VOUT conditions (during start-up) of 60% or more of the programmed output voltage, a
minimum 250-μs external soft start (CSS > 0.75 nF) is required. If the 250-μs soft start minimum is
not ensured and VOUT is prebiased above 60% of the programmed output voltage during start-up, PG
can be seen asserted "early" before VOUT reaches the PG rising threshold, a glitch on PG can be
observed, or both.
8.3.7 Output Discharge Function
The purpose of the discharge function is to make sure there is a defined down-ramp of the output voltage when
the device is being disabled, and to also keep the output voltage close to 0 V when the device is off. This can be
especially useful for applications with a system wide EN function that removes the output load in conjunction with
disabling the power supply.
The output discharge feature is only active after the TPS62993-Q1 has been enabled at least once since the
supply voltage was applied (VVIN > UVLO). The internal discharge resistor is connected to the VOS pin. The
discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage lockout.
The minimum supply voltage required for the discharge function to remain active typically is 2 V.
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8.3.8 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
8.3.9 Current Limit and Short-Circuit Protection
The TPS62993-Q1 is protected against overload and short-circuit events. If the inductor current exceeds the
high-side FET current limit (ILIMH), the high-side switch is turned off and the low-side switch is turned on to ramp
down the inductor current. The high-side FET turns on again only if the current in the low-side FET has
decreased below the low-side FET current limit threshold AND the internal ILIM recovery delay has expired.
备注
While the internal recovery delay generally keeps the switching frequency within the normal operating
range of the device , the switching frequency is not tightly controlled during overload events.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given as 方程式2:
V
L
L
I
= I
+
× t
pd
(2)
peak typ
LIMH
where
• ILIMH is the static high-side FET current limit as specified in the Electrical Characteristics.
• L is the effective inductance at the peak current.
• VL is the voltage across the inductor (VIN–VOUT).
• tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductance is
used. The dynamic high-side switch peak current can be calculated as follows:
V
− V
L
VIN
VOUT
I
= I
+
× 50ns
(3)
peak typ
LIMH
The TPS62993-Q1 also includes a low-side negative current limit (ILIM:SINK) to protect against excessive negative
currents that can occur in forced PMW mode under heavy to light load transient conditions. If the negative
current in the low-side switch exceeds the ILIM:SINK threshold, the low-side switch is disabled. Both the low-side
and high-side switches remain off until an internal timer re-enables the high-side switch based on the selected
PWM switching frequency.
CAUTION
If Forced PWM (FPWM) mode is being used, TI recommends that the inductor be sized such that
the inductor ripple current, ΔIL (see 方程式 9), does not exceed 2.6 A to avoid the potential for
continuous operation of the negative current limit with no output load (IO = 0 A).
8.3.10 High Temperature Specifications
The TPS62993-Q1 is capable of high operating junction temperatures up to 165°C. The AEC-Q100 Grade-1
maximum ambient temperature requirement (TA_max = 125°C) combined with power dissipation on integrated
chips often results in device operating temperatures well above 125 °C. Additionally, although Grade 1 with
extended temperature does not exist as a standard by itself, the 165°C maximum operating junction temperature
allows for the TPS62993-Q1 to be used in applications with ambient temperatures upwards of 150°C that require
less device power dissipation.
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备注
For more information on the different thermal metrics for semiconductor integrated circuits (ICs)
including the relationship between the operating junction (TJ) and ambient (TA) temperatures of a
device, refer to the Semiconductor and IC Package Thermal Metrics application report.
The TPS62993-Q1 is designed to sustain these high temperatures while maintaining performance and reliability,
which is accomplished by compliant electrical specifications up to TJ = 165°C. In addition, extra reliability testing
has been performed that exceeds the AEC-Q100 Grade 1 requirements.
8.3.11 Thermal Shutdown
The junction temperature, TJ, of the device is monitored by an internal temperature sensor. If TJ rises and
exceeds the thermal shutdown threshold, TSD, the device shuts down. Both the high-side and low-side power
FETs are turned off and PG goes low. When TJ decreases below the hysteresis, the converter resumes normal
operation, beginning with soft start. In PSM during a PFM skip pause (when both high-side and low-side FETs
are off, the thermal shutdown feature is not active. A shutdown or restart is only triggered during a switching
cycle. See 节8.4.2.
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8.4 Device Functional Modes
8.4.1 Forced Pulse Width Modulation (FPWM) Operation
The TPS62993-Q1 has two operating modes: Forced PWM (FPWM) mode discussed in this section and auto
PFM and PWM as discussed in 节8.4.2.
With the MODE/S-CONF pin configured for FPWM mode, the TPS62993-Q1 operates with pulse width
modulation in continuous conduction mode (CCM) with a nominal switching frequency of either 2.5 MHz or 1.0
MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT, and the inductance. The on time
in forced PWM mode is given by 方程式4:
V
OUT
1
T
=
×
(4)
ON
V
f
IN
SW
For very small output voltages, a minimum on time of approximately 30 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high.
8.4.2 Power Save Mode Operation (Auto PFM and PWM)
When the MODE/S-CONF pin is configured for power save mode (auto PFM and PWM). The device operates in
PWM mode as long the output current is higher than half of the ripple current of the inductor, and seamlessly
transitions to PSM operation as the load decreases. In power save mode, the device operates in PFM mode by
reducing the switching frequency linearly with the load current to maintain high efficiency under light load
operation. The device remains in power save mode as long as the inductor current remains discontinuous, and
the transition out of PSM also occurs seamlessly when the load current increases above the DCM boundary.
In addition to operating in PFM under light load, when the 2.5 MHz FSW option is selected, the TPS62993-Q1
further adjusts the on time (TON), depending on the input voltage and the output voltage to maintain highest
efficiency using the AEE function as described in 节8.4.3 .
In power save mode, the TON time can be estimated using 方程式4 for 1 MHz and 方程式8 for 2.5 MHz.
For higher input voltages and small output voltages, an absolute minimum on time of approximately 30 ns is kept
to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps
efficiency high. Using TON, the typical peak inductor current in power save mode is approximated by 方程式5:
V
− V
L
IN
OUT
ILPSM
=
× T
(5)
peak
ON
The output voltage ripple in power save mode is given by 方程式6:
2
L × V
IN
1
− V
1
∆ V =
+
+
V
(6)
200 × C
V
IN
OUT
OUT
where
• L is the effective inductance.
• C is the output effective capacitance.
备注
When VIN decreases to typically 15% above VOUT, the TPS62993-Q1 does not enter power save
mode, regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 AEE (Automatic Efficiency Enhancement)
When the MODE/S-CONF pin is configured for auto PFM/PWM with AEE mode, the TPS62993-Q1 provides the
highest efficiency over the entire input voltage and output voltage range by automatically adjusting the switching
frequency of the converter (see 方程式 7). To keep the efficiency high over the entire duty cycle range, the
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switching frequency is adjusted while maintaining the ripple current amplitudes. This feature compensates for the
very small duty cycles of high VIN to low VOUT conversions, which can limit the control range in other topologies.
V
− V
OUT
IN
F
MHz = 10 × V
×
(7)
SW
OUT
2
V
IN
Traditionally, the efficiency of a switched mode converter decreases if VOUT decreases, VIN increases, or both.
By decreasing the switching losses at lower VOUT values or higher VIN values, the AEE feature provides an
efficiency enhancement across various duty cycles, especially for the lower VOUT values, where fixed frequency
converters suffer from a significant efficiency drop.
To accomplish this, the AEE function in the TPS62993-Q1 adjusts the on time (TON) depending on the input
voltage and the output voltage, and the on time in steady-state operation can be estimated as using 方程式8:
V
IN
T
ns = 100 ×
(8)
ON
V
− V
OUT
IN
By using the same TON configuration (see 方程式 9) across the entire load range in AEE mode, the inductor
ripple current in AEE mode becomes effectively independent of the output voltage and can be approximated by
方程式9:
V
− V
L
V
V
IN
OUT
IN
L μH
∆ I mA = T
×
= 0.1 ×
(9)
L
ON
The TPS62993-Q1 operates in AEE mode as long as the output current is higher than half the ripple current of
the inductor. To maintain high efficiency at light loads, the device enters power save mode at the boundary to
discontinuous mode (DCM), which happens when the output current becomes smaller than half the inductor
ripple current.
8.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operating in PWM mode is given as D = VOUT / VIN. The duty cycle
increases as the input voltage comes close to the output voltage and the off time gets smaller. When the
minimum off time of typically 80 ns is reached, the TPS62993-Q1 scales down its switching frequency while it
approaches 100% mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side
switch stays turned on as long as the output voltage is below the internal set point, allowing the conversion of
small input to output voltage differences (for example, getting longest operation time of battery-powered
applications). In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
V
= V
+ I
× R
+ R
L
(10)
IN MIN
OUT
OUT
DS ON
where
• IOUT is the output current.
• RDS(on) is the on-state resistance of the high-side FET.
• RL is the DC resistance of the inductor used.
8.4.5 Starting into a Prebiased Load
The TPS62993-Q1 is capable of starting into a prebiased output. The device only starts switching when the
internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPS62993-Q1 does not start switching unless the voltage at the
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feedback pin drops to the target. See the note in 节 8.3.6 regarding the soft-start requirement during prebiased
conditions.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS62993-Q1 devices are highly efficient, small, and highly flexible synchronous step-down DC/DC
converters that are easy to use. A wide input voltage range of 3 V to 10 V supports a wide variety of inputs like
9-V supply rails, single-cell or multi-cell Li-Ion, and 5-V or 3.3-V rails.
9.2 Typical Application with Adjustable Output Voltage
VIN
3 V to 10 V
VOUT
0.6 V to 5.5 V
TPS6299x-Q1
1 H
VIN
SW
EN
VOS
C2
22 F
C1
10 F
R1
R2
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
GND
图9-1. Typical Application Circuit
9.2.1 Design Requirements
表9-1. List of Components
Description
Reference
IC
Manufacturer
10 V, 3-A step-down converter
1-µH inductor
TPS62993-Q1 series; Texas Instruments
XGL4020-102; Coilcraft
L
CIN
10 µF, 25 V, Ceramic, X8R
22 µF, 16 V, Ceramic, X8L
CGA6P1X8R1E106K250AE, TDK
CGA6P1X8L1C226M250AC, TDK
AEC-Q200 qualified, 16 V, Ceramic, X8R
COUT
CSS
Depends on soft-start time; see 节9.2.2.3.3.3.
Depending on VOUT; see 节9.2.2.2.
AEC-Q200 qualified, Standard 1% metal
film
R1
R2
R3
AEC-Q200 qualified, Standard 1% metal
film
Depending on VOUT; see 节9.2.2.2.
AEC-Q200 qualified, Standard 1% metal
film
Depending on device setting, see 节8.3.1.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62993-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
When the MODE/S_CONF pin is configured for external feedback, the output voltage of the TPS62993-Q1 is
fully adjustable. It can be programmed for output voltages from 0.6 V to 5.5 V using a resistor divider from VOUT
to GND. The voltage at the FB pin is regulated to 600 mV. The value of the output voltage is set by the selection
of the resistor divider from 方程式 11. TI recommends to choose resistor values that allow a current of at least 2
μA, meaning the value of R2 must not exceed 400 kΩ. Lower resistor values are recommended for highest
accuracy and most robust design.
VOUT
VFB
R = R ×
− 1
(11)
1
2
With typical VFB = 0.6 V:
表9-2. Setting the Output Voltage
Nominal Output Voltage
R1
R2
Exact Output Voltage
0.749 V
1.2 V
0.75 V
1.2 V
1.5 V
1.8 V
2.0 V
2.5 V
3.0 V
3.3 V
5.0V
24.9 kΩ
100 kΩ
150 kΩ
200 kΩ
49.9 kΩ
100 kΩ
100 kΩ
113 kΩ
182 kΩ
100 kΩ
100 kΩ
100 kΩ
100 kΩ
21.5 kΩ
31.6 kΩ
24.9 kΩ
24.9 kΩ
24.9 kΩ
1.5 V
1.8 V
1.992 V
2.498 V
3.009 V
3.322 V
4.985 V
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the control
loop of the device. The TPS62993-Q1 is optimized to work within a range of external components.
9.2.2.3.1 Output Filter and Loop Stability
The TPS62993-Q1 is designed to be stable with a range of L-C filter combinations. The LC output filters
inductance and capacitance have to be considered together, creating a double pole responsible for the corner
frequency of the converter using 方程式12.
1
f
=
(12)
LC
2π L × C
Proven nominal values for inductance and ceramic capacitance are given in 表 9-3 and are recommended for
use with the effective capacitance considered to vary by +20% and –50%. Different values can work, but care
has to be taken on the loop stability, which is affected. More information including a detailed LC stability matrix
can be found in the Optimizing the TPS62130/40/50/60 Output Filter application report.
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200 µF
表9-3. Recommended LC Output Filter Combinations
4.7 µF
10 µF
22 µF
47 µF
100 µF
(1)
(3)
1 µH
√
√
√
√
√
(3)
1.5 µH
2.2 µH
3.3 µH
√
√
√
√
(2)
(3)
√
√
√
√
√
√
√
√
(1) This LC combination is the standard value and recommended for most applications with 2.5-MHz switching frequency.
(2) This LC combination is the standard value and recommended for most applications with 1-MHz switching frequency.
(3) Output capacitance must have a ESR of ≥10 mΩfor stable operation, see 节9.4.2.
The TPS62993-Q1 includes an internal 3-pF feedforward capacitor, connected between the VOS and FB pins.
This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of
the feedback divider, per 方程式13 and 方程式14:
1
f
=
=
(13)
(14)
zero
pole
2π × R × 3pF
1
1
1
1
f
×
×
R
2π × 3pF
R
1
2
Although the TPS62993-Q1 devices are stable without the pole and zero being in a particular location, an
external feedforward capacitor can be added to adjust their locations to the specific needs of the application can
provide better performance in power save mode, improved transient response, or both. A more detailed
discussion on the optimization for stability versus transient response can be found in the Optimizing Transient
Response of Internally Compensated DC-DC Converters and Feedforward Capacitor to Improve Stability and
Bandwidth of TPS621/821-Family application reports.
9.2.2.3.2 Inductor Selection
The TPS62993-Q1 is designed for a nominal 1-µH inductor. Larger values can be used to achieve a lower
inductor current ripple, but they can have a negative impact on efficiency and transient response. Smaller values
than 1 µH cause a larger inductor current ripple, which causes larger negative inductor current in forced PWM
mode at low or no output current. Therefore, TI does not recommend them at large voltages across the inductor
as it is the case for high input voltages and low output voltages. Low-output current in forced PWM mode causes
a larger negative inductor current peak, which can exceed the negative current limit. At low or no output current
and small inductor values, the output voltage cannot be regulated any more. More detailed information on further
LC combinations can be found in the Optimizing the TPS62130/40/50/60 Output Filter application report.
The inductor selection is affected by several factors like inductor ripple current, output ripple voltage, PWM-to-
PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). 方程式15 calculates the maximum inductor current.
∆ I
L MAX
2
I
= I
+
(15)
(16)
L MAX
OUT MAX
V
OUT
1 −
V
IN MAX
∆ I
= V
×
L MAX
OUT
L
× f
MIN
SW
where
• IL(max) is the maximum inductor current.
• ΔIL(max) is the maximum peak-to-peak inductor ripple current.
• L(min) is the minimum effective inductor value.
• fsw is the actual PWM switching frequency.
• VOUT is the output voltage.
• VIN(max) is the maximum expected output voltage.
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Calculating the maximum inductor current using the actual operating conditions gives the needed minimum
saturation current of the inductor. TI recommends to add a margin of about 20%. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62993-Q1 and are recommended for use:
表9-4. List of Inductors
Dimensions [L × B
Type
Inductance [µH]
Current [A](1)
Manufacturer
× H] mm
XGL4020-102ME
XGL4020-222ME
1.0 µH, ±20%
8.8
6.2
4.0 × 4.0 × 2.1
4.0 × 4.0 × 2.1
Coilcraft
Coilcraft
2.2 μH, ±20%
(1) ISAT at 30% drop
The inductor value also determines the load current at which power save mode is entered:
1
2
I
=
× ∆ I
(17)
Load PSM
L
9.2.2.3.3 Capacitor Selection
9.2.2.3.3.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS62993-Q1 allows the use
of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, TI recommends the use of X7R or X8R dielectric capacitors. Using a
higher value has advantages like smaller voltage ripple and a tighter DC output accuracy in power save mode
(see the Optimizing the TPS62130/40/50/60 Output Filter application report).
In power save mode, the output voltage ripple depends on the following:
• Output capacitance
• ESR
• ESL
• Peak inductor current
Using ceramic capacitors provides small ESR, ESL, and low ripple. The output capacitor must be as close as
possible to the device.
For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance has to
be observed.
9.2.2.3.3.2 Input Capacitor
For most applications, 10 µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. TI recommends a low-ESR multilayer ceramic capacitor (MLCC) for best filtering and
must be placed between VIN and GND as close as possible to those pins.
表9-5. List of Capacitors
Type (1)
Nominal Capacitance [µF]
Voltage Rating [V]
Size
1210
1210
Manufacturer
TDK
CGA6P1X8R1E106K250AE
CGA6P1X8L1C226M250AC
10
22
25
16
TDK
(1) Lower of IRMS at 40°C rise or ISAT at 30% drop
9.2.2.3.3.3 Soft-Start Capacitor
A capacitor connected between SS/TR pin and GND allows a user-programmable start-up slope of the output
voltage.
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ISS
SS/TR
to VREF
图9-2. Soft-Start Operation Simplified Schematic
An internal constant current source is provided to charge the external capacitance. The capacitor required for a
given soft-start ramp time is given by:
I
SS
C
= T
×
(18)
SS
SS
V
REF
where
• CSS is the capacitance required at the SS/TR pin.
• TSS is the desired soft-start ramp time.
• ISS is the SS/TR source current, see the Electrical Characteristics.
• VREF is the feedback regulation voltage divided by tracking gain (VFB / 0.75); see the Electrical
Characteristics.
The fastest achievable typical ramp time is 150 µs, even if the external Css capacitance is lower than 680 pF or
the pin is open.
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9.2.3 Application Curves
9.2.3.1 Application Curves Vout = 1.8 V
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 1.8 V
Fsw = 2.5 MHz
Forced PWM
VOUT = 1.8 V
Fsw = 2.5 MHz
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-4. Efficiency vs Output Current
图9-3. Efficiency vs Output Current
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.8
3
4
5
6
7
8
9
10
Input Voltage (V)
VOUT = 1.8 V
Fsw = 2.5 MHz
VOUT = 1.8 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-5. Switching Frequency vs Input Voltage
图9-6. Switching Frequency vs Input Voltage
1
1
Vin = 3V
Vin = 6V
Vin = 3V
Vin = 6V
0.8
0.8
Vin = 9V
Vin = 9V
0.6
0.6
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 1.8 V
Fsw = 2.5 MHz
VOUT = 1.8 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-7. Output Voltage vs Output Current
图9-8. Output Voltage vs Output Current
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100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 1.8 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 1.8 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-10. Efficiency vs Output Current
图9-9. Efficiency vs Output Current
1.4
1.32
1.24
1.16
1.08
1
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
Iout = 0.1A
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.92
0.84
0.76
0.68
0.6
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 1.8 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 1.8 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-12. Switching Frequency vs Input Voltage
图9-11. Switching Frequency vs Input Voltage
1
Vin = 3V
Vin = 6V
0.8
Vin = 9V
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 1.8 V
Fsw = 1.0 MHz
VOUT = 1.8 V
Fsw = 1.0 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-13. Output Voltage vs Output Current
图9-14. Output Voltage vs Output Current
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9.2.3.2 Application Curves Vout = 1.2 V
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 1.2 V
Fsw = 2.5 MHz
Forced PWM
VOUT = 1.2 V
Fsw = 2.5 MHz
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-16. Efficiency vs Output Current
图9-15. Efficiency vs Output Current
4
3.6
3.2
2.8
2.4
2
3.2
3
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
1.6
1.2
0.8
0.4
0
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.8
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V
Fsw = 2.5 MHz
VOUT = 1.2 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-17. Switching Frequency vs Input Voltage
图9-18. Switching Frequency vs Input Voltage
1
1
Vin = 3V
Vin = 6V
Vin = 3V
Vin = 6V
0.8
0.8
Vin = 9V
Vin = 9V
0.6
0.6
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 1.2 V
Fsw = 2.5 MHz
VOUT = 1.2 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-19. Output Voltage vs Output Current
图9-20. Output Voltage vs Output Current
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Product Folder Links: TPS62993-Q1
English Data Sheet: SLVSGV5
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
www.ti.com.cn
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 1.2 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 1.2 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-22. Efficiency vs Output Current
图9-21. Efficiency vs Output Current
1.4
1.32
1.24
1.16
1.08
1
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
Iout = 0.1A
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.92
0.84
0.76
0.68
0.6
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 1.2 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-24. Switching Frequency vs Input Voltage
图9-23. Switching Frequency vs Input Voltage
1
1
Vin = 3V
Vin = 6V
Vin = 3V
Vin = 6V
0.8
0.8
Vin = 9V
Vin = 9V
0.6
0.6
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 1.2 V
Fsw = 1.0 MHz
VOUT = 1.2 V
Fsw = 1.0 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-25. Output Voltage vs Output Current
图9-26. Output Voltage vs Output Current
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English Data Sheet: SLVSGV5
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9.2.3.3 Application Curves Vout = 0.6 V
100
90
80
70
60
50
40
30
20
10
0
Vin = 3V
Vin = 6V
Vin = 9V
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 0.6 V
Fsw = 2.5 MHz
Forced PWM
VOUT = 0.6 V
Fsw = 2.5 MHz
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-28. Efficiency vs Output Current
图9-27. Efficiency vs Output Current
4
3.6
3.2
2.8
2.4
2
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
1.6
1.2
0.8
0.4
0
3
4
5
6
7
8
9
10
Input Voltage (V)
VOUT = 0.6 V
Fsw = 2.5 MHz
VOUT = 0.6 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-29. Switching Frequency vs Input Voltage
图9-30. Switching Frequency vs Input Voltage
3
1
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.8
0.6
2
1
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
-1
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 0.6 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
VOUT = 0.6 V
Fsw = 2.5 MHz
L = 1.0 μH
Auto PFM/PWM
图9-32. Output Voltage vs Output Current
图9-31. Output Voltage vs Output Current
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Product Folder Links: TPS62993-Q1
English Data Sheet: SLVSGV5
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
www.ti.com.cn
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 3V
Vin = 6V
Vin = 9V
Vin = 3V
Vin = 6V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 0.6 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 0.6 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-34. Efficiency vs Output Current
图9-33. Efficiency vs Output Current
1.4
1.36
1.32
1.28
1.24
1.2
1.16
1.12
1.08
1.04
1
0.96
0.92
0.88
0.84
0.8
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
Iout = 0.1A
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 0.6 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 0.6 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-36. Switching Frequency vs Input Voltage
图9-35. Switching Frequency vs Input Voltage
1
1
Vin = 3V
Vin = 6V
Vin = 3V
Vin = 6V
0.8
0.8
Vin = 9V
Vin = 9V
0.6
0.6
0.4
0.2
0
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 0.6 V
Fsw = 1.0 MHz
VOUT = 0.6 V
Fsw = 1.0 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-37. Output Voltage vs Output Current
图9-38. Output Voltage vs Output Current
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLVSGV5
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9.3 Typical Application with Selectable VOUT using VSET
VIN
VOUT
0.4 V to 5.5 V
TPS6299x-Q
3 V to 10 V
1 H
VIN
SW
EN
VOS
C2
22 F
C1
10 F
FB/
VSET
SS/TR
R2
MODE/
S-CONF
PG
R3
C3
GND
图9-39. Typical Application Circuit (VSET)
9.3.1 Design Requirements
表9-6. List of Components
Description
Reference
IC
Manufacturer
10 V, 3-A step-down converter
1-µH inductor
TPS62993-Q1 series; Texas Instruments
XGL4020-102; Coilcraft
L
CIN
10 µF, 25 V, Ceramic, X8R
22 µF, 16 V, Ceramic, X8L
CGA6P1X8R1E106K250AE, TDK
CGA6P1X8L1C226M250AC, TDK
AEC-Q200 qualified, 16 V, Ceramic, X8R
COUT
CSS
Depends on soft-start time; see 节9.2.2.3.3.3.
Depending on VOUT; see .节8.3.3
AEC-Q200 qualified, Standard 1% metal
film
R2
R3
AEC-Q200 qualified, Standard 1% metal
film
Depending on device setting, see 节8.3.1.
9.3.2 Detailed Design Procedure
9.3.2.1 Programming the Output Voltage
When the resitor (R3) on the MODE/S-CONF pin is sized for "VSET" (internal FB) operation (see 表 8-1) , the
output voltage of the TPS62993-Q1 becomes selectable with a resistor (R2) from the FB/VSET pin the GND.
The output can be programmed to one of 16 different fixed output voltages ranging from 0.4 V to 5.5 V based on
表8-2.
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English Data Sheet: SLVSGV5
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
www.ti.com.cn
9.3.3 Application Curves
9.3.3.1 Application Curves Vout = 5 V
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 7V
Vin = 9V
Vin = 7V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 5.0 V
Fsw = 2.5 MHz
Forced PWM
VOUT = 5.0 V
Fsw = 2.5 MHz
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-41. Efficiency vs Output Current
图9-40. Efficiency vs Output Current
4.8
4.4
4
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
6
7
8
9
10
Input Voltage (V)
VOUT = 5.0 V
Fsw = 2.5 MHz
VOUT = 5.0 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-42. Switching Frequency vs Input Voltage
图9-43. Switching Frequency vs Input Voltage
1
1
Vin = 7V
Vin = 9V
Vin = 7V
Vin = 9V
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 5.0 V
Fsw = 2.5 MHz
VOUT = 5.0 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-44. Output Voltage vs Output Current
图9-45. Output Voltage vs Output Current
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS62993-Q1
English Data Sheet: SLVSGV5
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
www.ti.com.cn
100
90
80
70
60
50
40
30
20
10
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 7V
Vin = 9V
Vin = 7V
Vin = 9V
0
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
VOUT = 5.0 V
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 5.0 V
Fsw = 1.0 MHz
Forced PWM
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-47. Efficiency vs Output Current
图9-46. Efficiency vs Output Current
1.4
1.32
1.24
1.16
1.08
1
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
Iout = 0.1A
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.92
0.84
0.76
0.68
0.6
6
7
8
9
10
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 5.0 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 5.0 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-49. Switching Frequency vs Input Voltage
图9-48. Switching Frequency vs Input Voltage
1
1
Vin = 7V
Vin = 9V
Vin = 7V
Vin = 9V
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 5.0 V
Fsw = 1.0 MHz
VOUT = 5.0 V
Fsw = 1.0 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-50. Output Voltage vs Output Current
图9-51. Output Voltage vs Output Current
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Product Folder Links: TPS62993-Q1
English Data Sheet: SLVSGV5
TPS62993-Q1
ZHCSQD4A –OCTOBER 2022 –REVISED MARCH 2023
www.ti.com.cn
9.3.3.2 Application Curves Vout = 3.3 V
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
Vin = 6V
Vin = 9V
Vin = 6V
Vin = 9V
0.05 0.07 0.1
0.2 0.3 0.40.5 0.7
Iout (A)
1
2
3
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
VOUT = 3.3 V
Fsw = 2.5 MHz
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-53. Efficiency vs Output Current
图9-52. Efficiency vs Output Current
3.2
3
4.8
4.4
4
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
2.8
2.6
2.4
2.2
2
3.6
3.2
2.8
2.4
2
1.8
1.6
1.4
1.2
1
1.6
1.2
0.8
0.4
0
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.8
4
5
6
7
8
9
10
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V
Fsw = 2.5 MHz
L = 1.0 μH
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
Auto PFM/PWM
图9-54. Switching Frequency vs Input Voltage
图9-55. Switching Frequency vs Input Voltage
1
0.8
0.6
0.4
0.2
0
1
Vin = 6V
Vin = 9V
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
Vin = 6V
-0.8
Vin = 9V
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 3.3 V
Fsw = 2.5 MHz
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
L = 1.0 μH
L = 1.0 μH
Auto PFM/PWM
图9-56. Output Voltage vs Output Current
图9-57. Output Voltage vs Output Current
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS62993-Q1
English Data Sheet: SLVSGV5
TPS62993-Q1
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www.ti.com.cn
100
90
80
70
60
50
40
30
20
10
Vin = 6V
Vin = 9V
0
1E-5
0.0001
VOUT = 3.3 V
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
VOUT = 3.3 V
Fsw = 1.0 MHz
Forced PWM
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-59. Efficiency vs Output Current
图9-58. Efficiency vs Output Current
1.4
1.32
1.24
1.16
1.08
1
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
Iout = 0.1A
Iout = 0.1A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
Iout = 0.5A
Iout = 1A
Iout = 2A
Iout = 3A
0.92
0.84
0.76
0.68
0.6
4
5
6
7
8
9
10
4
5
6
7
8
9
10
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V
Fsw = 1.0 MHz
Forced PWM
VOUT = 3.3 V
Fsw = 1.0 MHz
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-61. Switching Frequency vs Input Voltage
图9-60. Switching Frequency vs Input Voltage
1.2
1
1
Vin = 6V
Vin = 9V
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
Vin = 6V
Vin = 9V
-0.8
-1
1E-5
0.0001
0.001
0.01
Iout (A)
0.10.2 0.5 1 2 3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Iout (A)
3
VOUT = 3.3 V
Fsw = 1.0 MHz
VOUT = 3.3 V
Fsw = 1.0 MHz
Forced PWM
L = 2.2 μH
L = 2.2 μH
Auto PFM/PWM
图9-62. Output Voltage vs Output Current
图9-63. Output Voltage vs Output Current
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Product Folder Links: TPS62993-Q1
English Data Sheet: SLVSGV5
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VIN = 6 V
Css = 3.3 nF
IOUT = 0 A
Fsw = 2.5 MHz
VIN = 6 V
Css = 0 nF
IOUT = 0 A
Fsw = 2.5 MHz
VOUT = 3.3 V
Auto PFM/PWM
VOUT = 3.3 V
Auto PFM/PWM
图9-64. Start-Up Timing
图9-65. Start-Up Timing
VIN = 6 V
Css = 3.3 nF
IOUT = 3 A
Fsw = 2.5 MHz
FPWM
VIN = 6 V
Css = 0 nF
IOUT = 3 A
Fsw = 2.5 MHz
FPWM
VOUT = 3.3 V
VOUT = 3.3 V
图9-66. Start-Up Timing
图9-67. Start-Up Timing
VIN = 6 V
Fsw = 2.5 MHz
VIN = 6 V
Css = 3.3 nF
IOUT = 0 A
Fsw = 2.5 MHz
FPWM
L = 1.0 μH
VOUT = 3.3 V
VOUT = 3.3 V
IOUT = 10 mA
Auto PFM/PWM
图9-68. Start-Up into Prebiased Output
图9-69. Shutdown Timing with Output Discharge
Enabled
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VIN = 6 V
VOUT = 3.3 V
Fsw = 2.5 MHz
L = 1.0 μH
VIN = 6 V
Fsw = 2.5 MHz
FPWM
L = 1.0 μH
IOUT = 10 mA
Auto PFM/PWM
VOUT = 3.3 V
IOUT = 3 A
图9-70. Shutdown Timing with Output Discharge
图9-71. Shutdown Timing with Output Discharge
Disabled
Disabled
VIN = 6 V
Fsw = 2.5 MHz
L = 1.0 μH
VIN = 6 V
Fsw = 2.5 MHz
L = 1.0 μH
VOUT = 3.3 V IOUT = 10 mA to 1
A
Auto PFM/PWM
VOUT = 3.3 V IOUT = 10 mA to 1
A
Auto PFM/PWM
图9-72. Load Transient Response
图9-73. Load Transient Response Undershoot
VIN = 6 V
Fsw = 2.5 MHz
L = 1.0 μH
VIN = 6 V
Fsw = 2.5 MHz
L = 1.0 μH
VOUT = 3.3 V IOUT = 1 A to 10
mA
Auto PFM/PWM
VOUT = 3.3 V
IOUT = 0 A
Auto PFM/PWM
图9-75. Output Voltage Ripple
图9-74. Load Transient Response Overshoot
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VIN = 6 V
Fsw = 2.5 MHz
VIN = 6 V
Fsw = 1.0 MHz
L = 1.0 μH
L = 2.2 μH
VOUT = 3.3 V
IOUT = 1 A
Auto PFM/PWM
VOUT = 3.3 V
IOUT = 100 mA
Auto PFM/PWM
图9-77. Output Voltage Ripple
图9-76. Output Voltage Ripple
VIN = 6 V
Fsw = 2.5 MHz
FPWM
VIN = 6 V
Fsw = 2.5 MHz
FPWM
L = 1.0 μH
L = 1.0 μH
VOUT = 3.3 V
IOUT = 3 A
VOUT = 3.3 V
IOUT = 3 A
图9-79. Input Voltage Ripple
图9-78. Output Voltage Ripple
60
50
300
Gain
Phase
250
200
150
100
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-50
-100
-150
-200
-250
-300
1000 2000 5000 10000
100000
1000000
VIN = 6 V
Fsw = 1.0 MHz
FPWM
L = 2.2 μH
Frequency (Hz)
VOUT = 3.3 V
IOUT = 5 A
VIN = 6 V
Fsw = 2.5 MHz
FPWM
L = 1.0 μH
VOUT = 3.3 V
IOUT = 3 A
图9-80. Current Limit
图9-81. Bode Plot
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9.4 System Examples
9.4.1 LED Power Supply
The TPS62993-Q1 can be used as a power supply for power LEDs. The FB pin can be easily set to lower values
than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor (R2) is reduced to avoid
excessive power loss. Because the SS/TR pin provides 2.5 µA (typical), the feedback pin voltage can be
adjusted by an external resistor per 方程式 19. This drop, proportional to the LED current, is used to regulate the
output voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported
with the TPS62993-Q1. 图9-82 shows an application circuit, tested with analog dimming.
L1
TPS629xx-Q1
VIN
VOUT
VIN
SW
EN
VOS
C2
22 μF
C1
10 μF
FB/
VSET
SS/TR
R2
MODE/
S-CONF
PG
R3
R4
GND
图9-82. Single Power LED Supply
The resistor at SS/TR defines the FB voltage. The resistor at SS/TR is set to 304 mV by RSS/TR = R4 = 162 kΩ
using 方程式 19. This cuts the losses on R2 to half from the nominal 0.6 V of feedback voltage while it still
provides good accuracy.
VFB = 0.75 x 2.5μA x RSS/TR
(19)
The device now supplies a constant current set by resistor R2 from FB/VSET to GND. The minimum input
voltage has to be rated according the forward voltage needed by the LED used. More information is available in
the Step-Down LED Driver With Dimming With the TPS621-Family and TPS821-Family application report.
9.4.2 Powering Multiple Loads
In applications where the TPS62993-Q1 is used to power multiple load circuits, the total capacitance on the
output can be very large. To properly regulate the output voltage, there must be an appropriate AC signal level
on the VOS pin. Tantalum capacitors have a large enough ESR to keep output voltage ripple sufficiently high on
the VOS pin. With low-ESR ceramic capacitors, the output voltage ripple can get very low, so TI does not
recommend to use a large capacitance directly on the output of the device. If there are several load circuits with
their associated input capacitor on a PCB, these loads are typically distributed across the board. This adds
enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for proper regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n × CIN in the use
case below was 32 × 47 μF of ceramic X7R capacitors.
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Load-1
Rtrace
Rtrace
CIN1
CIN2
VOUT
0.6 V –
L1
TPS629xx-Q1
VIN
V
VIN
SW
Load-2
C2
22 F
EN
VOS
C1
10 F
R1
R2
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
GND
Load-n
Rtrace
CINn
图9-83. Multiple Loads
备注
图 9-83 shows an external feedback configuration, but the internal (VSET) configuration can also be
used.
9.4.3 Voltage Tracking
图 9-84 shows how two TPS62993-Q1s can be configured to tracking output voltages. In this configuration,
Device 2 follows the voltage applied to its SS/TR pin from Device 1 output. A ramp on the SS/TR pin of Device 2
to 0.8 V in turn ramps VOUT2 according to the 0.6-V reference on VFB and the R4//R5 resistor divider.
For this example, to track the 3.8 V (VOUT1) of Device 1 a resistor divider (R7//R8) on SS/TR of Device 2 is
required to generate 0.8 V when the output voltage (VOUT1) is in regulation. Due to the ISS current of 2.5 µA
from the SS/TR pin, the equivalent resistance of R7 // R8 must be kept below 15 kΩ to minimize any offset the
ISS current can cause on the SS/TR pin voltage.
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Device 1
L1
TPS629xx-Q1
VOUT1
VIN
VIN
SW
EN
VOS
R1
R2
22 μF
10 μF
FB/
VSET
SS/TR
MODE/
S-CONF
PG
GND
CSS
R3
Device 2
L2
TPS629xx-Q1
VOUT2
VIN
SW
EN
VOS
22 μF
R7
R8
10 μF
R4
R5
FB/
VSET
SS/TR
MODE/
S-CONF
PG
GND
R6
图9-84. Tracking Example
图9-85. Tracking
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9.4.4 Inverting Buck-Boost (IBB)
The need to generate negative voltage rails for electronic designs is a common challenge. The wide 3-V to 10-V
input voltage range of the TPS62993-Q1 makes it ideal for an inverting buck-boost (IBB) circuit, where the output
voltage is inverted or negative with respect to ground.
The circuit operation in the IBB topology differs from that in the traditional buck topology. Though the
components are connected the same as with a traditional buck converter, the output voltage terminals are
reversed. See 图9-86.
The maximum input voltage that can be applied to an IBB converter is less than the maximum voltage that can
be applied to the TPS62993-Q1 in a typical buck configuration. This is because the ground pin of the IC is
connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, and not
VIN to ground. Thus, the input voltage range of the TPS62993-Q1 in an IBB configuration becomes 3 V to 10 V +
VOUT, where VOUT is a negative value.
The output voltage range is the same as when configured as a buck converter, but only negative. Thus, the
output voltage for a TPS62993-Q1 in an IBB configuration can be set between –0.4 V and –5.5 V.
The maximum output current for the TPS62993-Q1 in an IBB topology is normally lower than a traditional buck
configuration due to the average inductor current being higher in an IBB configuration. Traditionally, lower input
or (more negative) output voltages results in a lower maximum output current. However, using a larger inductor
value or the higher 2.5-MHz frequency setting can be used to recover some or all of this lost maximum current
capability.
When implementing an IBB design, it is important to understand that the IC ground is tied to the negative voltage
rail, and in turn, the electrical characteristics of the TPS62993-Q1 device are referenced to this rail. During
power up, as there is no charge in the output capacitor and the IC GND pin (and VOUT) are effectively 0 V, thus
parameters such as the VIN UVLO and EN thresholds are the same as in a typical buck configuration. However,
after the output voltage is in regulation, due to the negative voltage on the IC GND pin, the device traditionally
continues to operate below what can appear to be the normal UVLO or EN falling thresholds relative to the
system ground. Take care if the user is using the dynamic mode change feature on the MODE pin of the
TPS62993-Q1 or driving the EN pin from an upstream microcontroller as the high and low thresholds are relative
to the negative rail and not the system ground.
More information on using a DCS regulator in an IBB configuration can be found in the Description
Compensating the Current Mode Boost Control Loop, Using the TPS6215x in an Inverting Buck-Boost Topology,
and Using the TPS629210 in an Inverting Buck-Boost Topology application notes.
TPS629xx-Q1
L1
VIN
VIN
SW
22 F
10 F
EN
VOS
SS/TR
FB/VSET
PG
Css
MODE/
S-CONF
VOUT
-0.6 V to -5.5 V
GND
图9-86. IBB Example with Adjustable Feedback
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备注
图 9-86 shows an external feedback configuration, but the internal (VSET) configuration can also be
used.
9.5 Power Supply Recommendations
The power supply to the TPS62993-Q1 must have a current rating according to the supply voltage, output
voltage, and output current of the TPS62993-Q1. At a minimum, the input power supply must provide enough
power to cover the maximum output power divided by the efficiency at maximum load. A good rule of thumb is to
use a supply with an additional 50% of power capability to withstand the additional loading associated with
power up, transient events, and potential overload events.
备注
For current limited input supplies with a variable supply voltage, the minimum supply voltage must be
used to determine if the power supply is sufficient.
9.6 Layout
9.6.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS62993-Q1 demands careful attention to make sure the device
works correctly and to get the performance specified. A poor layout can lead to issues like poor regulation (both
line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.
See 图 9-87 for the recommended layout of the TPS62993-Q1, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin of
TPS62993-Q1. Also, connect the VOS pin in the shortest way to VOUT at the output capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths, conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
traces with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an
alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (for
example, SW). As they carry information about the output voltage, they must be connected as close as possible
to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors,
R1 and R2, must be kept close to the IC and connected directly to those pins and the system ground plane. The
same applies to the VSET resistor if VSET is used to scale the output voltage.
The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat
through the PCB.
In case any of the digital inputs EN and MODE/S-CONF must be tied to the input supply voltage at VIN, the
connection must be made directly at the input capacitor as indicated in the schematics.
The recommended layout is implemented on the EVM and shown in the TPS6290x-Q1 Step-Down Converter
Evaluation Module user's guide.
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9.6.2 Layout Example
图9-87. Layout
9.6.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
The basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design, for example, increasing copper thickness,
thermal vias, number of layers
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics application reports.
The TPS62993-Q1 is designed for a maximum operating junction temperature (TJ) of 165°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the
size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal
resistance. To get an improved thermal behavior, TI recommends to use top layer metal to connect the device
with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved
thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
The device is qualified for long term qualification with 165°C junction temperature. For more details about the
derating and life time of the HotRod™ package, see the Derating and Lifetime Calculations for FCOL Packages
HotRod and FC-SOT application note.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62993-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Derating and Lifetime Calculations for FCOL Packages HotRod and FC-SOT application
note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
application report
• Texas Instruments, TPS6290x-Q1 Step-Down Converter Evaluation Module user's guide
• Texas Instruments, Using the TPS629210 in an Inverting Buck-Boost Topology application report
• Texas Instruments, Description Compensating the Current Mode Boost Control Loop application report
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62993QRYTRQ1
ACTIVE
VQFN-HR
RYT
9
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TS93
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62993QRYTRQ1
VQFN-
HR
RYT
9
3000
180.0
8.4
2.25
2.45
1.15
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RYT
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TPS62993QRYTRQ1
9
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RYT0009A
VQFN-HR - 1 mm max height
S
C
A
L
E
6
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
B
2.1
1.9
A
2.3
2.1
PIN 1 INDEX AREA
0.1 MIN
(0.05)
SECTION A-A
TYPICAL
1.05
0.95
C
SEATING PLANE
0.05
0.00
0.08
0.775
0.575
SYMM
(0.2) TYP
6X
3
4
A
A
PIN 1 ID
SYMM
2X 1.5
1
9
7
8X 0.5
0.3
13X
0.2
0.1
0.05
8
0.575
0.375
C A B
2X 1
4226765/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RYT0009A
VQFN-HR - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X
(0.875)
SYMM
8
2X
(0.825)
(0.65)
7
4X (0.4)
9
1
8X (0.5)
SYMM
2X (2.55)
2X (1.5)
13X
(0.25)
(R0.05) TYP
3
4
2X (1)
(1.525)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226765/A 04/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RYT0009A
VQFN-HR - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X
(0.875)
SYMM
8
4X
(0.825)
(0.65)
7
2X (0.4)
9
1
8X
(0.5)
(2.55)
SYMM
13X
(0.25)
2X (1.5)
(R0.05) TYP
4
3
2X (1)
(1.525)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4226765/A 04/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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