TPS631000DRLR [TI]
1.5A 输出电流、高功率密度降压/升压转换器 | DRL | 8 | -40 to 125;
| 型号： | TPS631000DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5A 输出电流、高功率密度降压/升压转换器 | DRL | 8 | -40 to 125 升压转换器 |
| 文件： | 总27页 (文件大小：4081K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS631000
ZHCSP59B – OCTOBER 2021 – REVISED JUNE 2022
TPS631000 1.5A 输出电流高功率密度降压/升压转换器
1 特性
2 应用
•
1.6V 至 5.5V 输入电压范围
•
•
•
系统预稳压器（智能手机、平板电脑、终端、远程
信息处理）
– 器件启动时输入电压大于 1.65 V
1.2V 至 5.3V 输出电压范围（可调节）
高输出电流能力，3A 峰值开关电流
– VIN ≥ 3V、VOUT = 3.3V 时，输出电流为 2A
– VIN ≥ 2.7V、VOUT = 3.3V 时，输出电流为 1.5A
在整个负载范围内具有高效率
– 8µA 静态电流（典型值）
– 省电模式
负载点调节（有线传感器、端口/电缆适配器和加密
狗）
•
•
指纹、摄像头传感器（电子智能锁、IP 网络摄像
机）
•
•
射频放大器电源（智能传感器）
稳压器（数据通信、光学模块、制冷/加热）
•
3 说明
•
•
1A 电流阶跃时具有 150mV 的负载阶跃响应
峰值电流降压/升压模式架构
TPS631000 是一款采用恒定频率峰值电流模式控制的
降压/升压转换器。该器件具有 3A 峰值电流限制（典
型值）和 1.6V 至 5.5V 输入电压范围。TPS631000 为
系统预稳压器和稳压器提供电源解决方案。
– 无缝转换模式，输出波纹 < 20mV
– 正向和反向电流运行
– 启动至预偏置输出
– 固定频率运行，2MHz 开关频率
安全、可靠运行的特性
根据输入电压不同，当输入电压近似等于输出电压时，
TPS631000 会自动以升压、降压或 3 周期降压/升
压模式运行。以定义的占空比进行模式切换，避免不必
要的模式内切换，以减少输出电压纹波。静态电流为
8μA，电源处于省电模式，可在轻载甚至空载条件下实
现出色效率。
•
– 过流保护和短路保护
– 采用有源斜坡的集成软启动
– 过热保护和过压保护
– 带负载断开功能的真正关断功能
– 正向和反向电流限制
小解决方案尺寸
TPS631000 提供非常小的解决方案尺寸，采用 1.2mm
× 2.1mm SOT-583 封装、一个 1μH 电感器和一个
0805 输出电容器。
•
•
– 小型 1µH 电感器
– 在整个 VOUT 范围内支持一个 0805 输出电容器
使用 TPS631000 并借助 WEBENCH® Power
Designer 创建定制设计
器件信息
器件型号
封装(1)
封装尺寸（标称值）
TPS631000
SOT-583
1.6 mm × 2.1 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
L1
100
95
LX1
VIN
LX2
VI
VOUT
VO
90
CI
CO
85
VEXT
80
VIN=1.6 V
VIN=2.8 V
VIN=3.6 V
VIN=4.2 V
Vin=5.5V
75
FB
MODE
EN
To/From
System
70
0.0001
GND
0.001
0.01
0.05
0.2 0.5
1
2 3 45
Output Current (A)
效率目标与输出电流间的关系 (VOUT = 3.3V)
典型应用
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFH3
TPS631000
ZHCSP59B – OCTOBER 2021 – REVISED JUNE 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Rating................................................................. 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics ............................................5
7 Detailed Description........................................................6
7.1 Overview.....................................................................6
7.2 Functional Block Diagram...........................................6
7.3 Feature Description ....................................................6
7.4 Device Functional Modes............................................8
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................19
11.1 Device Support .......................................................19
11.2 接收文档更新通知................................................... 19
11.3 支持资源..................................................................19
11.4 Trademarks............................................................. 19
11.5 Electrostatic Discharge Caution..............................19
11.6 术语表..................................................................... 19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2022) to Revision B (June 2022)
Page
•
•
•
Removed reference to PSM............................................................................................................................... 7
Updated 表 8-2 .................................................................................................................................................11
Updated 表 8-6 ................................................................................................................................................ 14
Changes from Revision * (October 2021) to Revision A (January 2022)
Page
•
将文档状态从“预告信息”更改为“量产数据”..........................................................................................................1
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5 Pin Configuration and Functions
VOUT
LX2
1
2
3
4
8
7
6
5
FB
GND
MODE
EN
LX1
VIN
Not to scale
图 5-1. 8-Pin DRL SOT-5X3 Package (Top View)
表 5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
VOUT
LX2
NO.
1
PWR
PWR
PWR
PWR
I
Power stage output
2
Inductor switching node of the boost stage
Inductor switching node of the buck stage
LX1
3
VIN
4
Supply input voltage
EN
5
Device enable. Set High to enable and Low to disable. It must not be left floating.
PFM/PWM selection. Set Low for power save mode, set High for forced PWM. It must not be
left floating.
MODE
6
I
GND
FB
7
8
PWR
I
Power ground
Voltage feedback. Sensing pin
(1) PWR = power, I = input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–40
–65
MAX
UNIT
V
Input voltage (VIN, LX1, LX2, VOUT, EN, FB, MODE)(2)
6
7
VI
Input voltage for less than 10 ns (LX1, LX2)(2)
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal, unless otherwise noted.
6.2 ESD Rating
VALUE
±1000
± 500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged-device model (CDM), per JEDEC specification JS-002, all pins(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature (unless otherwise noted)
MIN
1.6
NOM
MAX
5.5
UNIT
V
VI
Supply voltage
Output voltage
Input capacitance
VO
CI
1.2
5.3
V
VI = 1.6 V to 5.5 V
4.2
µF
µF
µF
µH
1.2 V ≤ VO ≤ 3.6 V, nominal value at VO = 3.3 V
3.6 V < VO ≤ 5.3 V, nominal value at VO = 5 V
10.4
7.95
0.7
16.9
10.6
1
330
330
1.3
CO
Output capacitance
L
Inductance
Operating junction
temperature range
TJ
–40
125
°C
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS631000
THERMAL METRIC(1)
DRL PACKAGE
UNIT
8 PINS
132.7
43.8
27.3
1.2
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
26.6
N/A
RΘJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values
are at VI = 3.8 V, VO = 3.3 V, and TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
ISD
Shutdown current into VIN
VI = 3.8 V, V(EN) = 0 V
TJ = 25°C
0.5
0.15
8
0.9
6.1
μA
μA
μA
V
Quiescent current into VIN
VI = 2.2 V, VO = 3.3 V, V(EN) = 2.2 V, no switching
VI = 2.2 V, VO = 3.3 V, V(EN) = 2.2 V, no switching
IQ
Quiescent current into VOUT
VIT+
Positive-going UVLO threshold voltage
Negative-going UVLO threshold voltage
UVLO threshold voltage hysteresis
Positive-going POR threshold voltage
Negative-going POR threshold voltage
1.5
1.4
1.55
1.45
1.599
1.499
VIT–
During start-up
V
Vhys
99
mV
V
VI(POR)T+
VI(POR)T-
I/O SIGNALS
maximum of VI or VO
1.25
1.22
1.45
1.43
1.65
1.6
V
Positive-going threshold
EN, MODE
VT+
0.77
0.5
0.98
1.2
V
voltage
Negative-going threshold
EN, MODE
VT-
Vhys
IIH
0.66
300
0.76
V
voltage
Hysteresis voltage
EN, MODE
mV
µA
V(EN) = V(MODE) = 1.5 V,
no pullup resistor
High-level input current
(EN, MODE)
±0.01
±0.25
V(EN) = V(MODE) = 0 V,
IIL
Low-level input current
Input bias current
(EN, MODE)
±0.01
±0.01
±0.1
±0.3
µA
µA
IBais
(EN, MODE) V(EN) = 5.5 V
POWER SWITCH
Q1
Q2
45
50
50
85
0.8
mΩ
mΩ
mΩ
mΩ
µA
VI = 3.8 V, VO = 3.3 V,
test current = 0.2 A
rDS(on)
On-state resistance
Q3
Q4
VI = 0 V,
TJ = 25°C
2
IReverse
Reverse current into VOUT
VO = 3.3 V,
V(EN) = 0 V
TJ = –40°C to 125°C
12
µA
CURRENT LIMIT
Output sourcing current
2.6
3
3.35
A
A
IL(PEAK)
Switch peak current limit (1) Q1
VO = 3.3 V
IO falling
Output sinking current, VI =
3.3 V
–0.7
–0.55
–0.45
The output current at PFM mode entry
threshold (peak) current (1)
IPFM_entry
145
500
mA
OUTPUT
CONTROL[FEEDBACK PIN]
VFB
Reference voltage on feedback pin
495
505
mV
PROTECTION FEATURES
Positive-going OVP threshold
voltage
VT+(OVP)
VT+(IVP)
5.55
5.55
5.75
5.75
5.95
5.95
V
V
Positive-going IVP threshold
voltage
TIMING PARAMETERS
Delay between a rising edge on the EN pin
and the start of the output voltage ramp
td(EN)
0.87
1.5
ms
td(ramp)
fSW
Soft-start ramp time
6.42
1.8
7.55
2
8.68
2.2
ms
Switching frequency
MHz
(1) Current limit production test are performed under DC conditions. The current limit in operation will be somewhat higher and depend on
propagation delay and the applied external components.
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7 Detailed Description
7.1 Overview
The TPS631000 is a constant frequency peak current mode control buck-boost converter. The converter uses
a fixed-frequency topology with approximately 2-MHz switching frequency. The modulation scheme has three
clearly defined operation modes where the converter enters with defined thresholds over the full operation range
of VIN and VOUT. The maximum output current is determined by the Q1 peak current limit, which is typically 3 A.
7.2 Functional Block Diagram
L
LX1
LX2
VOUT
VIN
CIN
COUT
Current
Sensor
Gate
Driver
Gate
Driver
Device
Control
Device
Control
VOUT
VIN
VMAX Switch
EN
+
–
Device Control
Power Safe Mode
Protection
FB
+
–
VIN
Ref
500 mV
Gate
Driver
MODE
GND
Current Limit
VOUT
Buck/Boost Control
Soft-Start
LX1, LX2
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The input voltage of the VIN pin is continuously monitored if the device is not in shutdown mode. UVLO only
stops or starts the converter operation. The UVLO does not impact the core logic of the device. UVLO avoids
a brownout of the device during device operation. In case the supply voltage on the VIN pin is lower that the
negative-going threshold of UVLO, the converter stops its operation. To avoid a false disturbance of the power
conversion, the UVLO falling threshold logic signal is digitally de-glitched.
If the supply voltage on the VIN pin recovers to be higher than the UVLO rising threshold, the converter returns
to operation. In this case, the soft-start procedure restarts faster than under start-up without a pre-biased output.
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7.3.2 Enable and Soft Start
EN
A
B
IL(lim_SS)
IL
95%* VOUT_TARGET
VOUT
td(RAMP)
td(EN)
图 7-1. Typical Soft-Start Behavior
When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2 V, the
TPS631000 is enabled and starts up after a short delay time, td(EN)
.
The TPS631000 has an inductor peak current clamp to limit inrush current during start-up. When the minimum
current clamp (IL(lim_SS)) is lower than the current that is necessary to follow the voltage ramp, the current
automatically increases to follow the voltage ramp. The minimum current limit ensures as fast as possible soft
start if the capacitance is chosen lower than what the ramp time td(RAMP) was selected for.
In a typical start-up case as shown in 图 7-1 (low output load, typical output capacitance), the minimum current
clamp limits the inrush current and charges the output capacitor. The output voltage then rises faster than the
reference voltage ramp (see phase A in 图 7-1). To avoid an output overshoot, the current clamp is deactivated
when the output is close to the target voltage and follows the reference voltage ramp slew value given by the
voltage ramp, which is finishing the start up (see phase B in 图 7-1). The transition from the minimum current
clamp operation is sensed by using the threshold 95% × VOUT_TARGET. After phase B, the output voltage is well
regulated to the nominal target voltage. The current waveform depends on the output load and operation mode.
7.3.3 Adjustable Output Voltage
The output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT,
FB, and GND. The feedback voltage is given by VFB. The low-side resistor R2 (between FB and GND) must not
exceed 100 kΩ. The high-side resistor R1 (between FB and VOUT) is calculated by 方程式 1.
R1 = R2 × (VOUT / VFB - 1)
(1)
The typical VFB voltage is 0.5 V.
7.3.4 Mode Selection (PFM/FPWM)
The mode pin is a digital input to enable PFM/FPWM.
When the MODE pin is connected to logic low, the device works in auto PFM mode. The device features a power
save mode to maintain the highest efficiency over the full operating output current range. PFM automatically
changes the converter operation from CCM to pulse frequency modulation.
When the MODE pin is connected to logic high, the device works in forced PWM mode, regardless of the output
current, to achieve minimum output ripple.
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7.3.5 Reverse Current Operation
The device can support reverse current operation (the current flows from VOUT pin to VIN pin). If the output
feedback voltage on the FB pin is higher than the reference voltage, the converter regulation forces a current
into the input capacitor. The reverse current operation is independent of the VIN voltage or VOUT voltage ratio,
hence it is possible on all device operation modes boost, buck, or buck-boost.
7.3.6 Protection Features
The following sections describe the protection features of the device.
7.3.6.1 Input Overvoltage Protection
The TPS631000 has input overvoltage protection. It avoids any damage to the device in case the current flows
from the output to the input and the input source cannot sink current (for example, a diode in the supply path).
If forced PWM mode is active, the current can go negative until it reaches the sink current limit. Once the input
voltage threshold, VT+(IVP), is reached on the VIN pin, the protection disables forced PWM mode and only allows
current to flow from VIN to VOUT. After the input voltage drops under the input voltage protection threshold,
forced PWM mode can be activated again.
7.3.6.2 Output Overvoltage Protection
The TPS631000 has the output overvoltage protection. It avoids any damage to the device in case the external
feedback pin is not working properly.
If the output voltage threshold VT+(OVP) is reach on the VOUT pin, the protection disables converter power stage
and enter a high impedance at the switch nodes.
7.3.6.3 Short Circuit Protection
The device features peak current limit performance at short circuit protection. 图 7-2 shows a typical device
behavior of an short/overload event of the short circuit protection.
VO
IL(PEAK)
IL
图 7-2. Typical Device Behavior During Short Circuit Protection
7.3.6.4 Thermal Shutdown
To avoid thermal damage of the device, the temperature of the die is monitored. The device stops operation
once the sensed temperature rises over the thermal threshold. After the temperature drops below the thermal
shutdown hysteresis, the converter returns to normal operation.
7.4 Device Functional Modes
The device has two functional modes: off and on. The device enters the on mode when the voltage on the VIN
pin is higher than the UVLO threshold and a high logic level is applied to the EN pin. The device enters the off
mode when the voltage on the VIN pin is lower than the UVLO threshold or a low logic level is applied to the EN
pin.
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on
VI > VIT+ &&
EN pin = high
VI < VITœ ||
EN pin = low
off
图 7-3. Device Functional Modes
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS631000 is a high-efficiency, low-quiescent current, buck-boost converter. The device is suitable for
applications needing a regulated output voltage from an input supply that can be higher or lower than the output
voltage.
8.2 Typical Application
L1
1 µH
LX1
VIN
LX2
VI = 1.6 œ 5.5 V
VO = 3.3 V
VOUT
CI
CO
47 µF
22 µF
R1
511 kꢀ
FB
MODE
EN
To/From
System
R2
91 kꢀ
GND
图 8-1. 3.3-VOUT Typical Application
8.2.1 Design Requirements
The design parameters are listed in 表 8-1.
表 8-1. Design Parameters
PARAMETERS
Input voltage
VALUES
2.7 V to 4.3 V
3.3 V
Output voltage
Output current
1.5 A
8.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, 节 6.3 outlines minimum
and maximum values for inductance and capacitance. Tolerance and derating should be taken into account
when selecting nominal inductance and capacitance.
8.2.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the TPS631000 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint or cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
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3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance,
Run thermal simulations to understand the thermal performance of your board,
Export your customized schematic and layout into popular CAD formats,
Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
8.2.2.2 Inductor Selection
The inductor selection is affected by several parameters such as the following:
•
•
•
•
Inductor ripple current
Output voltage ripple
Transition point into power save mode
Efficiency
See 表 8-2 for typical inductors.
For high efficiencies, the inductor should have a low DC resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors,
the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady state operation is calculated using 方程式 3. Only the equation that defines the switch
current in boost mode is shown because this provides the highest value of current and represents the critical
current value for selecting the right inductor.
V
- V
IN
OUT
V
Duty Cycle Boost
D =
OUT
(2)
(3)
Iout
η ´ (1 - D)
Vin ´ D
IPEAK
=
+
2 ´ f ´ L
where:
•
•
•
•
D = duty cycle in boost mode
f = converter switching frequency (typical 2.2 MHz)
L = inductor value
η = estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption)
备注
The calculation must be done for the minimum input voltage in boost mode.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher
than the value calculated using 方程式 3. Possible inductors are listed in 表 8-2.
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表 8-2. List of Recommended Inductors
SIZE
(L × W × H
mm)
INDUCTOR
VALUE [µH]
SATURATION
CURRENT [A]
DCR [mΩ]
PART NUMBER
MANUFACTURER(1)
MuRata
1
1
1
1
4.3
4.2
2.2
2.0
42
43
DFE252012P-1R0M=P2
HTEK20161T-1R0MSR
MAKK2016T1R0M (2)
DFE18SAN1R0ME0 (2)
2.5 × 2.0 ×
1.2
Cyntec
2.0 × 1.6 ×
1.0
75
Taiyo Yuden
Murata
2.0 × 1.6 ×
1.0
144
1.6 × 0.8 ×
0.8
(1) See the Third-Party Products Disclaimer.
(2) This inductor does not support full output current range.
8.2.2.3 Output Capacitor Selection
For the output capacitor, use small ceramic capacitors placed as close as possible to the VOUT and PGND pins
of the IC. The recommended nominal output capacitor value is a single 47 µF. If, for any reason, the application
requires the use of large capacitors that cannot be placed close to the IC, use a smaller ceramic capacitor in
parallel to the large capacitor. The small capacitor should be placed as close as possible to the VOUT and
PGND pins of the IC.
It is important that the effective capacitance is given according to the recommended value in 节 6.3. In general,
consider DC bias effects resulting in less effective capacitance. The choice of the output capacitance is mainly a
tradeoff between size and transient behavior as higher capacitance reduces transient response over/undershoot
and increases transient response time. Possible output capacitors are listed in 表 8-3.
There is no upper limit for the output capacitance value.
表 8-3. List of Recommended Capacitors
CAPACITOR
VALUE [µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER(1)
47
47
6.3
10
10
40
GRM219R60J476ME44
CL10A476MQ8QRN
Murata
Semco
0805 (2012)
0603 (1608)
(1) See the Third-Party Products Disclaimer.
8.2.2.4 Input Capacitor Selection
A 22-µF input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior
of the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN and
PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input supply is
located more than a few inches from the TPS631000, additional bulk capacitance can be required in addition to
the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 µF is a typical choice.
表 8-4. List of Recommended Capacitors
CAPACITOR
VALUE [µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER(1)
22
10
6.3
10
43
40
GRM187R61A226ME15
GRM188R61A106ME69
Murata
Murata
0603 (1608)
0603 (1608)
(1) See the Third-Party Products Disclaimer.
8.2.2.5 Setting the Output Voltage
The output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT,
FB, and GND. The feedback voltage is 500 mV nominal.
The low-side resistor R2 (between FB and GND) should not exceed 100 kΩ. The high-side resistor (between FB
and VOUT) R1 is calculated with 方程式 4.
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æ
ç
è
ö
VOUT
VFB
R1 = R2 ×
- 1
÷
ø
(4)
where
VFB = 500 mV
•
表 8-5. Resistor Selection For Typical Output Voltages
VOUT
R1
365
511
562
806
R2
91
91
91
91
2.5 V
3.3 V
3.6 V
5 V
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8.2.3 Application Curves
3.3
3
100
80
60
40
20
0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
VIN=1.6 V
VIN=2.8 V
VIN=3.6 V
VIN=4.2 V
VIN=5.5 V
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3 45
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Current (A)
Input Voltage (V)
VOUT = 3.3 V
MODE = High
VOUT = 3.3 V
图 8-3. Efficiency vs Output Current (FPWM)
图 8-2. Typical Output Current Capability vs Input Voltage
3.3
100
95
90
85
80
75
3.28
3.26
3.24
VIN=1.6V
VIN=2.8V
VIN=3.6V
VIN=4.2V
VIN=5.5V
VIN=1.6 V
VIN=2.8 V
VIN=3.6 V
VIN=4.2 V
Vin=5.5V
3.22
3.2
0.0001
70
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3 45
0.001
0.01
0.05
0.2 0.5
1
2 3 45
Output Current (A)
Output Current (A)
VOUT = 3.3 V
MODE = High
VOUT = 3.3 V
MODE = Low
图 8-4. Load Regulation (FPWM)
图 8-5. Efficiency vs Input Voltage (PFM)
3.28
3.26
3.24
3.22
3.2
VIN=1.6V
VIN=2.8V
VIN=3.6V
VIN=4.2V
Vin=5.5V
Vout(3.3V o set)
20mV/div
LX1
2.0V/div
LX2
2.0V/div
Inductor Current
500mA/div
Time Scale: 200ns/div
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3 45
Output Current (A)
VIN = 2.7 V, VOUT = 3.3 V
IOUT = 1 A, MODE = Low
VO = 3.3 V
MODE = High
图 8-7. Switching Waveforms, Boost Operation with 1-A Load
图 8-6. Load Regulation (PFM)
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8.2.3 Application Curves (continued)
Vout(3.3V o set)
20mV/div
Vout(3.3V o set)
20mV/div
LX1
2.0V/div
LX1
2.0V/div
LX2
2.0V/div
LX2
2.0V/div
Inductor Current
500mA/div
Inductor Current
500mA/div
Time Scale: 200ns/div
Time Scale: 200ns/div
VIN = 3.3 V, VOUT = 3.3 V
IOUT = 1 A, MODE = Low
VIN = 3.6 V, VOUT = 3.3 V
IOUT = 1 A, MODE = Low
图 8-8. Switching Waveforms with 1-A Load
图 8-9. Switching Waveforms with 1-A Load
Vout(3.3V o set)
20mV/div
Vout(3.3V o set)
20mV/div
LX1
2.0V/div
LX1
2.0V/div
LX2
2.0V/div
LX2
2.0V/div
Inductor Current
500mA/div
Inductor Current
500mA/div
Time Scale: 200ns/div
Time Scale: 2.0ms/div
VIN = 4.3 V, VOUT = 3.3 V
IOUT = 1 A, MODE = Low
VIN = 3.6 V, VOUT = 3.3 V
IOUT = 1 mA, MODE = Low
图 8-10. Switching Waveforms, Buck Operation with 1-A Load
图 8-11. Switching Waveforms at 1-mA Load
EN
2.0V/div
EN
2.0V/div
Vout
2.0V/div
LX1
Vout
2.0V/div
2.0V/div
LX1
2.0V/div
Inductor Current
500mA/div
Inductor Current
500mA/div
Time Scale: 5.0ms/div
Time Scale: 500 s/div
VIN = 3.6 V, VOUT = 3.3 V
Rload = 4 Ω, MODE = Low
VIN = 3.6 V, VOUT = 3.3 V
Rload = 4 Ω, MODE = Low
图 8-12. Start-Up by EN
图 8-13. Shutdown by EN
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8.2.3 Application Curves (continued)
Vout(3.3V o set)
200mV/div
Vout(3.3V o set)
50mV/div
LX1
5.0V/div
LX1
5.0V/div
LX2
5.0V/div
LX2
5.0V/div
Inductor Current
1.0A/div
Inductor Current
1.0A/div
Time Scale: 100 s/div
Time Scale: 5.0ms/div
VIN = 2.7 V, VOUT = 3.3 V
IOUT = 100 mA to 1 A with 20-
µs slew rate
VIN = 2.7 V, VOUT = 3.3 V
IOUT = 100 mA to 1-A sweep
图 8-15. Load Sweep at 2.7-V Input Voltage
图 8-14. Load Transient at 2.7-V Input Voltage
Vout(3.3V o set)
50mV/div
Vout(3.3V o set)
200mV/div
LX1
5.0V/div
LX1
5.0V/div
LX2
5.0V/div
LX2
5.0V/div
Inductor Current
1.0A/div
Inductor Current
1.0A/div
Time Scale: 100 s/div
Time Scale: 5.0ms/div
VIN = 3.6 V, VOUT = 3.3 V
IOUT = 100 mA to 1 A with 20-
µs slew rate
VIN = 3.6 V, VOUT = 3.3 V
IOUT = 100 mA to 1-A sweep
图 8-17. Load Sweep at 3.6-V Input Voltage
图 8-16. Load Transient at 3.6-V Input Voltage
Vout(3.3V o set)
200mV/div
Vout(3.3V o set)
50mV/div
LX1
5.0V/div
LX1
5.0V/div
LX2
5.0V/div
LX2
5.0V/div
Inductor Current
1.0A/div
Inductor Current
1.0A/div
Time Scale: 100 s/div
Time Scale: 5.0ms/div
VIN = 4.3 V, VOUT = 3.3 V
IOUT = 100 mA to 1 A with 20-
µs slew rate
VIN = 4.3 V, VOUT = 3.3 V
IOUT = 100 mA to 1-A sweep
图 8-19. Load Sweep at 4.3-V Input Voltage
图 8-18. Load Transient at 4.3-V Input Voltage
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8.2.3 Application Curves (continued)
Vin
1.0V/div
Vin
1.0V/div
Vout(3.3V o set)
50mV/div
Vout (3.3V o set)
50mV/div
Inductor Current
500mA/div
Inductor Current
500mA/div
Time Scale: 500 s/div
Time Scale: 100ms/div
VIN = 2.7 V to 4.3 V with 20-µs
slew rate, VOUT = 3.3 V
IOUT = 1 A
VIN = 2.7-V to 4.3-V sweep,
VOUT = 3.3 V
IOUT = 1 A
图 8-20. Line Transient at 1-A Load Current
图 8-21. Line Sweep at 1-A Load Current
Vout
2.0V/div
Vout
2.0V/div
LX1
2.0V/div
LX1
2.0V/div
LX2
2.0V/div
LX2
2.0V/div
Inductor Current
1.0A/div
Inductor Current
1.0A/div
Time Scale: 1.0ms/div
Time Scale: 10 s/div
VIN = 3.6 V, VOUT = 3.3 V
IOUT = 1 A, FPWM
VIN = 3.6 V, VOUT = 3.3 V
IOUT = 1 A, FPWM
图 8-22. Output Short Protection (Entry)
图 8-23. Output Short Protection (Recover)
表 8-6. Components for Application Characteristic Curves for VOUT = 3.3 V
REFERENCE
DESCRIPTION(2)
PART NUMBER
MANUFACTURER(1)
Texas Instruments
MuRata
U1
L1
High Power Density 1.5 A Buck-Boost Converter
1.0 µH, 2.5 mm x 2.0 mm, 4.3 A, 42 mΩ
22 µF, 0603, Ceramic Capacitor, ±20%, 6.3 V
47 µF, 0805, Ceramic Capacitor, ±20%, 6.3 V
511 kΩ, 0603 Resistor, 1%, 100 mW
TPS631000
DFE252012P-1R0M=P2
GRM187R61A226ME15
GRM219R60J476ME44
Standard
C1
C2
R1
R2
Murata
Murata
Standard
91 kΩ, 0603 Resistor, 1%, 100 mW
Standard
Standard
(1) See the Third-Party Products Disclaimer.
(2) For other output voltages, refer to 表 8-5 for resistor values.
9 Power Supply Recommendations
The TPS631000 device has no special requirements for its input power supply. The input power supply output
current needs to be rated according to the supply voltage, output voltage, and output current of the TPS631000.
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10 Layout
10.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TPS631000 device.
•
Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Route
wide and direct traces to the input and output capacitors results in low trace resistance and low parasitic
inductance.
•
The sense trace connected to FB is signal trace. Keep these traces away from LX1 and LX2 nodes.
10.2 Layout Example
图 10-1. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 Development Support
11.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the TPS631000 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint or cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance,
Run thermal simulations to understand the thermal performance of your board,
Export your customized schematic and layout into popular CAD formats,
Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS631000DRLR
ACTIVE
SOT-5X3
DRL
8
4000 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2N4W
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS631000DRLR
SOT-5X3
DRL
8
4000
180.0
8.4
2.75
1.9
0.8
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-5X3 DRL
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS631000DRLR
8
4000
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
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EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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