TPS63810 [TI]
可实现动态电压调节且具有 I²C 接口的 2.5A 高效降压/升压转换器;
| 型号： | TPS63810 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 可实现动态电压调节且具有 I²C 接口的 2.5A 高效降压/升压转换器 升压转换器 |
| 文件： | 总44页 (文件大小：1943K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS63810, TPS63811
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
TPS63810 和 TPS63811 - 具有 I2C 接口的 2.5A 降压/升压转换器
1 特性
2 应用
1
•
输入电压范围：2.2V 至 5.5V
•
系统前置稳压器（智能手机、平板电脑、跟踪和远
程信息处理、EPOS、TWS 耳机、医用助听器）
•
•
•
•
输出电压范围：1.8V 至 5.2V
运行和关断期间，I2C 可配置
•
负载点调节（飞行时间摄像头传感器、端口/电缆适
配器和加密狗）
–
–
VSEL 引脚用于在两个输出电压预设之间切换
•
•
热电器件电源（TEC、光纤模块）
输出电流
宽带网络无线电或 SoC 电源（物联网、家庭自动
化、EPOS）
–
–
当 VI ≥ 2.5V、VO = 3.3V 时可达 2.5A
当 VI ≥ 2.8V、VO = 3.5V 时可达 2.5A
在整个负载范围内具有高效率
3 说明
–
–
13μA 低工作静态电流
自动节电模式和强制 PWM 模式（I2C 可配置）
TPS63810 和 TPS63811 是完全可编程（通过 I2C）
的高效率、高输出电流降压/升压转换器。根据输入电
压不同，当输入电压近似等于输出电压时，它们它会自
动以升压、降压或全新的 4 周期降压/升压模式运行。
峰值电流降压/升压模式架构
–
可在降压、降压/升压和升压操作模式之间定义
转换
在定义的阈值内进行模式切换，避免不必要的模式内切
换，以减少输出电压纹波。
–
–
正向和反向电流运行
启动至预偏置输出
两个可通过 I2C 访问的寄存器用于设置输出电
压，VSEL 引脚用于选择哪个输出电压寄存器处于激活
状态。这样，这些器件就能够支持动态电压调节。如果
输出电压寄存器在运行过程中发生了更改或切换了
VSEL 引脚，则器件将以定义的可编程斜坡速率转换运
行模式。
•
安全、可靠运行 特性
–
–
–
–
集成软启动
过热和过压保护
关断期间的真正负载断开
正向和反向电流限制
•
•
两个器件选项
–
–
TPS63810：预编程输出电压（3.3V、3.45V）
TPS63811：启动前的程序输出电压
器件信息(1)
器件型号
TPS63810
TPS63811
封装
封装尺寸（标称值）
解决方案尺寸小于 20 mm2，仅有四个外部器件
DSBGA (15)
2.3mm × 1.4mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
效率与输出电流间的关系
0.47 µH
100
90
80
70
60
50
40
30
VI
2.2 V to 5.5 V
VO
3.3 V
LX1
VIN
LX2
VOUT
EN
10 µF
2 × 22 µF
TPS63810 /
TPS63811
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
20
10
0
SCL
SDA
VSEL
VI = 3.6 V
TA = 25°C
Power-save mode enabled
GND
AGND
0.01
0.1
Output Current (A)
1
3
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEK4
TPS63810, TPS63811
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 17
8.6 Register Map........................................................... 21
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Applications ............................................... 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Switching Characteristics.......................................... 7
7.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
9
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 34
12 器件和文档支持 ..................................................... 35
12.1 器件支持 ............................................................... 35
12.2 文档支持................................................................ 35
12.3 相关链接................................................................ 35
12.4 接收文档更新通知 ................................................. 35
12.5 支持资源................................................................ 35
12.6 商标....................................................................... 35
12.7 术语表 ................................................................... 35
13 机械、封装和可订购信息....................................... 36
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (November 2019) to Revision C
Page
•
•
•
•
Changed the unit in 图 2 ........................................................................................................................................................ 7
Changed "Output Disabled (Hi-Z)" to "Output Discharge Active" in 表 2 ............................................................................ 13
Changed "EN pin is low" to "EN pin is low or the ENABLE bit is set to zero" in the Output Discharge section.................. 17
Changed "TPS63810" to "Start-up value for TPS63810" in bit 5 of Table 3........................................................................ 22
Changes from Revision A (October 2019) to Revision B
Page
•
将产品状态从“预告信息”更改成了“生产数据” .......................................................................................................................... 1
5 器件比较表
器件型号
TPS63810
TPS63811
输出启动状态
已启用
输出电压
VSEL = 低：3.3V
VSEL = 高：3.45V
已禁用
启动时可编程
2
版权 © 2019–2020, Texas Instruments Incorporated
TPS63810, TPS63811
www.ti.com.cn
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
6 Pin Configuration and Functions
YFF Package
15-Ball DSBGA
Top View
1
2
3
A
B
C
D
E
EN
VIN
VIN
VSEL
AGND
SCL
LX1
GND
LX2
LX1
GND
LX2
SDA
VOUT
VOUT
Not to scale
BGA Package (YFF) Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
A1
Device enable. A high logic level on this pin enables the device; a low logic level on this pin
disables the device.
EN
I
A2
A3
VIN
VIN
—
—
Supply voltage for power stage
Supply voltage for power stage
This pin selects which VOUT register is active. When a low logic level is applied to this pin, the
VOUT1 register sets the output voltage. When a high logic level is applied to this pin, the VOUT2
register sets the output voltage.
B1
VSEL
I
B2
B3
C1
C2
C3
D1
D2
D3
E1
E2
E3
LX1
LX1
—
—
—
—
—
I/O
—
—
I/O
—
—
Inductor connection
Inductor connection
AGND
GND
GND
SCL
Analog ground
Power ground
Power ground
I2C serial interface clock. Pull this pin up to the I2C bus voltage with a resistor or a current source.
LX2
Inductor connection
LX2
Inductor connection
SDA
VOUT
VOUT
I2C serial interface data. Pull this pin up to the I2C bus voltage with a resistor or a current source.
Converter output
Converter output
Copyright © 2019–2020, Texas Instruments Incorporated
3
TPS63810, TPS63811
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–3
MAX
UNIT
V
Input voltage (VIN, LX1, LX2, VOUT, SCL, SDA, EN, VSEL)(2)
Input voltage for less than 10 ns (LX1, LX2)(2)
6
9
VI
V
TJ
Operating junction temperature
Storage temperature
–40
–65
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal, unless otherwise noted.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2
1.8
2.025
1.3
0
NOM
MAX
5.5
4.975
5.2
VI
UNIT
VI
Supply voltage
Output voltage
V
Low range
VO
V
High range
VIH
High-level input voltage
Low-level input voltage
Input voltage
SCL, SDA, VSEL
SCL, SDA, VSEL
EN
V
V
V
VIL
0.3
VI
V(EN)
0
VO = 3.3 V, VI ≥ 2.5 V
VO = 3.5 V, VI ≥ 2.5 V
VO = 3.5 V, VI ≥ 2.8 V
VO = 3.3 V, VI ≥ 3 V
2.5
2
IO
Output current(1)
A
2.5
3
CI
CO
L
Input capacitance(2)
Output capacitance(2)
5
13
µF
µF
nH
°C
°C
16
Inductance
390
–40
–40
470
560
85
TA
TJ
Operating free-air temperature range
Operating junction temperature range
125
(1) The device can sustain the maximum recommended output current only for short durations before its junction temperature gets too hot.
Users must verify that the thermal performance of the end application can support the maximum output current.
(2) Effective capacitance after DC bias effects have been considered.
4
Copyright © 2019–2020, Texas Instruments Incorporated
TPS63810, TPS63811
www.ti.com.cn
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
7.4 Thermal Information
TPS63810,
TPS63811
THERMAL METRIC(1)
UNIT
YFF (DSBGA)
15 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
80.5
0.6
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
20.5
0.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
20.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values
are at VI = 3.6 V, VO = 3.3 V and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VI = 3.6 V, VO = 3.3 V, V(EN) = 3.6 V,
not switching, TJ = 25°C
IQ;VIN
Supply current into VIN
Supply current into VIN
Shutdown current into VIN
13
µA
VI = 3.6 V, VO = 0 V, V(EN) = 3.6 V, Output
disabled with ENABLE bit in Control
Register
15
µA
TJ = 25°C
VI = 3.6 V, VO = 0 V, V(EN) = 0 V
TJ = 25°C
ISD
0.35
µA
VIT+
Positive-going UVLO threshold voltage
UVLO threshold voltage hysteresis
2
2.1
2.2
V
Vhys
200
mV
I/O SIGNALS
SCL, SDA,
VSEL
1.2
Positive-going input
threshold voltage
VIT+
V
V
EN
1.07
0.4
1.1
1
1.13
SCL, SDA,
VSEL
Negative-going input
threshold voltage
VIT–
EN
EN
0.97
40
1.03
Vhys
IIH
Hysteresis voltage
mV
µA
V(SCL) = V(SDA) = V(VSEL) = 1.8 V,
no pullup resistor
SCL, SDA,
VSEL
High-level input current
±0.01
±0.01
±0.1
±0.1
V(SCL) = V(SDA) = V(VSEL) = 0 V,
no pullup resistor
SCL, SDA,
VSEL
IIL
Low-level input current
µA
IOL
Low-level output current
Input bias current
SCL, SDA
EN
VOL = 0.4 V
20
mA
µA
IIB
V(EN) = 0 V to 5.5 V
±0.01
±0.1
POWER STAGE
Low range
1.8
2.025
–1.5
4.975
5.2
VO
Output voltage range
V
%
V
High range
PWM operation
PSM operation
VSEL = low
VSEL = high
1.5
Output voltage accuracy
–1.5
3.5
3.3
Default output voltage (RANGE = 0)
3.45
VI = 2.9 V, VO = 3.6 V,
boost operation, output sourcing current
5.2
3.8
6.5
5.2
VI = 4.1 V, VO = 3.3 V,
buck operation, output sourcing current
4.3
Switch current limit
A
A
VI = 5 V, VO = 3.3 V,
reverse-boost operation, output sinking
current
–1.3
–0.35
IT–(PSM)
PSM entry threshold (peak) current
VI = 4.2 V; VO = 3.3 V
0.85
Copyright © 2019–2020, Texas Instruments Incorporated
5
TPS63810, TPS63811
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Electrical Characteristics (continued)
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values
are at VI = 3.6 V, VO = 3.3 V and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output discharge current
VI = 3.6 V, VO ≥ 0.8 V
50
mA
Positive-going power-good threshold
voltage
VT+(PG)
VT–(PG)
95
%
Negative-going power-good
threshold voltage
90
%
V
Positive-going input overvoltage threshold
Reverse current operation
5.7
I2C INTERFACE
7-Bit slave address
75h
THERMAL SHUTDOWN
Thermal shutdown threshold temperature
TJ rising
150
20
°C
°C
Thermal shutdown hysteresis
7.6 Timing Requirements
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
100
UNIT
Standard mode
0
fSCL
SCL clock frequency
Fast mode
0
400
kHz
Fast mode plus
Standard mode
Fast mode
0
1000
4.7
1.3
0.5
4.0
0.6
0.26
4.7
1.3
0.5
4.7
0.6
0.26
4.0
0.6
0.26
250
100
50
tLOW
tHIGH
tBUF
LOW period of the SCL clock
HIGH period of the SCL clock
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
Fast mode plus
Standard mode
Fast mode
Fast mode plus
Standard mode
Fast mode
Bus free time between a STOP and
a START condition
Fast mode plus
Standard mode
Fast mode
Set-up time for a repeated START
condition
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tr
Fast mode plus
Standard mode
Fast mode
Hold time (repeated) START
condition
Fast mode plus
Standard mode
Fast mode
Data set-up time
Data hold time
Fast mode plus
Standard mode
Fast mode
0
0
Fast mode plus
Standard mode
Fast mode
0
1000
300
120
300
300
120
Rise time of both SDA and SCL
signals
20
Fast mode plus
Standard mode
Fast mode
Fall time of both SDA and SCL
signals
tf
20×VDD/5.5
20×VDD/5.5
4.0
Fast mode plus
Standard mode
Fast mode
tsu;STO
Set-up time for STOP condition
0.6
Fast mode plus
0.26
6
Copyright © 2019–2020, Texas Instruments Incorporated
TPS63810, TPS63811
www.ti.com.cn
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
Timing Requirements (continued)
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.45
0.9
UNIT
Standard mode
tVD;DAT
Data valid time
Fast mode
µs
Fast mode plus
Standard mode
Fast mode
0.45
3.45
0.9
tVD;ACK
Data valid acknowledge time
µs
µs
Fast mode plus
Standard mode
Fast mode
0.45
400
400
550
Cb
Capacitive load for each bus line
VSEL pulse duration
Fast mode plus
VSEL = high or low
tw(VSEL)
5
7.7 Switching Characteristics
Over operating junction temperature range and recommended input voltage range (unless otherwise noted). Typical values
are at VI = 3.6 V, VO = 3.3 V, and TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay between a rising edge on the
EN pin and the start of the output
voltage ramp
td(EN)
td(PG)
TJ = 25°C, VI = 3.6 V
229
440
µs
Power-good delay
VO falling
50
±1
µs
SLEW = 00b, forced-PWM operation
SLEW = 01b, forced-PWM operation
SLEW = 10b, forced-PWM operation
SLEW = 11b, forced-PWM operation
±2.5
±5
Slew rate of internal ramp during dynamic
voltage scaling
SR
V/ms
±10
Inductor Switching Frequency, Boost
Mode
VI = 2.3 V, VO = 3.3 V, no Load, PWM
operation
2.6
1.6
2.0
MHz
MHz
MHz
µs
Inductor Switching Frequency, Buck-
Boost Mode
VI = 3.3 V, VO = 3.3 V, no Load, PWM
operation
fSW
Inductor Switching Frequency, Buck
Mode
VI = 4.3 V, VO = 3.3 V, no Load, PWM
operation
Delay between rising edge of VSEL and
start of DVS ramp
Measured from rising edge of VSEL to
start of ramp.
td(VSEL)
5
7.8 Typical Characteristics
1.2
1
20
VI = 2.2 V
VI = 3.6 V
VI = 5.5 V
VI = 2.2 V
VI = 3.6 V
VI = 5.5 V
18
0.8
0.6
0.4
0.2
0
16
14
12
10
8
-0.2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperatur (èC)
EN = LOW
图 2. Shutdown Current versus Temperature
MODE = LOW
VO = 3.3 V
IO = 0 mA, not
switching
图 1. Quiescent Current versus Temperature
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7
TPS63810, TPS63811
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS63810 and TPS63811 devices are high-efficiency buck-boost converters. Each device uses four
switches to maintain synchronous power conversion under all operating conditions, so that the device achieves
high efficiency power conversion over a wide range of input voltages and output currents. The device
automatically switches between buck, boost, and buck-boost operation as required by the operating conditions.
The device operates as a true buck converter when VI > VO and as a true boost converter when VI < VO. When
VI ≈ VO, the device operates in a 4-cycle buck-boost mode. The RMS current through the switches and the
inductor is thus kept to a minimum, minimizing switching and conduction losses. Controlling the switches this way
lets the converter achieve high efficiency over the whole input voltage range.
8.2 Functional Block Diagram
LX1
LX2
Q1
Q4
VIN
VOUT
ISNS
Gate
Drivers
Gate
Drivers
Q2 Q3
PGND
Overvoltage
Protection
VSEL
Control Logic
EN
SCL
SDA
Output
Discharge
Interface
Control
+
ISNS
œ
œ
Current
Comparator
+
Vref
Error
Amplifier
AGND
Clamp
8.3 Feature Description
8.3.1 Control Scheme
The device automatically selects the best switching scheme for the operating conditions. To make sure of stable
operation, the selection logic includes hysteresis (see 图 3).
Boost
Buck-Boost
Buck
VI < VO
VI ≈ VO
VI > VO
Hysteresis
Hysteresis
图 3. Switching Scheme Selection
8
版权 © 2019–2020, Texas Instruments Incorporated
TPS63810, TPS63811
www.ti.com.cn
ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
Feature Description (接下页)
8.3.1.1 Buck Operation
When VI > VO, the device switches like a buck converter:
•
•
•
•
Q1 is the switch.
Q2 is the rectifier.
Q3 is permanently off.
Q4 is permanently on.
See 图 4. During buck operation, one switching cycle comprises two phases: on–off.
I(SNS)
L
Q1
Q4
CI
Q2
Q3
CO
On phase
Off phase
图 4. Buck Switch Configuration
8.3.1.2 Boost Operation
When VI < VO, the device switches like a boost converter:
•
•
•
•
Q1 is permanently on.
Q2 is permanently off.
Q3 is the switch.
Q4 is the rectifier.
See 图 5. During boost operation, one switching cycle comprises two phases: on–off.
I(SNS)
Q1
L
Q4
CI
Q2
Q3
CO
On phase
Off phase
图 5. Boost Switch Configuration
8.3.1.3 Buck-Boost Operation
When VI ≈ VO, all four transistors switch continuously (see 图 6). During buck-boost operation, one switching
cycle comprises four phases: on–commutate–off–commutate.
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Feature Description (接下页)
I(SNS)
Q1
L
Q4
CI
Q2
Q3
CO
On phase
Off phase
Commutate phase
图 6. Buck-Boost Switch Configuration
8.3.2 Control Scheme
The device uses a constant off-time, peak-current-mode control scheme where an outer voltage control loop
generates the demand signal for an inner current control loop. During the on-time, the inner current control loop
monitors the inductor current, and when the inductor current equals the demand signal from the error amplifier,
the on-time stops and the next part of the switching cycle starts.
The off-time is a function of VI and VO and the operating mode (buck, boost, or buck-boost) of the converter.
Inductor
Current
Peak inductor current
during the on time
0
Time
图 7. Peak Current Control (Buck and Boost Operation)
Inductor
Current
Peak inductor current
during the on time
0
Time
图 8. Peak Current Control – Buck-Boost Operation with VI < VO
10
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Feature Description (接下页)
Inductor
Current
Peak inductor current
during the on time
0
Time
图 9. Peak Current Control – Buck-Boost Operation with VI > VO
Inductor
Current
Peak inductor current
during the on time
0
Time
图 10. Peak Current Control – Buck-Boost Operation with VI = VO
During PWM operation, current can flow in the reverse direction (from output to input). In this case, the error
amplifier provides a negative peak current target. Note that the average reverse current is greater (more
negative) than the peak current (see 图 11 and 图 12).
Inductor
Current
Time
0
Peak inductor current
during the on time
Average inductor current
图 11. Reverse Peak Current Control – Buck and Boost Operation
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Feature Description (接下页)
Inductor
Current
Time
0
Peak inductor current
during the on time
Average inductor current
图 12. Reverse Peak Current Control – Buck-Boost Operation, with VI > VO
8.3.3 Power-Save Mode Operation (PSM)
To increase efficiency across a wide range of operating conditions, the device automatically changes from pulse-
width modulation (PWM) at medium and high output currents to pulse-frequency modulation (PFM) at low output
currents.
•
During PWM operation, the device switches continuously and adjusts the duty cycle of each switching cycle
to regulate the output voltage.
•
During PFM operation, the device switches in bursts of a few switching cycles, separated by periods when the
device does not switch (see 图 13). PFM operation increases efficiency at low output currents because when
the device does not switch, there are no switching losses and most of the internal circuitry is disabled, which
reduces quiescent power consumption. A comparator with hysteresis compares the output voltage of the error
amplifier to a predefined PFM threshold voltage. When the output voltage of the error amplifier is greater than
the burst threshold voltage, the device starts switching. When the output voltage of the error amplifier is less
than the burst threshold voltage, the device stops switching. This scheme automatically adjusts the frequency
and the duration of the switching bursts to regulate the output voltage. During PFM operation, the output
voltage ripple can be higher and the transient response is not as good as during PWM operation (see 表 1).
To enable power-save mode, clear the FPWM bit in the Control register to 0.
Converter
output voltage
Output voltage ripple
Burst start threshold
Burst stop threshold
Error amplifier
output voltage
Inductor
current
Time
tBurst
tBurst periodt
tdurationt
图 13. Pulse-Frequency Modulation
WHITESPACE
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表 1. Forced-PWM versus Power-Save Mode
Performance Comparison
PERFORMANCE PARAMETER
BEST OPERATING MODE
Power-Save Mode (PSM)
No difference
Low-power efficiency
Medium- and high-power efficiency
DC Output voltage accuracy
Transient response
Forced-PWM
Forced-PWM
Output voltage ripple
Forced-PWM
WHITESPACE
8.3.4 Forced-PWM Operation (FPWM)
During forced-PWM operation, the device uses PWM for all operating conditions. Forced-PWM operation has
lower output voltage ripple and better transient response than power-save mode operation, but lower efficiency at
low output currents (see 表 1).
Note that the device inhibits forced-PWM operation during start-up (that is, until the converter output has reached
power-good for the first time).
To enable forced-PWM operation, set the FPWM bit in the Control register to 1.
8.3.5 Ramp-PWM Operation (RPWM)
If Ramp-PWM operation is enabled, the device operates in forced-PWM when it ramps from one output voltage
to another during dynamic voltage scaling. This function is useful if you want the device to operate in power-save
mode, but you want to make sure that dynamic voltage scaling ramps the output voltage up and down in a
controlled way. If the device operates in power-save mode and Ramp-PWM is disabled, the device cannot
always control the ramp from a higher output voltage to a lower output voltage, because in power-save mode the
device cannot sink current (see 图 14).
To enable Ramp-PWM operation, set the RAMP bit in the Control register to 1. To disable Ramp-PWM
operation, clear the RAMP bit in the Control register to 0.
VO(2)
Forced-PWM /
Ramp-PWM
VO(1)
VO(2)
Power-Save
Mode
VO(1)
图 14. Ramp-PWM Operation
8.3.6 Device Enable (EN)
The EN pin enables and disables the device.
•
•
When the EN pin is high, the device is enabled.
When the EN pin is low, the device is disabled.
You can also use the ENABLE bit in the Control register to enable and disable the output of the converter (see
the Register Map).
表 2. Device Enable Truth Table
ENABLE PIN (EN)
ENABLE BIT
DEVICE STATE
Device in Shutdown
Programming Interface Active
Device Active
OUTPUT STATE
Output Discharge Active
Output Discharge Active
Output Enabled
0
1
1
X
0
1
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8.3.7 Undervoltage Lockout (UVLO)
The device has an undervoltage lockout function that disables the device when the supply voltage is too low for
correct operation.
8.3.8 Soft Start
To minimize inrush current and output voltage overshoot during start-up, the device has a soft-start function. At
turn on, the switch current limit ramps gradually to its maximum value and the device starts up in a controlled
way. The gradual increase of the current limit generates the smallest inrush current for no-load conditions. It is
also possible to start into a high load as long as the load does not exceed the device current limit.
The rise time of the output voltage changes with the application circuit and the operating conditions. The output
voltage rise time increases if the following occurs:
•
•
•
The output capacitance is large.
The load current is large.
The device operates in boost mode.
See the Application and Implementation section for output voltage rise times in a typical application.
WHITESPACE
EN
VIT
ttr(SS)
t
max
min
0
Peak Inductor
Current Limit
ttd(EN)
t
Inductor
Current
Output
Voltage
图 15. Device Start-Up
8.3.9 Output Voltage Control
The device can generate output voltages from 1.8 V to 5.2 V with a resolution of 25 mV. To set the output
voltage, you must first program the RANGE bit in the Control register to select the output voltage range:
•
•
When RANGE = 0, you can program the output voltage from 1.8 V to 4.975 V.
When RANGE = 1, you can program the output voltage from 2.025 V to 5.2 V.
WHITESPACE
When you have selected the output voltage range, you can program the VOUT1 register and VOUT2 register to
set the output voltage:
•
•
When RANGE = 0, VO = (VOUT[6:0] × 0.025) + 1.8 V
When RANGE = 1, VO = (VOUT[6:0] × 0.025) + 2.025 V
VOUT[6:0] is the 7-bit value in the VOUT1 register or VOUT2 register, whichever is active.
WHITESPACE
The VSEL pin selects which VOUT register is active:
•
•
When VSEL = low, the VOUT1 register sets the output voltage.
When VSEL = high, the VOUT2 register sets the output voltage.
WHITESPACE
14
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注
To prevent output voltage transients, TI recommends that you do not change the output
voltage range while the converter is in operation. Instead, clear the ENABLE bit in the
Control register to 0 to disable the DC/DC converter before you change the RANGE bit.
8.3.9.1 Dynamic Voltage Scaling
The device has a dynamic voltage scaling (DVS) function which lets you change the output voltage in a
controlled way during operation. 图 16 shows a simplified block diagram of the DVS function. The VSEL pin
controls a multiplexer which selects either the VOUT1 register or the VOUT2 register to control the set voltage.
The ramp control block detects when the target output voltage is different from the actual output voltage and
ramps the output voltage to the target voltage in 25-mV steps. You can use the 2-bit SLEW parameter in the
Control register to select one of four slew rates from 0.5 V/ms to 10 V/ms.
The device starts a DVS ramp when you change the logic level on the VSEL pin or program to a new value in
the active VOUT register.
WHITESPACE
VOUT1[6:0]
VOUT2[6:0]
0
1
VOUT[6:0]
VSET[6:0]
Ramp
Control
To rest of
converter
MUX
VSEL
SLEW[1:0]
图 16. Dynamic Voltage Scaling Block Diagram
Note that if you change the contents of the active VOUT register or change the state of the VSEL pin during
start-up (that is, before the end of the soft start), the converter uses the new value immediately and does not
ramp gradually to the final value.
图 17 shows the timing diagram when you use the VSEL pin to change between the output voltage values in the
VOUT1 and VOUT2 registers.
WHITESPACE
td(VSEL)
td(VSEL)
VSEL
tr
tf
VO(2)
VO
VO(1)
+VO(1) œ VO(2)
+
tr = tf =
Where
SR
°
°
°
VO(1) is the output voltage set by the VOUT1 register
VO(2) is the output voltage set by the VOUT2 register
SR is the slew rate set by the SLEW bits in the CONTROL register
图 17. DVS Timing Diagram Using the VSEL Pin
WHITESPACE
图 18 shows the timing diagram when you use the I2C interface to change the output voltage value in one of the
VOUT registers.
WHITESPACE
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VSEL
low
Write 30h
to VOUT1
Write 20h
to VOUT1
I2C
tr
tf
3.0 V
2.6 V
VO
ꢀ
ꢀ
3.0 œ 2.6
tr = tf =
SR
Where SR is the slew rate set by the SLEW bits in the CONTROL register.
图 18. DVS Timing Using the I2C Interface
8.3.10 Protection Functions
8.3.10.1 Input Voltage Protection (IVP)
Under certain operating conditions, current can flow from the output of the device to the input. For example, this
can occur during dynamic voltage scaling when the output ramps down to a lower voltage and the VOUT pin
sinks current from the output capacitor. Under such conditions, if the voltage source supplying the device cannot
sink current, the voltage on the VIN pin can rise uncontrollably.
To make sure the input voltage stays within the permitted range, the device stops switching if the voltage on the
VIN pin is greater than 5.7 V. The device automatically starts to switch again when the voltage on the VIN pin is
less than 5.7 V.
The device sets the PG bit in the Status register when an input overvoltage event occurs. The device clears the
PG bit if the Status register is read when the power-not-good condition no longer exists.
8.3.10.2 Current Limit Mode and Overcurrent Protection
The device has a clamp circuit which limits the peak inductor current in the event of an overload. The exact value
of the output current during an overload changes with the operating conditions (VI and VO) and the switching
mode (buck, buck-boost, or boost) – see 图 52.
Overloads increase the power dissipation in the device, which increases its temperature. If the device becomes
too hot, the thermal shutdown function turns off the converter. When the device cools down, the thermal
shutdown function automatically turns on the converter again. Thus, under a permanent overload condition, the
device can periodically turn on and off, as it cools down and then heats up.
8.3.10.3 Thermal Shutdown
The device has a thermal shutdown function which turns off the converter if the junction temperature is greater
than 150°C. The device automatically turns on the converter again when the junction temperature is less than
130°C. You can still use the I2C interface to read and write to the registers when the device is in an
overtemperature condition.
When the device detects an overtemperature condition, it sets the TSD bit in the Status register to 1. The device
clears the TSD bit to 0 if you read the Status register when the junction temperature of the device is less than
130°C.
8.3.11 Power Good
The device has a power-good function which indicates if the output of the DC/DC converter is in regulation or
not. The device detects a power-good condition when the output voltage is greater than 95% of its nominal value
and detects a power-not-good condition when the output voltage is less than 90% of its nominal value.
When a power-not-good condition occurs, the device sets the PG bit in the Status register to 1. The device clears
the PG bit to 0 if you read the Status register when a power-good condition exists.
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8.3.12 Load Disconnect
During device shutdown, the input is disconnected from the output. This prevents any current flow from the
output to the input or from the input to the output.
8.3.13 Output Discharge
The device actively discharges the output when the EN pin is low or the ENABLE bit is set to zero.
8.4 Device Functional Modes
The device has two functional modes: off and on. The device enters the on mode when the voltage on the VIN
pin is higher than the UVLO threshold and a high logic level is applied to the EN pin. The device enters the off
mode when the voltage on the VIN pin is lower than the UVLO threshold or a low logic level is applied to the EN
pin.
on
VI > VIT+ &&
EN pin = high
VI < VITœ ||
EN pin = low
off
图 19. Device Functional Modes
8.5 Programming
8.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see NXP
Semiconductors, UM10204 – I2C-Bus Specification and User Manual ). The bus consists of a data line (SDA)
and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All
the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA, and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating
the SCL signal and device addresses. The master also generates specific conditions that indicate the START
and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master
device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification:
•
•
•
Standard-mode (100 kbps)
Fast-mode (400 kbps)
Fast-mode Plus (1 Mbps)
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values, depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.1 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, it is referred to as F/S-
mode in this document. The device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7-bit address is 75h (1110101b).
To make sure that the I2C function in the device is correctly reset, it is recommended that the I2C master initiates
a STOP condition on the I2C bus after the initial power up of SDA and SCL pullup voltages.
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Programming (接下页)
8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
The master initiates a data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 20. All I2C-compatible devices recognize a
start condition.
DATA
CLK
S
P
START
STOP
Condition
Condition
图 20. START and STOP Conditions
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit, R/W,
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see 图 21). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see 图 22) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line stable;
data valid
Change of
data allowed
图 21. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see 图 20). This releases the bus and stops the communication link with the
addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
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Programming (接下页)
Data Output by
Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL from
Master
1
2
8
9
S
START
Condition
Clock pulse for
acknowledgment
图 22. Acknowledge on the I2C Bus
P
SDA
SCL
acknowledgement
signal from slave
acknowledgement
signal from receiver
MSB
Sr
S
or
Sr
Sr
or
P
1
2
7
8
9
1
2
3 to 8
9
ACK
ACK
START or
repeated START
condition
byte complete,
interrupt within slave
clock line held low while
interrupts are serviced
STOP or
repeated START
condition
图 23. Bus Protocol
8.5.3 I2C Update Sequence
A single update requires the following:
•
•
•
•
A start condition
A valid I2C slave address
A register address
A data byte
To acknowledge the receipt of each byte, the device pulls the SDA line low during the high period of a single
clock pulse. The device performs an update on the falling edge of the acknowledge signal that follows the last
byte.
WHITESPACE
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Programming (接下页)
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
From master to slave
From slave to master
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
图 24. “Write” Data Transfer Format in Standard, Fast, and Fast-Plus Modes
1
7
1
1
8
1
1
8
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A/A
P
"0" Write
"1" Read
From master to slave
From slave to master
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
图 25. “Read” Data Transfer Format in Standard, Fast, and Fast-Plus Modes
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8.6 Register Map
8.6.1 Register Description
8.6.1.1 Register Map
ADDRESS
0x01
ACRONYM
CONTROL
STATUS
DEVID
REGISTER NAME
SECTION
Go
Control Register
Status Register
DEVID Register
VOUT1 Register
VOUT2 Register
0x02
Go
0x03
Go
0x04
VOUT1
Go
0x05
VOUT2
Go
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8.6.1.2 Register CONTROL (Slave address: 0b1110101; Register address: 0x01; Default: 0x00 or 0x20)
Return to Register Map.
Figure 26. Register CONTROL Format
7
6
5
4
3
2
1
0
RESERVED
R/W
RANGE
R/W
ENABLE
R/W
RESERVED
R/W
FPWM
R/W
RPWM
R/W
SLEW[1:0]
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 3. Register CONTROL Field Descriptions
Bit Field
Type Reset
Description
7
6
5
4
3
2
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
Reserved for future use.
This bit can be written to and read from but it has no function. For compatibility with
possible future device variants, it is recommended to program this bit to 0.
RANGE
ENABLE
RESERVED
FPWM
0
This bit selects the output voltage range.
0: Low range (1.800 V to 4.975 V)
1 : High range (2.025 V to 5.200 V)
X
0
This bit controls operation of the converter.
0 : Converter operation disabled (Start-up value for TPS63811)
1 : Converter operation enabled (Start-up value for TPS63810)
Reserved for future use.
This bit can be written to and read from but it has no function. For compatibility with
possible future device variants, it is recommended to program this bit to 0.
0
This bit controls the forced-PWM function.
0: Forced-PWM operation disabled
1 : Forced-PWM operation enabled
RPWM
0
This bit controls the ramp-PWM function.
0: Ramp-PWM operation disabled
1 : Ramp-PWM operation enabled
1:0 SLEW[1:0]
00
These bits control the slew rate of the DVS function.
00: 1.0 V/ms
01: 2.5 V/ms
10: 5.0 V/ms
11: 10.0 V/ms
8.6.1.3 Register STATUS (Slave address: 0b1110101; Register address: 0x02; Default: 0x00)
Return to Register Map.
Figure 27. Register STATUS Format
7
6
5
4
3
2
1
TSD
R
0
PGn
R
NIL[5:0]
R
LEGEND: R/W = Read/Write; R = Read only
Table 4. Register STATUS Field Descriptions
Bit Field
Type Reset
Description
7:2 NIL[5:0]
R
000000
Not used.
These bits always return 0 when read.
1
TSD
R
0
This bit shows the status of the thermal shutdown function.
This bit is cleared if the STATUS register is read when the overtemperature condition
no longer exists.
0: Temperature good
1 : An overtemperature event was detected.
0
PGn
R
0
This bit shows the status of the power-good comparator.
This bit is cleared if the STATUS register is read when the power-not-good condition no
longer exists.
0: Power-good
1 : A power-not-good event was detected.
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8.6.1.4 Register DEVID (Slave address: 0b1110101; Register address: 0x03; Default: 0x04)
Return to Register Map.
Figure 28. Register DEVID Format
7
6
5
4
3
2
1
0
MANUFACTURER[3:0]
R
MAJOR[1:0]
R
MINOR[1:0]
R
LEGEND: R/W = Read/Write; R = Read only
Table 5. Register DEVID Field Descriptions
Bit Field
Type Reset
Description
7:4 MANUFACTURER[3:0]
R
0000
These bits identify the device manufacturer.
0000: Texas Instruments
3:2 MAJOR[1:0]
R
01
These bits identify the major silicon revision.
00: A (initial silicon)
01: B (first major revision)
10: C (second major revision)
11: D (third major revision)
1:0 MINOR[1:0]
R
00
These bits identify the minor silicon revision.
00: 0 (initial silicon)
01: 1 (first minor revision)
10: 2 (second minor revision)
11: 3 (third minor revision)
8.6.1.5 Register VOUT1 (Slave address: 0b1110101; Register address: 0x04; Default: 0x3C)
Return to Register Map.
Figure 29. Register VOUT1 Format
7
NIL
R
6
5
4
3
2
1
0
VOUT1[6:0]
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 6. Register VOUT1 Field Descriptions
Bit Field
NIL
Type Reset
Description
7
R
0
Not used
This bit always returns 0 when read.
6:0 VOUT1[6:0]
R/W
0111100
These bits set the output voltage when the VSEL pin is low.
Output voltage = 1.800 + (VOUT1[6 :0] × 0.025) V (low range) (default = 3.3 V)
Output voltage = 2.025 + (VOUT1[6 :0] × 0.025) V (high range) (default = 3.525 V)
8.6.1.6 Register VOUT2 (Slave address: 0b1110101; Register address: 0x05; Default: 0x42)
Back to Register Map.
Figure 30. Register VOUT2 Format
7
NIL
R
6
5
4
3
2
1
0
VOUT2[6:0]
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 7. Register VOUT2 Field Descriptions
Bit Field
NIL
Type Reset
Description
7
R
0
Not used
This bit always returns 0 when read.
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Table 7. Register VOUT2 Field Descriptions (continued)
Bit Field
Type Reset
R/W 1000010
Description
6:0 VOUT2[6:0]
These bits set the output voltage when the VSEL pin is high.
Output voltage = 1.800 + (VOUT2[6 :0] × 0.025) V (low range) (default = 3.45 V)
Output voltage = 2.025 + (VOUT2[6 :0] × 0.025) V (high range) (default = 3.675 V)
24
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS63810 and TPS63811 devices are high efficiency, high current buck-boost converters, suitable for
applications where the input voltage is higher, lower, or equal to the output voltage. The maximum peak current
in the switches is limited to a typical value of 6 A.
9.2 Typical Applications
9.2.1 1.8-V to 5.2-V Output Smartphone Power Supply
L1
0.47 µH
VI
2.5 V to 4.8 V
VO
1.8 V to 5.2 V
L1
VIN
L2
VOUT
EN
C1
10 µF
C2
22 µF
C3
22 µF
C4
22 µF
3.3 V
TPS63810 /
TPS63811
3.3 kΩ 3.3 kΩ
SCL
SDA
To system
VSEL
GND
AGND
图 31. Typical Application Schematic
9.2.1.1 Design Requirements
This example uses the design parameters listed in 表 8.
表 8. Design Parameters
DESIGN PARAMETER
Input voltage
SYMBOL
EXAMPLE VALUE
2.5 V to 4.8 V
1.8 V to 5.2 V
2 A
VI
VO
Output voltage
Output current
IO
I2C bus voltage
I2C bus capacitance
I2C bus speed
VBUS
Cb
3.3 V
100 pF
Fast-mode (400 kHz)
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Input Capacitor Selection
TI recommends a minimum input capacitance (including DC bias effects) of 5 µF. A 10-µF, 10-V ceramic
capacitor is suitable for typical applications. If the input supply is located more than a few centimeters from the
converter, you may need to add additional bulk capacitance (a 47-µF electrolytic or tantalum capacitor is a typical
choice).
The output capacitance does not have an upper limit; you can make it as big as you want.
9.2.1.2.2 Inductor Selection
TI recommends you use the TPS63810 device with 0.47-µH inductors. For high efficiencies, use an inductor with
a low DC resistance (DCR) and low core losses.
The saturation current of the inductor must be greater than the maximum inductor current in your application. To
include sufficient margin for worst-case and transient operating conditions, TI recommends you use an inductor
with saturation current that is at least 20% higher than the maximum inductor current in your application. The
maximum current in the inductor occurs when the device operates in boost mode and the following is true:
•
•
•
The input voltage is at its minimum value.
The output voltage is at its maximum value.
The output current is at its maximum value.
To calculate the maximum inductor current, first use 公式 1 to calculate the maximum duty cycle during boost
operation (which is when the maximum inductor current occurs).
WHITESPACE
VO œ VI
D =
VO
where
•
•
•
D is the duty cycle
VI is the input voltage
VO is the output voltage
(1)
WHITESPACE
5 V œ 2.5 V
D =
= 0.5
5 V
WHITESPACE
Next, use 公式 2 to calculate the maximum inductor current.
IO
DVI
ILM
=
+
:
;
ꢀ 1 œ D
2fL
where
•
•
•
•
•
•
•
ILM is the peak inductor current
IO is the output current
η is the converter efficiency (use the value from the application curves or assume 90%)
D is the duty cycle (calculated with 公式 1)
VI is the input voltage
f is the switching frequency (assume 2 MHz)
L is the inductance (use 0.47 µH)
(2)
WHITESPACE
:
;: ;
0.5 2.5 V
2 A
;:
ILM
=
+
= 5.1 A
:
;
: ;:
;: ;
0.9 1 œ 0.5
2 2 MHz 0.47 ꢀH
WHITESPACE
26
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To include enough margin for transient conditions, TI recommends you use an inductor with a saturation current
rating at least 20% higher than the calculated maximum current. In this example, TI recommends an inductor
with a saturation current of at least 6.1 A.
9.2.1.2.3 Output Capacitor Selection
TI recommends a minimum output capacitance (including DC bias effects) of 16 µF. Two 22-µF, 10-V ceramic
capacitors are suitable for typical applications with VO ≤ 3.6 V. For VO > 3.6 V, three 22-µF or two 47-µF ceramic
capacitors are suitable. If you want to minimize switching noise on the output, connect a small ceramic capacitor
(100 nF is a typical value) in parallel to the two main output capacitors and place it closest to the VOUT pin.
Smaller capacitors have lower parasitic inductance and are more effective at filtering high frequencies than the
two main output capacitors.
The output capacitance does not have an upper limit, however, very large values of output capacitance make the
transient response of the converter slower.
It is important that the effective capacitance is given according to the recommended value in Recommended
Operating Conditions. In general, consider DC bias effects resulting in less effective capacitance. The choice of
the output capacitance is mainly a trade-off between size and transient behavior as higher capacitance reduces
transient response overshoot and undershoot and increases transient response time. 表 9 lists possible output
capacitors.
表 9. List of Recommended Capacitors(1)
CAPACITOR
[µF]
SIZE
(METRIC)
VOLTAGE RATING [V]
ESR [mΩ]
PART NUMBER
MANUFACTURER
22
22
47
47
6.3
10
10
40
43
43
GRM187R60J226ME15
GRM187R61A226ME15
GRM188R60J476ME15
GRM219R60J476ME44
Murata
Murata
Murata
Murata
0603 (1608)
0603 (1608)
0603 (1608)
0805 (2012)
6.3
6.3
(1) See Third-party Products Disclaimer.
9.2.1.2.4 I2C Pullup Resistor Selection
Refer to the NXP Semiconductors, UM10204 – I2C-Bus Specification and User Manual for the specifications
relevant to your application.
Use 公式 3 to calculate the maximum permitted pullup resistor value for the bus speed used in the application.
WHITESPACE
tr
: ;
RP max =
0.8473 × Cb
where
•
•
tr is the maximum permitted rise time (300 ns for Fast-mode)
Cb is the capacitive load on each bus line
(3)
WHITESPACE
300 ns
: ;
RP max =
= 3.541 kꢀ
0.8473 × 100 pF
WHITESPACE
If you do not know what the bus capacitance is in your application, start with a 1-kΩ pullup resistor and measure
the rise time with an oscilloscope. Use 公式 3 to calculate the bus capacitance and thus the maximum permitted
pullup resistor.
Use 公式 4 to calculate the minimum permitted pullup resistor value for different bus speeds.
WHITESPACE
VBUS œ VOL
: ;
RP min =
IOL
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where
•
•
•
VBUS is the I2C bus pullup voltage
VOL is the low-level output voltage (0.4 V)
IOL is the low-level output current (3 mA for Fast-mode)
(4)
WHITESPACE
3.3 V œ 0.4 V
: ;
RP min =
= 967 ꢀ
3 mA
WHITESPACE
A pullup resistor value of 3.3 kΩ meets both of these requirements.
28
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9.2.1.3 Application Curves
表 10 lists the components that were used for the measurements contained in the following pages.
表 10. Components for Application Characteristic Curves
REFERENCE
DESCRIPTION
Capacitor, 10 µF, 10 V, 0603, ceramic
Capacitor, 22 µF, 10 V, 0603, ceramic
Inductor, 0.47 µH
PART NUMBER
GRM188R61A106ME69
GRM187R61A226ME15
XFL4015-471MEC
MANUFACTURER
Murata
C1
C2, C3
L1
Murata
Coilcraft
U1
Integrated circuit
TPS63810YFF
Texas Instruments
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WHITESPACE
100
90
80
70
60
50
40
100
90
80
70
60
50
40
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.01
0.1
Output Current (A)
1
2.5
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
VI = 3.6 V
PSM
TA = 25°C
IO = 1 A
PSM
TA = 25°C
图 32. Efficiency versus Output Current
图 33. Efficiency versus Input Voltage
0.3
0.15
0
0.3
0.15
0
-0.15
-0.3
-0.45
-0.6
-0.15
-0.3
-0.45
-0.6
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0
0.5
1 1.5
Output Current (A)
2
2.5
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
VI = 3.6 V
FPWM
TA = 25°C
IO = 1 A
FPWM
TA = 25°C
图 34. Load Regulation
图 35. Line Regulation
tV(LX1) (2 V/div)t
tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tV(LX2) (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 2 µs/divt
tTime = 2 µs/divt
VI = 5 V
PSM
TA = 25°C
VI = 3.3 V
VO = 3.3 V
PSM
TA = 25°C
VO = 3.3 V
IO = 100 mA
IO = 100 mA
图 36. PFM Switching Waveforms
图 37. PFM Switching Waveforms
(Buck Operation)
(Buck-Boost Operation)
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tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 2 µs/divt
tTime = 400 ns/divt
VI = 2.5 V
VO = 3.3 V
PSM
TA = 25°C
VI = 5 V
FPWM
TA = 25°C
IO = 100 mA
VO = 3.3 V
IO = 100 mA
图 38. PFM Switching Waveforms
图 39. PWM Switching Waveforms
(Boost Operation)
(Buck Operation)
tV(LX1) (2 V/div)t
tV(LX1) (2 V/div)t
tV(LX2) (2 V/div)t
tV(LX2) (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 400 ns/divt
tTime = 400 ns/divt
VI = 3.3 V
VO = 3.3 V
FPWM
TA = 25°C
VI = 2.5 V
VO = 3.3 V
FPWM
TA = 25°C
IO = 100 mA
IO = 100 mA
图 40. PWM Switching Waveforms
图 41. PWM Switching Waveforms
(Buck-Boost Operation)
(Boost Operation)
tVO (200 mV/div, ac)t
tVO (200 mV/div, ac)t
tVI (2 V/div)t
tIL (2 A/div)t
tVI (2 V/div)t
tIL (2 A/div)t
tTime = 200 µs/divt
tTime = 200 µs/divt
VI = 2.5 V to 5.5 V
VO = 3.3 V
PSM
TA = 25°C
VI = 2.5 V to 5.5 V
VO = 3.3 V
PSM
TA = 25°C
IO = 200 mA
IO = 2 A
图 42. Line Transient Response
图 43. Line Transient Response
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tVO (200 mV/div, ac)t
tVO (200 mV/div, ac)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 200 µs/divt
tTime = 200 µs/divt
VI = 4.2 V
VO = 3.3 V
PSM
TA = 25°C
VI = 3.3 V
VO = 3.3 V
PSM
TA = 25°C
IO = 10 mA to 2 A
IO = 10 mA to 2 A
图 44. Load Transient Response (Buck)
图 45. Load Transient Response (Buck-Boost)
tVI (1 V/div, ac)t
tVO (200 mV/div, ac)t
tVO (1 V/div, ac)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 200 µs/divt
tTime = 200 µs/divt
VI = 2.6 V
VO = 3.3 V
PSM
TA = 25°C
VI = 3.3 V ±0.9 V
VO = 3.3 V
FPWM
TA = 25°C
IO = 10 mA to 2 A
RL = 3 Ω
图 46. Load Transient Response (Boost)
图 47. Line Sweep (PWM)
tVI (2 V/div)t
tVO (2 V/div)t
tIL (1 A/div)t
tVI (2 V/div)t
tVO (2 V/div)t
tIL (1 A/div)t
tTime = 40 µs/divt
tTime = 40 µs/divt
VI = 3.6 V
VO = 3.3 V
PSM
TA = 25°C
VI = 3.6 V
VO = 3.3 V
PSM
TA = 25°C
RL = 33 Ω
RL = 3.3 Ω
图 48. Start-Up Waveforms
图 49. Start-Up Waveforms
(Light Load)
(Heavy Load)
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tVO (2 V/div)t
tVO (2 V/div)t
tIL (1 A/div)t
tIL (1 A/div)t
tTime = 4 ms/divt
tTime = 4 ms/divt
VI = 3.6 V
PSM
TA = 25°C
VI = 3.6 V
PSM
TA = 25°C
VO = 2 V to 4 V
RL = 330 Ω
VO = 2 V to 4 V
RPWM
RL = 330 Ω
图 50. Dynamic Voltage Scaling (PFM)
图 51. Dynamic Voltage Scaling (RPWM)
3.5
3
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
tIL (5 A/div)t
2.5
2
tIO (2 A/div)t
tVO (2 V/div, ac)t
1.5
1
tTime = 40 µs/divt
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
VI = 3.6 V
VO = 3.3 V
PSM
TA = 25°C
IO = 1 A
VI rising
FPWM
TA = 25°C
图 52. Overcurrent Protection
图 53. Switching Frequency versus Input Voltage
0.5
0.1
6
5
4
3
2
1
0
0.01
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
VO = 1.8 V
VO = 3.3 V
VO = 5.2 V
0.001
0.005 0.01
0.1
Output Current (A)
1
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
VI = 3.6 V
PSM
TA = 25°C
PSM
TA = 25°C
图 54. Burst Switching Frequency versus Output Current
图 55. Maximum Output Current versus Input Voltage
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10 Power Supply Recommendations
The device is designed to operate with a DC supply voltage in the range 2.2 V to 5.5 V. If the input supply is
more than a few centimeters from the device, TI recommends adding some bulk capacitance to the ceramic
bypass capacitors. A 47-µF electrolytic capacitor is a typical selection for the bulk capacitance.
11 Layout
11.1 Layout Guidelines
Correct PCB layout is necessary to obtain the full performance from the device. TI recommends to follow these
basic principles:
•
•
Place input and output capacitors close to the device to minimize the input and output loop areas.
If you combine different-sized capacitors to make up the total input capacitance, place the smallest capacitor
closest to the device. The same applies to the output capacitance.
•
•
Keep PCB traces short and wide to minimize parasitic resistance and inductance.
Use the following PCB layer stack (or something similar):
–
–
–
–
Layer 1 (top): All components and all power traces
Layer 2 (inner): Signals
Layer 3 (inner): Signals
Layer 4 (bottom): Ground plane
图 56 shows an example of the PCB layout used for all of the measurement data in Application Curves.
11.2 Layout Example
Input
Capacitance
Output
Capacitance
TPS63810 /
TPS63811
图 56. Recommended PCB Layout for the TPS63810 Device
34
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ZHCSKE6C –JULY 2019–REVISED FEBRUARY 2020
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
NXP 半导体，《UM10204 - I2C 总线规范和用户手册》
德州仪器 (TI)，《TPS63810 EVM 用户指南》
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 11. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具和软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TPS63810
TPS63811
12.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 术语表
SLYZ022 - TI 术语表
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
36
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS63810YFFR
TPS63811YFFR
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
15
15
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TPS63810
TPS63811
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS63810YFFR
TPS63811YFFR
DSBGA
DSBGA
YFF
YFF
15
15
3000
3000
180.0
180.0
8.4
8.4
1.5
1.5
2.42
2.42
0.75
0.75
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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24-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS63810YFFR
TPS63811YFFR
DSBGA
DSBGA
YFF
YFF
15
15
3000
3000
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0015
DSBGA - 0.625 mm max height
S
C
A
L
E
6
.
0
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
0.8 TYP
SYMM
E
D
C
1.6
D: Max = 2.285 mm, Min =2.225 mm
E: Max = 1.374 mm, Min =1.314 mm
TYP
SYMM
B
A
0.4 TYP
0.3
3
1
2
15X
0.2
0.015
C A B
0.4
TYP
4219378/B 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
15X ( 0.23)
(0.4) TYP
2
3
1
A
B
C
SYMM
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219378/B 05/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
3
15X ( 0.25)
1
2
A
B
(0.4) TYP
METAL
TYP
SYMM
C
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219378/B 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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