TPS650002TRTETQ1 [TI]
具有双 LDO 和 SVS 电源管理 IC (PMIC) 的 2.25MHz 降压转换器 | RTE | 16 | -40 to 105;
| 型号： | TPS650002TRTETQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双 LDO 和 SVS 电源管理 IC (PMIC) 的 2.25MHz 降压转换器 | RTE | 16 | -40 to 105 集成电源管理电路 转换器 |
| 文件： | 总26页 (文件大小：2441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS650002-Q1
ZHCSJN8 –APRIL 2019
TPS650002-Q1 具有双路 LDO 的 2.25MHz 降压转换器
1 特性
3 说明
1
•
•
适用于汽车 应用
具有符合 AEC-Q100 标准的下列特性：
器件温度等级 2：-40°C 至 +105°C，TA
降压转换器：
TPS650002-Q1 器件是一款适合汽车应用的单芯片 电
源管理 IC (PMIC)。这个器件包含一个带有两个低压降
稳压器的单个降压转换器。为了在最大可能的负载电流
范围内实现最大效率，这个降压转换器在轻负载时进入
低功耗模式。对于低噪声 应用，该器件可通过 MODE
引脚强制进入固定频率 PWM。此降压转换器允许使用
小型电感器和电容器，因此可实现较小的解决方案尺
寸。电源正常状态输出可用于排序。LDO 可提供
300mA 的电流，并且可在 1.6V 至 6V 的输入电压范围
内工作，因此可由降压转换器供电。该降压转换器和
LDO 具有独立电压输入和使能端，从而实现了设计和
排序的灵活性。
–
•
•
•
–
–
–
输入电压范围为 2.3V 至 6V
2.25MHz 固定频率运行
600mA 输出电流
LDO：
–
–
–
VIN 范围从 1.6V 至 6V
高达 300mA 的输出电流
独立电源输入和使能端
3mm × 3mm 16 引脚 WQFN
TPS650002-Q1该器件采用 16 引脚无引线封装 (3mm
× 3mm WQFN)。
2 应用
•
•
•
•
汽车摄像头模块
器件信息(1)
汽车信息娱乐系统
汽车仪表组
器件型号
封装
封装尺寸（标称值）
TPS650002-Q1
WQFN (16)
3.00mm × 3.00mm
汽车传感器融合
(1) 如需了解所有可用封装，请参阅数据表书末尾的可订购产品附
录。
典型应用原理图
TI Device
2.2 µH
VDCDC
1.8 V
EN_DCDC
SW
FB_DCDC
VIN
VINDCDC
MODE
10 …F
A
10 …F
P
P
470 kꢀ
VIN
PG
VIN
EN_LDO1
VINLDO1
VLDO1
2.8 V
VLDO1
2.2 …F
FB_LDO1
10 …F
P
P
P
P
VIN
EN_LDO2
VINLDO2
VLDO2
1.2 V
VLDO2
2.2 …F
FB_LDO2
10 …F
AGND
PGND
A
P
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEW4
TPS650002-Q1
ZHCSJN8 –APRIL 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Examples................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 器件支持................................................................ 19
11.2 文档支持................................................................ 19
11.3 接收文档更新通知 ................................................. 19
11.4 社区资源................................................................ 19
11.5 商标....................................................................... 19
11.6 静电放电警告......................................................... 19
11.7 术语表 ................................................................... 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
4 月2019
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
TPS650002-Q1
www.ti.com.cn
ZHCSJN8 –APRIL 2019
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
16
15
14
13
EN_LDO1
EN_LDO2
PG
1
2
3
4
12
11
10
9
VLDO1
FB_LDO1
AGND
Exposed Thermal Pad
PGND
FB_DCDC
5
6
7
8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
10
8
AGND
—
I
Analog ground – Star back to PGND as close to the IC as possible
Enable DC-DC converter
EN_DCDC
EN_LDO1
EN_LDO2
FB_DCDC
FB_LDO1
FB_LDO2
MODE
1
I
Enable LDO1
2
I
Enable LDO2
9
I
Voltage to DC-DC error amplifier
Voltage to LDO1 error amplifier
Voltage to LDO2 error amplifier
Selects forced-PWM or PWM-to-PFM automatic-transition mode
Open-drain active-low power-good output
Power ground – connected to the thermal pad
Switch pin – connect inductor here
Input voltage to DC-DC converter and all other control blocks
Input voltage to LDO1
11
14
7
I
I
I
PG
3
O
—
O
I
PGND
4
SW
5
VINDCDC
VINLDO1
VINLDO2
VLDO1
VLDO2
EP
6
13
16
12
15
I
I
Input voltage to LDO2
O
O
—
LDO1 output voltage
LDO2 output voltage
Exposed thermal pad
Copyright © 2019, Texas Instruments Incorporated
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ZHCSJN8 –APRIL 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
On all pins except AGND, PGND, EN_DCDC, FB_LDO1, FB_LDO2,
pins with respect to AGND
–0.3
7
Input voltage
V
On EN_DCDC with respect to AGND
–0.3
-0.3
–0.3
-0.3
-0.6
-2
VIN + 0.3, ≤ 7
FB_LDO1, FB_LDO2
Output voltage On VLDO1, VLDO2,
Output voltage /PG
3.6
3.6
7
V
V
Output voltage SW
7
V
Output voltage SW for 20ns transients
VINDCDC, SW, PGND,
10
V
1800
800
1
mA
mA
mA
°C
°C
°C
Current
VINLDO1, VINLDO2, VLDO1, VLDO1, AGND
At all other pins
Operating free-air temperature, TA
Maximum junction temperature, TJ
Storage temperature, Tstg
–40
–65
105
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
Electrostatic
discharge
Corner pins (1, 4, 5, 8, 9, 12, 13,
and 16)
V(ESD)
±750
±500
V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Other pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VINDCDC
2.3
6.0
V
V
V
VINLDO1,
VINLDO2
1.6
0
VINDCDC
VINDCDC
MODE
EN_DCDC
,
EN_LDO1,
EN_LDO2
0
VINDCDC
3.3
V
L1
SW pin inductor
1.5
10
2.2
μH
μF
Input capacitor at VINDCDC
Input capacitor at VINLDO1, VINLDO2
Output capacitor for VDCDC
Output capacitor for LDO1, LDO2
DC-DC converter output current
LDO1 output current
CI
2.2
10
μF
22
μF
CO
2.2
μF
600
300
300
105
mA
mA
mA
°C
IO
LDO2 output current
TA
Operating ambient temperature
–40
4
Copyright © 2019, Texas Instruments Incorporated
TPS650002-Q1
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ZHCSJN8 –APRIL 2019
6.4 Thermal Information
TPS650002-Q1s
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
46.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
56.1
19.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.1
ψJB
19.1
RθJC(bot)
5.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER
OPERATING VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage for VINDCDC of DC-
DC converter
2.3
6
V
VIN
(1)
(1)
Input voltage for LDO1 (VINLDO1) See
Input voltage for LDO2 (VINLDO2) See
Internal undervoltage (UVLO)
1.6
1.6
6
6
V
V
VCC falling
1.72
1.77
160
1.82
V
lockout threshold
Internal undervoltage (UVLO)
lockout hysteresis
mV
SUPPLY CURRENT
MODE low, EN_DCDC high,
EN_LDO1, EN_LDO2 low,
IOUT = 0 mA and no switching
23
50
32
57
μA
MODE low, EN_DCDC low,
EN_LDO1, EN_LDO2 high, IOUT = 0 mA
IOUT = 0 mA and no switching
IQ
Operating quiescent current
EN_DCDC high, MODE high,
EN_LDO1, EN_LDO2 low, IOUT = 0 mA
4
mA
ISD
Shutdown Current
EN_DCDC low EN_LDO1 and EN_LDO2 low
0.16
2.2
μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG
VIH
VIL
High-level input voltage
Low-level input voltage
Low-level output voltage
1.2
V
V
V
0.4
0.4
VOL
PG pins only, IO = –100 μA
MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to
GND or VINDCDC,
Ilkg
Input leakage current
0.01
2.25
0.1
μA
OSCILLATOR
fSW
Oscillator frequency
2.01
2.41
MHz
STEP-DOWN CONVERTER POWER SWITCH
High-side MOSFET ON-resistance VINDCDC = VGS = 3.6 V
Low-side MOSFET ON-resistance VINDCDC = VGS = 3.6 V
240
185
480
380
300
600
mΩ
mΩ
rDS(on)
2.3 V ≤ VINDCDC ≤ 2.5 V
2.5 V ≤ VINDCDC ≤ 6 V
IO
DC output current
mA
mA
Forward current limit, PMOS and
NMOS
ILIMF
2.3 V ≤ VINDCDC ≤ 6 V
800
1000
1400
(1) The design principle allows only VINDCDC to be the highest supply in the system. If separate input voltage supplies are used for the
DC-DC converter and LDOs, then choose VINDCDC ≥ VINLDO1 and VINDCDC ≥ VINLDO2.
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Electrical Characteristics (continued)
Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STEP-DOWN CONVERTER POWER SWITCH (continued)
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
150
30
°C
°C
TSD
Thermal shutdown hysteresis
STEP-DOWN CONVERTER OUTPUT VOLTAGE
VDCDC
Fixed output voltage, VDCDC
1.825
V
Output-voltage DC accuracy (PWM MODE = high,
-1.5%
+1.5%
mode)(2)
2.3 ≤ VINDCDC ≤ 6 V
VDCDC
Output-voltage DC accuracy (PFM MODE low
1%
0.5
mode)
+1% voltage positioning active
Load regulation (PWM mode)
MODE high
%/A
Internal discharge resistance at
SW
RDIS
EN_DCDC low
450
Ω
LOW-DROPOUT REGULATORS
VI
Input voltage for LDOx (VINLDOx)
1.6
6
V
V
Fixed output voltage, LDO1
(VLDO1)(3)
VLDO1
2.8
1.2
Fixed output voltage, LDO2
(VLDO2)(3)
VLDO2
IO
V
Continuous-pass FET current
300
825
825
370
370
mA
2.3 V ≤ VINLDOx
340
210
ISC
Short-circuit current limit
mA
VINLDOx < 2.3 V
VINLDOx ≥ 2.3 V, IOUT = 250 mA
VINLDOx < 2.3 V, IOUT = 175 mA
mV
mV
(4)
VDO
Dropout voltage
IO = 1 mA to 300 mA, VINLDOx = 2.3 V–6 V,
VLDOx = 1.2 V
–3.5%
–3.5%
–1.5%
–0.5%
3.5%
3.5%
1.5%
0.5%
Output voltage accuracy
IO = 1 mA to 175 mA, VINLDOx = 1.6 V–6 V,
VLDOx = 1.2 V
IO = 1 mA to 300 mA, VINLDOx = 3.6 V
VLDOx = 1.2 V
Load regulation
VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V at
IO = 1 mA
Line regulation
f
NOISE ≤ 10 kHz, COUT ≥ 2.2 μF, VIN = 2.3 V,
PSRR
Power-supply rejection ratio
40
dB
VOUT = 1.3 V, IOUT = 10 mA
Internal discharge resistance at
VLDOx
RDIS
TSD
EN_LDOx low
450
Ω
Thermal shutdown
Increasing temperature
Decreasing temperature
150
30
°C
°C
Thermal shutdown hysteresis
(2) For VINDCDC = VDCDC + 1 V
(3) Maximum output voltage VLDOx = 3.6 V.
(4) VDO = VINLDOx – VLDOx, where VINLDOx = VLDOx(nom) – 100 mV
6
Copyright © 2019, Texas Instruments Incorporated
TPS650002-Q1
www.ti.com.cn
ZHCSJN8 –APRIL 2019
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STEP-DOWN CONVERTER OUTPUT VOLTAGE
EN_DCDC to start of switching
(10%)
tStart
Start-up time
250
250
µs
µs
tRamp
VDCDC ramp-up time
VDCDC ramp from 10% to 90%
LOW-DROPOUT REGULATORS
tRAMP VLDOx ramp time
VLDOx ramp from 10% to 90%
200
µs
6.7 Typical Characteristics
100
100
90
80
70
60
50
40
30
V
T
= 1.2V
OUT
= 25oC
V
T
= 1.2V
OUT
= 25oC
90
80
70
60
50
40
30
4.2V
A
A
3.6V
3.3V
6V
2.8V
3.3V
5.5V
6V
5V
4.5V
2.3V
2.8V
5.5V
4.2V
3.6V
2.3V
5V
20
10
0
20
10
0
4.5V
0.00001 0.0001
0.001
0.01
0.1
1
0.00001 0.0001
0.001
- Output Current - A
O
0.01
0.1
1
I
- Output Current - A
I
O
Figure 1. Efficiency (DC-DC 600-mA PFM Mode)
vs Output Current
Figure 2. Efficiency (DC-DC 600-mA PWM Mode)
vs Output Current
Load Current = 60mA
EN_DCDC = high
EN_LDO1 = low
VINDCDC = 3.6 V
= 25oC
Load DCDC = 400mA
EN_DCDC = high
EN_LDO1 = low
VINDCDC = 3.6 V
= 25oC
T
T
A
A
VDCDC = 1.2 V
VDCDC = 1.2 V
EN_LDO2 = low
EN_LDO2 = low
t - Time - 2ms/div
t - Time - 200ns/div
Figure 4. Output Voltage Ripple (DC-DC PWM Mode)
Figure 3. Output Voltage Ripple (DC-DC PFM Mode)
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Typical Characteristics (continued)
VINDCDC = 3.6 V
VINLDOx = 2.3V
T
= 25oC
A
VLDOx = 1.2 V
VINDCDC = 3.6 V
T
= 25oC
A
VDCDC = 1.2 V
Load LDOx = 100mA
EN_LDOx = 0V to 2.3V
EN_DCDC = low
Load DCDC = 100mA
EN_DCDC = 0V to 3.6V
EN_LDO1 = low
EN_LDO2 = low
t - Time - 100µs/div
t - Time - 100µs/div
Figure 5. Start-Up Timing (DC-DC)
Figure 6. Start-Up Timing (LDOx)
VINDCDC = 3.6 V to 4.2V to 3.6V
= 25oC
VINDCDC = 3.6 V to 4.2V to 3.6V
= 25oC
T
A
T
A
VDCDC = 1.8V
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = VINDCDC
DCDC Load Current = 50mA
Mode = GND
t - Time - 100ms/div
t - Time - 100ms/div
Figure 7. Line Transient Response (DC-DC PFM Mode)
Figure 8. Line Transient Response (DC-DC PWM Mode)
VINDCDC = 3.6V
= 25oC
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
T
A
T
= 25oC
VDCDC = 1.8V
A
DCDC Load Current = 60mA to 540 mA
Mode = GND
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
t - Time - 100ms/div
t - Time - 100ms/div
Figure 9. Line Transient Response (LDOx)
Figure 10. Load Transient Response (DC-DC PFM Mode)
8
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ZHCSJN8 –APRIL 2019
Typical Characteristics (continued)
VINDCDC = 3.6V
= 25oC
T
A
VDCDC = 1.8V
VINDCDC = 3.6V
VINLDOx = 3.6V
T
= 25oC
A
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
t - Time - 100ms/div
t - Time - 200ms/div
Figure 11. Load Transient Response (DC-DC PWM Mode)
Figure 12. Load Transient Response (LDOx)
VINDCDC = 3.6V
= 25oC
T
A
DCDC Load Current = 30mA
VDCDC = 1.8V
VINDCDC = 3.6V
= 25oC
T
A
DCDC Load Current = 30mA
VDCDC = 1.8V
t - Time - 4ms/div
t - Time - 4ms/div
Figure 13. PFM to PWM Transition (DC-DC)
Figure 14. PWM to PFM Transition (DC-DC)
100
V
= 2.3V
IN
VLDOx = 1.3V
CI = 2.2mF
90
C
= 10mF
O
80
70
60
50
I
= 10mA
O
40
30
20
10
0
10
100
1k
10k
100k
1M
10M
f - Frequency - MHz
Figure 15. Power-Supply Rejection Ratio (LDOx) vs Frequency
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7 Detailed Description
7.1 Overview
The TPS650002-Q1 device has one step-down converter, and two low dropout regulators. The device has an
input voltage range of 2.3 V to 6 V. This device is intended for (but not limited to) powering automotive camera
modules.
To maximize efficiency, there are two modes of operation based on load conditions: PWM or PFM. By pulling the
MODE pin high, forced PWM can be achieved. Pulling this pin low results in an automatic adjustment between
PFM and PWM modes.
The two general-purpose low-dropout regulators each have their own separate enables and voltage inputs. The
inputs can be tied to the output of the step-down converter or to a separate voltage source.
The switching frequency of the step-down converter is handled by the oscillator, with a typical frequency of
2.25 MHz.
The TPS650002-Q1 device also provides a power good signal to monitor the condition of the DC-DC and both
LDOs. The DC-DC and LDOs are only monitored if their enable signal is high. If all enabled resources are in
regulation, the pin is pulled low. If one or more of the enabled resources are out of regulation, the pin is placed in
Hi-Z.
7.2 Functional Block Diagram
Oscillator
VINDCDC
EN_DCDC
MODE
SW
Buck Converter
600 mA
FB_DCDC
PG
VLDO1
VINLDO1
EN_LDO1
LDO1
FB_LDO1
300 mA
PGND
VINLDO2
EN_LDO2
VLDO2
LDO2
FB_LDO2
300 mA
AGND
Band-Gap Reference
7.3 Feature Description
7.3.1 Step-Down Converter
The step-down converter is intended to allow maximum flexibility in the end equipment. Figure 16 shows the
necessary connections.
10
Copyright © 2019, Texas Instruments Incorporated
TPS650002-Q1
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ZHCSJN8 –APRIL 2019
Feature Description (continued)
VIN_DCDC
SW
EN_DCDC
CO
Switch Control
DISCHG
P
ZLOAD
MODE
FB_DCDC
Oscillator
ꢀJA DIODE
VREF(DCDC)
P
P
AGND
PGND
P
A
Figure 16. DC-DC Converter Block Diagram
Externally adjustable output voltages and additional current-limit options are also possible. Contact TI for further
information.
The step-down converter has two modes of operation to maximize efficiency at different load conditions. At
moderate to heavy load currents, the device operates in a fixed-frequency pulse-width modulation (PWM) mode
that results in small output ripple and high efficiency. Pulling the MODE pin to a DC-high level results in PWM
mode over the entire load range.
At light load currents, the device operates in a pulsed frequency-modulation (PFM) mode to improve efficiency.
The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating
discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from the PWM mode
value. This voltage positioning is intended to minimize both the voltage undershoot of a load step from light to
heavy loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load
removal. shows the voltage positioning behavior for a light-to-heavy load step.
Output voltage
VOUT(nom) + 1%
Light load
PFM Mode
VOUT(nom)
moderate to heavy load
PWM Mode
Time
Figure 17. PFM Voltage Positioning
Pulling the MODE pin to DC ground results in an automatic transition between PFM and PWM modes to
maximize efficiency.
Copyright © 2019, Texas Instruments Incorporated
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TPS650002-Q1
ZHCSJN8 –APRIL 2019
www.ti.com.cn
Feature Description (continued)
The DC-DC converter output automatically discharges to ground through an internal 450-Ω load when EN_DCDC
goes low or when the UVLO condition is met.
7.3.2 Soft Start
The step-down converter has an internal soft-start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp-up is controlled as shown in Figure 18.
EN
90%
10%
VOUT
tRAMP
tStart
Figure 18. Soft Start
7.3.3 Linear Regulators
The two linear dropout regulators (LDOs) in the TPS650002-Q1 are designed to provide flexibility in system
design. Each LDO has a separate voltage input and enable signal. The input can be tied to the output of the
step-down converter or the output of another voltage source. Each LDO output discharges to ground
automatically when EN_LDOx goes low.
The LDOs are general-purpose devices that can handle inputs from 6 V down to 1.6 V. Figure 19 shows the
necessary connections for LDO1. The same architecture applies to LDO2.
VLDO1
VINLDO1
CO(LDO1)
FB_LDO1
DISCHG
ꢀJA DIODE
ZLOAD
EN_LDO1
VREF(LD01)
P
AGND
PGND
A
P
Figure 19. LDO Block Diagram
7.3.4 Power Good
The open-drain PG output is used to indicate the condition of the step-down converter and each LDO. This is a
combined output, with the outputs being compared when the appropriate enable signal is high. The pin is pulled
low when all enabled outputs are greater than 95%of the target voltage, and it is pulled into Hi-Z when an
enabled output is less than 90% of its intended value or when all the enable signals are pulled low.
12
Copyright © 2019, Texas Instruments Incorporated
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ZHCSJN8 –APRIL 2019
Feature Description (continued)
EN_DCDC
EN_LDO1
EN_LDO2
VDCDC
VDCDC
+
PG
VDCDC
-
Target
A
VLDO1
+
VLDO1
-
Target
VLDO2
+
VLDO2
-
Target
Figure 20. Power-Good Functionality
7.4 Device Functional Modes
The step-down converter has two modes of operation to maximize efficiency:
1. PFM
–
–
For light loads
For automatic transition between this mode and PWM mode when MODE pin is pulled low over all load
ranges
2. PWM
–
–
–
For moderate to heavy loads
For a small output ripple
For maintaining the specified switching frequency variation by pulling the MODE pin high which places
the device in a forced PWM mode over the entire load range.
Copyright © 2019, Texas Instruments Incorporated
13
TPS650002-Q1
ZHCSJN8 –APRIL 2019
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS650002-Q1 can be used in an automotive-camera sensor module to generate the AVDD, DVDD, and
IOVDD voltage rails. For noise immunity, one of the LDOs should be used to generate the AVDD voltage rail. To
minimize power dissipation, the DC-DC converter should be used to power the DVDD rail because the DVDD rail
normally has a lower operating voltage and higher current consumption.
8.2 Typical Application
Regulators with fixed voltage outputs do not require external feedback resistors. Feedback pins must externally
connect to the output capacitors.
TI Device
2.2 µH
VDCDC
EN_DCDC
SW
1.8 V
FB_DCDC
VIN
VINDCDC
MODE
10 …F
A
10 …F
P
P
470 kꢀ
VIN
PG
VIN
EN_LDO1
VINLDO1
VLDO1
2.8 V
VLDO1
2.2 …F
FB_LDO1
10 …F
P
P
P
P
VIN
EN_LDO2
VINLDO2
VLDO2
1.2 V
VLDO2
2.2 …F
FB_LDO2
10 …F
AGND
PGND
A
P
Figure 21. Typical Fixed Voltage Application Schematic
8.2.1 Design Requirements
For this example, the fixed voltage TPS650002-Q1 device operates with the parameters listed in Table 1.
Table 1. Design Parameters
RESOURCES
SW
VOLTAGE
1.8 V
VLDO1
2.8 V
VLDO2
1.2 V
14
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
8.2.2.1.1 Inductor Selection
The typical value for the converter inductor is 2.2-μH output inductor. Larger or smaller inductor values in the
range of 1.5 μH to 3.3 μH can optimize the performance of the device for specific operation conditions. The
selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance
influences the efficiency of the converter directly. An inductor with lowest DC resistance must be selected for
highest efficiency. For more information on inductor selection, refer to the Choosing Inductors and Capacitors for
DC/DC Converters application report.
Equation 1 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 2. TI
recommends this because during heavy load transient, the inductor current rises above the calculated value.
VOUT
1 -
V
IN
DIL = VOUT
x
L x f
where
•
•
•
f = Switching Frequency (2.25-MHz typical)
L = Inductor Value
ΔIL = Peak-to-peak Inductor Ripple Current
DIL
(1)
(2)
ILmax = IOUTmax
+
2
where
•
ILmax = Maximum Inductor Current
The highest inductor current occurs at maximum VIN.
Open-core inductors have a soft saturation characteristic and can usually handle higher inductor currents versus
a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consider that the core material from inductor to inductor differs and impacts the
efficiency especially at high-switching frequencies.
The step down converter has internal loop compensation. TI designed the internal loop compensation to work
with a certain output filter corner frequency calculated as in Equation 3:
1
fC
=
with L = 2.2mH, COUT = 10mF
2p L x COUT
(3)
The selection of external L-C filter must be consistent with Equation 3. The product of L × COUT must be constant
while selecting smaller inductor or increasing output capacitor value.
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TPS650002-Q1
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www.ti.com.cn
8.2.2.1.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the converter allows the use of small ceramic
capacitors with a typical value of 22 μF, without having large output voltage under and overshoots during heavy
load transients. TI recommends ceramic capacitors with low ESR values because they result in lowest output
voltage ripple. See for the TI-recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. The RMS ripple current is calculated as in Equation 4:
VOUT
1 -
V
1
IN
IRMSCout = VOUT
x
x
L x f
2 x
3
(4)
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor as calculated in Equation 5:
VOUT
1 -
æ
ç
ç
ö
V
1
÷
÷
÷
÷
ø
IN
DVOUT = VOUT
x
x
+ ESR
ç
ç
è
L x f
8 x C
x f
OUT
(5)
Where the highest output voltage ripple occurs at the highest input voltage VIN.
At light load currents, the converter operates in power save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
8.2.2.2 Input Capacitor Selection
Due to the DC-DC converter having a pulsating input current, a low-ESR input capacitor is required for best input
voltage filtering, and minimizing the interference with other circuits caused by high-input voltage spikes . Place
the input capacitor as close as possible to the VINDCDC pin with the clean GND connection. Do the same for
the output capacitor and the inductor. The converters require a ceramic input capacitor, a 10 μF is
recommended . The input capacitor can increase without any limit for better input voltage filtering.
8.2.3 Application Curves
VINDCDC = 3.6 V to 4.2V to 3.6V
= 25oC
VINDCDC = 3.6 V to 4.2V to 3.6V
= 25oC
T
A
T
A
VDCDC = 1.8V
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = GND
DCDC Load Current = 50mA
Mode = VINDCDC
t - Time - 100ms/div
t - Time - 100ms/div
Figure 22. Line Transient Response (DC-DC PFM Mode)
Figure 23. Line Transient Response (DC-DC PWM Mode)
16
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ZHCSJN8 –APRIL 2019
VINDCDC = 3.6V
= 25oC
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
T
A
T
= 25oC
VDCDC = 1.8V
A
DCDC Load Current = 60mA to 540 mA
Mode = GND
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
t - Time - 100ms/div
t - Time - 100ms/div
Figure 24. Line Transient Response (LDOx)
Figure 25. Load Transient Response (DC-DC PFM Mode)
VINDCDC = 3.6V
= 25oC
T
A
VDCDC = 1.8V
VINDCDC = 3.6V
VINLDOx = 3.6V
T
= 25oC
A
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
t - Time - 100ms/div
t - Time - 200ms/div
Figure 26. Load Transient Response (DC-DC PWM Mode)
Figure 27. Load Transient Response (LDOx)
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TPS650002-Q1
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9 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 1.6 V to 6 V. This input supply can be
from a DC supply, or other externally regulated supply. If the input supply is located more than a few inches from
the TPS650002-Q1, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
An electrolytic capacitor with a value of 10 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
The VINDCDC and VINLDOx pins must be bypassed to ground with a low-ESR ceramic bypass capacitor. TI
recommends the typical bypass capacitance is 10 μF and 2.2 μF with a X5R dielectric.
•
The optimum placement is closest to the VINDCDCx and VINLDOx pins of the device. Minimize the loop area
formed by the bypass capacitor connection, the VINDCDC and VINLDO pins, and the thermal pad of the
device.
•
•
The thermal pad must be tied to the PCB ground plane with multiple vias.
The traces of the VLDOx and VDCDCx pins (feedback pins) must be routed away from any potential noise
source to avoid coupling.
•
VODC output capacitance must be placed immediately at the VODC pin. Excessive distance between the
capacitance and DCDCx pin may cause poor converter performance.
•
•
AGND star back to PGND as close to the device as possible.
DGND connect to the thermal pad
10.2 Layout Examples
Thermal pad
Vias to GND
plane
Figure 28. Layout Recommendation
Bypass capacitors to GND for VIN pins
Vias to
GND
Figure 29. Bypass Capacitor and Via Placement Recommendation
18
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TPS650002-Q1
www.ti.com.cn
ZHCSJN8 –APRIL 2019
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，为直流/直流转换器选择电感器和电容器 应用报告
德州仪器 (TI)，使用具有双路 LDO 的 TPS65000EVM 2.25MHz 降压转换器 用户指南
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS650002TRTERQ1
TPS650002TRTETQ1
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
SJO2
SJO2
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS650003RTE
IC 1.4 A SWITCHING REGULATOR, 2847 kHz SWITCHING FREQ-MAX, PQCC16, 3 X 3 MM, PLASTIC, QFN-16, Switching Regulator or Controller
TI
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