TPS650231RSBR_技术文档

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS

Check for Samples: TPS650231

1

FEATURES

DESCRIPTION

23

•

1.7 A, 90% Efficient Step-Down Converter for

Processor Core (VDCDC1)

The TPS650231 is an integrated Power Management

IC for applications powered by one Li-Ion or

Li-Polymer cell, and which require multiple power

rails. The TPS650231 provides three highly efficient,

step-down converters targeted at providing the core

voltage, peripheral, I/O and memory rails in a

processor based system. The core converter allows

for on-the-fly voltage changes via serial interface,

allowing the system to implement dynamic power

savings. All three step-down converters enter a

low-power mode at light load for maximum efficiency

across the widest possible range of load currents.

The TPS650231 also integrates two general-purpose

200 mA LDO voltage regulators, which are enabled

with an external input pin. Each LDO operates with

an input voltage range between 1.5 V and 6.5 V,

allowing them to be supplied from one of the

step-down converters or directly from the battery. The

default output voltage of the LDOs can be digitally set

•

1.2 A, Up to 95% Efficient Step-Down

Converter for System Voltage (VDCDC2)

•

0.8 A, 92% Efficient Step-Down Converter for

Memory Voltage (VDCDC3)

•

30 mA LDO/Switch for Real Time Clock (VRTC)

2 × 200 mA General-Purpose LDO

Dynamic Voltage Management for Processor

Core

•

Preselectable LDO Voltage Using Two Digital

Input Pins

•

Externally Adjustable Reset Delay Time

Battery Backup Functionality

Separate Enable Pins for Inductive Converters

I²C™ Compatible Serial Interface

85-mA Quiescent Current

to

4

different voltage combinations using the

Low Ripple PFM Mode

DEFLDO1 and DEFLDO2 pins. The serial interface

can be used for dynamic voltage scaling, masking

interrupts, or for dis/enabling and setting the LDO

output voltages. The interface is compatible with the

Fast/Standard mode I²C specification, allowing

transfers at up to 400 kHz. The TPS650231 is

available in a 40-pin (RSB) QFN package or in a 49

Thermal Shutdown Protection

40 Pin, 5 mm × 5 mm QFN /RSB) Package or

49 Ball 3 mm x 3 mm WCSP (YFF) package

APPLICATIONS

ball 3mm

x 3mm WCSP (YFF) package, and

•

Smart phones

Netbooks / MIDs

Portable Media Players

operates over a free-air temperature of –40°C to

85°C.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PowerPAD is a trademark of Texas Instruments.

I²C is a trademark of NXP Semiconductors.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE

PACKAGE SIZE

PART NUMBER⁽²⁾

TPS650231RSB

TPS650231YFF

–40°C to 85°C

40 pin QFN (RSB)

49 ball WCSP (YFF)

see package drawings

E = 3.082mm ± 30µm

D = 3.066mm ± 30µm

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) The RSB and YFF packages are available in tape and reel. Add the R suffix (TPS650231RSBR, TPS650231YFFR) to order quantities of

3000 parts per reel. Add the T suffix (TPS650231RSBT, TPS650231YFFT) to order quantities of 250 parts per reel.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

7

V_I

Input voltage range on all pins except AGND and PGND pins with respect to AGND

–0.3

V

Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3,

PGND3

2500

mA

Peak current at all other pins

Operating free-air temperature

Junction temperature

1000

85

mA

°C

T_A

–40

–65

T_J

125

150

T_stg

Storage temperature

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

THERMAL INFORMATION

TPS650231

THERMAL METRIC⁽¹⁾

RSB

40 PINS

32.7

15.3

13.6

0.1

YFF

UNITS

49 BALLS

q_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

40

10

q_JCtop

q_JB

15

°C/W

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

14

y_JB

5.4

q_JCbot

1.1

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

Input voltage range step-down converters

(VINDCDC1, VINDCDC2, VINDCDC3)

V_CC

2.5

6

V

Output voltage range for VDCDC1 step-down converter⁽¹⁾

0.6

1.5

1

VINDCDC1

VINDCDC2

VINDCDC3

6.5

V_O

Output voltage range for VDCDC2 step-down converter⁽¹⁾

Output voltage range for VDCDC3 step-down converter⁽¹⁾

Input voltage range for LDOs (VINLDO)

Output voltage range for LDOs (VLDO1, VLDO2)

Output current at L1

V

V_I

V

V_O

VINLDO1-2

1700

V

I_O(DCDC1)

mA

mH

mF

mA

mH

mF

mA

mH

mF

mA

mF

°C

Ω

Inductor at L1⁽²⁾

1.5

10

2.2

22

(2)

C_I(DCDC1)

C_O(DCDC1)

I_O(DCDC2)

Input capacitor at VINDCDC1

(2)

Output capacitor at VDCDC1

Output current at L2

1200

800

(2)

Inductor at L2

1.5

10

2.2

22

(2)

C_I(DCDC2)

C_O(DCDC2)

I_O(DCDC3)

Input capacitor at VINDCDC2

(2)

Output capacitor at VDCDC2

Output current at L3

(2)

Inductor at L3

1.5

10

1

2.2

22

C_I(DCDC3)

C_O(DCDC3)

C_I(VCC)

Input capacitor at VINDCDC3⁽²⁾

(2)

Output capacitor at VDCDC3

(2)

Input capacitor at VCC

(2)

C_I(VINLDO)

C_O(VLDO1-2)

I_O(VLDO1-2)

C_O(VRTC)

T_A

Input capacitor at VINLDO

1

(2)

Output capacitor at VLDO1, VLDO2

2.2

Output current at VLDO1, VLDO2

200

(2)

Output capacitor at VRTC

4.7

–40

Operating ambient temperature

85

125

10

T_J

Operating junction temperature

Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering⁽³⁾

1

(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1

(2) See Applications Information section for more information.

(3) Up to 3 mA can flow into V_CCwhen all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted

accordingly.

Submit Documentation Feedback

3

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C, typical values are

at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONTROL SIGNALS : SCLK, SDAT (input)

Rpullup at SCLK = 4.7 kΩ, pulled to VRTC;

For V_CC= 2.5V to 5.25V

V_IH

High level input voltage for the SCLK pin

High level input voltage for the SDAT pin

1.4

1.69

1.55

0

V_CC

V

Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;

For V_CC= 2.5V to 5.25V

Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;

For V_CC= 2.5V to 4.5V

Rpullup at SCLK and SDAT = 4.7 kΩ, pulled

to VRTC

V_IL

I_H

Low level input voltage

Input bias current

0.35

0.1

V

0.01

mA

CONTROL SIGNALS : HOT_RESET , DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2

V_IH

V_IL

I_IB

High-level input voltage

Low-level input voltage

Input bias current

1.3

0

V_CC

0.4

0.1

35

V

0.01

30

mA

ms

t_glitchDeglitch time at HOT_RESET

25

0

CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)

V_OHHigh-level output voltage

6

V

V_OL

Low-level output voltage

Duration of low pulse at RESPWRON

Resetpwron threshold

I_IL= 5 mA

0.3

External capacitor 1 nF

VRTC falling

100

2.4

ms

V

–3%

3%

0.1

Resetpwron threshold

VRTC rising

2.52

0.001

V

I_LK

leakage current

output inactive high

mA

4

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C, typical values are

at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3,

VINDCDC13 (for TPS650231YFF)

All 3 DCDC converters enabled,

zero load, and no switching, LDOs

enabled

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

85 100

All 3 DCDC converters enabled,

zero load, and no switching, LDOs

off

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

78

57

90

70

Operating quiescent

current, PFM

I_(q)

mA

DCDC1 and DCDC2 converters

enabled, zero load, and no

switching, LDOs off

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

DCDC1 converter enabled, zero

load, and no switching, LDOs off

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

43

2

55

3

All 3 DCDC converters enabled

and running in PWM, LDOs off

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

DCDC1 and DCDC2 converters

enabled and running in PWM,

LDOs off

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

I_I

Current into VCC; PWM

1.5

2.5

mA

DCDC1 converter enabled and

running in PWM, LDOs off

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

0.85

23

2

33

5

VCC = 3.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

mA

VCC = 2.6 V, VBACKUP = 3 V;

V_(VSYSIN)= 0 V

I_(q)

Quiescent current

All converters disabled, LDOs off

3.5

VCC = 3.6 V, VBACKUP = 0 V;

V_(VSYSIN)= 0 V

43

Shutdown supply current

into VINDCDC1; for

TPS650231RSB

I_(SD)

DCDC1_EN = GND

DCDC2_EN = GND

DCDC3_EN = GND

0.1

0.2

1

2

mA

Shutdown supply current

into VINDCDC2; for

TPS650231RSB

Shutdown supply current

into VINDCDC3; for

TPS650231RSB

Shutdown supply current

into VINDCDC13; for

TPS650231YFF

DCDC1_EN = DCDC3_EN =

GND

Submit Documentation Feedback

5

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C,

typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY PINS: VBACKUP, VSYSIN, VRTC

VBACKUP = 3 V, VSYSIN = 0 V;

VCC = 2.6 V, current into VBACKUP

I_(q)

Operating quiescent current

20

33

3

mA

VBACKUP < V_VBACKUP, current into

VBACKUP

I_(SD)

2

3

VRTC LDO output voltage

Output current for VRTC

VSYSIN = VBACKUP = 0 V, I_O= 0 mA

VSYSIN < 2.57 V and VBACKUP < 2.57 V

VRTC = GND; VSYSIN = VBACKUP = 0 V

V

I_O

30

mA

VRTC short-circuit current limit

100

Maximum output current at VRTC for

RESPWRON = 1

VRTC > 2.6 V, V_CC= 3 V;

VSYSIN = VBACKUP = 0 V

30

mA

V_O

Output voltage accuracy for VRTC

Line regulation for VRTC

VSYSIN = VBACKUP = 0 V; I_O= 0 mA

VCC = VRTC + 0.5 V to 6.5 V, I_O= 5 mA

–1%

1%

I_O= 1 mA to 30 mA;

VSYSIN = VBACKUP = 0 V

Load regulation VRTC

–3%

1%

Regulation time for VRTC

Input leakage current at VSYSIN

r_DS(on)of VSYSIN switch

r_DS(on)of VBACKUP switch

Input voltage range at VBACKUP

Input voltage range at VSYSIN

VSYSIN threshold

Load change from 10% to 90%

VSYSIN < V_VSYSIN

10

ms

mA

Ω

V

I_lkg

2

12.5

3.75

3%

2.73

–3%

V

VSYSIN falling

VSYSIN rising

2.55

2.65

2.55

2.65

V

VSYSIN threshold

3%

V

VBACKUP threshold

VBACKUP falling

3%

V

VBACKUP threshold

3%

V

SUPPLY PIN: VINLDO

I_(q)

Operating quiescent current

Current per LDO into VINLDO

20

33

1

mA

Total current for both LDOs into VINLDO,

VLDO = 0 V

I_(SD)

Shutdown current

0.1

6

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C, typical values are

at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VDCDC1 STEP-DOWN CONVERTER

V_I

I_O

Input voltage range, VINDCDC1

Maximum output current

2.5

6

V

1700

mA

mΩ

mA

r_DS(on)P-channel MOSFET on-resistance

I_lkgP-channel leakage current

r_DS(on)N-channel MOSFET on-resistance

VINDCDC1 (VINDCDC13) = V_(GS)= 3.6 V

VINDCDC1 (VINDCDC13) = 6 V

VINDCDC1 (VINDCDC13) = V_(GS)= 3.6 V

V_(DS)= 6 V

125

261

2

130

7

260

10

mΩ

mA

I_lkg

N-channel leakage current

Forward current limit (P-channel and

N-channel)

2.5 V < V_(VINDCDC1)< 6 V

1.94

1.95

–2%

2.19

2.25

2.44

2.55

2%

A

f_S

Oscillator frequency

MHz

Fixed output voltage

FPWMDCDC1=0

VINDCDC1 (VINDCDC13) = 2.5 V to 6 V;

0 mA ≤ I_O≤ 1.7 A

All VDCDC1

Fixed output voltage

FPWMDCDC1=1

VINDCDC1 (VINDCDC13) = 2.5 V to 6 V;

0 mA ≤ I_O≤ 1.7 A

–1%

–2%

–1%

1%

2%

1%

Adjustable output voltage with resistor

divider at DEFDCDC1; FPWMDCDC1=0

VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V

(min 2.5 V) to 6 V; 0 mA ≤ I_O≤ 1.7 A

Adjustable output voltage with resistor

divider at DEFDCDC1; FPWMDCDC1=1

VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V

(min 2.5 V) to 6 V; 0 mA ≤ I_O≤ 1.7 A

VINDCDC1 (VINDCDC13) = VDCDC1 + 0.3 V

(min. 2.5 V) to 6 V; I_O= 10 mA

Line Regulation

0

%/V

Load Regulation

Start-up time

I_O= 10 mA to 1700 mA

0.25

175

750

1

%/A

ms

t_Start

Time from active EN to start switching

Time to ramp from 5% to 95% of V_OUT

145

400

200

t_RampV_OUTramp-up time

Internal resistance from L1 to GND

1000

ms

MΩ

Ω

VDCDC1 discharge resistance

DCDC1 discharge = 1

300

Submit Documentation Feedback

7

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C,

typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VDCDC2 STEP-DOWN CONVERTER

V_I

Input voltage range, VINDCDC2

2.5

6

V

VDCDC2 = 1.2V

1200

I_O

Maximum output current

mA

VINDCDC2 = 3.7 V;

3.3 V - 1% ≤ VDCDC2 ≤ 3.3V + 1%

1000

r_DS(on)

I_lkg

r_DS(on)

I_lkg

P-channel MOSFET on-resistance

P-channel leakage current

VINDCDC2 = V_(GS)= 3.6 V

VINDCDC2 = 6 V

140

300

2

mΩ

mA

N-channel MOSFET on-resistance

N-channel leakage current

VINDCDC2 = V_(GS)= 3.6 V

V_(DS)= 6 V

150

7

297

10

mΩ

mA

Forward current limit (P-channel and

N-channel)

I_LIMF

2.5 V < VINDCDC2 < 6 V

1.74

1.95

–2%

1.94

2.25

2.12

2.55

2%

A

f_S

Oscillator frequency

MHz

Adjustable output voltage with resistor

divider at DEFDCDC2; FPWMDCDC2=0

VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V)

to 6 V; 0 mA ≤ I_O≤ 1.2 A

VDCDC2

Adjustable output voltage with resistor

divider at DEFDCDC2; FPWMDCDC2=1

VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V)

to 6 V; 0 mA ≤ I_O≤ 1.2 A

VDCDC2

–1%

1%

VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V)

to 6 V; I_O= 10 mA

Line Regulation

0

%/V

Load Regulation

I_O= 10 mA to 1.2 A

0.25

175

750

1

%/A

µs

t_Start

Start-up time

Time from active EN to start switching

Time to ramp from 5% to 95% of V_OUT

145

400

200

t_Ramp

V_OUTramp-up time

1000

ms

Internal resistance from L2 to GND

VDCDC2 discharge resistance

MΩ

Ω

DCDC2 discharge =1

300

8

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C,

typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VDCDC3 STEP-DOWN CONVERTER

V_I

Input voltage range, VINDCDC3

2.5

6

V

DEFDCDC3 = GND

800

I_O

Maximum output current

mA

VINDCDC3 (VINDCDC13) = 3.6 V;

3.3V - 1% ≤ VDCDC3 ≤ 3.3V + 1%

525

r_DS(on)

I_lkg

r_DS(on)

I_lkg

P-channel MOSFET on-resistance

P-channel leakage current

VINDCDC3 (VINDCDC13) = V_(GS)= 3.6 V

VINDCDC3 (VINDCDC13) = 6 V

VINDCDC3 (VINDCDC13) = V_(GS)= 3.6 V

V_(DS)= 6 V

310

0.1

220

7

698

2

mΩ

mA

N-channel MOSFET on-resistance

N-channel leakage current

503

10

mΩ

mA

Forward current limit (P-channel and

N-channel)

2.5 V < VINDCDC3 (VINDCDC13) < 6 V

1.28

1.95

–2%

1.49

2.25

1.69

2.55

2%

A

f_S

Oscillator frequency

MHz

VINDCDC3 (VINDCDC13) = 2.5 V to 6 V;

0 mA ≤ I_O≤ 0.8 A

VDCDC3 = 1.8V

Fixed output voltage

FPWMDCDC3=0

VINDCDC3 (VINDCDC13) = 3.6 V to 6 V;

0 mA ≤ I_O≤ 0.8 A

VDCDC3 = 3.3V

VDCDC3 = 1.8V

VDCDC3 = 3.3V

–1%

–2%

–1%

–2%

–1%

1%

2%

1%

2%

1%

VINDCDC3 (VINDCDC13) = 2.5 V to 6 V;

0 mA ≤ I_O≤ 0.8 A

Fixed output voltage

FPWMDCDC3=1

VINDCDC3 (VINDCDC13) = 3.6 V to 6 V;

0 mA ≤ I_O≤ 0.8 A

Adjustable output voltage with resistor

divider at DEFDCDC3 FPWMDCDC3=0

VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V

(min 2.5 V) to 6 V; 0 mA ≤ I_O≤ 800 mA

Adjustable output voltage with resistor

divider at DEFDCDC3; FPWMDCDC3=1

VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V

(min 2.5 V) to 6 V; 0 mA ≤ I_O≤ 800 mA

VINDCDC3 (VINDCDC13) = VDCDC3 + 0.3 V

(min. 2.5 V) to 6 V; I_O= 10 mA

Line Regulation

0

%/V

Load Regulation

I_O= 10 mA to 800 mA

0.25

175

750

1

%/A

µs

t_Start

Start-up time

Time from active EN to start switching

Time to ramp from 5% to 95% of V_OUT

145

400

200

t_Ramp

V_OUTramp-up time

1000

ms

Internal resistance from L3 to GND

VDCDC3 discharge resistance

MΩ

Ω

DCDC3 discharge =1

300

Submit Documentation Feedback

9

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, T_A= –40°C to 85°C,

typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VLDO1 and VLDO2 LOW DROPOUT REGULATORS

V_I

Input voltage range for LDO1, 2

LDO1 output voltage range

LDO2 output voltage range

1.5

1

6.5

3.15

3.3

V

V_O(LD01)

V_O(LDO2)

1.05

200

V_I= 1.8 V, V_O= 1.3 V

I_O

Maximum output current for LDO1, LDO2

mA

V_I= 1.5 V, V_O= 1.3 V

120

65

I_(SC)

LDO1 and LDO2 short circuit current limit V_(LDO1)= GND, V_(LDO2)= GND

I_O= 50 mA, VINLDO = 1.8 V

400

120

150

300

1%

Minimum voltage drop at LDO1, LDO2

I_O= 50 mA, VINLDO = 1.5 V

I_O= 200 mA, VINLDO = 1.8 V

mV

Output voltage accuracy for LDO1, LDO2 I_O= 10 mA

–2%

–1%

VINLDO1, 2 = VLDO1,2 + 0.5 V

(min. 2.5 V) to 6.5 V, I_O= 10 mA

Line regulation for LDO1, LDO2

1%

Load regulation for LDO1, LDO2

Regulation time for LDO1, LDO2

I_O= 0 mA to 50 mA

Load change from 10% to 90%

10

ms

ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3

V_IH

V_IL

High-level input voltage

Low-level input voltage

Input bias current

1.3

0

VCC

0.1

V

0.001

0.05

mA

THERMAL SHUTDOWN

T_(SD)Thermal shutdown

Thermal shutdown hysteresis

INTERNAL UNDERVOLTAGE LOCK OUT

Increasing junction temperature

Decreasing junction temperature

160

20

°C

UVLO

Internal UVLO

VCC falling

–2%

2.35

120

2%

1%

V

V_{(UVLO_HYST)}

Internal UVLO comparator hysteresis

mV

VOLTAGE DETECTOR COMPARATOR INPUTS PWRFAIL_SNS, LOWBAT_SNS

Comparator threshold

(PWRFAIL_SNS, LOWBAT_SNS)

LOWBAT_SNS for TPS650231RSB only

Falling threshold

25-mV overdrive

–1%

40

1

V

Hysteresis

50

60

10

mV

ms

Propagation delay

Input leakage current

I_LK

0.001

0.1

mA

POWER GOOD

VDCDC1, VDCDC2, VDCDC3,

VLDO1, VLDO2, decreasing

V_(PGOODF)

V_(PGOODR)

–12%

–7%

–10%

–5%

–8%

–3%

VDCDC1, VDCDC2, VDCDC3,

VLDO1, VLDO2, increasing

10

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

PIN ASSIGNMENT FOR TPS650231RSB

(TOP VIEW)

40 39 38 37 36 35 34 33 32 31

30

SCLK

1

2

DEFDCDC3

VDCDC3

PGND3

29

28

27

SDAT

INT

3

4

RESPWRON

TRESPWRON

DCDC1_EN

DCDC2_EN

DCDC3_EN

LDO_EN

LOWBAT

L3

26

25

VINDCDC3

VINDCDC1

L1

5

6

24

23

22

7

PGND1

8

VDCDC1

DEFDCDC1

9

21

10

11 12 13 14 15 16 17 18 19 20

PIN FUNCTIONS FOR TPS650231RSB

I/O

DESCRIPTION

NAME

SWITCHING REGULATOR SECTION

NO.

AGND1

40

17

–

Analog ground. All analog ground pins are connected internally on the chip.

Connect the power pad to analog ground.

AGND2

PowerPAD™

Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage

supply as VINDCDC2, VINDCDC3, and VCC.

VINDCDC1

6

I

L1

7

9

8

Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.

VDCDC1 feedback voltage sense input. Connect directly to VDCDC1

Power ground for VDCDC1 converter.

VDCDC1

PGND1

Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage

supply as VINDCDC1, VINDCDC3, and VCC.

VINDCDC2

36

L2

35

33

34

Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.

VDCDC2 feedback voltage sense input. Connect directly to VDCDC2

Power ground for VDCDC2 converter

VDCDC2

PGND2

Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage

supply as VINDCDC1, VINDCDC2, and VCC.

VINDCDC3

5

L3

4

2

3

Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.

VDCDC3 feedback voltage sense input. Connect directly to VDCDC3

Power ground for VDCDC3 converter.

VDCDC3

PGND3

Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. VCC

must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also

supplies serial interface block.

VCC

37

I

Submit Documentation Feedback

11

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

PIN FUNCTIONS FOR TPS650231RSB (continued)

I/O

DESCRIPTION

NAME

NO.

Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected

to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a

range from 0.6 V to VINDCDC1 V.

DEFDCDC1

10

I

Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC2 can also be connected

to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a

range from 0.6 V to VINDCDC2 V.

DEFDCDC2

DEFDCDC3

32

1

I

Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected

to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a

range from 0.6 V to VINDCDC3 V.

DCDC1_EN

DCDC2_EN

DCDC3_EN

25

24

23

I

VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.

VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.

VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.

LDO REGULATOR SECTION

VINLDO

VLDO1

19

20

18

22

15

16

14

12

13

I

O

I

Input voltage for LDO1 and LDO2

Output voltage of LDO1

VLDO2

Output voltage of LDO2

LDO_EN

VBACKUP

VRTC

Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.

Connect the backup battery to this input pin.

I

O

I

Output voltage of the LDO/switch for the real time clock.

Input of system voltage for VRTC switch.

VSYSIN

DEFLD01

DEFLD02

I

Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.

Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.

I

CONTROL AND I²C SECTION

HOT_RESET

TRESPWRON

RESPWRON

PWRFAIL

LOW_BAT

INT

11

26

27

31

21

28

30

29

38

39

I

Push button input that reboots or wakes up the processor via RESPWRON output pin.

Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms.

Open drain system reset output.

I

O

I

Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.

Open drain output of LOW_BAT comparator.

Open drain output

SCLK

Serial interface clock line

SDAT

I/O Serial interface data/address

PWRFAIL_SNS

LOWBAT_SNS

I

Input for the comparator driving the PWRFAIL output.

Input for the comparator driving the LOW_BAT output.

12

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

FUNCTIONAL BLOCK DIAGRAM

TPS650231RSB

V

CC

VSYSIN

VBACKUP

VRTC

BBAT

SWITCH

Thermal

Shutdown

VINDCDC1

L1

DCDC1

Buck Converter

1700 mA

VDCDC1

DEFDCDC1

PGND1

SCLK

SDAT

Serial Interface

VINDCDC2

L2

DCDC1_EN

DCDC2_EN

DCDC3_EN

LDO_EN

DCDC2

Buck Converter

1200 mA

VDCDC2

DEFDCDC2

PGND2

CONTROL

HOT_RESET

RESPWRON

INT

Dynamic

Voltage

Management

VINDCDC3

L3

LOWBAT_SNS

PWRFAIL_SNS

LOW_BATT

DCDC3

Buck Converter

1000 mA

VDCDC3

DEFDCDC3

PGND3

UVLO

VREF

OSC

PWRFAIL

TRESPWRON

LDO1

200 mA

VLDO1

VINLDO

VLDO2

DEFLDO1

DEFLDO2

LDO2

200 mA

AGND1

AGND2

Submit Documentation Feedback

13

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

PIN ASSIGNMENT FOR TPS650231YFF

(BOTTOM VIEW)

VLDO1

VINLDO

VLDO2

AGND

VBACKUP

DEFLDO2

DEFLDO1

VDCDC1

PGND1

A7

A6

A5

LDO_EN

DCDC2_EN

VSYSIN

PGND1

DCDC3_EN

Trespwron

DCDC1_EN

VRTC

DEFDCDC1

L1

SDAT

VDCDC2

Vcc

VINDCDC13

A4

DEFDCDC2

PGND2

L2

VINDCDC2

VDCDC3

L3

VINDCDC13

A3

A2

PWRFAIL

_SNS

SCLK

PGND3

AGND

L3

/PWRFAIL

DEFDCDC3

PGND3

C1

A1

E1

D1

B1

G1

F1

PIN FUNCTIONS FOR TPS650231YFF

I/O

DESCRIPTION

NAME

SWITCHING REGULATOR SECTION

NO.

AGND

B1, E6

Analog ground. All analog ground pins are connected internally on the chip.

A3,

A4,

B4,

C4

Input voltage for VDCDC1 and VDCDC3 step-down converter. This must be connected to the same

voltage supply as VINDCDC2 and VCC.

VINDCDC13

I

A5,

B5,

C5

L1

O

I

Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.

VDCDC1 feedback voltage sense input. Connect directly to VDCDC1

Power ground for VDCDC1 converter.

VDCDC1

PGND1

A7

A6,

B6,

C6

D1,

D2,

D3

Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage

supply as VINDCDC13 and VCC.

VINDCDC2

I

E1,

E2, E3

L2

O

I

Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.

VDCDC2 feedback voltage sense input. Connect directly to VDCDC2

Power ground for VDCDC2 converter

VDCDC2

PGND2

E4

F1,

F2, F3

L3

A2, B3

C3

O

I

Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.

VDCDC3 feedback voltage sense input. Connect directly to VDCDC3

Power ground for VDCDC3 converter.

VDCDC3

PGND3

A1, B2

14

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

PIN FUNCTIONS FOR TPS650231YFF (continued)

I/O

DESCRIPTION

NAME

NO.

Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. VCC

must be connected to the same voltage supply as VINDCDC13 and VINDCDC2. VCC also supplies the

serial interface block.

VCC

D4

I

Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected

to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a

range from 0.6 V to VINDCDC1 V.

DEFDCDC1

DEFDCDC2

DEFDCDC3

D5

G3

C1

I

This pin needs to be connected to a resistor divider between VDCDC2 and GND. The output voltage of

the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V.

Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected

to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a

range from 0.6 V to VINDCDC3 V.

DCDC1_EN

DCDC2_EN

DCDC3_EN

F5

F6

G5

I

VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.

VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.

VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.

LDO REGULATOR SECTION

VINLDO

VLDO1

F7

G7

E7

G6

D7

E5

D6

B7

C7

I

O

I

Input voltage for LDO1 and LDO2

Output voltage of LDO1

VLDO2

Output voltage of LDO2

LDO_EN

VBACKUP

VRTC

Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.

Connect the backup battery to this input pin.

I

O

I

Output voltage of the LDO/switch for the real time clock.

Input of system voltage for VRTC switch.

VSYSIN

DEFLD01

DEFLD02

I

Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.

Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.

I

CONTROL AND I²C SECTION

TRESPWRON

PWRFAIL

SCLK

G4

G1

G2

F4

I

O

I

Connect a 1nF capacitor from this pin to GND.

Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.

Serial interface clock line

SDAT

I/O Serial interface data/address

Input for the comparator driving the PWRFAIL output.

PWRFAIL_SNS

C2

I

Submit Documentation Feedback

15

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

FUNCTIONAL BLOCK DIAGRAM FOR TPS650231YFF

VSYSIN

L3

DCDC3

THERMAL

SHUTDOWN

VDCDC3

DEFDCDC3

STEP -DOWN

CONVERTER

VCC

VBACKUP

VRTC

PGND3

BBAT

SWITCH

VINDCDC13

L1

VDCDC1

DEFDCDC1

DCDC1

SCLK

SDAT

STEP-DOWN

CONVERTER

PGND1

Serial Interface

VINDCDC2

DCDC1_EN

DCDC2_EN

DCDC3_EN

LDO_EN

L2

VDCDC2

DEFDCDC2

DCDC2

CONTROL

STEP-DOWN

CONVERTER

Dynamic

Voltage

Scaling

PGND2

VLDO1

PWRFAIL_SNS

/PWRFAlL

UVLO

VREF

OSC

200 mA LDO

TRESPWRON

AGND

VINLDO

DEFLDO1

DEFLDO2

VLDO2

200 mA LDO

16

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

TYPICAL CHARACTERISTICS

Graphs were taken using the EVM with the following inductor/output capacitor combinations:

CONVERTER

VDCDC1

INDUCTOR

LQH32PN1R5

LQH32PN2R2

OUTPUT CAPACITOR

JMK107BJ106

OUTPUT CAPACITOR VALUE

2 × 10 mF

VDCDC2

JMK107BJ106

2 × 10 mF

VDCDC3

JMK107BJ106

2 × 10 mF

Table 1. Table of Graphs

FIGURE

1, 2, 3, 4, 5, 6

7, 8

h

Efficiency

vs Output current

Output voltage

vs Output current at 85°C

Line transient response

Load transient response

VDCDC2 PFM operation

9, 10, 11

12, 13, 14

15

VDCDC2 low ripple PFM operation

VDCDC2 PWM operation

16

17

Startup VDCDC1, VDCDC2 and VDCDC3

Startup LDO1 and LDO2

18

19

Line transient response

20, 21, 22

23, 24, 25

Load transient response

DCDC1: EFFICIENCY

vs

DCDC1: EFFICIENCY

vs

OUTPUT CURRENT

100

V = 2.5 V

I

T = 25°C,

A

90

80

70

60

50

40

30

20

V

= 1.2 V,

O

PWM Mode

V = 3 V

I

V = 2.5 V

I

80

V = 3.6 V

I

V = 3 V

I

70

60

50

40

30

20

V = 4.2 V

I

V = 3.6 V

I

V = 5 V

I

V = 4.2 V

I

V = 5 V

I

T

= 25°C,

= 1.2 V,

A

V

O

PFM Mode

10

0

10

0

0.01

0.1

1

10

100

- Output Current - mA

1 k

10 k

0.01

0.1

1

10

- Output Current - mA

100

1 k 10 k

I

O

Figure 1.

Figure 2.

Submit Documentation Feedback

17

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

DCDC2: EFFICIENCY

vs

DCDC2: EFFICIENCY

vs

OUTPUT CURRENT

100

90

T

= 25°C,

= 1.8 V,

V = 3 V

I

A

90

80

70

60

50

40

30

20

V

O

PWM Mode

80

70

60

50

40

30

20

V = 2.5 V

I

V = 3.6 V

I

V = 2.5 V

I

V = 3 V

I

V = 4.2 V

I

V = 3.6 V

I

V = 5 V

I

V = 4.2 V

I

V = 5 V

I

T

= 25°C,

= 1.8 V,

A

V

O

PFM Mode

10

0

10

0

0.01

0.1

1

10

100

- Output Current - mA

1 k

10 k

0.01

0.1

1

10

100

- Output Current - mA

1 k

10 k

I

O

I

O

Figure 3.

Figure 4.

DCDC3: EFFICIENCY

vs

DCDC3: EFFICIENCY

vs

OUTPUT CURRENT

100

90

100

T

= 25°C,

= 1.8 V,

V = 2.5 V

I

A

90

80

70

60

50

40

30

20

V

V = 2.5 V

I

O

PWM Mode

80

70

60

50

40

30

20

V = 3 V

I

V = 3 V

I

V = 3.6 V

I

V = 3.6 V

I

V = 4.2 V

I

V = 4.2 V

I

V = 5 V

I

V = 5 V

I

T

= 25°C,

= 1.8 V,

A

V

O

PFM Mode

10

0

10

0

0.01

0.1

1

10

100

- Output Current - mA

1 k

10 k

0.01

0.1

1

10

100

- Output Current - mA

1 k

10 k

I

O

Figure 5.

Figure 6.

18

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

DCDC2: OUTPUT VOLTAGE

vs

DCDC3: OUTPUT VOLTAGE

vs

OUTPUT CURRENT at 85°C

3.3

3.267

3.234

3.201

3.168

3.135

3.4

T_A= 85°C

V_I= 3.8 V

DEFDCDC3 = VINDCDC3

3.35

3.3

V_I= 3.8 V

V_I= 3.7 V

3.25

3.2

V_I= 3.5 V

V_I= 3.6 V

V_I= 3.5 V

3.15

3.1

T_A= 85°C

DEFDCDC2 = VINDCDC2

0.1

1

10

0.1

1

10

I_O- Output Current - A

Figure 7.

Figure 8.

VDCDC1 LINE TRANSIENT RESPONSE

VDCDC2 LINE TRANSIENT RESPONSE

C1 High

4.72 V

C1 High

4.02 V

C1 Low

3.72 V

C1 Low

3.02 V

V = 3 V to 4 V,

I

V_I= 3.7 V to 4.7 V

V

= 1.8 V, I = 100 mA;

O

V_O= 1.2 V, I_O= 100 mA

C2 Pk-Pk

24.7 mV

C2 Pk-Pk

128 mV

DEFDCDC2 = resistor divider; set for V = 1.8 V,

O

DEFDCDC1 = GND

PWM Mode

C2 Mean

1.20701 V

C2 Mean

1.8002 V

Figure 9.

Figure 10.

Submit Documentation Feedback

19

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

VDCDC3 LINE TRANSIENT RESPONSE

VDCDC1 LOAD TRANSIENT RESPONSE

C4 High

1.56 A

C1 High

4.62 V

C4 Low

120 mA

C1 Low

3.62 V

V_I= 3.8 V, V_O= 1.2 V,

I_O= 170 mA to 1530 mA

V = 3.6 V to 4.6 V,

I

C2 Pk-Pk

166 mV

V

= 3.3 V, I = 100 mA,

O

C2 Pk-Pk

91 mV

O

DEFDCDC1 = VINDCDC3,

PWM Mode

C2 Mean

3.2993 V

C2 Mean

1.2046 V

Figure 11.

Figure 12.

VDCDC3 LOAD TRANSIENT RESPONSE

VDCDC2 LOAD TRANSIENT RESPONSE

V_I= 3.8 V, V_O= 3.3 V,

I_O= 120 mA to 720 mA

C4 High

720 mA

C4 High

1.12 A

C4 Low

80 mA

C4 Low

80 mA

V_I= 3.8 V, V_O= 1.8 V,

I_O= 120 mA to 1080 mA

C2 Pk-Pk

194 mV

C2 Pk-Pk

147 mV

C2 Mean

3.2961 V

C2 Mean

1.7993 V

Figure 13.

Figure 14.

20

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

VDCDC2 OUTPUT VOLTAGE RIPPLE

V_I= 3.8 V, V_O= 1.8 V,

I_LOAD= 1 mA; PFM Mode

C2 Pk-Pk

20.6 mV

C2 Mean

1.81186 V

Figure 15.

Figure 16.

VDCDC2 OUTPUT VOLTAGE RIPPLE

STARTUP VDCDC1, VDCDC2, AND VDCDC3

mV

Figure 17.

Figure 18.

Submit Documentation Feedback

21

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

STARTUP LDO1 AND LDO2

LDO1 LINE TRANSIENT RESPONSE

ENABLE

C1 High

3.82 V

C1 Low

3.29 V

V_CC= 3.8 V, V_ILDO = 3.3 V to 3.8 V

V_O= 2.1 V, I_O= 25 mA

LDO1

C2 Pk-Pk

4.2 mV

C2 Mean

2.10252 V

LDO2

Figure 19.

LDO2 LINE TRANSIENT RESPONSE

Figure 20.

VRTC LINE TRANSIENT RESPONSE

I

= 10 mA

= 3 V

O

I

= 25 mA

= 3.3 V

Ch1 = V

Ch2 = V

O

I

Ch1 = V

Ch2 = V

I

V

T

C1 High

3.82 V

O

V

T

C1 High

4.51 V

O

= 25^oC

O

= 25^oC

A

C1 Low

3.28 V

C1 Low

3.99 V

C2 PK-PK

22.8 mV

C2 PK-PK

6.1 mV

C2 Mean

2.98454 V

C2 Mean

3.29828 V

Figure 21.

Figure 22.

22

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

LDO1 LOAD TRANSIENT RESPONSE

LDO2 LOAD TRANSIENT RESPONSE

C4 High

184 mA

C4 High

180 mA

C4 Low

16 mA

C4 Low

16 mA

V_CC= 3.8 V, V_I= 3.3 V, V_O= 2.1 V,

I_O= 20 mA to 180 mA

C2 Pk-Pk

53.1 mV

C2 Pk-Pk

78.1 mV

C2 Mean

2.10024 V

C2 Mean

3.29606 V

V_CC= 3.8 V, V_I= 3.8 V, V_O= 3.3 V,

I_O= 20 mA to 180 mA

Figure 23.

Figure 24.

VRTC LOAD TRANSIENT RESPONSE

C4 High

21.4 mA

C4 Low

-1.4 mA

C2 PK-PK

76 mV

C2 Mean

2.9762 V

V = 3.8 V

I

Ch2 = V

Ch4 = I

V

T

= 3 V

= 25^oC

O

A

Figure 25.

Submit Documentation Feedback

23

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

DETAILED DESCRIPTION

VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY

The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (i.e. for a

Real Time Clock). The TPS650231 asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is

selected from a priority scheme based on the VSYSIN and VBACKUP inputs.

When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input via a PMOS switch

and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30 mA, which

should be considered when using VRTC. VSYSIN can be connected to any voltage source with the appropriate

input voltage, including VCC or, if set to 3.3 V output, DCDC2 or DCDC3. When VSYSIN falls below 2.65 V or

shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to either

VBACKUP or the output of a dedicated 3V/30mA LDO. Texas Instruments recommends connecting VSYSIN to

VCC or ground - VCC if a non-replaceable primary cell is connected to VBACKUP and ground if the VRTC

output will float.

If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to

VBACKUP via a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which should be

considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any

battery that provides a voltage between 2.65 V and 6 V (i.e. a single Li-Ion cell or a single boosted NiMH battery)

is acceptable, to supply the VRTC output. In systems with no backup battery, the VBACKUP pin should be

connected to GND.

If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V/30-mA LDO, driven from

VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V.

Inside TPS650231 there is a switch (Vmax switch) which selects the higher voltage between VCC and

VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output

of the Vmax switch are:

•

INT output

RESPWRON output

HOT_RESET input

LOW_BATT output

PWRFAIL output

Enable pins for dc-dc converters, LDO1 and LDO2

Undervoltage lockout comparator (UVLO)

Reference system with low frequency timing oscillators

LOW_BATT and PWRFAIL comparators

The main 2.25-MHz oscillator, and the I²C™ interface are only powered from V_CC

.

24

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

V

VSYSIN

CC

VBACKUP

V

ref

V_VSYSIN

V_VBACKUP

V_VSYSIN

EN

VRTC

LDO

V_VBACKUP

priority

#1

priority

#2

priority

#3

VRTC

RESPWRON

V

ref

A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%

B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%

Figure 26.

STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3

The TPS650231 incorporates three synchronous step-down converters operating typically at 2.25MHz fixed

frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the

converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). The

VDCDC1 converter is capable of delivering 1.7A output current, the VDCDC2 converter is capable of delivering

1.2A and the VDCDC3 converter delivers up to 800mA.

The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. For

DEFDCDC1 and DEFDCDC3, the pins can either be connected to GND, VCC or to a resistor divider between

the output voltage and GND.

The VDCDC1 converter defaults to 1.2V or 1.6V depending on the DEFDCDC1 configuration pin, if DEFDCDC1

is tied to ground the default is 1.2V, if it is tied to VCC the default is 1.6V. When the DEFDCDC1 pin is

connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC1 V. See the

application section for more details. The core voltage can be reprogrammed via the serial interface in the range

of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst any

programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE

and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions.

The DEFDCDC2 pin does not have the logic function in parallel and always needs to be connected with a

resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.

The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3

is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is

connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The

step-down converter outputs (when enabled) are monitored by Power Good comparators, the outputs of which

are available via the serial interface. The outputs of the DC-DC converters can be optionally discharged via

on-chip 300Ω resistors when the DC-DC converters are disabled.

Submit Documentation Feedback

25

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

During PWM operation the converters use a unique fast response voltage mode controller scheme with input

voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output

capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is

turned on and the inductor current ramps up until the comparator trips and the control logic will turn off the

switch. The current limit comparator will also turn off the switch in case the current limit of the P-channel switch is

exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier

is turned on and the inductor current will ramp down. The next cycle will be initiated by the clock signal again

turning off the N-channel rectifier and turning on the P-channel switch.

The three DC-DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A

180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3

switch turn on decreases the input RMS current and smaller input capacitors can be used. The phase of the

three converters can be changed using the CON_CTRL register.

POWER SAVE MODE OPERATION

As the load current decreases, the converters enter the power save mode operation. During power save mode,

the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal

for one burst cycle. However, the frequency between different burst cycles depends on the actual load current

and is typically far less than the switching frequency with a minimum quiescent current to maintain high

efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode

the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM

is calculated as follows:

VINDCDC1

I

=

PFMDCDC1 enter

24 W

VINDCDC2

I

=

PFMDCDC2 enter

26 W

VINDCDC3

PFMDCDC3 enter

39 W

(1)

During the power save mode the output voltage is monitored with a comparator, and by maximum skip burst

width. As the output voltage falls below the threshold, set to the nominal V_O, the P-channel switch turns on and

the converter effectively delivers a constant current defined as follows.

VINDCDC1

I

=

PFMDCDC1 leave

18 W

VINDCDC2

I

=

PFMDCDC2 leave

20 W

VINDCDC3

=

PFMDCDC3 leave

29 W

(2)

If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the

other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage

has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode

if either of the following conditions are met:

1. the output voltage drops 2% below the nominal V_Odue to increasing load current

2. the PFM burst time exceeds 16 × 1/fs (7.11 ms typical).

26

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

These control methods reduce the quiescent current to typically 14 mA per converter, and the switching activity to

a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal

output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator

delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The

PSM is disabled through the I²C interface to force the individual converters to stay in fixed frequency PWM

mode.

LOW RIPPLE MODE

Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in

PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is

reduced, depending on the actual load current. The lower the actual output current on the converter, the lower

the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage

ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is

used to keep the switching frequency above the audible range in PFM mode down to a low output current.

SOFT START

Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft

start is realized by using a low current to initially charge the internal compensation capacitor. The soft start time

is typically 750 ms if the output voltage ramps from 5% to 95% of the final target value. If the output is already

precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a

short delay of typically 170 ms between the converter being enabled and switching activity actually starting. This

allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent

discharging of the output while the internal soft start ramp catches up with the output voltage.

100% DUTY CYCLE LOW DROPOUT OPERATION

The TPS650231 converters offer a low input to output voltage difference while still maintaining operation with the

use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly

useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole

battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current

and output voltage. It is calculated as:

ǒ_r

_{max ) R}Ǔ

Vin

+ Vout

) Iout

max

min

DS(on)

L

(3)

with:

Iout_max= maximum load current (Note: ripple current in the inductor is zero under these conditions)

r_DS(on)max = maximum P-channel switch r_DS(on)

R_L= DC resistance of the inductor

Vout_min= nominal output voltage minus 2% tolerance limit

ACTIVE DISCHARGE WHEN DISABLED

When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or

OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is

individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the

VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as

the converters are disabled.

POWER GOOD MONITORING

All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.

Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%

hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An

interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when

the converters are disabled and the relevant PGOODZ register bits indicate that power is good.

Submit Documentation Feedback

27

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

LOW DROPOUT VOLTAGE REGULATORS

The low dropout voltage regulators are designed to operate well with low value ceramic input and output

capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of

300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the

LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and

LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect

external regulators in parallel in systems with a backup battery. The TPS650231 step-down and LDO voltage

regulators automatically power down when the V_CCvoltage drops below the UVLO threshold or when the junction

temperature rises above 160°C.

POWER GOOD MONITORING

Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the

relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these

comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any

voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the

relevant PGOODZ register bits indicate that power is good.

UNDERVOLTAGE LOCKOUT

The undervoltage lockout circuit for the five regulators on the TPS650231 prevents the device from

malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and

LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV)

hysteresis. Note that when any of the dc-dc converters are running, there is an input current at the VCC pin,

which is up to 3 mA when all three converters are running in PWM mode. This current needs to be taken into

consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS650231

internal analog circuitry supply.

POWER-UP SEQUENCING

The TPS650231 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved

by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs.

The relevant control pins are described in Table 2.

Table 2. Control Pins and Status Outputs for DC-DC Converters

PIN NAME

I/O

FUNCTION

Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.8 V,

DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V.

DEFDCDC3

I

Feedback pin of the VDCDC2 switching converter, connected to a resistive divider. The output voltage can be set

between 0.6V and VINDCDC2 V.

DEFDCDC2

DEFDCDC1

I

Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2 V,

DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V.

DCDC3_EN

DCDC2_EN

DCDC1_EN

I

Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter

Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter

Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter

TPS650231RSB only:

The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any

TPS650231 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of VDCDC1

to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the TPS650231.

HOT_RESET

I

TPS650231RSB only:

RESPWRON is held low when power is initially applied to the TPS650231. The VRTC voltage is monitored:

RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the

TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.

RESPWRON

O

I

TRESPWRON

Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms).

28

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

SYSTEM RESET + CONTROL SIGNALS

The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The

RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for t_nrespwron

seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). t_nrespwronis set by an

external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the

HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.

The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and

LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)

hysteresis.

The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET

is asserted. Other I²C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with

one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout

(UVLO) condition, or RESPWRON active.

The RESPWRON, HOT_RESET, LOW_BAT and LOWBAT_SNS pins are not available in TPS650231YFF.

DEFLDO1 and DEFLDO2

These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to

the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of

both LDOs can be changed during operation with the I²C interface as described in the interface description.

Table 3.

DEFLDO2

DEFLDO1

VLDO1

1.3 V

2.8 V

1.3 V

2.1 V

VLDO2

3.3 V

1.8 V

3.3 V

0

1

0

1

0

1

Interrupt Management and the INT Pin

The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and the LDOs. The

INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin

remains active (low state) during power up as long as all enabled power rails are below their regulation limit.

Once the last enabled power rail is within regulation, the INT pin transitions to a high state.

During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the

corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT

transitions back to a high state.

While INT is in an active low state, reading the PGOODZ register via the I²C bus forces INT into a high-Z state.

Since this pin requires an external pull-up resistor, the INT pin transitions to a logic high state even though the

supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the

power rail is out of regulation.

Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts

since this provides the POWER_OK function. If none of the DCDC converters or LDOs are enabled, /INT defaults

to a low state independently of the settings of the MASK register.

Submit Documentation Feedback

29

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

TIMING DIAGRAMS

Figure 27. HOT_RESET Timing (TPS650231RSB only)

2.35V

1.9V

1.2V

2.47V

1.9V

V

CC

0.8V

UVLO*

VRTC

2.52V

2.4V

3.0V

RESPWRON

DCDCx_EN

t_NRESPWRON

Ramp within

800 μs

V

DCDCx

O

slope depending

on load

LDO_EN

V

LDOx

O

VSYSIN=VBACKUP=GND;

VINLDO=V

CC

*... internal signal

Figure 28. Power-Up and Power-Down Timing

30

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

Figure 29. DVS Timing

SERIAL INTERFACE

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to

400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements and charger status to be monitored.

Register contents remain intact as long as VCC remains above 2 V. The TPS650231 has a 7-bit address:

1001000, other addresses are available upon contact with the factory. Attempting to read data from the register

addresses not listed in this section results in FFh being read out.

Submit Documentation Feedback

31

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start

condition and terminated with a stop condition. When addressed, the TPS650231 device generates an

acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra

clock pulse that is associated with the acknowledge bit. The TPS650231 device must pull down the DATA line

during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the

acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock

pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of

data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this

case, the slave TPS650231 device must leave the data line high to enable the master to generate the stop

condition

DATA

CLK

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 30. Bit Transfer on the Serial Interface

CE

DATA

CLK

S

P

START Condition

STOP Condition

Figure 31. START and STOP Conditions

SCLK

SDAT

A6

A5

A4

A0

ACK

0

R7

R6

R5

R0 ACK

0

D7

D6

D5

D0 ACK

R/W

0

Register Address

Stop

Start

Slave Address

Data

Note: SLAVE = TPS650231

Figure 32. Serial I/f WRITE to TPS650231 Device

32

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

SCLK

SDAT

A6

A0

R/W ACK

R7

R0 ACK

0

A6

A0

R/W ACK

D7

D0 ACK

0

1

0

Slave

Drives

the Data

Stop

Register

Address

Master

Drives

ACK and Stop

Start

Slave Address

Repeated

Start

Note: SLAVE = TPS650231

Figure 33. Serial I/f READ from TPS650231: Protocol A

SCLK

SDA

A6

A0

R/W ACK

R7

R0 ACK

A6

A0

R/W ACK D7

D0

ACK

0

1

0

Stop Start

Stop

Slave

Drives

the Data

Register

Address

Master

Drives

ACK and Stop

Start

Slave Address

Note: SLAVE = TPS650231

Figure 34. Serial I/f READ from TPS650231: Protocol B

DATA

t

(BUF)

t

h(STA)

t

(LOW)

t

r

t

f

CLK

t

(HIGH)

su(STA)

t

su(STO)

h(STA)

t

su(DATA)

h(DATA)

STO

STA

STO

Figure 35. Serial I/f Timing Diagram

Submit Documentation Feedback

33

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

MIN MAX UNIT

Operating conditions:

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5V to 5.5V,

VBACKUP = 3.0V,

T_A= -40 °C to +85 °C

f_MAX

Clock frequency

400

kHz

ns

t_wH(HIGH)

t_wL(LOW)

t_R

Clock high time

600

Clock low time

1300

DATA and CLK rise time

300

t_F

DATA and CLK fall time

t_h(STA)

t_su(DATA)

t_h(DATA)

t_su(DATA)

t_su(STO)

t_(BUF)

Hold time (repeated) START condition (after this period the first clock pulse is generated)

600

Setup time for repeated START condition

Data input hold time

100

Data input setup time

100

STOP condition setup time

Bus free time

600

1300

VERSION. Register Address: 00h (read only)

VERSION

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

function

0

1

0

1

Read/Write

R

34

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

PGOODZ. Register Address: 01h (read only)

PGOODZ

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

function

LOWBATTZ

PGOODZ

VDCDC1

PGOODZ

VDCDC2

PGOODZ

VDCDC3

PGOODZ

LDO2

PGOODZ

LDO1

PWRFAILZ

LOWBATT

LOWBATTZ

R

PGOODZ

VDCDC1

PGOODZ

VDCDC2

PGOODZ

VDCDC3

PGOODZ

LDO2

PGOODZ

LDO1

Set by signal

PWRFAIL

Default value

loaded by:

PGOOD

VDCDC1

PGOOD

VDCDC2

PGOOD

VDCDC3

PGOOD

LDO2

PGOOD

LDO1

PWRFAILZ

R

Read/Write

R

Bit 7 PWRFAILZ:

0 = indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.

1 = indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.

Bit 6 LOWBATTZ:

0 = indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.

1 = indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.

Bit 5 PGOODZ VDCDC1:

0 = indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if

the VDCDC1 converter is disabled.

1 = indicates that the VDCDC1 converter output voltage is below its target regulation voltage

Bit 4 PGOODZ VDCDC2:

0 = indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if

the VDCDC2 converter is disabled.

1 = indicates that the VDCDC2 converter output voltage is below its target regulation voltage

Bit 3 PGOODZ VDCDC3: .

0 = indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if

the VDCDC3 converter is disabled and during a DVM controlled output voltage transition

1 = indicates that the VDCDC3 converter output voltage is below its target regulation voltage

Bit 2 PGOODZ LDO2:

0 = indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is

disabled.

1 = indicates that LDO2 output voltage is below its target regulation voltage

Bit 1 PGOODZ LDO1

0 = indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is

disabled.

1 = indicates that the LDO1 output voltage is below its target regulation voltage

Submit Documentation Feedback

35

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

MASK. Register Address: 02h (read/write)

Default Value: C0h

MASK

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

function

MASK

PWRFAILZ

MASK

LOWBATTZ

MASK

VDCDC1

MASK

VDCDC2

MASK

VDCDC3

MASK

LDO2

MASK

LDO1

Default

1

0

Default value

loaded by:

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

Read/Write

The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1

masks PGOODZ<n>.

REG_CTRL. Register Address: 03h (read/write)

Default Value: FFh

The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of

the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition

resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The

REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.

REG_CTRL

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

function

VDCDC1

ENABLE

VDCDC2

ENABLE

VDCDC3

ENABLE

LDO2

ENABLE

LDO1

ENABLE

Default

1

Set by signal

DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ

LDO_ENZ

Default value

loaded by:

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

Read/Write

Bit 5 VDCDC1 ENABLE

DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1

converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The

bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when

DCDC1_EN returns high.

Bit 4 VDCDC2 ENABLE

DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2

converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The

bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when

DCDC2_EN returns high.

Bit 3 VDCDC3 ENABLE

DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3

converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The

bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when

DCDC3_EN returns high.

Bit 2 LDO2 ENABLE

LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to

1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when

the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.

Bit 1 LDO1 ENABLE

LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to

1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when

the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.

36

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

CON_CTRL. Register Address: 04h (read/write)

Default Value: B1h

CON_CTRL

B7

B6

B5

B4

B3

B2

B1

B0

Bit name and

function

DCDC2

PHASE1

DCDC2

PHASE0

DCDC3

PHASE1

DCDC3

PHASE0

LOW

RIPPLE

FPWM

DCDC2

FPWM

DCDC1

FPWM

DCDC3

Default

1

0

1

0

Default value

loaded by:

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

UVLO

R/W

Read/Write

The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low

output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to

minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is

taken as the reference and consequently has a fixed zero phase shift.

DCDC2 CONVERTER

DELAYED BY

DCDC3 CONVERTER

DELAYED BY

CON_CTRL<7:6>

CON_CTRL<5:4>

00

01

10

11

zero

00

01

10

11

zero

1/4 cycle

1/2 cycle

3/4 cycle

1/4 cycle

1/2 cycle

3/4 cycle

Bit 3 LOW RIPPLE:

0 =

1 =

PFM mode operation optimized for high efficiency for all converters

PFM mode operation optimized for low output voltage ripple for all converters

Bit 2 FPWM DCDC2:

0 =

1 =

DCDC2 converter operates in PWM / PFM mode

DCDC2 converter is forced into fixed frequency PWM mode

Bit 1 FPWM DCDC1:

0 =

1 =

DCDC1 converter operates in PWM / PFM mode

DCDC1 converter is forced into fixed frequency PWM mode

Bit 0 FPWM DCDC3:

0 =

1 =

DCDC3 converter operates in PWM / PFM mode

DCDC3 converter is forced into fixed frequency PWM mode

Submit Documentation Feedback

37

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

CON_CTRL2. Register Address: 05h (read/write)

Default Value: 40h

CON_CTRL2

B7

GO

0

B6

B5

B4

B3

B2

B1

B0

Bit name and

function

Core adj

allowed

DCDC2

discharge

DCDC1

discharge

DCDC3

discharge

Default

1

0

Default value

loaded by:

UVLO +

DONE

RESET(1)

UVLO

R/W

UVLO

R/W

UVLO

R/W

Read/Write

R/W

The CON_CTRL2 register can be used to take control the inductive converters.

RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:

undervoltage lockout (UVLO)

HOT_RESET pulled low

RESPWRON active

VRTC below threshold

•

Bit 7

GO:

0 = no change in the output voltage for the DCDC1 converter

1 = the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with

the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is

complete. The transition is considered complete in this case when the desired output voltage

code has been reached, not when the VDCDC1 output voltage is actually in regulation at the

desired voltage.

Bit 6

CORE ADJ Allowed:

0 = the output voltage is set with the I²C register

1 = DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When

connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up

Bit 2– 0 0 = the output capacitor of the associated converter is not actively discharged when the converter is

disabled

1 = the output capacitor of the associated converter is actively discharged when the converter is

disabled. This decreases the fall time of the output voltage at light load

38

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

DEFCORE. Register Address: 06h (read/write

Default Value: 14h/1Eh

DEFCORE

B7

B6

B5

B4

CORE4

1

B3

B2

B1

B0

Bit name and

function

CORE3

CORE2

CORE1

CORE0

Default

0

DEFDCDC1 DEFDCDC1 DEFDCDC1 DEFDCDC1

Default value

loaded by:

RESET(1)

R/W

RESET(1)

R/W

RESET(1)

R/W

RESET(1)

R/W

RESET(1)

R/W

Read/Write

RESET(1): DEFCORE is reset to its default value by one of these events:

•

undervoltage lockout (UVLO)

HOT_RESET pulled low

RESPWRON active

VRTC below threshold

CORE4 CORE3 CORE2 CORE1 CORE0

VDCDC1

0.8 V

CORE4

CORE3

CORE2

CORE1 CORE0

VDCDC1

1.2 V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.825 V

0.85 V

0.875 V

0.9 V

1.225 V

1.25 V

1.275 V

1.3 V

0.925 V

0.95 V

0.975 V

1 V

1.325 V

1.35 V

1.375 V

1.4 V

1.025 V

1.05 V

1.075 V

1.1 V

1.425 V

1.45 V

1.475 V

1.5 V

1.125 V

1.15 V

1.175 V

1.525 V

1.55 V

1.6 V

Submit Documentation Feedback

39

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

DEFSLEW. Register Address: 07h (read/write)

Default Value: 06h

DEFSLEW

B7

B6

B5

B4

B3

B2

SLEW2

1

B1

SLEW1

1

B0

SLEW0

0

Bit name and

function

Default

Default value

loaded by:

UVLO

R/W

UVLO

R/W

UVLO

R/W

Read/Write

SLEW2

SLEW1

SLEW0

VDCDC1 SLEW RATE

0.225 mV/ms

0.45 mV/ms

0.9 mV/ms

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.8 mV/ms

3.6 mV/ms

7.2 mV/ms

14.4 mV/ms

Immediate

40

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

LDO_CTRL. Register Address: 08h (read/write)

Default Value: set with DEFLDO1 and DEFLDO2

LDO_CTRL

B7

B6

LDO2_2

DEFLDOx

UVLO

B5

LDO2_1

DEFLDOx

UVLO

B4

LDO2_0

DEFLDOx

UVLO

B3

B2

LDO1_2

DEFLDOx

UVLO

B1

LDO1_1

DEFLDOx

UVLO

B0

LDO1_0

DEFLDOx

UVLO

Bit name and

function

RSVD

Default

Default value

loaded by:

Read/Write

R/W

The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and

LDO_CTRL[3] are reserved and should always be written to 0.

The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.

LDO2 OUTPUT

VOLTAGE

LDO1 OUTPUT

VOLTAGE

LDO2_2

LDO2_1

LDO2_0

LDO1_2

LDO1_1

LDO1_0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.05 V

1.2 V

1.3 V

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 V

1.1 V

1.3 V

2.1 V

2.2 V

2.6 V

2.8 V

3.15 V

DESIGN PROCEDURE

Inductor Selection for the DC-DC Converters

Each of the converters in the TPS650231 typically use a 2.2 mH output inductor. Larger or smaller inductor

values are used to optimize the performance of the device for specific operation conditions. The selected

inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance

influences directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be

selected for highest efficiency.

For a fast transient response, a 2.2-mH inductor in combination with a 22-mF output capacitor is recommended.

Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed

because during heavy load transient the inductor current rises above the value calculated under Equation 4.

Vout

Vin

1 *

DI + Vout

L

L ƒ

(4)

(5)

DI

L

I

+ I

)

outmax

Lmax

2

with:

f = Switching Frequency (2.25 MHz typical)

L = Inductor Value

ΔI_L= Peak-to-Peak inductor ripple current

I_LMAX= Maximum Inductor current

The highest inductor current occurs at maximum Vin.

Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents

versus a comparable shielded inductor.

Submit Documentation Feedback

41

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

A more conservative approach is to select the inductor current rating just for the maximum switch current of the

TPS650231 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core

material from inductor to inductor differs and has an impact on the efficiency especially at high switching

frequencies.

See Table 4 and the typical applications for possible inductors.

Table 4. Tested Inductors

DEVICE

INDUCTOR

VALUE

TYPE

COMPONENT SUPPLIER

2.2 mH

1.5 mH

LPS4012-222LMB

VLCF4020T-2R2N1R7

LQH32PN2R2NN0

PSI25201T-2R2

Coilcraft

TDK

All Converters

Murata

Cyntec

Murata

For DCDC2 or

DCDC3

For DCDC1

LQH32PN1R5NN0

Output Capacitor Selection

The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the

TPS650231 allow the use of small ceramic capacitors with a typical value of 10 mF for each converter without

having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low

ESR values have the lowest output voltage ripple and are recommended. See Table 5 for recommended

components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application

requirements. Just for completeness, the RMS ripple current is calculated as:

V

out

1 -

V

1

in

x

I

= V

x

RMSCout

out

L x ¦

2 x Ö3

(6)

At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the

sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and

discharging the output capacitor:

V

out

1 -

V

in

1

DV

= V

x

+ ESR

out

(

)

L x ¦

8 x C

x ¦

out

(7)

Where the highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output

capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The

typical output voltage ripple is less than 1% of the nominal output voltage.

Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering and minimizing the interference with other circuits caused by high input

voltage spikes. Each dc-dc converter requires a 10-mF ceramic input capacitor on its input pin VINDCDCx. The

input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the

input for the dc-dc converters. A filter resistor of up to 10R and a 1-mF capacitor is used for decoupling the VCC

pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow via

this resistor into the VCC pin when all converters are running in PWM mode.

42

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

Table 5. Possible Capacitors

CAPACITOR VALUE

CASE SIZE

COMPONENT SUPPLIER

TDK C2012X5R0J226MT

Taiyo Yuden JMK212BJ226MG

Taiyo Yuden JMK212BJ106M

TDK C2012X5R0J106M

COMMENTS

Ceramic

22 mF

22mF

0805

0603

10 mF

Taiyo Yuden JMK107BJ106

Output Voltage Selection

The DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins are used to set the output voltage for each step-down

converter. For DEFDCDC1 and DEFDCDC3 there are default voltages defined when the pin is tied to a logic low

or logic high signal. See Table 6for the default voltages if the pins are pulled to GND or to Vcc. If a different

voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 36.

The output voltage of VDCDC1 is set with the I²C interface. If the voltage is changed from the default, using the

DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1

will not change the voltage set with the register. It is not recommended to change the divider ratio of a resistor

divider connected at DEFDCDC1 or DEFDCDC3 during operation as the internal logic may detect a logic high

signal in error during the change from a high voltage to a lower voltage and will scale the output to the voltage

defined by DEFDCDCx = HIGH. As DEFDCDC2 does not have these default fixed voltages, the resistor divider

can be changed during operation.

Table 6.

LEVEL

VCC

DEFAULT OUTPUT VOLTAGE

1.6 V

1.2 V

3.3 V

1.8 V

DEFDCDC1

GND

VCC

DEFDCDC3

GND

This function is not available on the DCDC2 converter. DEFDCDC2 always needs to be connected to a resistive

divider as shown below.

Using an external resistor divider at DEFDCDCx:

1 Ω

V

(bat)

CC

1 mF

VDCDC3

L3

V

O

VINDCDC3

DCDC3_EN

L

C

I

C

O

R1

R2

DEFDCDC3

AGND PGND

Figure 36. External Resistor Divider

When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input

voltage V_(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MΩ range in order to

maintain a high efficiency at light load.

V_(DEFDCDCx)= 0.6 V

Submit Documentation Feedback

43

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

V

OUT

R1 + R2

R2

V

= V

x

- R2

R1 = R2 x

OUT

DEFDCDCx

(

)

V

DEFDCDCx

(8)

VRTC Output

It is recommended that a 4.7-mF (minimum) capacitor be added to the VRTC pin.

LDO1 and LDO2

The LDOs in the TPS650231 are general-purpose LDOs which are stable using ceramics capacitors. The

minimum output capacitor required is 2.2 mF. The LDOs output voltage can be changed to different voltages

between 1 V and 3.3 V using the I²C interface. The supply voltage for the LDOs needs to be connected to the

VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the highest

efficiency.

TRESPWRON

This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.

The timing is generated by charging and discharging the capacitor with a current of 2 mA between a threshold of

0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.

(1 V - 0.25 V) x C_(reset)

t_(reset)= 2 x 128 x

(

)

2 mA

(9)

Where:

t_(reset)is the reset delay time

C_(reset)is the capacitor connected to the TRESPWRON pin

V_CC-Filter

An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other

analog circuitry. A typical value of 1 Ω and 1 mF is used to filter the switching spikes, generated by the dc-dc

converters. A larger resistor than 10 Ω should not be used because the current into VCC of up to 3 mA causes a

voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off

too early.

44

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

APPLICATION INFORMATION

Typical Configuration for the Texas Instruments® TMS320DM644x DaVinci Processors

TPS650231

Reset Condition of DCDC1

If DEFDCDC1 is connected to ground and DCDC1_EN is pulled high after VINDCDC1 is applied, the output

voltage of DCDC1 defaults to 1.225V instead of 1.2V (high by 2%). Figure 37 illustrates the problem.

VCC/VINDCDC1

DCDC1_EN

1.225 V

VDCDC1

Figure 37. Default DCDC1

Workaround 1: Tie DCDC1_EN to VINDCDC1 (Figure 38)

Submit Documentation Feedback

45

Product Folder Link(s) : TPS650231

TPS650231

SLVSAE3 –AUGUST 2010

www.ti.com

VCC/VINDCDC1

DCDC1_EN

1.20 V

VDCDC1

Figure 38. Workaround 1

Workaround 2: Write the correct voltage to the DEF_CORE register via I²C. This can be done before or after the

converter is enabled. If written before the enable, the only bit changed is DEF_CORE[0]. The voltage will be

1.2V, however, when the enable is pulled high (Figure 39).

VCC/VINDCDC1

DCDC1_EN

I2C Bus

DEF_CORE

VDCDC1

??

0x1F

0x1F 0x1E

0x10

0x11

1.225 V

0x10

1.20 V

Write DEF_CORE to 0x10

Pull DCDC1_EN High

Write DEF_CORE to 0x10

Write CON_CTRL [7] to 1

Figure 39. Workaround 2

Workaround 3: Generate a HOT_RESET after enabling DCDC1 (Figure 40)

VCC/VINDCDC1

DCDC1_EN

HOT_RESET

1.225 V

1.20 V

1.225 V

1.20 V

VDCDC1

Figure 40. Workaround 3

46

Submit Documentation Feedback

Product Folder Link(s) : TPS650231

TPS650231

www.ti.com

SLVSAE3 –AUGUST 2010

DIFFERENCES OF TPS650231 VERSUS TPS65023 and TPS65023B

ITEM

DESCRIPTION

TPS65023

TPS65023B

TPS650231

Minimum 1.65V;

Vcc = 2.5V to 5.25V

Minimum 1.65V;

Vcc = 2.5V to 5.25V

V_IH

High level input voltage for the SDAT pin

Minimum 1.3V

Minimum 1.4V,

Vcc = 2.5V to 5.25V

Minimum 1.4V,

Vcc = 2.5V to 5.25V

V_IH

V_IL

High level input voltage for the SCLK pin

Minimum 1.3V

Maximum 0.4V

Low level input voltage for SCLK and

SDAT pin

Maximum 0.35V

t_h(DATA)

Data input hold time

Minimum 300ns

1.8V

Minimum 100ns

1.8V

Minimum 100ns

2.1V

t_su(DATA)

Data input setup time

LDO1 voltage for setting LDO1_[2..0] = 011

1) DEFDCDC2=LOW:

Vo=1.8V

2) DEFDCDC2=HIGH:

Vo=3.3V

1) DEFDCDC2=LOW:

Vo=1.8V

2)DEFDCDC2=HIGH:

Vo=3.3V

0.6V feedback input only

(allows voltage scaling

with external resistor

divider without

DEFDCDC2 pin functionality

3) 0.6V feedback input

3)0.6V feedback input

restrictions)

Submit Documentation Feedback

47

Product Folder Link(s) : TPS650231

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Sep-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS650231RSBR

TPS650231RSBT

TPS650231YFFR

TPS650231YFFT

WQFN

DSBGA

RSB

YFF

40

49

3000

250

330.0

180.0

12.4

8.4

5.25

3.3

5.25

3.3

1.1

8.0

4.0

12.0

8.0

Q2

Q1

3000

250

0.75

8.4

3.3

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Sep-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS650231RSBR

TPS650231RSBT

TPS650231YFFR

TPS650231YFFT

WQFN

DSBGA

RSB

YFF

40

49

3000

250

340.5

190.5

338.1

212.7

20.6

31.8

3000

250

Pack Materials-Page 2

X: Max = 3132 µm, Min = 3032 µm

Y: Max = 3116 µm, Min = 3016 µm

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

Automotive

www.ti.com/automotive

www.ti.com/communications

Communications and

Telecom

DSP

dsp.ti.com

Computers and

Peripherals

www.ti.com/computers

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Consumer Electronics

Energy

www.ti.com/consumer-apps

www.ti.com/energy

Logic

Industrial

www.ti.com/industrial

Power Mgmt

Microcontrollers

RFID

power.ti.com

Medical

www.ti.com/medical

microcontroller.ti.com

www.ti-rfid.com

Security

www.ti.com/security

Space, Avionics &

Defense

www.ti.com/space-avionics-defense

RF/IF and ZigBee® Solutions www.ti.com/lprf

Video and Imaging

Wireless

www.ti.com/video

www.ti.com/wireless-apps

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS650231RSBR
厂家：	TEXAS INSTRUMENTS
描述：	POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS 电源管理IC，适用于锂离子电池供电系统电池
文件：	总55页 (文件大小：1306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS650231RSBR [TI]

相关型号：

TPS650231RSBT

TPS650231YFF

TPS650231YFFR

TPS650231YFFT

TPS650231_10

TPS65023B

TPS65023BRSB

TPS65023BRSBR

TPS65023BRSBT

TPS65023QRHARQ1

TPS65023QRSBRQ1

TPS65023RSB