TPS65051QRSMRQ1 [TI]
汽车类 1.5V 至 6.5V 电源管理 IC，具有 2 个降压转换器和 4 个 LDO | RSM | 32 | -40 to 125;
| 型号： | TPS65051QRSMRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 1.5V 至 6.5V 电源管理 IC，具有 2 个降压转换器和 4 个 LDO | RSM | 32 | -40 to 125 输入元件 转换器 |
| 文件： | 总33页 (文件大小：1810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
具有 2 个降压转换器和 4 个低输入电压 LDO 的 TPS65051-Q1
6 通道电源管理 IC
1 特性
对于低噪声 应用，用户可以通过将 MODE 引脚的电平
1
拉高来强制器件进入固定频率 PWM 模式。运行在关
断模式中可将流耗减少到少于 1μA。此器件允许使用
小型电感器和电容器以实现一个小型解决方案尺寸。
TPS65051-Q1 器件提供高达 1A (DCDC1) 和 0.6A
(DCDC2) 的输出电流。TPS65051-Q1 器件还集成了
两个 400mA LDO 和两个 200mA LDO 电压稳压器，
可以使用每个 LDO 上的独立使能引脚打开或关闭相应
的稳压器。每个 LDO 的工作输入电压介于 1.5V 至
6.5V 之间，这使得它们可以由其中一个降压转换器供
电，也可以由主电池直接供电。
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
–
–
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
器件组件充电模式 (CDM) ESD 分类等级 C3B
•
•
效率高达 95%
直流/直流转换器的输出电流：
DCDC1 = 1A；DCDC2 = 0.6A
•
•
直流/直流转换器的外部可调节输出电压
TPS65051-Q1 器件的 LDO 电压可以使用外部电阻分
压器进行调节。
DC-DC 转换器的 VI范围是
2.5V 至 6V
•
•
•
•
•
•
2.25MHz 固定频率运行
器件信息(1)
轻负载电流时的省电模式
180°异相操作
器件型号
封装
封装尺寸（标称值）
TPS65051-Q1
VQFN (32)
4.00mm x 4.00mm
脉宽调制模式下的输出电压精度 ±1%
低纹波脉冲频率调制 (PFM) 模式
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
方框图
针对两个 DC-DC 转化器的总值为 32μA（典型值）
的静态电流
VINDCDC1/2
1 ꢀ
VCC
Vbat
22 …F
•
•
•
•
•
•
针对最低压降的占空比为 100%
两个通用 400mA，高电源抑制比 (PSRR) LDO
两个通用 200mA，高 PSRR LDO
LDO 的 VI范围：1.5V 至 6.5V
L1
1 …F
Cff
DCDC1 (I/O)
R1
FB_DCDC1
10 …F
Step-Down
Converter
1 A
R2
EN_DCDC1
MODE
ENABLE
PGND1
L2
LDO 的数字电压选择
R3
R4
VDCDC2
DEFDCDC2
PGND2
DCDC2 (core)
Step-Down
Converter
600 mA
采用 4mm × 4mm、32 引脚 VQFN 封装
10 …F
EN_DCDC2
ENABLE
2 应用
VIN_LDO1
EN_LDO1
VLDO1
FB1
VIN
车用信息娱乐
VLDO1
R5
R6
400-mA LDO
ENABLE
汽车仪表盘
4.7 …F
4.7 …F
2.2 …F
VLDO2
FB2
VIN_LDO2
EN_LDO2
汽车数字音频广播
VIN
VLDO2
R5
R6
400-mA LDO
ENABLE
3 说明
VIN_LDO3/4
EN_LDO3
VLDO3
VIN
VLDO3
R9
TPS65051-Q1 器件是一款集成式电源管理 IC，适用于
由一节锂离子或锂聚合物电池供电并需要多个电源轨的
应用 。TPS65051-Q1 器件提供两个高效的 2.25MHz
降压转换器，用于在基于处理器的系统中提供内核电压
和 I/O 电压。为了在可能的最宽负载电流范围内实现最
大效率，这两个降压转换器在轻负载时进入低功耗模
式。
200-mA LDO
FB3
BP
ENABLE
R10
0.1 …F
VLDO4
FB4
EN_LDO4
ENABLE
VLDO4
R11
R12
I/O Voltage
2.2 …F
200-mA LDO
THRESHOLD
R19
RESET
RESET
HYSTERESIS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBJ1
TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
www.ti.com.cn
目录
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 8
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 器件和文档支持 ..................................................... 25
11.1 接收文档更新通知 ................................................. 25
11.2 社区资源................................................................ 25
11.3 商标....................................................................... 25
11.4 静电放电警告......................................................... 25
11.5 Glossary................................................................ 25
12 机械、封装和可订购信息....................................... 25
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2012) to Revision B
Page
•
已添加 添加了引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关
建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ................................................................. 1
•
•
•
•
•
已删除 删除了所有 TPS65050-Q1、TPS65052-Q1、TPS65054-Q1 和 TPS65056-Q1 器件型号引用 ................................. 1
Deleted the Ordering Information table .................................................................................................................................. 3
Changed the resistor labels of R3, R4, and R5 to R13, R14, and R15 in the RESET section............................................ 20
已添加 添加了接收文档更新通知 部分 .................................................................................................................................. 25
已更改 更改了静电放电声明.................................................................................................................................................. 25
2
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65051-Q1
www.ti.com.cn
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
5 Pin Configuration and Functions
RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
VLDO1
25
16
15
14
13
12
11
10
9
EN_LDO4
EN_LDO3
RESET
FB4
26
27
28
29
30
31
32
Thermal
Pad
VLDO4
VINLDO3/4
VLDO3
FB3
FB1
MODE
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
2
AGND
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog GND, connect to PGND and thermal pad
Input for bypass capacitor for internal reference
BP
1
DEFDCDC2
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
EN_LDO3
EN_LDO4
FB1
17
25
26
27
28
15
16
31
6
Feedback pin for converter 2. Connect DEFDCDC2 to the center of the external resistor divider.
Enable input for converter 1, active-high
Enable input for converter 2, active-high
Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
Enable input for LDO4. Logic high enables the LDO, logic low disables the LDO.
Feedback input for the external voltage divider
FB2
Feedback input for the external voltage divider
FB3
9
Feedback input for the external voltage divider
FB4
13
Feedback input for the external voltage divider
Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect an external resistor divider
between VOUT1, this pin, and GND.
FB_DCDC1
24
I
HYSTERESIS
8
I
Input for hysteresis on reset threshold
L1
L2
22
20
O
O
Switch pin of converter 1. Connected to inductor
Switch pin of converter 2. Connected to inductor
Copyright © 2012–2017, Texas Instruments Incorporated
3
TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Select between power-safe mode and forced-PWM mode for DCDC1 and DCDC2. In power-safe mode, the
device uses PFM at light loads, PWM for higher loads. Setting this pin to high level selects forced-PWM mode.
If this pin has low level, then the device operates in power-safe mode.
MODE
32
I
PGND1
23
19
14
7
I
I
GND for converter 1
PGND2
GND for converter 2
RESET
O
I
Open-drain active-low reset output, 100-ms reset-delay time
Reset input
THRESHOLD
Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. Connect this pin to the same
voltage supply as VINDCDC1/2.
VCC
3
I
I
I
VDCDC2
VINDCDC1/2
18
21
Feedback voltage-sense input, connect directly to the output of converter 2.
Input voltage for VDCDC1 and VDCDC2 step-down converters. Connect this pin to the same voltage supply as
VCC
.
VINLDO1
VINLDO2
VINLDO3/4
VLDO1
29
4
I
I
Input voltage for LDO1
Input voltage for LDO2
Input voltage for LDO3 and LDO4
Output voltage of LDO1
Output voltage of LDO2
Output voltage of LDO3
Output voltage of LDO4
Connect to GND
11
30
5
I
O
O
O
O
—
VLDO2
VLDO3
10
12
VLDO4
Thermal pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
Input voltage on all pins except AGND, PGND, and EN_LDO1 pins with respect to
AGND
7
VI
V
Input voltage range on EN_LDO1 pins with respect to AGND
Current at VINDCDC1/2, L1, PGND1, L2, PGND2
Current at all other pins
VCC + 0.5
1800
1000
4
mA
mA
V
II
VO
Output voltage for LDO1, LDO2, LDO3, and LDO4
–0.3
See the Thermal
Information
Continuous total power dissipation
TA
Operating free-air temperature
Storage temperature
–40
–65
125
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
2000
750
UNIT
V
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65051-Q1
www.ti.com.cn
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0.6
0.6
1.5
1
NOM
MAX UNIT
VI
Input voltage for step-down converters, VINDCDC1/2
Output voltage for step-down converter, VDCDC1
Output voltage for step-down converter, VDCDC2
Input voltage for LDOs, VINLDO1, VINLDO2, VINLDO3/4
Output voltage for LDO1 and LDO2
6
V
V
VINDCDC1/2
VO
VI
VINDCDC1/2
V
6.5
3.6
V
V
VO
Output voltage for LDO3 and LDO4
1
3.6
V
Output current at L1 (DCDC1)
1000
600
400
200
mA
mA
mA
mA
μH
μF
μF
μF
μF
μF
°C
Ω
Output current at L2 (DCDC2)
IO
Output current at VLDO1, VLDO2
Output current at VLDO3, VLDO4
Inductor at L1, L2(1)
1.5
10
2.2
22
Output capacitor at VDCDC1, VDCDC2(1)
Output capacitor at VLDO1, VLDO2, VLDO3, VLDO4(1)
Input capacitor at VCC(1)
Input capacitor at VINLDO1, VINLDO2(1)
Input capacitor at VINLDO3/4(1)
CO
2.2
1
CI
2.2
2.2
–40
TA
Operating ambient temperature
Resistor from battery voltage to VCC used for filtering(2)
125
10
1
(1) See the Application Information section of this data sheet for more details.
(2) Up to 2 mA can flow into VCC; when both converters are running in PWM, this resistor causes the UVLO threshold to shift accordingly.
6.4 Thermal Information
TPS65051-Q1
THERMAL METRIC(1)
RSM (VQFN)
32 PINS
37.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
30.1
7.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
7.6
RθJC(bot)
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2012–2017, Texas Instruments Incorporated
5
TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
www.ti.com.cn
6.5 Electrical Characteristics
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF, TA = –40°C to 125°C, typical values are at TA
= 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6
UNIT
V
SUPPLY CURRENT
VI
Input voltage range at VINDCDC1/2
2.5
One converter, IO = 0 mA.
PFM mode enabled (Mode = GND) device not switching,
EN_DCDC1 = VI OR EN_DCDC2 = VI;
EN_LDO1= EN_LDO2 = EN_LDO3 = EN_LDO = GND
20
32
30
μA
Two converters, IO = 0 mA
Operating quiescent current
PFM mode enabled (Mode = 0) device not switching,
EN_DCDC1 = VI AND EN_DCDC2 = VI;
EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = GND
IQ
Total current into VCC, VINDCDC1/2,
VINLDO1, VINLDO2, VINLDO3/4
40
μA
μA
One converter, IO = 0 mA.
PFM mode enabled (Mode = GND) device not switching,
EN_DCDC1 = VI OR EN_DCDC2 = VI;
180
0.85
1.25
250
EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = VI
One converter, IO = 0 mA.
Switching with no load (Mode = VI), PWM operation
EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1 = EN_LDO2
= EN_LDO3 = EN_LDO = GND
mA
mA
IQ
Operating quiescent current into VCC
Two converters, IO = 0 mA
Switching with no load (Mode = VI), PWM operation
EN_DCDC1 = VI AND EN_DCDC2 = VI; EN_LDO1 =
EN_LDO2 = EN_LDO3 = EN_LDO = GND
EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 = EN_LDO2 =
EN_LDO3 = EN_LDO4 = GND
I(SD)
Shutdown current
9
12
2
μA
Undervoltage lockout threshold for DC-
DC converters and LDOs
V(UVLO)
Voltage at VCC
1.8
V
EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
MODE, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1,
VIH
VIL
High-level input voltage
Low-level input voltage
DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2,
EN_LDO3, EN_LDO4
1.2
0
VCC
0.4
V
V
MODE, EN_DCDC1, EN_DCDC2, DEFLDO1, DEFLDO2,
DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3,
EN_LDO4, DEFDCDC2
MODE = GND or VI MODE, EN_DCDC1, EN_DCDC2,
DEFDCDC2,
DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1,
EN_LDO2,
EN_LDO3, EN_LDO4
0.01
1
μA
IlB
Input bias current
V_FB_LDOx = 1 V, FB_LDO1, FB_LDO2, FB_LDO3,
FB_LDO4
100
nA
POWER SWITCH
VINDCDC1/2 = 3.6 V
280
400
280
400
630
630
DCDC1
VINDCDC1/2 = 2.5 V
rDS(on)
P-channel MOSFET on-resistance
mΩ
μA
VINDCDC1/2 = 3.6 V
DCDC2
VINDCDC1/2 = 2.5 V
Ilkg
P-channel leakage current
VDCDCx = V(DS) = 6 V
1
VINDCDC1/2 = 3.6 V
220
320
220
320
7
450
DCDC1
VINDCDC1/2 = 2.5 V
rDS(on)
N-channel MOSFET on-resistance
mΩ
VINDCDC1/2 = 3.6 V
450
DCDC2
VINDCDC1/2 = 2.5 V
Ilkg
N-channel leakage current
VDCDCx = V(DS) = 6 V
10
1.65
1.15
μA
DCDC1, 2.5 V ≤ VINDCDC1/2 ≤ 6 V
DCDC2, 2.5 V ≤ VINDCDC1/2 ≤ 6 V
Increasing junction temperature
Decreasing junction temperature
1.19
0.85
1.4
1
Forward current limit PMOS (high side)
and NMOS (low side)
I(LIMF)
A
Thermal shutdown
150
20
°C
°C
Thermal shutdown hysteresis
OUTPUT
VO
Output-voltage range for DCDC1,
DCDC2
0.6
VINDCDC1/2
600
V
Vref
Reference voltage
mV
6
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65051-Q1
www.ti.com.cn
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
Electrical Characteristics (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF, TA = –40°C to 125°C, typical values are at TA
= 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VINDCDC1/2 = 2.5 V to 6 V, 0 mA < IO = < IO(maximum)
MODE = GND, PFM operation
–2%
0
2%
DC output-voltage accuracy, DCDC1,
DCDC2(1)
VO
VINDCDC1/2 = 2.5 V to 6 V, 0 mA < IO = < IO(maximum)
MODE = VI, PWM operation
–1%
0
1%
0.2
ΔVO
VOL
IOL
Power-save-mode ripple voltage(2)
RESET, PB_OUT output low voltage
RESET, PB_OUT sink current
IO = 1 mA, MODE = GND, VO = 1.3 V, bandwith = 20 MHz
IOL = 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V
25
mVPP
V
1
10
1
mA
RESET, PB_OUT output leakage
current
After PB_IN has been pulled high once; Vthreshold > 1 V and
Vhysteresis > 1 V, VOH = 6 V
nA
V
Vth
Vthreshold, Vhysteresis threshold
0.98
1.5
1.02
6.5
VLDO1, VLDO2, VLDO3 AND VLDO4 LOW-DROPOUT REGULATORS
Input-voltage range for LDO1, LDO2,
LDO3, LDO4
VI
V
V
Feedback voltage for FB_LDO1,
V(FB)
1
FB_LDO2, FB_LDO3, and FB_LDO4
Maximum output current for LDO1,
LDO2
400
200
IO
mA
mA
Maximum output current for LDO3,
LDO4
LDO1 short-circuit current limit
LDO2 short-circuit current limit
VLDO1 = GND
VLDO2 = GND
750
850
I(SC)
LDO3 and LDO4 short-circuit current
limit
VLDO3 = GND, VLDO4 = GND
420
Dropout voltage at LDO1
Dropout voltage at LDO2
Dropout voltage at LDO3, LDO4
IO = 400 mA, VINLDO = 3.4 V
IO = 400 mA, VINLDO = 1.8 V
IO = 200 mA, VINLDO = 1.8 V
400
280
280
mV
Leakage current from VinLDOx to
VLDOx
Ilkg
VO
LDO enabled, VINLDO = 6.5 V, VO = 1 V at TA = 140°C
IO = 10 mA
3
μA
Output voltage accuracy for LDO1,
LDO2, LDO3, LDO4
–2%
–1%
–1%
1%
1%
1%
VINLDO1,2 = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V,
VINLDO3,4 = VLDO3,4 + 0.5 V (minimum 2.5 V) to 6.5 V,
IO = 10 mA
Line regulation for LDO1, LDO2, LDO3,
LDO4
Load regulation for LDO1, LDO2,
LDO3, LDO4
IO = 0 mA to 400 mA for LDO1, LDO2
IO = 0 mA to 200 mA for LDO3, LDO4
PSRR
R(DIS)
Power-supply rejection ratio
f = 10 kHz; IO = 50 mA; VI = VO + 1 V
Active when LDO is disabled
70
dB
Internal discharge resistor at VLDO1,
VLDO2, VLDO3, VLDO4
350
Ω
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
140
20
°C
°C
Thermal shutdown hysteresis
(1) Output voltage specification does not include tolerance of external voltage-programming resistors.
(2) In power-save mode, device typically enters operation at IPSM = VI / 32 Ω.
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6.6 Switching Characteristics
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF, TA = –40°C to 125°C, typical values are at TA
= 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCILLATOR
fSW
Oscillator frequency
2.025
2.25
2.475
MHz
OUTPUT
Time from active EN to start
switching
tStart
Start-up time
170
μs
tRamp
VOUT ramp-up time
RESET delay time
Time to ramp from 5% to 95% of VO
Input voltage at threshold pin rising
750
100
32
μs
ms
ms
80
26
120
38
PB-ONOFF debounce time
VLDO1, VLDO2, VLDO3 AND VLDO4 LOW-DROPOUT REGULATORS
Regulation time for LDO1, LDO2,
LDO3, LDO4
Load change from 10% to 90%
10
μs
6.7 Typical Characteristics
100
90
100
90
80
80
70
60
50
40
30
20
3.8 V
5 V
4.2 V
70
3.8 V
5 V
60
50
40
30
20
3.4 V
3.4 V
4.2 V
V
T
= 3.3 V
= 25oC
V
T
= 3.3 V
= 25oC
O
O
A
A
10
10
0
PWM Mode
PWM/PFM Mode
0
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
− Output Current − A
O
0.1
1
10
I
− Output Current − A
I
O
Figure 1. Efficiency vs Output Current
Figure 2. Efficiency vs Output Current
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Typical Characteristics (continued)
100
100
90
3.3 V
90
V
T
= 1.3 V
= 25oC
O
A
PWM Mode
80
80
70
60
50
40
30
20
70
3.8 V
3.8 V
60
4.2 V
5 V
50
3.3 V
5 V
40
4.2 V
30
20
10
V
T
= 1.3 V
= 25oC
O
A
10
0
PFM Mode
0
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
I
− Output Current − A
I
O
− Output Current − A
O
Figure 3. Efficiency vs Output Current
Figure 4. Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
10
100
1k
f − Frequency − Hz
Figure 5. Power-Supply Rejection Ratio vs Frequency
10k
100k
1M
10M
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7 Detailed Description
7.1 Overview
The TPS65051-Q1 device has 2 DC-DC buck converters and 4 LDOs. Each DC-DC and LDO has enable pins,
allowing external sequence control of the PMU rails. The device also has a RESET feature that is generated
from a THRESHOLD comparator. This RESET signal can be used to reset or warn of power shutdown to the
embedded mircocontroller or processor. The TPS65051-Q1 device makes power-system integration easy for a
variety of embedded processors or FPGAs.
7.2 Functional Block Diagram
VINDCDC1/2
1 ꢀ
VCC
Vbat
22 …F
L1
1 …F
Cff
R1
FB_DCDC1
DCDC1 (I/O)
10 …F
Step-Down
Converter
1 A
R2
EN_DCDC1
MODE
ENABLE
PGND1
L2
R3
R4
VDCDC2
DEFDCDC2
PGND2
DCDC2 (core)
Step-Down
Converter
600 mA
10 …F
EN_DCDC2
ENABLE
VIN_LDO1
EN_LDO1
VLDO1
FB1
VIN
VLDO1
R5
R6
400-mA LDO
ENABLE
4.7 …F
4.7 …F
2.2 …F
VLDO2
FB2
VIN_LDO2
EN_LDO2
VIN
VLDO2
R5
R6
400-mA LDO
ENABLE
VIN_LDO3/4
EN_LDO3
VLDO3
VIN
VLDO3
R9
200-mA LDO
FB3
BP
ENABLE
R10
0.1 …F
VLDO4
FB4
EN_LDO4
ENABLE
VLDO4
R11
R12
I/O Voltage
2.2 …F
200-mA LDO
THRESHOLD
R19
RESET
RESET
HYSTERESIS
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7.3 Feature Description
7.3.1 Operation
The TPS65051-Q1 device has two synchronous step-down converters. The converters operate with 2.25-MHz
(typical) fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load
currents, the converters automatically enter power-save mode and operate with PFM (pulse-frequency
modulation).
During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input
voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns
on, the inductor current ramps up until the current comparator trips, and the control logic turns off the switch. The
current-limit comparator turns off the switch if the current exceeds the limit of the P-channel switch. After the
adaptive dead time, which prevents shoot-through current, the N-channel MOSFET rectifier turns on, and the
inductor current ramps down. The clock signal turning off the N-channel rectifier and turning on the on the P-
channel switch initiates the next cycle.
The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase
shift between converter 1 and converter 2 decreases the input rms current, allowing the use of smaller input
capacitors.
7.3.2 DCDC1 Converter
An external resistor divider connected to FB_DCDC1 pin sets the converter 1 output voltage. See the Converter
1 (DCDC1) section for more details. The maximum output current is 1 A.
7.3.3 DCDC2 Converter
Connect the VDCDC2 pin directly to the DCDC2 converter output voltage. The DEFDCDC2 pin selects the
DCDC2 converter output voltage. See the Converter 2 (DCDC2) section for more details. The maximum output
current is 600 mA.
An external resistor divider sets the output voltage. Connect the DEFDCDC2 pin to the external resistor divider.
7.3.4 Dynamic Voltage Positioning
This feature reduces the voltage under- and overshoots at load steps from light to heavy load and vice versa. It
is activated In the power-save mode of operation, running the converter in PFM mode activates dynamic voltage
positioning. Dynamic voltage positioning provides more headroom for both the voltage drop at a load step and
the voltage increase at a load throw-off, thereby improving load-transient behavior.
At light loads, in which the converters operate in PFM mode, the typical output-voltage regulation is 1% higher
than the nominal value. In the event of a load transient from light load to heavy load, the output voltage drops
until it reaches the skip-comparator-low threshold, set to 1% below the nominal value, and enters PWM mode.
During a release from heavy load to light load, active regulation turning on the N-channel switch minimizes the
voltage overshoot.
Smooth
Increased Load
Fast Load Transient
+1%
OUT_NOM
-1%
PFM Mode
Light Load
PFM Mode
Light Load
V
PFM Mode
Medium/Heavy Load
PFM Mode
Medium/Heavy Load
COMP_LOW Threshold
Figure 6. Dynamic Voltage Positioning
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Feature Description (continued)
7.3.5 Soft Start
The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft
start, control of the output-voltage ramp-up is as shown in Figure 7.
EN
95%
5%
V
OUT
t
t
RAMP
Start
Figure 7. Soft Start
7.3.6 100% Duty-Cycle Low-Dropout Operation
The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the
100% duty-cycle mode. In this mode, the P-channel switch is constantly on. This operational mode is useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range, (that is, the minimum input voltage to maintain regulation depends on the load current and output
voltage) and can be calculated as:
VI (min) = VO (max) + IO (max) x (rDS(on) (max) + RL)
where
•
•
•
•
IO max = maximum output current plus inductor ripple current
rDS(on) max = maximum P-channel switch rDS(on)
RL = dc resistance of the inductor
VO (max) = nominal output voltage plus maximum output-voltage tolerance
(1)
7.3.7 Undervoltage Lockout
The undervoltage-lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery, and disables all internal circuitry. The undervoltage-lockout threshold, sensed
at the VCC pin, is typically 1.8 V, maximum 2 V.
7.3.8 Mode Selection
The MODE pin allows mode selection between forced PWM mode and power-save mode for both converters.
Connecting this pin to GND enables the automatic PWM and power-save mode of operation. The converters
operate in fixed-frequency PWM mode at moderate-to-heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load-current range.
Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load
currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-
save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced-
PWM mode during operation. This allows efficient power management by adjusting the operation of the
converters to the specific system requirements.
7.3.9 Enable
To start up each converter independently, the device has a separate enable pin for each DC-DC converter and
for each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, or EN_LDO4 is set to high, the
corresponding converter starts up with soft start as previously described.
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Feature Description (continued)
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the
electrical characteristics. In this mode, the P- and N-Channel MOSFETs turn off, and the entire internal control
circuitry switches off. If disabled, internal 350-Ω resistors pull the outputs of the LDOs low, actively discharging
the output capacitor. Proper operation requires termination of the enable pins. Do not leave them unconnected.
7.3.10 RESET
The device contains circuitry that can generate a reset pulse for a processor with a 100-ms delay time. The
device senses the input voltage for a comparator at the THRESHOLD pin. When the voltage exceeds the
threshold, the output goes high with a 100-ms delay time. An external resistor connected to the HYSTERESIS
input defines the hysteresis. This circuitry is functional as soon as the supply voltage at VCC exceeds the
undervoltage-lockout threshold. The TPS65051-Q1 device has a shutdown current (all DC-DC converters and
LDOs are off) of 9 μA.
Vbat
HYSTERESIS
RESET
THRESHOLD
+
100 ms
Delay
-
V
= 1 V
ref
Vbat
THRESHOLD
THRESHOLD - HYSTERESIS
Comparator
Output (Internal)
t
NRESET
RESET
Figure 8. RESET Pulse Circuit
7.3.11 Short-Circuit Protection
All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics.
7.3.12 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typically) for the DC-DC converters, the device goes
into thermal shutdown. In this mode, the P- and N-channel MOSFETs turn off. The device continues its operation
when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of
the DC-DC converters disables both converters simultaneously.
The thermal shutdown temperature for the LDOs is typically 140°C. Therefore, an LDO used to power an
external voltage never heats up the chip high enough to turn off the DC-DC converters. If one LDO exceeds the
thermal shutdown temperature, all LDOs turn off simultaneously.
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Feature Description (continued)
7.3.13 Low Dropout Voltage Regulators
The design of the low-dropout voltage regulators allows them to operate well with small ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 400
mV (LDO1) and 280 mV (LDO2, LDO3, and LDO4) at rated output current. Each LDO supports a current-limit
feature. The EN_LDO1, ENLDO2, EN_LDO3, and EN_LDO4 pins enable the LDOs. The use of external resistor
dividers sets the output voltage of the LDOs.
7.4 Device Functional Modes
7.4.1 Power-Save Mode
The TPS65051-Q1 device is either in the ON or the OFF mode. The OFF mode is entered when the voltage on
VCC is below the UVLO threshold of 1.8 V (typically). When the voltage at the VCC pin is higher than UVLO, the
device enters ON mode. In the ON mode, the converters and LDOs are available for use.
Setting the MODE pin to 0 enables the power-save mode. If the load current decreases, the converters enter the
power-save mode of operation automatically. During power-save mode, the converters operate with reduced
switching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency. The
converters position the output voltage 1% above the nominal output voltage. This voltage-positioning feature
minimizes voltage drops caused by a sudden load step.
To optimize the converter efficiency at light load, the TPS65051-Q1 device monitors average current. If in PWM
mode, the inductor current remains below a certain threshold, then the device enters power-save mode. Use
Equation 2 to calculate the average output current threshold to enter PFM mode. Use Equation 3 to calculate the
average output current threshold to leave PFM mode.
VINDCDC
I(PFM_enter)
=
32 W
VINDCDC
(2)
I(PSMDCDC_leave)
=
24 W
(3)
During power-save mode, a comparator monitors the output voltage. As the output voltage falls below the skip-
comparator (skip comp) threshold, the P-channel switch turns on, and the converter effectively delivers a
constant current. If the load is below the delivered current, the output voltage rises until it crosses the skip comp
threshold again; then all switching activity ceases, reducing the quiescent current to a minimum until the output
voltage has dropped below the threshold. If the load current is greater than the delivered current, the output
voltage falls until it crosses the skip-comparator-low (skip comp low) threshold set to 1% below nominal VO; then
the device exits power-save mode, and the converter returns to the PWM mode.
These control methods reduce the quiescent current to 12 μA per converter and the switching frequency to a
minimum, achieving the highest converter efficiency. The PFM mode operates with low output-voltage ripple. The
ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor value
decreases the output ripple voltage.
Disable the power-save mode by driving the MODE pin high. In forced-PWM mode, both converters operate with
fixed-frequency PWM mode regardless of the load.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This device integrates two step-down converters and four LDOs, which can be used to power the voltage rails
needed by a processor or any other application. The power management IC (PMIC) can be controlled through
the ENABLE and MODE pins or sequenced from the VIN using RC delay circuits. A logic output (RESET)
provides the application processor or load a logic signal indicating power good or reset.
8.2 Typical Application
VINDCDC1/2
1 ꢀ
VCC
Vbat
Vbat
22 …F
L1
2.2 µH
Vout1 = 2.85 V
Cff
1 …F
R1
10 …F
FB_DCDC1
PGND1
Vbat
R2
R13
HYSTERESIS
L2
Vout2 = 1.575 V
R14
THRESHOLD
2.2 µH
R3
R4
VDCDC2
DEFDCDC2
PGND2
VLDO1
R15
1 Mꢀ
10 …F
RESET
Vbat
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
EN_LDO3
EN_LDO4
TPS65051-Q1
VLDO1 = 3.3 V
R5
R6
FB1
4.7 …F
VLDO2
FB2
VLDO2 = 1.8 V
R7
R8
4.7 …F
VLDO3
VLDO3 = 1.2 V
R9
VIN_LDO1
VIN_LDO2
Vbat
FB3
BP
2.2 …F
R10
Vbat
VIN_LDO3/4
0.1 …F
Vout1
VLDO4
FB4
VLDO4 = 1.3 V
R11
R12
MODE
Vbat
2.2 …F
AGND
Copyright © 2017, Texas Instruments Incorporated
Figure 9. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 lists the design requirements for this example.
Table 1. Design Parameters
PARAMETER
VALUE
2.5 V to 6 V
2.85 V
1 A
DCDC1 and DCDC2 input voltage
DCDC1 output voltage
DCDC1 output current
DCDC2 output voltage
DCDC2 output current
LDO1 output voltage
LDO1 output current
LDO2 output voltage
LDO2 output current
LDO3 output voltage
LDO3 output current
LDO4 output voltage
LDO4 output current
1.575 V
600 mA
3.3 V
400 mA
1.8 V
400 mA
1.2 V
200 mA
1.3 V
200 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Output-Voltage Setting
8.2.2.1.1 Converter 1 (DCDC1)
An external resistor network can set the output voltage of converter 1. Calculate the output voltage using
Equation 4,
R1
VO = Vref
x
1 +
(
)
R2
where
•
the internal reference voltage, Vref, is 0.6 V
(4)
TI recommends setting the total resistance of R1 + R2 to less than 1 MΩ. The resistor network connects to the
input of the feedback amplifier, therefore requiring a small feed-forward capacitor in parallel with R1. A typical
value of 47 pF is sufficient.
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8.2.2.1.2 Converter 2 (DCDC2)
The adjustable output voltage is defined with external resistor network on the DEFDCDC2 pin.
Calculation of the adjustable output voltage is similar to that for the DCDC1 converter. TI recommends setting the
total resistance of R3 + R4 to less than 1 MΩ. Route the DEFDCDC2 line separate from noise sources, such as
the inductor or the L2 line. Connect the VDCDC2 line directly to the output capacitor. As VDCDC2 is the sense
pin for the output of L2, there is no need for a feedforward capacitor in conjunction with R3.
Use an external resistor divider at DEFDCDC2 as shown in Figure 10.
1 W
V
Vbat
CC
1 mF
VDCDC2
L2
V
O
VINDCDC1/2
ENDCDC2
L
C
I
C
O
R3
R4
DEFDCDC2
AGND PGND
Figure 10. External Resistor Divider
V(DEFDCDC2) = 0.6 V
VO = V(DEFDCDC2)
VO
R3 + R4
R4
x
R3 = R4 x
- R4
V(DEFDCDC2)
(5)
See Table 2 for typical resistor values:
Table 2. Typical Resistor Values
OUTPUT VOLTAGE
R3
R4
NOMINAL VOLTAGE
Typical CFF
47 pF
3.3 V
3 V
680 kΩ
510 kΩ
560 kΩ
510 kΩ
300 kΩ
200 kΩ
300 kΩ
330 kΩ
150 kΩ
130 kΩ
150 kΩ
160 kΩ
150 kΩ
120 kΩ
200 kΩ
330 kΩ
3.32 V
2.95 V
2.84 V
2.51 V
1.8 V
47 pF
2.85 V
2.5 V
1.8 V
1.6 V
1.5 V
1.2 V
47 pF
47 pF
47 pF
1.6 V
47 pF
1.5 V
47 pF
1.2 V
47 pF
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8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
8.2.2.2.1 Inductor Selection
The two converters operate with a 2.2-μH output inductor. A designer can use larger or smaller inductor values to
optimize the performance of the device for specific operation conditions. The selected inductor must be rated for
its dc resistance and saturation current. The dc resistance of the inductance directly influences the efficiency of
the converters. Therefore, select an inductor with lowest dc resistance for highest efficiency. The minimum
inductor value is 1.5 μH, but the circuit requires an output capacitor of 22 μF minimum in this case. For an output
voltage above 2.8 V, TI recommends an inductor value of 3.3 μH minimum. Lower values result in an increased
output-voltage ripple in PFM mode.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation-current rating of
the inductor should be higher than the maximum inductor current as calculated with Equation 6. This
recommendation is because during heavy load transient the inductor current rises above the calculated value.
VO
1 -
VI
DIL
DIL = VO
x
IL(max) = IO (max) +
2
L x ¦
where
•
•
•
•
f = Switching frequency (2.25-MHz typical)
L = Inductor value
Δ IL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(6)
The highest inductor current occurs at maximum VI. Open-core inductors have a soft saturation characteristic,
and they can normally handle higher inductor currents versus a comparable shielded inductor.
A more-conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Give consideration to the difference in the core material from inductor to inductor, which
has an impact on the efficiency, especially at high switching frequencies. See Table 3 and the typical applications
for possible inductors.
Table 3. Tested Inductors
INDUCTOR TYPE
LPS3010
INDUCTOR VALUE
2.2 μH
SUPPLIER
Coilcraft
Coilcraft
Coilcraft
TDK
LPS3015
3.3 μH
LPS4012
2.2 μH
VLF4012
2.2 μH
8.2.2.2.2 Output-Capacitor Selection
The advanced fast-response voltage-mode control scheme of the two converters allows the use of small ceramic
capacitors with a value of 22-μF (typical), without having large output-voltage undershoots and overshoots during
heavy load transients. TI recommends ceramic capacitors having low ESR values, which result in the lowest
output-voltage ripple.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. For completeness, the RMS ripple current is calculated as:
VO
1 -
VI
1
x
I(RMSCout) = VO
x
2 x Ö3
L x ¦
(7)
At nominal load current, the inductive converters operate in PWM mode, and the overall output voltage ripple is
the sum of the voltage spike caused by the output-capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
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VO
VI
1 -
1
x
+ ESR
DVO = VO
x
8 x CO x ¦
L x ¦
(8)
where the highest output voltage ripple occurs at the highest input voltage VI.
At light load currents, the converters operate in power-save mode and the output-voltage ripple depends on the
output-capacitor value. The internal comparator delay and the external capacitor set the output-voltage ripple.
The typical output-voltage ripple is less than 1% of the nominal output voltage.
8.2.2.2.3 Input-Capacitor Selection
The nature of the buck converters having a pulsating input current requires a low-ESR input capacitor for best
input-voltage filtering and minimizing the interference with other circuits caused by high input-voltage spikes. The
converters require a ceramic input capacitor of 10 μF. Increase the input capacitor as desired for better input-
voltage filtering, without any limit.
Table 4. Possible Capacitors
CAPACITOR VALUE
SIZE
0805
0805
0805
0805
0603
SUPPLIER
TYPE
2.2 μF
2.2 μF
10 μF
10 μF
10 μF
TDK C2012X5R0J226MT
Taiyo Yuden JMK212BJ226MG
Taiyo Yuden JMK212BJ106M
TDK C2012X5R0J106M
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Taiyo Yuden JMK107BJ106MA
8.2.2.3 Low-Dropout Voltage Regulators (LDOs)
An external resistor network sets the output voltage of all four LDOs. Calculate the output voltage using
Equation 9:
R5
VO = Vref
x
1 +
(
)
R6
where
•
the internal reference voltage, Vref, is 1 V (typical).
(9)
TI recommends setting the total resistance of R5 + R6 to less than 1 MΩ. Typically, there is no feedforward
capacitor needed at the voltage dividers for the LDOs.
VO
R5 + R6
VO = V(FB_LDOs)
x
R5 = R6 x
- R6
V(FB_LDOs)
R6
(10)
Typical resistor values:
Table 5. Typical Resistor Values
OUTPUT VOLTAGE
R5
R6
NOMINAL VOLTAGE
3.3 V
3 V
300 kΩ
300 kΩ
240 kΩ
360 kΩ
300 kΩ
240 kΩ
150 kΩ
36 kΩ
130 kΩ
150 kΩ
130 kΩ
200 kΩ
200 kΩ
300 kΩ
300 kΩ
120 kΩ
510 kΩ
330 kΩ
3.31 V
3 V
2.85 V
2.8 V
2.5 V
1.8 V
1.5 V
1.3 V
1.2 V
1.1 V
2.85 V
2.8 V
2.5 V
1.8 V
1.5 V
1.3 V
1.19 V
1.1 V
100 kΩ
33 kΩ
Copyright © 2012–2017, Texas Instruments Incorporated
19
TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
www.ti.com.cn
8.2.2.4 RESET
The device contains a comparator for supervising a voltage connected to an external voltage divider, and
generating a reset signal if the voltage is lower than the threshold. The rising-edge delay is 100 ms at the open-
drain RESET output. Calculate the values for the external resistors R13 to R15 as follows:
VL = lower voltage threshold
VH = higher voltage threshold
VREF = reference voltage (1 V)
Example:
•
•
VL = 3.3 V
VH = 3.4 V
Set R15 = 100 kΩ
→ R13 + R14 = 240 kΩ
→ R14 = 3.03 kΩ
→ R13 = 237 kΩ
≈
∆
«
’
VH
R13 + R14 = R15 ì
-1
÷
◊
V
ref
VH - VL
R14 = R15 ì
VL
(11)
Vout1
Vbat
R13
HYSTERESIS
R14
THRESHOLD
1 Mꢀ
R15
RESET
Figure 11. RESET Circuit
20
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65051-Q1
www.ti.com.cn
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
8.2.3 Application Curves
V
= 4.2 V,
T
= 25oC
A
CH1 (VDCDC1 = 3.3 V)
= 25oC
A
I
V
= 4.2 V,
T
CH1 (VDCDC1 = 3.3 V)
I
CH1 (VDCDC2 = 1.5 V)
CH2 (VDCDC2 = 1.5 V)
CH3 (I DCDC2 = 600 mA)
L
CH3 (I DCDC2 = 80 mA)
L
CH4 (I DCDC1 = 600 mA)
L
CH4 (I DCDC1 = 80 mA)
L
t − Time = 500 ns/div
t − Time = 2 ms/div
Figure 13. Output Voltage Ripple PWM MODE = HIGH
Figure 12. Output Voltage Ripple PWM or PFM MODE =
LOW
CH1 (EN)
EN
CH1 (VLDO1)
CH4 (VLDO1)
V
T
= 3.6 V
= 25oC
I
A
Mode = Low
CH2 (VLDO2)
CH3 (VLDO3)
CH4 (VLDO4)
CH3
(VDCDC2 = 1.5 V)
V
T
= 3.6 V
= 25oC
I
A
CH2
(VDCDC1 = 3.3 V)
Load DCDC1 = 600 mA
Load DCDC2 = 600 mA
ILDO1/2/3/4 = 100 mA
Mode = Low
t − Time = 200 ms/div
Figure 14. DCDC1 Startup Timing
t − Time = 20 ms/div
Figure 15. LDO1 to LDO4 Startup Timing
CH1 (VDCDC1)
CH1 (VDCDC1)
V
T
= 4.2 V
= 25oC
I
V
T
= 4.2 V
= 25oC
I
A
A
Mode = Low
Mode = High
CH2
I(DCDC1)
CH2
I(DCDC1)
VDCDC1 = 3.3 V
ENDCDC1 = High
ENDCDC2 = Low
VDCDC1 = 3.3 V
ENDCDC1 = High
ENDCDC2 = Low
Load Current = 60 mA to 540 mA
Load Current = 60 mA to 540 mA
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 16. DCDC1 Load Transient Response
Figure 17. DCDC1 Load Transient Response
Copyright © 2012–2017, Texas Instruments Incorporated
21
TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
www.ti.com.cn
CH1 (VDCDC2)
CH1 (VDCDC2)
V
T
= 3.6 V
= 25oC
I
V
T
= 3.6 V
= 25oC
I
A
A
Mode = High
Mode = Low
CH2
I(DCDC2)
CH2
I(DCDC2)
VDCDC2 = 1.5 V
VDCDC2 = 1.5 V
ENDCDC1 = Low
ENDCDC2 = High
ENDCDC1 = Low
ENDCDC2 = High
Load Current = 60 mA to 540 mA
Load Current = 60 mA to 540 mA
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 19. DCDC2 Load Transient Response
Figure 18. DCDC2 Load Transient Response
CH1
VIN (VDCDC1)
CH1
VIN (VDCDC2)
V
= 3.6 V to 4.5 V to 3.6 V
I
T
= 25oC
A
Mode = High
VDCDC1 = 3.3 V
ENDCDC1 = High
ENDCDC2 = Low
Load Current = 600 mA
CH2 (VDCDC2)
CH2 (VDCDC1)
VDCDC2 = 1.5 V
V
T
= 3.4 V to 4.4 V to 3.4 V
= 25oC
I
ENDCDC1 = Low
ENDCDC2 = High
Load Current = 600 mA
A
Mode = High
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 20. DCDC1 Line Transient Response
Figure 21. DCDC2 Line Transient Response
CH1 (VLDO4)
CH1 (VLDO1)
V
= 3.6 V
I
VLDO4 = 1.3 V
V
T
= 3.6 V
= 25oC
I
A
VLDO4 = 20 mA to 180 mA
= 25oC
VLDO1 = 3.3 V
VLDO1 = 40 mA to 360 mA
T
A
CH2
I(LDO4)
CH2
I(LDO1)
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 22. LDO1 Load Transient Response
Figure 23. LDO4 Load Transient Response
22
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65051-Q1
www.ti.com.cn
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
CH1
VIN (LDO1)
CH2 (VLDO1)
V
T
= 3.6 V to 4.2 V to 3.6 V
= 25oC
I
A
VLDO1 = 3.3 V
VLDO1 = 100 mA
Mode = High
t − Time = 100 ms/div
Figure 24. LDO1 Line Transient Response
9 Power Supply Recommendations
In addition to the values listed in the Recommended Operating Conditions table, additional recommendations for
the power supply are as follows:
•
•
•
1-μF bypass capacitor on VCC, located as close as possible to the VCC pin to ground.
VCC and VINDCDC1/2 must be connected to the same voltage supply with minimal voltage difference.
Input capacitors must be present on the VINDCDC1/2, VIN_LDO1, VINLDO2, and VIN_LDO3/4 supplies if
used.
•
•
Output inductor and capacitors must be used on the outputs of the DC-DC converters if used.
Output capacitors must be used on the outputs of the LDOs if used.
10 Layout
10.1 Layout Guidelines
•
•
•
The input capacitors for the DC-DC converters should be placed as close as possible to the VINDCDC1/2 pin
and the PGND1 and PGND2 pins.
The inductor of the output filter should be placed as close as possible to the device to provide the shortest
switch node possible, reducing the noise emitted into the system and increasing the efficiency.
Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy.
Feedback should be routed away from noisy sources such as the inductor. If possible route on the opposing
side as the switch node and inductor and place a GND plane between the feedback and the noisy sources or
keep out underneath them entirely.
•
•
•
•
Place the output capacitors as close as possible to the inductor to reduce the feedback loop as much as
possible. This will ensure best regulation at the feedback point.
Place the device as close as possible to the most demanding or sensitive load. The output capacitors should
be placed close to the input of the load. This will ensure the best AC performance possible.
The input and output capacitors for the LDOs should be placed close to the device for best regulation
performance.
TI recommends using the common ground plane for the layout of this device. The AGND can be separated
from the PGND but, a large low parasitic PGND is required to connect the PGNDx pins to the CIN and
external PGND connections. If the AGND and PGND planes are separated, have one connection point to
reference the grounds together. Place this connection point close to the IC.
Copyright © 2012–2017, Texas Instruments Incorporated
23
TPS65051-Q1
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
www.ti.com.cn
10.2 Layout Example
/out
[out
[out
/in
/in
ëin
/out
w1 C.
Figure 25. Layout Example from EVM for TPS65051-Q1
24
版权 © 2012–2017, Texas Instruments Incorporated
TPS65051-Q1
www.ti.com.cn
ZHCSAG3B –SEPTEMBER 2012–REVISED JANUARY 2017
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
版权 © 2012–2017, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65051QRSMRQ1
ACTIVE
VQFN
RSM
32
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65051Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65051QRSMRQ1
VQFN
RSM
32
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RSM 32
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TPS65051QRSMRQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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TPS65052RSMR
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65052RSMRG4
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65052RSMT
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65052RSMTG4
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65053
5-CHANNEL POWER MGMT IC WITH TWO STEP DOWN CONVERTERS AND 3 LOW-INPUT VOLTAGE LDOsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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