TPS6508641RSKT_技术文档

TPS650864

ZHCSG44E –JUNE 2017 –REVISED DECEMBER 2022

TPS650864 适用于Xilinx^®MPSoC 和FPGA 的可配置多轨PMU

1 特性

2 应用

• 5.6V 至21V 的宽V_IN范围

• 三个采用D-CAP2^™拓扑的

可变输出电压同步降压控制器

– 使用外部FET 的可扩展输出电流，支持可选电

流限制

• 可编程逻辑控制器

• 机器视觉摄像机

• 视频监控

• 测试和测量

• 嵌入式PC

• 运动控制

• 便携式超声波设备

– 在0.41V 至1.67V 之间以10mV 为步长或

在1V 至3.575V 之间以25mV 为步长的I²C

DVS 控制

3 说明

• 三个采用DCS-Control 拓扑的可变输出电压同步降

压转换器

TPS650864 器件系列是一款单芯片电源管理 IC

(PMIC) ，专为 Xilinx Zynq^®多处理器片上系统

(MPSoC) 和现场可编程门阵列 (FPGA) 系列而设计。

TPS650864 器件的输入电压范围为 5.6V 至 21V，支

持广泛的应用（请参阅器件比较表）。该器件适用于壁

式供电应用或 2、3、4 节串联锂离子电池包（NVDC

或非 NVDC 电源架构）。有关 5V 输入电源的信息，

请参阅典型应用部分。D-CAP2 和 DCS-Control 高频

稳压器采用小型无源器件，用于减小解决方案尺寸。

D-CAP2 和 DCS-Control 拓扑具有出色的瞬态响应性

能，非常适用于具有快速负载开关的处理器内核和系统

内存电压轨。I²C 接口可通过嵌入式控制器 (EC) 或

SoC 进行轻松控制。PMIC 的尺寸为 8mm × 8mm，采

用单行VQFN 封装，所带的散热垫可改善散热功能。

– 输入电压范围为3V 至5.5 V

– 输出电流高达3A

– 在0.41V 至1.67V 之间以10mV 为步长或

在0.425V 至3.575V 之间以25mV 为步长的

I²C DVS 控制

• 三个具有可调节输出电压的LDO 稳压器

– LDOA1：I²C 可选电压的范围为1.35V 至

3.3V，输出电流可高达200mA

– LDOA2 和LDOA3：I²C 可选电压的范围为0.7V

至1.5V，每个的输出电流可高达600mA

• 用于DDR 存储器终端的VTT LDO

• 三个具有压摆率控制功能的负载开关

– 输出电流高达300mA，压降小于标称输入电压

的1.5%

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

VQFN (64)

– 输入电压为1.8V 时，R_DSON< 96mΩ

• 5V 固定输出电压LDO (LDO5)

TPS650864 ⁽²⁾

8.00mm x 8.00mm

– 用于SMPS 的栅极驱动器和LDOA1 的电源

– 可自动切换至外部5V 降压以实现更高效率

• 内置可通过工厂OTP 编程功能实现的灵活性和可配

置性

(1) 如需更多信息，请参阅机械、封装和可订购信息部分。

(2) 有关器件选项，请参阅器件比较表。

– 六个GPI 引脚均可配置为启用（CTL1 至

CTL6）任意所选电压轨或使其进入睡眠模式

（CTL3 和CTL6）

– 四个GPO 引脚均可配置为指示任意所选轨道的

电源正常

– 漏极开路中断输出引脚

• I²C 接口支持标准模式(100kHz)、快速模式

(400kHz) 和超快速模式(1MHz)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWCS138

TPS650864

ZHCSG44E –JUNE 2017 –REVISED DECEMBER 2022

www.ti.com.cn

LDO5V

LDO1

VIN

BOOT1

DRVH1

LDOA1

1.35 œ 3.3 V

200 mA

CTL1

CTL2

SW1

V1

VSET

EN

BUCK1

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL1

CTL3/SLPENB1

Control

CTL4

EN

VSET

FBVOUT1

Inputs

PGNDSNS1

CTL5

ILIM1

CTL6/SLPENB2

VPULL

VIN

BOOT2

DRVH2

CLK

SoC

&

System

I²C CTL

SW2

DATA

V2

VSET

EN

VPULL

DRVL2

BUCK2

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

Control

Outputs

FBVOUT2

PGNDSNS2

IRQB

GPO1

GPO2

GPO3

GPO4

FBGND2

ILIM2

Internal

Interrupt

Events

3.3 V œ 5 V

PVIN3

LX3

TEST CTL

OTP

BUCK3

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

V3

FB3

Registers

REGISTERS

<PGND_BUCK3>

3 A

3.3 V œ 5 V

PVIN4

LX4

BUCK4

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

LDO5P0

V5ANA

LDO5P0

VSET

EN

Digital Core

V4

3.3V œ 5V

FB4

3 A

<PGND_BUCK4>

3.3V œ 5V

PVIN5

LX5

BUCK5

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

œ

VSET

EN

4.7V

V5

+

FB5

STDBY

3 A

<PGND_BUCK5>

LDO5V

VIN

REFSYS

LDO3P3

BOOT6

DRVH6

Thermal

Monitoring

VSYS

5.6Vœ21V

LDO3P3

SW6

DRVL6

Thermal Shutdown

VDDQ

VSET

EN

BUCK6

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VREF

AGND

Bandgap

FBVOUT6

PGNDSNS6

ILIM6

PVIN_VTT

VTT

EN

VTT_LDO

VDDQ/2

VTTFB

LDOA2

0.7 ꢀ 1.5 V

600 mA

LDOA3

0.7 ꢀ 1.5 V

600 mA

LOAD SWA1

LOAD SWB1

LOAD SWB2

图3-1. PMIC 功能框图

2

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Table of Contents

8.2 Functional Block Diagram.........................................22

8.3 TPS6508640 Design and Settings............................24

8.4 TPS65086401 Design and Settings..........................29

8.5 TPS6508641 Design and Settings............................33

8.6 TPS65086470 Design and Settings..........................39

8.7 SMPS Voltage Regulators........................................ 43

8.8 LDOs and Load Switches......................................... 51

8.9 Power Goods (PGOOD or PG) and GPOs............... 51

8.10 Power Sequencing and VR Control........................ 53

8.11 Device Functional Modes........................................58

8.12 I²C Interface............................................................58

8.13 Register Maps.........................................................62

9 Applications, Implementation, and Layout............... 108

9.1 Application Information........................................... 108

9.2 Typical Application.................................................. 108

9.3 Power Supply Coupling and Bulk Capacitors..........119

9.4 Do's and Don'ts.......................................................119

10 Device and Documentation Support........................120

10.1 Device Support..................................................... 120

10.2 Documentation Support........................................ 120

10.3 接收文档更新通知................................................. 120

10.4 支持资源................................................................120

10.5 Trademarks...........................................................120

10.6 Electrostatic Discharge Caution............................120

10.7 术语表................................................................... 120

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 3

5 Device Comparison Table...............................................5

6 Pin Configuration and Functions...................................6

7 Specifications.................................................................. 9

7.1 Absolute Maximum Ratings........................................ 9

7.2 ESD Ratings............................................................... 9

7.3 Recommended Operating Conditions.......................10

7.4 Thermal Information..................................................10

7.5 Electrical Characteristics: Total Current

Consumption............................................................... 10

7.6 Electrical Characteristics: Reference and

Monitoring System.......................................................11

7.7 Electrical Characteristics: Buck Controllers.............. 12

7.8 Electrical Characteristics: Synchronous Buck

Converters...................................................................13

7.9 Electrical Characteristics: LDOs............................... 14

7.10 Electrical Characteristics: Load Switches............... 16

7.11 Digital Signals: I²C Interface................................... 17

7.12 Digital Input Signals (CTLx).................................... 17

7.13 Digital Output Signals (IRQB, GPOx)..................... 17

7.14 Timing Requirements..............................................17

7.15 Switching Characteristics........................................18

7.16 Typical Characteristics............................................19

8 Detailed Description......................................................21

8.1 Overview...................................................................21

Information.................................................................. 121

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (November 2020) to Revision E (December 2022)

Page

• Changed the power-up sequence for TPS6508640 in the TPS6508640 Power-Up Sequence diagram......... 24

• Changed the power-down sequence for TPS6508640 in the TPS6508640 Power-Down Sequence diagram....

24

• Changed the OTP_VERSION[1:0] bits from 01 to 10 for the TPS6508640 device in the DEVICEID2 Register

table..................................................................................................................................................................64

• Changed the OTP_VERSION[1:0] bits from 00 to 01 for the TPS65086401 and TPS6506470 devices in the

DEVICEID2 Register table................................................................................................................................64

Changes from Revision C (June 2018) to Revision D (November 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Changed the incorrect LX3 pin description from connect to ground when not in use to leave floating when not

in use in the Pin Functions table.........................................................................................................................6

• Removed the line above the LDOA1 block in the PMIC Functional Block Diagram ........................................22

• Removed incorrect VREF notes from the middle and right DDR blocks in the Power Map Example figure.... 22

• Added when configured as push-pull, LDO3P3 is used for logic-level high to the Power Good Tree figure

description ....................................................................................................................................................... 51

• Changed the bit values for BUCK4_MODE bits in the BUCK4CTRL Register table from 0 to 1 for the

TPS65086401 and TPS65086470 devices ......................................................................................................69

• Changed the bit values for BUCK5_MODE bits in the BUCK5CTRL Register table from 0 to 1 for the

TPS65086401 and TPS65086470 devices ......................................................................................................70

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• Added links and step ranges to BUCK2SLPCTRL Register Descriptions table............................................... 78

• Changed the bit values for BUCK3_MODE bits in the BUCK123CTRL Register table from 0 to 1 for the

TPS65086401 and TPS65086470 devices.......................................................................................................82

• Removed the incorrect VREF notes from the middle and right DDR blocks in the VIN 5-V Application diagram

........................................................................................................................................................................108

Changes from Revision B (December 2017) to Revision C (June 2018)

Page

• 向数据手册添加了TPS6508640 和TPS6508641.............................................................................................. 1

• Added typical MPSoC variants to Device Comparison Table ............................................................................ 5

• Added BUCKx_MODE test condition for quiescent current .............................................................................13

• Added BUCKx_MODE information to relevant graphs .................................................................................... 19

• Changed the TPS65086401 Power Map Example in the TPS65086401 Design and Settings section............29

• Changed the TPS65086470 Power Map Example in the TPS65086470 Design and Settings section ...........39

• Added information regarding ILIM resistor minimum value for Force PWM condition .....................................50

Changes from Revision A (November 2017) to Revision B (December 2017)

Page

• Changed TPS65086401 from preview to production data..................................................................................5

Changes from Revision * (February 2017) to Revision A (November 2017)

Page

• 将器件状态从“产品预发布”更改为“量产数据”.............................................................................................1

• Added pin connection when unused...................................................................................................................6

• Changed the TPS65086401 Power Map Example in the TPS65086401 Design and Settings section............29

• Fixed SWB1 and SWB2 current to 0.4A from 0.3A ......................................................................................... 39

• Changed typo from TPS6508470 to TPS65086470......................................................................................... 42

• Changed description to Sleep State from Connected Standby for consistency in the Sleep State Entry and

Exit section....................................................................................................................................................... 57

• Changed the description of all PGOODs in the note in the Sleep State Entry and Exit section from stay to can

stay because the behavior can vary based on the part-number specific settings............................................ 57

• Added failure to reach power good within 10 ms as emergency shutdown condition to the Emergency

Shutdown section............................................................................................................................................. 57

• Changed bit 0 in the BUCK3VID Register register to Read only (R) ...............................................................68

• Changed the PG_DELAY2: 2nd Power Good Delay Register description from GPO3 to GPO1, GPO2, and

GPO4 ...............................................................................................................................................................84

• Fixed a typo which showed the '000' option resulting in 2.5 ms instead of 0 ms in the PG_DELAY2 Register

Descriptions table............................................................................................................................................. 84

4

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5 Device Comparison Table

表 5-1 lists a brief summary of the default values for each part number stored in one-time programmable (OTP)

memory. A full summary of each part number can be found in the applications section linked in the SECTION

column. The step size is indicated by the values in parenthesis. If alternate voltages are available through pin-

strapping, they are separated with a comma.

表5-1. Default Values

PART NUMBER APPLICATION

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

LDOA1

LDOA2

LDOA3

SECTION

Xilinx Zynq

3.3 V

(25 mV)

0.85 V, 0.9 V

(10 mV)

1.2 V

(25 mV)

0.9 V

(25 mV)

1.8 V

(25 mV)

1.2 V, 1.35 V

(10 mV)

TPS6508640

TPS65086401

Ultrascale+

2.5 V

1.5 V

1.2 V

节8.3

ZU7 - ZU15⁽¹⁾

Xilinx Zynq

Ultrascale+

ZU2 - ZU5⁽¹⁾

1.5 V, 1.2 V,

1.1 V

(10 mV)

1.8 V

(25 mV)

0.85 V

(10 mV)

0.85 V

(25 mV)

3.3 V

(25 mV)

3.3 V

(25 mV)

1.8 V

1.2 V

节8.4

Xilinx Zynq

Ultrascale+

ZU2 - ZU5⁽¹⁾

0.85 V

(10 mV)

1.1 V, 1.2 V

(25 mV)

3.3 V

(25 mV)

1.2 V

(25 mV)

1.8 V

(25 mV)

TPS6508641

TPS65086470

Ext FB

1.8 V

1.2 V

0.7 V

1.2 V

0.7 V

节8.5

节8.6

Xilinx

1 V

(10 mV)

1.8 V

(25 mV)

1.2 V

(25 mV)

2.5 V

(25 mV)

3.3 V

(25 mV)

1.35 V, 1.5 V

(25 mV)

Artix 7⁽¹⁾

(1) Indicates the original intent of the part number. Parts can be used for alternate applications.

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6 Pin Configuration and Functions

图6-1 shows the 64-pin RSK Plastic Quad Flatpack No-Lead package.

FBGND2

FBVOUT2

DRVH2

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VTTFB

2

VTT

3

PVINVTT

ILIM6

SW2

4

BOOT2

5

FBVOUT6

DRVH6

SW6

PGNDSNS2

DRVL2

6

7

DRV5V_2_A1

LDOA1

8

BOOT6

PGNDSNS6

DRVL6

Thermal

Pad

9

LX3

10

11

12

13

14

15

16

PVIN3

DRV5V_1_6

DRVL1

FB3

CTL1

PGNDSNS1

BOOT1

SW1

CTL6/SLPENB2

IRQB

GPO1

DRVH1

Not to scale

The thermal pad must be connected to the system power ground plane.

图6-1. 64-Pin RSK VQFN With Exposed Thermal Pad (Top View)

表6-1. Pin Functions

NAME

SMPS REGULATORS

I/O

DESCRIPTION

NO.

Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor. Connect to

ground when not in use.

1

FBGND2

I

Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor. Connect to

ground when not in use.

2

3

FBVOUT2

DRVH2

I

O

High-side gate driver output for BUCK2 controller. Leave floating when not in use.

6

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表6-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

4

SW2

I

Switch node connection for BUCK2 controller. Connect to ground when not in use.

Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin. Leave floating

when not in use.

5

BOOT2

Power GND connection for BUCK2. Connect to ground terminal of external low-side FET. Connect to ground when not in

use.

6

PGNDSNS2

DRVL2

I

O

I

7

Low-side gate driver output for BUCK2 controller. Leave floating when not in use.

5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on

board to LDO5P0 pin typically. Bypass not required if BUCK2 and LDOA1 are not in use.

8

DRV5V_2_A1

LX3

10

11

O

I

Switch node connection for BUCK3 converter. Leave floating when not in use.

Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if

BUCK3 is not in use.

PVIN3

Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor. Connect to ground when

not in use.

12

20

21

FB3

LX5

I

O

I

Switch node connection for BUCK5 converter. Leave floating when not in use.

Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if

BUCK5 is not in use.

PVIN5

Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor. Connect to ground when

not in use.

22

23

FB5

FB4

I

Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor. Connect to ground when

not in use.

Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if

BUCK4 is not in use.

24

25

29

PVIN4

LX4

I

O

I

Switch node connection for BUCK4 converter. Leave floating when not in use.

Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor. Connect to ground when

not in use.

FBVOUT1

Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side

FET. Connect to ground when BUCK1 not in use.

30

ILIM1

I

33

34

DRVH1

SW1

O

I

High-side gate driver output for BUCK1 controller. Leave floating when not in use.

Switch node connection for BUCK1 controller. Connect to ground when not in use.

Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin. Leave floating

when not in use.

35

BOOT1

I

Power GND connection for BUCK1. Connect to ground terminal of external low-side FET. Connect to ground when not in

use.

36

37

38

39

40

PGNDSNS1

DRVL1

I

O

I

Low-side gate driver output for BUCK1 controller. Leave floating when not in use.

5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on

board to LDO5P0 pin typically. Bypass not required if BUCK1 and BUCK6 are not in use.

DRV5V_1_6

DRVL6

O

I

Low-side gate driver output for BUCK6 controller. Leave floating when not in use.

Power GND connection for BUCK6. Connect to ground terminal of external low-side FET. Connect to ground when not in

use.

PGNDSNS6

Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin. Leave floating

when not in use.

41

BOOT6

I

42

43

SW6

I

Switch node connection for BUCK6 controller. Connect to ground when not in use.

High-side gate driver output for BUCK6 controller. Leave floating when not in use.

DRVH6

O

Remote feedback sense for BUCK6 controller and reference voltage for VTT LDO regulation. Connect to positive

terminal of output capacitor. Connect to ground when not in use.

44

45

64

FBVOUT6

ILIM6

I

Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side

FET. Connect to ground when BUCK6 not in use.

Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side

FET. Connect to ground when BUCK2 not in use.

ILIM2

LDO AND LOAD SWITCHES

9

LDOA1

SWB1

O

LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.

Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.

17

Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient

performance. Connect to ground when not in use.

18

PVINSWB1_B2

I

19

31

SWB2

SWA1

O

Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.

Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.

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表6-1. Pin Functions (continued)

NAME

I/O

DESCRIPTION

NO.

Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient

performance. Connect to ground when not in use.

32

PVINSWA1

PVINVTT

VTT

I

Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic capacitor. Bypass not required if VTT

LDO is not in use.

46

47

Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic capacitors. Leave floating when not in

use.

O

Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor. Connect to ground when not in

use.

48

49

50

VTTFB

LDOA3

I

O

I

Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.

Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Connect to ground

when not in use.

PVINLDOA2_A3

51

54

LDOA2

O

Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.

Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.

LDO3P3

Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF

(typical) ceramic capacitor.

56

57

LDO5P0

V5ANA

O

I

Bias used by converters (BUCK3, BUCK4, and BUCK5) for regulation. Must be same supply as PVINx. Also has an

internal load switch that connects this pin to LDO5P0 pin if 5-V is used. Bypass this pin with an optional ceramic

capacitor to improve transient performance.

INTERFACE

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this

pin.

13

CTL1

I

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this

pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of

(H) sleep state where their output voltages may be different from those in normal state.

14

15

16

CTL6/SLPENB2

IRQB

I

O

Open-drain output interrupt pin. Refer to 节8.13.4, IRQ: PMIC Interrupt Register, for definitions.

General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the

configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled by

an I²C register bit by the user, which then can be used as an enable signal to an external VR.

GPO1

General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the

configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled by

an I²C register bit by the user, which then can be used as an enable signal to an external VR.

26

GPO2

O

General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the

configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled by

an I²C register bit by the user, which then can be used as an enable signal to an external VR.

27

28

GPO3

GPO4

O

Open-drain output that can be configured to reflect Power Good status of VRs of any choice or to be controlled by an I²C

register bit by the user, which then can be used as an enable signal to an external VR.

58

59

CLK

I

I²C clock

I²C data

DATA

I/O

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this

pin.

60

61

CTL2

I

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this

pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of

(H) sleep state where their output voltages may be different from those in normal state.

CTL3/SLPENB1

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this

pin.

62

63

CTL4

CTL5

I

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this

pin.

REFERENCE

52

AGND

VREF

Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.

—

Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic capacitor between this pin and quiet

ground.

53

55

O

System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (typical) ceramic

capacitor.

VSYS

I

THERMAL PAD

Thermal pad

Connect to PCB ground plane using multiple vias for good thermal and electrical performance.

—

(PGND)

8

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

ANALOG

Input voltage from battery, VSYS

28

7

V

–0.3

–5⁽²⁾

–2⁽³⁾

–0.3

PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6

V5ANA

6

PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2

DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6

SW1, SW2, SW6

0.3

34

28

8

LX3, LX4, LX5

Differential voltage, BOOTx to SWx

5.5

VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6,

PVINVTT, VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1

3.6

3.3

V

–0.3

PVINLDOA2_A3, LDOA2, LDOA3

DIGITAL IO

DATA, CLK, GPO1-GPO3

CTL1-CTL6, GPO4, IRQB

Storage temperature, T_stg

3.6

7

V

–0.3

–40

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transient for less than 5 ns

(3) Transient for less than 20 ns

7.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾

Charged Device Model (CDM), per JESD22-C101⁽²⁾

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

ANALOG

VSYS

5.6

–0.3

–1

13

21

1.3

5.5

0.3

26.5

5.5

21

V

v

VREF

PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1

PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2

DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6

DRVL1, DRVL2, DRVL6

V

SW1, SW2, SW6

LX3, LX4, LX5

5.5

3.6

3.3

–1

FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5

LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1

PVINVTT

–0.3

BUCK6 FBVOUT6

0.5 ×

FBVOUT6

VTT, VTTFB

V

–0.3

PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2

PVINLDOA2_A3

3.6

1.8

1.5

V

–0.3

LDOA2, LDOA3

DIGITAL IO

3.3

V

DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB

CHIP

–0.3

Operating ambient temperature, T_A

Operating junction temperature, T_J

27

85

°C

–40

125

7.4 Thermal Information

TPS650864

RSK (VQFN)

64 PINS

25.8

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

11.3

4.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JT

4.4

ψ_JB

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics: Total Current Consumption

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PMIC shutdown current that includes I_Qfor

references, LDO5, LDO3P3, and digital core

V_SYS= 13 V, all functional output rails are

disabled

I_SD

65

µA

10

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7.6 Electrical Characteristics: Reference and Monitoring System

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE

Band-gap reference voltage

Accuracy

1.25

V

V_REF

0.5%

0.22

5.56

–0.5%

0.047

5.24

C_VREF

Band-gap output capacitor

VSYS UVLO threshold for LDO5

0.1

5.4

µF

V

V_{SYS_UVLO_5V}

V_SYSfalling

VSYS UVLO threshold hysteresis for V_SYSrising above

V_{SYS_UVLO_5V_HYS}

V_{SYS_UVLO_3V}

200

3.6

mV

V

LDO5

V_{SYS_UVLO_5V}

VSYS UVLO threshold for LDO3P3

V_SYSfalling

3.45

3.75

VSYS UVLO threshold hysteresis for V_SYSrising above

LDO3P3 V_{SYS_UVLO_3V}

V_{SYS_UVLO_3V_HYS}

150

mV

T_CRIT

Critical threshold of die temperature T_Jrising

130

110

145

10

160

120

°C

T_{CRIT_HYS}

T_HOT

Hysteresis of T_CRIT

T_Jfalling

T_Jrising

T_Jfalling

Hot threshold of die temperature

Hysteresis of T_HOT

115

10

T_{HOT_HYS}

LDO5

V_IN

Input voltage at V_SYSpin

DC output voltage

5.6

4.9

13

5

21

5.1

V

V_OUT

I_OUT= 10 mA

I_OUT

DC output current

100

180

mA

Measured with output shorted to

ground

I_OCP

Overcurrent protection

200

mA

Power Good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_OUTrising

94%

V_{TH_PG_HYS}

I_Q

Power Good deassertion hysteresis V_OUTrising or falling

4%

20

Quiescent current

V_IN= 13 V, I_OUT= 0 A

µA

µF

C_OUT

External output capacitance

2.7

4.7

10

1

V5ANA-to-LDO5P0 LOAD SWITCH

V_IN= 5 V, measured from

V5ANA pin to LDO5P0 pin at

I_OUT= 200 mA

R_DSON

On resistance

Ω

Power Good threshold for external 5-

V supply

V_{TH_PG}

V_{TH_HYS_PG}

I_LKG

V_V5ANArising

V_V5ANAfalling

4.7

V

Power Good threshold hysteresis for

external 5-V supply

100

mV

µA

Switch disabled,

V_V5ANA= 5 V, V_LDO5= 0 V

Leakage current

10

21

LDO3P3

V_IN

Input voltage at V_SYSpin

DC output voltage

5.6

13

V

I_OUT= 10 mA

3.3

V_OUT

V_IN= 13 V,

I_OUT= 10 mA

Accuracy

3%

40

–3%

I_OUT

I_OCP

DC output current

Overcurrent protection

mA

Measured with output shorted to

ground

70

Power Good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_OUTrising

92%

3%

V_{TH_PG_HYS}

Power Good deassertion hysteresis V_OUTfalling

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7.6 Electrical Characteristics: Reference and Monitoring System (continued)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_IN= 13 V,

I_OUT= 0 A

MIN

TYP

MAX

UNIT

I_Q

Quiescent current

20

µA

C_OUT

External output capacitance

2.2

4.7

10

µF

7.7 Electrical Characteristics: Buck Controllers

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BUCK1, BUCK2, BUCK6

Power input voltage for

external HSD FET

V_IN

5.6

0.41

1⁽¹⁾

13

See 节5

21

1.67

3.575

2%

V

VID step size = 10 mV, BUCKx_VID[6:0]

progresses from 0000001 to 1111111

DC output voltage VID

range and options

VID step size = 25 mV, BUCKx_VID[6:0]

progresses from 0000001 to 1111111

V_OUT

DC output voltage

accuracy

V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,

I_OUT= 100 mA to 7 A

–2%

Total output voltage

accuracy (DC + ripple) in

DCM

40

416

65

mV

I_OUT= 10 mA, V_OUT≤1 V

–30

Applies only to the Buck1 Controller if

programmed for external feedback voltage

adjustability

Feedback regulation

voltage

V_{FB_EXT_BUCK1}

384

400

Applies only to the Buck1 Controller if

programmed for external feedback voltage

adjustability

Feedback pin leakage

current

I_{FB_LKG_BUCK1}

nA

VID step size = 10 mV

VID step size = 25 mV

2.5

3.125

4

SR(V_OUT

)

Output DVS slew rate

mV/µs

3.125

Low-side output valley

current limit accuracy

(programmed by external

I_{LIM_LSD}

15%

–15%

resistor R_LIM

)

Source current out of

ILIM1 pin

I_LIMREF

V_LIM

T = 25°C

45

0.2

50

55

2.25

µA

V

Voltage at ILIM1 pin

Line regulation

V_LIM= R_LIM× I_LIMREF

V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,

I_OUT= 7 A

0.5%

ΔV_OUT/ΔV_IN

ΔV_OUT/ΔI_OUT

–0.5%

V_IN= 13 V, V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5,

3.3 V, I_OUT= 0 A to 7 A,

Load regulation

0%

1%

referenced to V_OUTat I_OUT= I_{OUT_MAX}

Power Good deassertion V_OUTrising

threshold in percentage of

V_OUTfalling

target V_OUT

105.5%

89.5%

108%

92%

110.5%

94.5%

V_{TH_PG}

3

2

Source, IDRVH = –50 mA

Ω

R_{DSON_DRVH}

Driver DRVH resistance

Driver DRVL resistance

Sink, IDRVH = 50 mA

3

Source, IDRVL = –50 mA

Sink, IDRVL = 50 mA

R_{DSON_DRVL}

0.4

100

200

500

BUCKx_DISCHG[1:0] = 01

BUCKx_DISCHG[1:0] = 10

BUCKx_DISCHG[1:0] = 11

Output auto-discharge

resistance

R_DIS

12

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7.7 Electrical Characteristics: Buck Controllers (continued)

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

C_BOOT

Bootstrap capacitance

100

nF

Bootstrap switch ON

resistance

R_{ON_BOOT}

20

Ω

(1) BUCKx_VID[6:0] = 0000001 –0011000

7.8 Electrical Characteristics: Synchronous Buck Converters

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BUCK3, BUCK4, BUCK5

V_IN

Power input voltage

3.0

5.5

V

VID step size = 10 mV,

BUCKx_VID[6:0] progresses from

0000001 to 1111111

0.41

1.67

See 节5

DC output voltage VID range

and options

V

VID step size = 25 mV,

BUCKx_VID[6:0] progresses from

0000001 to 1111111

0.425

–2%

3.575

2%

V_IN= 5.0 V, V_OUT= 1, 1.2, 1.35, 1.5,

1.8, 2.5, 3.3 V,

I_OUT= 1.5 A

V_OUT

V_IN= 3.3 V, V_OUT= 1, 1.2, 1.35, 1.5,

1.8 V,

2%

–2%

I_OUT= 1.5 A

DC output voltage accuracy

V_IN= 5.0 V, V_OUT= 1, 1.2, 1.35, 1.5,

1.8 V, 2.5, 3.3 V,

2.5%

–2.5%

I_OUT= 100 mA

V_IN= 3.3 V, V_OUT= 1, 1.2, 1.35, 1.5,

1.8 V,

I_OUT= 100 mA

2.5%

40

–2.5%

–30

Total output voltage accuracy

(DC + ripple) in DCM

V_IN= 5.0 V, I_OUT= 10 mA, V_OUT≤1

V

V_DCM

mV

VID step size = 10 mV

VID step size = 25 mV

2.5

3.125

4

SR(V_OUT

)

Output DVS slew rate

mV/µs

3.125

I_OUT

Continuous DC output current

HSD FET current limit

3

7

A

I_{IND_LIM}

4.3

V_IN= 5 V, V_OUT= 1 V,

BUCKx_MODE = 0b

I_Q

Quiescent current

Line regulation

35

µA

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 1.5 A

0.5%

2%

ΔV_OUT/ΔV_IN

ΔV_OUT/ΔI_OUT

–0.5%

–0.2%

V_IN= 5 V, V_OUT= 1, 1.2, 1.35, 1.5,

1.8, 2.5, 3.3 V,

I_OUT= 0 A to 3 A, referenced to V_OUT

at I_OUT= 1.5 A

Load regulation

Power Good deassertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

108%

92%

V_{TH_PG}

Power Good reassertion

hysteresis entering back into

V_{TH_PG}

V_{TH_HYS_PG}

V_OUTrising or falling

3%

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7.8 Electrical Characteristics: Synchronous Buck Converters (continued)

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

BUCKx_DISCHG[1:0] = 01

BUCKx_DISCHG[1:0] = 10

BUCKx_DISCHG[1:0] = 11

MIN

TYP

100

200

500

MAX

UNIT

Output auto-discharge

resistance

R_DIS

Ω

7.9 Electrical Characteristics: LDOs

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LDOA1

V_IN

Input voltage

4.5

1.35

5

5.5

3.3

V

DC output voltage

Accuracy

Set by LDOA1_VID[3:0]

See 节5

V_OUT

I_OUT= 0 to 200 mA

2%

V

–2%

I_OUT

DC output current

Line regulation

200

0.5%

mA

I_OUT= 40 mA

ΔV_OUT/ΔV_IN

–0.5%

–2%

ΔV_OUT

ΔI_OUT

/

Load regulation

I_OUT= 10 mA to 200 mA

2%

V_IN= 5 V, Measured with output

shorted to ground

I_OCP

Overcurrent protection

500

mA

Power Good deassertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

108%

92%

V_{TH_PG}

Measured from EN = H to reach 95%

of final value,

t_STARTUP

Start-up time

500

µs

C_OUT= 4.7 µF

I_Q

Quiescent current

External output capacitance

ESR

I_OUT= 0 A

23

µA

µF

mΩ

Ω

2.7

4.7

10

C_OUT

100

LDOA1_DISCHG[1:0] = 01

LDOA1_DISCHG[1:0] = 10

LDOA1_DISCHG[1:0] = 11

100

190

450

Output auto-discharge

resistance

R_DIS

Ω

LDOA2 and LDOA3

(1)

V_IN

Power input voltage

V_OUT+ V_DROP

1.8

See 节5

1.98

1.5

V

LDOA2 DC output voltage

LDOA3 DC output voltage

DC output voltage accuracy

DC output current

Set by LDOA2_VID[3:0]

Set by LDOA3_VID[3:0]

I_OUT= 0 to 600 mA

0.7

V_OUT

1.5

3%

600

–2%

I_OUT

mA

mV

V_OUT= 0.99 × V_{OUT_NOM}

I_OUT= 600 mA

,

V_DROP

Dropout voltage

Line regulation

Load regulation

350

0.5%

2%

I_OUT= 300 mA

ΔV_OUT/ΔV_IN

–0.5%

–2%

ΔV_OUT

ΔI_OUT

/

I_OUT= 10 mA to 600 mA

Measured with output shorted to

ground

I_OCP

Overcurrent protection

0.65

1.25

A

Power Good assertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

108%

92%

V_{TH_PG}

Measured from EN = H to reach 95%

of final value, C_OUT= 4.7 µF

t_STARTUP

Start-up time

500

µs

14

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7.9 Electrical Characteristics: LDOs (continued)

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_Q

Quiescent current

I_OUT= 0 A

20

µA

f = 1 kHz, V_IN= 1.8 V, V_OUT= 1.2 V,

I_OUT= 300 mA,

C_OUT= 2.2 µF –4.7 µF

48

dB

PSRR

Power supply rejection ratio

f = 10 kHz, V_IN= 1.8 V, V_OUT= 1.2 V,

I_OUT= 300 mA,

30

C_OUT= 2.2 µF –4.7 µF

External output capacitance

ESR

2.2

4.7

10

µF

C_OUT

100

mΩ

LDOA[2,3]_DISCHG[1:0] = 01

LDOA[2,3]_DISCHG[1:0] = 10

LDOA[2,3]_DISCHG[1:0] = 11

80

180

475

Output auto-discharge

resistance

R_DIS

Ω

VTT LDO

V_IN

Power input voltage

DC output voltage

1.2

3.3

V

V_IN= 1.2 V, Measured at VTTFB pin

V_IN/ 2

Relative to V_IN/ 2, I_OUT≤10 mA,

1.1 V ≤V_IN≤1.35 V

10

25

–10

–25

V_OUT

DC output voltage accuracy

mV

mA

Relative to V_IN/ 2, I_OUT≤500 mA,

1.1 V ≤V_IN≤1.35 V

DC Output Current (Rms

Value Over Operation)

0

500

1800

10

1.1 V ≤V_IN≤1.5 V

–500

–1800

–10

source(+) and sink(–): I_OCP= 0.95 A,

1.1 V ≤V_IN≤1.5 V

I_OUT

Pulsed Current (Duty Cycle

Limited to Remain Below DC

Rms Specification)

source(+) and sink(–): I_OCP= 1.8 A,

1.1 V ≤V_IN≤1.5 V

Relative to V_IN/ 2, I_OUT≤10 mA,

1.1 V ≤V_IN≤1.5 V

Relative to V_IN/ 2, I_OUT≤500 mA,

1.1 V ≤V_IN≤1.5 V

20

–20

ΔV_OUT

ΔI_OUT

/

Load regulation

mV

Relative to V_IN/ 2, I_OUT≤1200 mA,

1.1 V ≤V_IN≤1.5 V

30

–30

Relative to V_IN/ 2, I_OUT≤1800 mA,

1.1 V ≤V_IN≤1.5 V

40

–40

DC + AC at sense point, 1.1 V ≤V_IN

≤1.5 V,

(I_OUT= 0 to 350 mA and 350 mA to 0)

AND

(0 to –350 mA and –350 mA to 0)

with 1 µs of rise and fall time

C_OUT= 40 µF

Load transient regulation

Overcurrent protection

5%

ΔV_{OUT_TR}

–5%

Measured with output shorted to

ground: OTPs with VTT I_LIM= 0.95 A

0.95

1.8

I_OCP

A

Measured with output shorted to

ground: OTPs with VTT I_LIM= 1.8 A

Power Good deassertion

threshold in percentage of

target V_OUT

V_OUTrising

V_OUTfalling

110%

95%

V_{TH_PG}

Power Good reassertion

hysteresis entering back into

V_{TH_PG}

V_{TH_HYS_PG}

I_Q

5%

Total ground current

V_IN= 1.2 V, I_OUT= 0 A

240

µA

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7.9 Electrical Characteristics: LDOs (continued)

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_LKG

C_IN

OFF leakage current

External input capacitance

External output capacitance

V_IN= 1.2 V, disabled

1

µA

10

35

µF

C_OUT

µF

VTT_DISCHG = 0

VTT_DISCHG = 1

1000

60

kΩ

Ω

Output auto-discharge

resistance

R_DIS

80

100

(1) The minimum value must be equal to or greater than 1.62 V.

7.10 Electrical Characteristics: Load Switches

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SWA1

V_IN

Input voltage range

DC output current

0.5

3.3

V

I_OUT

300 mA

V_IN= 1.8 V, measured from PVINSWA1 pin

to SWA1 pin at I_OUT= I_OUT(MAX)

60

93

mΩ

165

R_DSON

ON resistance

V_IN= 3.3 V, measured from PVINSWA1 pin

to SWA1 pin at I_OUT= I_OUT(MAX)

100

V_OUTrising

V_OUTfalling

108%

92%

Power Good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Power Good reassertion hysteresis

entering back into V_{TH_PG}

V_{TH_HYS_PG}

I_INRUSH

V_OUTrising or falling

2%

Inrush current upon turnon

V_IN= 3.3 V, C_OUT= 0.1 µF

V_IN= 3.3 V, I_OUT= 0 A

10 mA

µA

10.5

9

I_Q

Quiescent current

V_IN= 1.8 V, I_OUT= 0 A

Switch disabled, V_IN= 1.8 V

Switch disabled, V_IN= 3.3 V

7

370

nA

900

I_LKG

Leakage current

10

C_OUT

External output capacitance

0.1

100

200

500

µF

SWA1_DISCHG[1:0] = 01

SWA1_DISCHG[1:0] = 10

SWA1_DISCHG[1:0] = 11

R_DIS

Output auto-discharge resistance

Ω

SWB1, SWB2, SWB1_2

V_IN

Input voltage range

0.5

3.3

V

I_OUT

DC current per output

400 mA

V_IN= 1.8 V, measured from PVINSWB1_B2

pin to SWBx pin at I_OUT= I_OUT(MAX), per

output switch

68

75

92

mΩ

R_DSON

ON resistance per output

V_IN= 3.3 V, measured from PVINSWB1_B2

pin to SWBx pin at I_OUT= I_OUT(MAX), per

output switch

125

V_OUTrising

V_OUTfalling

108%

92%

Power Good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Power Good reassertion hysteresis

entering back into V_{TH_PG}

V_{TH_HYS_PG}

I_INRUSH

V_OUTrising or falling

2%

Inrush current upon turning on

V_IN= 3.3 V, C_OUT= 0.1 µF

V_IN= 3.3 V, I_OUT= 0 A

V_IN= 1.8 V, I_OUT= 0 A

10 mA

µA

10.5

9

I_Q

Quiescent current

16

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7.10 Electrical Characteristics: Load Switches (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

Switch disabled, V_IN= 1.8 V

Switch disabled, V_IN= 3.3 V

7

460

I_LKG

Leakage current

nA

µF

10 1150

0.1

C_OUT

External output capacitance

SWBx_DISCHG[1:0] = 01

SWBx_DISCHG[1:0] = 10

SWBx_DISCHG[1:0] = 11

100

R_DIS

Output auto-discharge resistance

200

Ω

500

7.11 Digital Signals: I²C Interface

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

Low-level output voltage

High-level input voltage

Low-level input voltage

Leakage current

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OL

V_IH

V_IL

V_{PULL_UP}= 1.8 V

0.4

V

1.2

0.4

0.3

8.5

2.5

1

V

I_LKG

V_{PULL_UP}= 1.8 V

Standard mode

Fast mode

0.01

µA

R_PULL-UPPullup resistance

kΩ

Fast mode plus

C_OUT

Total load capacitance per pin

50

pF

7.12 Digital Input Signals (CTLx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

High-level input voltage

Low-level input voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

V_IL

0.85

V

0.4

V

7.13 Digital Output Signals (IRQB, GPOx)

Over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

Low-level output voltage

Leakage current

TEST CONDITIONS

I_OL< 2 mA

V_{PULL_UP}= 1.8 V

MIN

TYP

MAX UNIT

V_OL

I_LKG

0.4

V

0.35

µA

7.14 Timing Requirements

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

MIN

NOM

MAX

UNIT

I²C INTERFACE

Clock frequency (standard mode)

100

400

kHz

ns

f_CLK

Clock frequency (fast mode)

Clock frequency (fast mode plus)

Rise time (standard mode)

Rise time (fast mode)

1000

300

t_r

ns

Rise time (fast mode plus)

120

ns

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over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

MIN

NOM

MAX

300

120

UNIT

Rise time (standard mode)

Rise time (fast mode)

ns

t_f

ns

Rise time (fast mode plus)

ns

7.15 Switching Characteristics

over operating free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BUCK CONTROLLERS

Measured from enable going high to when output reaches

90% of target value.

t_PG

Total turnon time

550

50

850

µs

ns

Minimum on-time of

DRVH

T_ON,MIN

DRVH off to DRVL on

DRVL off to DRVH on

15

30

ns

T_DEAD

Driver dead-time

Continuous-conduction mode,

V_IN= 13 V, V_OUT≥1 V

f_SW

Switching frequency

1000

kHz

BUCK CONVERTERS

Measured from enable going high to when output reaches

90% of target value.

t_PG

Total turnon time

250

1000

µs

f_SW

Switching frequency

Continuous-conduction mode

MHz

See 图7-10

LDOAx

Measured from enable going high to when output reaches

95% of final value,

V_OUT= 1.2 V, C_OUT= 4.7 µF

t_STARTUP

Start-up time

180

22

µs

VTT LDO

t_STARTUP

SWA1

Measured from enable going high to PG assertion,

V_OUT= 0.675 V, C_OUT= 40 µF

Start-up time

Turnon time

Measured from enable going high to reach 95% of final

value,

V_IN= 3.3 V, C_OUT= 0.1 µF

0.85

0.63

ms

t_TURN-ON

SWB1_2

t_TURN-ON

Measured from enable going high to reach 95% of final

value,

V_IN= 1.8 V, C_OUT= 0.1 µF

Measured from enable going high to reach 95% of final

value,

V_IN= 3.3 V, C_OUT= 0.1 µF

1.1

ms

Turnon time

Measured from enable going high to reach 95% of final

value,

0.82

V_IN= 1.8 V, C_OUT= 0.1 µF

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7.16 Typical Characteristics

Measurements are taken at 25°C.

FET = CSD87588N

L = PIMB061H-R22ms

C_OUT= 2 × 150 µF + 1 × 22 µF

图7-1. Example BUCK2 Controller Start-Up

BUCK3_MODE = 0b

L = PIFE32251B-R47ms

C_OUT= 4 × 22 µF

BUCK2_MODE = 0b

图7-2. Example BUCK3 Converter Start-Up

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

Vout = 1 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

0.1

0.2 0.3 0.40.5 0.7 1

Iout (A)

2

3

4 5 6 7

0.1

0.2 0.3 0.40.5 0.7 1

Iout (A)

2

3

4 5 6 7

D012

D011

FET = CSD87381P

BUCK1_MODE = 0b

图7-4. Example BUCK1 Efficiency at V_IN= 18 V

L = PIMB061H-R47ms

FET = CSD87381P

BUCK1_MODE = 0b

图7-3. Example BUCK1 Efficiency at V_IN= 13 V

L = PIMB061H-R47ms

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

Vout = 1 V

V_OUT= 1 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

V_OUT= 1.5 V

V_OUT= 1.8 V

V_OUT= 2.5 V

0.1

0.2

0.3 0.4 0.5 0.7

Iout (A)

1

2

3

0.1

0.2

0.3 0.4 0.5 0.7

Load Current (A)

1

2

3

D009

D013

BUCK3_MODE = 0b

L = PIFE32251B-R47ms

BUCK3_MODE = 0b

L = PIFE32251B-R47ms

图7-5. Example BUCK3 Efficiency at V_IN= 5 V

图7-6. Example BUCK3 Efficiency at V_IN= 3.3 V

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7.16 Typical Characteristics (continued)

Measurements are taken at 25°C.

2.9

710

700

690

680

670

660

650

640

630

V_OUT= 1.8 V

V_OUT= 2.5 V

V_OUT= 2.8 V

-40èC

25èC

85èC

2.7

2.5

2.3

2.1

1.9

1.7

1.5

-2

-1.5

-1

-0.5

0

Load Current (A)

0.5

1

1.5

2

0

1

2

Load Current (A)

3

4

D015

D014

FBVOUT6 = PVINVTT = 1.35 V

图7-8. VTT LDO Regulation

L = PIFE32251B-R47ms

图7-7. Converter Load Current Limitations with V_IN= 3.3 V

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

V_IN= 5 V

V_IN= 3.3 V

V_IN= 5 V

V_IN= 3.3 V

0

0.4

0.6

0.8

1

Output Voltage Setting (V)

1.2

1.4

1.6 1.8

0.4

0.8

1.2

1.6

2

Output Voltage Setting (V)

2.4

2.8

3.2

3.6

D016

D017

L = PIFE32251B-R47ms

图7-9. Converter Switching Frequency (10-mV Step Size)

图7-10. Converter Switching Frequency (25-mV Step Size)

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8 Detailed Description

8.1 Overview

The TPS650864 power-management integrated circuit (PMIC) provides a highly flexible and configurable power

solution that can power a wide array of processors along with DDR3/DDR4 memory and other peripherals.

Integrated in the PMIC are three step-down controllers (BUCK1, BUCK2, and BUCK6), three step-down

converters (BUCK3, BUCK4, and BUCK5), a sink or source LDO (VTT LDO), three low-voltage V_INLDOs

(LDOA1–LDOA3), and three load switches (SWA1, SWB1, and SWB2). With on-chip one-time programmable

(OTP) memory, configuration of each rail for default output value, power-up sequence, fault handling, and Power

Good mapping into a GPO pin are all conveniently flexible. All VRs have a built-in discharge resistor, and the

value can be changed using the DISCHCNT1–DISCHCNT3 and LDOA1_SWB2_CTRL registers. When

enabling a VR, the PMIC automatically disconnects the discharge resistor for that rail without any I²C command.

表8-1 lists the key characteristics of the voltage rails.

表8-1. Summary of Voltage Regulators

INPUT VOLTAGE (V)

OUTPUT VOLTAGE RANGE (V)

RAIL

TYPE

CURRENT (mA)

MIN

4.5

3

MAX

21

MIN

0.41

1.35

0.7

TYP

MAX

3.575

3.3

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

LDOA1

LDOA2

LDOA3

SWA1

Step-down controller

Step-down converter

Step-down Converter

Step-down converter

Step-down controller

LDO

scalable

3000

See 节5

21

5.5

21

3

3000

3

3000

4.5

1.62

0.5

1.1

scalable

200⁽¹⁾

600

5.5

1.98

3.3

1.8

LDO

1.5

LDO

0.7

1.5

600

Load switch

300

SWB1/SWB2

VTT

Load switch

400

Sink and source LDO

FBVOUT6 / 2

See 节5

(1) When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, max current is limited by max I_OUTof LDO5.

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8.2 Functional Block Diagram

LDO5V

LDO1

VIN

BOOT1

DRVH1

LDOA1

1.35 œ 3.3 V

200 mA

CTL1

CTL2

SW1

V1

VSET

EN

BUCK1

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL1

CTL3/SLPENB1

Control

CTL4

EN

VSET

FBVOUT1

Inputs

PGNDSNS1

CTL5

ILIM1

CTL6/SLPENB2

VPULL

VIN

BOOT2

DRVH2

CLK

SoC

&

System

I²C CTL

SW2

DATA

V2

VSET

EN

VPULL

DRVL2

BUCK2

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

Control

Outputs

FBVOUT2

PGNDSNS2

IRQB

GPO1

GPO2

GPO3

GPO4

FBGND2

ILIM2

Internal

Interrupt

Events

3.3 V œ 5 V

PVIN3

LX3

TEST CTL

OTP

BUCK3

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

V3

FB3

Registers

REGISTERS

<PGND_BUCK3>

3 A

3.3 V œ 5 V

PVIN4

LX4

BUCK4

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

LDO5P0

V5ANA

LDO5P0

VSET

EN

Digital Core

V4

3.3V œ 5V

FB4

3 A

<PGND_BUCK4>

3.3V œ 5V

PVIN5

LX5

BUCK5

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

œ

VSET

EN

4.7V

V5

+

FB5

STDBY

3 A

<PGND_BUCK5>

LDO5V

VIN

REFSYS

LDO3P3

BOOT6

DRVH6

Thermal

Monitoring

VSYS

5.6Vœ21V

LDO3P3

SW6

DRVL6

Thermal Shutdown

VDDQ

VSET

EN

BUCK6

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VREF

AGND

Bandgap

FBVOUT6

PGNDSNS6

ILIM6

PVIN_VTT

VTT

EN

VTT_LDO

VDDQ/2

VTTFB

LDOA2

0.7 ꢀ 1.5 V

600 mA

LDOA3

0.7 ꢀ 1.5 V

600 mA

LOAD SWA1

LOAD SWB1

LOAD SWB2

图8-1. PMIC Functional Block Diagram

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PMIC

Example SoC

PLATFORM

V_IN

BUCK1

EXT FET

V_IN

VCORE

VGPU

BUCK2

BUCK3 3A

BUCK4 3A

BUCK5 3A

BUCK6

EXT FET

5V Supply

VCCIO

VCPU1

Note: An LDO or

Buck Can Supply

the VPP Rail if

VCPU2

Needed for DDR.

V_IN

EXT FET

VDDQ, VDD1&2

VTT LDO ±0.5A

VTT

DDR

LDO5V or

5V Supply

VSUPP1

VSUPP2

VSUPP3

VSUPP4

VSUPP5

VSUPP6

LDOA1 0.2A

LDOA2 0.6A

LDOA3 0.6A

SWA1 0.3A

SWB1 0.3A

SWB2 0.3A

LDO5

1.8V

Input up to 3.3V

LDO5V

V_SYS

V_IN

5V Supply

PG_5V

LDO3P3

IRQB

GPO1 – GPO4

SDA

CTL1 – CTL6

SCL

图8-2. Power Map Example

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8.3 TPS6508640 Design and Settings

The TPS6508640 device is optimized to power the higher range of the Xilinx Zynq Ultrascale+ MPSoC, but is

compatible with the lower range as well. See 图8-3 for an example block diagram. Dashed lines show the option

to short VCCINT with VCCBRAM for cases where their voltages are the same and current < 25 A. In this case,

the TPS544C25 device is not needed and GPO1 should be shorted to CTL4.

V_IN

(4.5 œ 18 V)

TPS544C25

Xilinx Zynq UltraScale+

ZU7CG œ ZU15EG²

0.72 V

VCCINT

V_IN

V_OUT

BUCK2_PG

(GPO1)

VCCINT_PG

(CTL4)

TPS6508640

CNTL PGOOD

V_IN

(5.6 œ 21 V)

5 V (for DRV)

LDO5

V_IN

3.3 V

CSD87381P¹

V_IN

BUCK1

Peripherals

0.85 V or 0.9 V

VCCINT_IO

5 V (from LDO5)

CSD87381P¹

BUCK2

BUCK5

VCCBRAM

PL Domain

1.8 V

VCCAUX

VCCAUX_IO

VCCADC

Filter

3.3 V (from BUCK1)

1.8 V (from BUCK5)

1.2 V

0.9 V

1.8 V

VMGTAVTT

BUCK3

BUCK4

SWB1

VMGTAVCC

VMGTAVCCAUX

VCCO_HDIO

0.7 œ 1.5 V

1.8 V

LDOA2

LDOA3

SWB2

VCCO_HPIO

VCC_PSINTLP

VCC_PSAUX

VCC_PSADC

Filter

Low-Power

Domain

VCC_PSPLL

VCCO_PSIO

3.3 V (from BUCK1)

3.3 V

SWA1

PS Domain

VCC_PSINTFP

VCC_PSINTFP_DDR

VCC_PSDDR_PLL

Full-Power

Domain

Filter

VCCO_PSDDR

V_IN

5 V (from LDO5)

BUCK6 Output

1.2 V or 1.35 V

VDDQ / VDD2

VTT

CSD87381P¹

BUCK6

VTT LDO

LDOA1

0.6 V or 0.675 V

DDR Memory

5 V (from LDO5)

DDR_EN

2.5 V

VPP

I²C CLK & DATA

I²C

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

DDR_SEL

BUCK2_PG

I2C_GPO

GPO1

GPO2

GPO3

GPO4

Main Sequence

VCCINT_PG

VTT_EN

PS_POR_B

BUCK4_PG

BUCK2_SEL

(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.

(2) The TPS6508640 is not limited to the ZU7CG - ZU15EG. It can support other Ultrascale+ devices as long as the use case does not

exceed the maximum specifications of the TPS6508640.

图8-3. TPS6508640 Power Map Example

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The power up and power down sequences can be seen in 图 8-4 and 图 8-5. Regulators and GPOs are enabled

by combination of CTL pins and regulator power good signals.

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VSYS

5.6 V

LDO5/LDO3P3

I²C Available

CTL3

[and CTL1 if used]

0.85 V (CTL6 = ‘0’)

0.9 V (CTL6 = ‘1’)

BUCK2

(VCCBRAM)

GPO1

(BUCK2_PG)

0.72 V

VCCINT External Rail when

not merged with VCCBRAM

CTL4

(VCCINT_PG)

3.3 V

BUCK1

(VCC_3V3)

0.9 V

BUCK4

(VMGTAVCC)

GPO4

(BUCK4_PG)

1.2 V

BUCK3

(VMGTAVTT)

2 ms

1.8 V

BUCK5

(VCCAUX)

SWB1

(VMGTAVCCAUX)

Disabled if CTL1 = ‘0’

2.5 V (CTL1 = ‘1’)

LDOA1

(VPP)

2 ms

SWA1

(VCCO_PSIO)

Disabled if CTL1 = ‘0’

1.2 V (CTL1 = ‘1’ & CTL2 = ‘0’)

1.35 V (CTL1 = ‘1’ & CTL2 = ‘1’)

BUCK6

(VCCO_PSDDR / VDDQ)

Disabled if CTL5 = ‘0’ or CTL1 = ‘0’

0.6 V (CTL5 = ‘1’ & CTL2 = ‘0’)

0.675 V (CTL5 = ‘1’ & CTL2 = ‘1’)

VTT LDO

(VTT)

GPO3

(PS_POR_B)

75 ms

图8-4. TPS6508640 Power-Up Sequence

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CTL3

[and CTL1 if used]

GPO3,

GPO4

SWA1

[BUCK6, VTT LDO

if used]

BUCK3, BUCK5,

SWB1 [LDOA1 if

used]

2 ms

4 ms

BUCK1, BUCK2,

BUCK4

GPO1

图8-5. TPS6508640 Power-Down Sequence

TPS6508640 sequence includes an optional slot for an external rail to power VCCINT. When using an external

rail, GPO1 should be connected to the enable of the external rail and the power good of the external rail should

be connected to CTL4. When merging VCCINT and VCCBRAM, GPO1 can be connected directly to CTL4.

CTL1 and CTL5 are used to enable the portion of the sequencing related to DDR memory. This includes BUCK6,

LDOA1, and VTT LDO. Connecting the CTL1 pin to the same input as CTL3 will result in BUCK6 being enabled

2 ms after BUCK5 and LDOA1 being enabled after BUCK6 PG. If CTL5 is connected to the same input as well,

VTT LDO will turn on after BUCK6 PG as well.

CTL2 is used to select DDR voltage between 1.2 V (logic level low) and 1.35 V (logic level high).

CTL6 is used to select BUCK2 (VCCBRAM) voltage between 0.85 V (logic level low) and 0.9 V (logic level high).

BUCK3 also has SLP_EN = 1b by default, so if using 0.85 V for VCCBRAM (CTL6 logic level low), then to

modify BUCK3 VID during operation, BUCK3_SLP_VID register bits should be used.

LDOA2 and LDOA3 are controlled only by I²C.

A summary of the part number specific settings can be seen in 节8.3.1.

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8.3.1 TPS6508640 OTP Summary

The following tables list the TPS6508640 device settings for the buck regulators, general purpose LDOs, VTT

LDO, load switches, and GPOs. LDOA1 is used in sequence so all registers with SWB2_LDOA1 will function as

LDOA1. Additionally, SWB1 and SWB2 are not merged so all registers with LDOA1_SWB2 will function as

SWB2. All values which can be modified by I²C after power on are shown in italics. Additional details (such as

GPO power good inputs) can be found in the register map.

表8-2. TPS6508640 Settings Summary—Buck Regulators

SLEEP

VOLTAGE

POWER FAULT

MASKED

FORCE

PWM

REGULATOR

DEFAULT VOLTAGE

STEP SIZE

SLP PIN

SLP_EN

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

3.3 V

0.9 V

1.2 V

0.9 V

1.8 V

3.3 V

0.85 V

1.2 V

0.9 V

1.8 V

25 mV

10 mV

25 mV

CTL6

No

Yes

No

Yes

No

CTL2 &

CTL6

BUCK6

1.35 V / 1.2 V

1.35

10 mV

No

Yes

表8-3. TPS6508640 Settings Summary—General Purpose LDOs

DEFAULT

VOLTAGE

POWER FAULT

MASKED

REGULATOR

SLEEP VOLTAGE

ALWAYS ON

SLP PIN

SLP_EN

LDOA1

LDOA2

LDOA3

2.5 V

1.5 V

1.2 V

No

Yes

—

No

1.5 V

1.2 V

CTL6

表8-4. TPS6508640 Settings Summary—VTT LDO

REGULATOR

ILIM SETTING

ENABLE PIN

POWER FAULT MASKED

VTT LDO

1.8 A

CTL3

No

表8-5. TPS6508640 Settings Summary—Load Switches

REGULATOR

SWA1

POWER GOOD VOLTAGE

SWB1_2 MERGED

POWER FAULT MASKED

3.3 V

1.8 V

Yes

—

No

SWB1

SWB2

表8-6. TPS6508640 Settings Summary—GPOs

GPO

GPO1

GPO2

GPO3

GPO4

POWER GOOD (PG) or I²C

STATE

OUTPUT TYPE

Push Pull

PG

I²C

PG

—

Low

Open Drain

—

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8.4 TPS65086401 Design and Settings

The TPS65086401 device is intended to power the lower range of the Xilinx Zynq Ultrascale+ platform. An

example block diagram for this system can be seen in 图8-6.

TPS65086401

Xilinx Zynq UltraScale+

ZU2CG œ ZU5EG²

V_IN

0.85 V

1.8 V

5 V (from LDO5)

VCCINT

VCCBRAM

VCCINT_IO

CSD87381P¹

BUCK2

BUCK3³

BUCK1

5 V (from ext supply)

0.85 V

V_IN

VCCAUX

VCCAUX_IO

VCCADC

PL Domain

CSD87381P¹

1.8 V (BUCK1)

1.8 V

SWB1_2³

BUCK4

Filter

3.3 V

VCCO

BUCK5³

VCC_PSINTLP

5 V (from LDO5)

1.8 V (BUCK1)

1.8 V

VCC_PSADC

VCC_PSAUX

LDOA1

Low-Power

Domain

1.2 V

VCC_PSPLL

VCCO_PSIO

LDOA2

LDOA3³

SWA1

1.2 V

PS Domain

VCC_PSINTFP

0.5 œ 3.3 V

VCC_PSINTFP_DDR

VCC_PSDDR_PLL

VPS_MGTRAVTT

Full-Power

Domain

Filter

VPS_MGTRAVCC

VCCO_PSDDR

Filter

V_IN

1.1, 1.2, or 1.5 V

CSD87381P¹

BUCK6

DDR Memory

0.55, 0.6, or 0.75 V

I²C CLK & DATA

VTT LDO

I²C

Main Sequence

DDR_SEL1

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

CTL1 Seq PG

CTL4 Seq PG

GPO1

GPO2

GPO3

GPO4

DDR_SEL2

Secondary Sequence

SWA1_EN

PS_POR_B (CTL1 Seq PG + 5 ms)

SWA1_PG

BUCK4_VTT_EN

(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.

(2) The TPS65086401 is not limited to the ZU2CG - ZU5EG. It can support other Ultrascale+ devices as long as the use case does not

exceed the maximum specifications of the TPS65086401.

(3) PL Domain can be optionally powered by BUCK3, SWB1_2, BUCK5, and LDOA3 to allow it to be enabled and disabled by CTL4.

This applies only to use cases where VCCINT current is less than 3 A.

图8-6. TPS65086401 Power Map Example

The power up and power down sequences can be seen in 图 8-7 and 图 8-8. Regulators and GPOs are enabled

by combination of CTL pins and regulator power good signals.

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VSYS

5.6 V

LDO5/LDO3P3

I²C Available

CTL1

0.85 V

BUCK2

1.8 V

1.2 V

1.8 V

2 ms

BUCK1

LDOA2

LDOA1

BUCK6

GPO1

1.1 V (CTL3 = 0, CTL2 = 0 or 1)

1.2 V (CTL3 = 1, CTL2 = 0)

1.5 V (CTL3 = 1, CTL2 = 1)

2 ms

CTL1 and PG of above regulators

Typically shorted to GPO1

3.3 V

CTL6

0.55 V (CTL3 = 0, CTL2 = 0 or 1)

0.6 V (CTL3 = 1, CTL2 = 0)

0.75 V (CTL3 = 1, CTL2 = 1)

BUCK4

VTT LDO

GPO3

5 ms

GPO1 + 5 ms delay

CTL4

0.85 V

BUCK3

1.2 V

2 ms

LDOA3

SWB1_2

BUCK5

GPO2

1.8 V (default PG level)

3.3 V

2 ms

PG of BUCK3, BUCK5,

LDOA3, and SWB1_2

图8-7. TPS65086401 Power-Up Sequence

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CTL1

GPO1,

GPO3

CTL6

BUCK4, BUCK6,

VTT LDO

BUCK1, LDOA1,

LDOA2

2 ms

4 ms

BUCK2

CTL4 or CTL1

GPO2

BUCK5

LDOA3,

SWB1_2

2 ms

4 ms

BUCK3

图8-8. TPS65086401 Power-Down Sequence

CTL1 is used to enable the general system, CTL6 is typically connected to GPO1, and CTL4 can be used or not

used depending on the application. CTL5 enables SWA1 independently of the rest of the sequence. CTL2 and

CTL3 are used for BUCK6 voltage selection.

A summary of the part number specific settings can be seen in 节8.4.1.

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8.4.1 TPS65086401 OTP Summary

The following tables list the TPS65086401 device settings for the buck regulators, general purpose LDOs, VTT

LDO, load switches, and GPOs. LDOA1 is used in sequence so all registers with SWB2_LDOA1 will function as

LDOA1. Additionally, SWB1 and SWB2 are merged so all registers with LDOA1_SWB2 will be unused. All

values which can be modified by I²C after power on are shown in italics. Additional details (such as GPO power

good inputs) can be found in the register map.

表8-7. TPS65086401 Settings Summary—Buck Regulators

SLEEP

VOLTAGE

POWER FAULT

MASKED

FORCE

PWM

REGULATOR

DEFAULT VOLTAGE

STEP SIZE

SLP PIN

SLP_EN

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

1.8 V

0.85 V

3.3 V

1.8 V

0.85 V

0 V

25 mV

10 mV

25 mV

CTL3

CTL6

CTL3

No

Yes

No

3.3 V

CTL2 &

CTL3

BUCK6

1.5 V / 1.2 V

1.1 V

10 mV

Yes

No

表8-8. TPS65086401 Settings Summary—General Purpose LDOs

DEFAULT

VOLTAGE

POWER FAULT

MASKED

REGULATOR

SLEEP VOLTAGE

ALWAYS ON

SLP PIN

SLP_EN

LDOA1

LDOA2

LDOA3

1.8 V

No

—

No

—

No

1.2 V

CTL3

1.2 V

表8-9. TPS65086401 Settings Summary—VTT LDO

REGULATOR

ILIM SETTING

ENABLE PIN

POWER FAULT MASKED

VTT LDO

0.95 A

CTL6

Yes

表8-10. TPS65086401 Settings Summary—Load Switches

REGULATOR

SWA1

POWER GOOD VOLTAGE

SWB1_2 MERGED

POWER FAULT MASKED

3.3 V

1.8 V

No

—

SWB1

Yes

SWB2

表8-11. TPS65086401 Settings Summary—GPOs

GPO

GPO1

GPO2

GPO3

GPO4

POWER GOOD (PG) or I²C

STATE

OUTPUT TYPE

Open Drain

PG

—

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8.5 TPS6508641 Design and Settings

The TPS6508641 device is intended to power the lower range of the Xilinx Zynq Ultrascale+ platform. It removes

the need for an external 5 V regulator when compared with the TPS65086401 device and also supports a wider

variety of Zynq Ultrascale+ power states. 图 8-9 shows a simple example block diagram for an always-on

system, while 图 8-10 shows a block diagram for full power domain flexibility. See Xilinx's Ultrascale Architecture

PCB Design for explanation of the power supply configurations.

TPS6508641

Xilinx Zynq UltraScale+

ZU2CG œ ZU5EG²

V_IN

5 V

CSD87381P¹

V_IN

BUCK1

0.85 V

VCCINT

VCCINT_IO

VCCBRAM

5 V (from LDO5)

CSD87381P¹

BUCK2

PL Domain

0.5 œ 3.3 V

VCCAUX

VCCAUX_IO

VCCADC

SWB1_2

Filter

VCCO_HDIO

1.2 V

V_IN

1.8 V (from BUCK6)

VCCO_HPIO

LDOA3

BUCK6

VCC_PSINTLP

1.8 V

VCC_PSAUX

VCC_PSADC

VCCO_PSIO

CSD87381P¹

Low-Power

Domain

Filter

1.2 V

VCC_PSPLL

LDOA2

PS Domain

VCC_PSINTFP

VCC_PSINTFP_DDR

VCC_PSDDR_PLL

VCCO_PSDDR

Filter

Full-Power

Domain

V_IN

(5.6 œ 21 V)

5 V (for DRV)

LDO5

VTT LDO

LDOA1

0.9 V

1.8 V

1.8 V (from BUCK6)

VPS_MGTRAVCC

VPS_MGTRAVTT

VDDQ / VDD2

VDD1

1.1 V or 1.2 V

BUCK3

DDR Memory

Peripherals

5 V (from BUCK1)

3.3 V

1.2 V

BUCK4

BUCK5

SWA1

0.5 œ 3.3 V

I²C CLK & DATA

I²C

PS_POR_PB_B

SWA1_EN

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

BUCK1_PG

I2C_GPO

GPO1

GPO2

GPO3

GPO4

POWER_EN

DDR_SEL

PS_POR_B

BUCK4_PG

(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.

(2) The TPS6508641 is not limited to the ZU2CG - ZU5EG. It can support other Ultrascale+ devices as long as the use case does not

exceed the maximum specifications of the TPS6508641.

图8-9. TPS6508641 Always-On Power Map Example

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TPS6508641

Xilinx Zynq UltraScale+

ZU2CG œ ZU5EG²

V_IN

5 V

CSD87381P¹

V_IN

BUCK1

GPO4

0.85 V

Load

Switch

VCCINT

VCCINT_IO

VCCBRAM

5 V (from LDO5)

BUCK2

CSD87381P¹

PL Domain

1.8 V

1.8 V (from BUCK6)

SWB1_2

VCCAUX

VCCAUX_IO

VCCADC

Filter

VCCO_HDIO

1.2 V

V_IN

1.8 V (from BUCK6)

LDOA3

VCCO_HPIO

VCC_PSINTLP

1.8 V

VCC_PSAUX

VCC_PSADC

VCCO_PSIO

BUCK6

LDOA2

CSD87381P¹

Low-Power

Domain

Filter

1.2 V

VCC_PSPLL

GPO1

PS Domain

VCC_PSINTFP

Load

Switch

VCC_PSINTFP_DDR

VCC_PSDDR_PLL

VCCO_PSDDR

Filter

Full-Power

Domain

V_IN

(5.6 œ 21 V)

5 V (for DRV)

LDO5

0.9 V

1.8 V

1.8 V (from BUCK6)

VTT LDO

VPS_MGTRAVCC

VPS_MGTRAVTT

LDOA1

VDDQ / VDD2

VDD1

1.1 V or 1.2 V

BUCK3

DDR Memory

Peripherals

5 V (from BUCK1)

BUCK4

3.3 V

1.2 V

BUCK5

0.5 œ 3.3 V

SWA1

I²C CLK & DATA

I²C

PS_POR_PB_B

CTL1

SWA1_EN

CTL2

PSINTFP_EN

I2C_GPO

GPO1

GPO2

GPO3

GPO4

PS_FP_PWR_EN_LS

CTL3

POWER_EN

CTL4

PS_POR_B

VCCINT_EN

PL_PWR_EN

CTL5

DDR_SEL

CTL6

(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.

(2) The TPS6508641 is not limited to the ZU2CG - ZU5EG. It can support other Ultrascale+ devices as long as the use case does not

exceed the maximum specifications of the TPS6508641.

图8-10. TPS6508641 Full Power Domain Flexibility Power Map Example

The power up and power down sequences can be seen in 图 8-11 and 图 8-12. Regulators and GPOs are

enabled by combination of CTL pins and regulator power good signals.

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VSYS

5.6 V

LDO5/LDO3P3

I²C Available

CTL4

(POWER_EN)

5 V

BUCK1

(VCC_5V0)

CTL3

(PS_FP_PWR_EN_LS)

0.85 V

BUCK2

(VCC_PSINTLP)

GPO1

(PSINTFP EN)

0.85 V

1.2 V

External Load Switch #1

(VCC_PSINTFP)

BUCK5

(VCC_1V2)

1.8 V

BUCK6

(VCC_PSAUX)

1.2 V

LDOA2

(VCC_PSPLL)

0.9 V

VTT LDO

(VPS_MGTRAVCC)

1.8 V

LDOA1

(VPS_MGTRAVTT)

1.1 V (CTL6 = ”1‘)

1.2 V (CTL6 = ”0‘)

BUCK3

(VDDQ / VCCO_PSDDR)

3.3 V

BUCK4

(VCC_3V3)

CTL5

(PL_PWR_EN)

GPO4

(VCCINT_EN)

0.85 V

External Load Switch #2

(VCCINT)

1.8 V

2 ms

4 ms

SWB1_2

(VCCAUX)

1.2 V

LDOA3

(VCCO_HPIO)

CTL1 = ”1‘

& 50 ms

GPO3

(PS_POR_B)

图8-11. TPS6508641 Power-Up Sequence

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CTL4

(POWER_EN)

GPO3

(PS_POR_B)

BUCK3, LDOA1¹

BUCK6, BUCK4,

LDOA2, VTT LDO¹,

SWB1_2², LDOA3²

2 ms

GPO4²

(VCCINT_EN)

External Load Switch #2²

(VCCINT)

BUCK1, BUCK2,

BUCK5

4 ms

GPO1¹

(PSINTFP_EN)

External Load Switch #1¹

(VCC_PSINTFP)

(1) Sequence shown assumes CTL3 is high. If CTL3 is set low before this point, these voltage regulators will already be disabled.

(2) Sequence shown assumes CTL5 is high. If CTL5 is set low before this point, these voltage regulators will already be disabled.

图8-12. TPS6508641 Power-Down Sequence

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Full Power

PL Disabled

PS FP Disabled

PL Disabled

Full Power

CTL5

(PL_PWR_EN)

GPO4

(VCCINT_EN)

External Load Switch #2

(VCCINT)

2 ms

4 ms

SWB1_2

(VCCAUX)

LDOA3

(VCCO_HPIO)

CTL3

(PS_FP_PWR_EN_LS)

GPO1

(PSINTFP EN)

External Load Switch #1

(VCC_PSINTFP)

VTT LDO

(VPS_MGTRAVCC)

LDOA1

(VPS_MGTRAVTT)

图8-13. TPS6508641 Low Power States

The TPS6508641 device is designed to be able to support always on and full power domain flexibility power

modes. The low power states can be omitted if not required.

CTL4 is used to start the primary power sequence and CTL1, CTL3, and CTL5 should all be high initially to

complete the power up sequence. For always-on case, CTL3 and CTL5 can be shorted with CTL4.

CTL6 is used to select BUCK3 voltage between BUCK3_VID and BUCK3_SLP_VID register bits. Logic level low

will result in 1.2 V while logic level high will result in 1.1 V.

CTL2 is used to enable and disable SWA1 and is independent of the rest of the sequence.

When CTL1 is set low, GPO3 (PS_POR_B) is set low regardless of the power state and has 50 ms delay before

going high after CTL1 goes high. It is used as a reset for the Zynq Ultrascale+ device. It can be pulled up to

LDO3P3 (3.3 V) or BUCK6 (1.8 V) as preferred with a 10 kΩresistor and a pushbutton can short this CTL pin to

GND when MPSoC reset is desired.

GPO1 and GPO4 are used to control load switches when utilizing the low power modes. The load switches can

be omitted for cases where low power modes are not necessary.

VTT LDO voltage used to power VPS_MGTRAVCC is configured to 0.9 V in order to support all variant speeds,

including -3E designs. It is within the absolute voltage range and is not expected to impact performance for

non-3E designs based on testing with the Ultra96 board. For more information on VPS_MGTRAVCC voltage,

see Xilinx's Ultrascale Architecture PCB Design, Table 7-2 MPSoC PS Voltage Matrix by Speed/Temperature

Grade.

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A summary of the part number specific settings can be seen in 节8.5.1.

8.5.1 TPS6508641 OTP Summary

The following tables list the TPS6508641 device settings for the buck regulators, general purpose LDOs, VTT

LDO, load switches, and GPOs. LDOA1 is used in sequence so all registers with SWB2_LDOA1 will function as

LDOA1. Additionally, SWB1 and SWB2 are merged so all registers with LDOA1_SWB2 are unused. All values

which can be modified by I²C after power on are shown in italics. Additional details (such as GPO power good

inputs) can be found in the register map.

表8-12. TPS6508641 Settings Summary—Buck Regulators

SLEEP

VOLTAGE

POWER FAULT

MASKED

FORCE

PWM

REGULATOR

DEFAULT VOLTAGE

STEP SIZE

SLP PIN

SLP_EN

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

Ext FB

0.85 V

1.1 V

3.3 V

1.2 V

1.8 V

Ext FB

0.85 V

1.2 V

3.3 V

1.2 V

1.8 V

CTL6

No

Yes

No

Yes

—

10 mV

25 mV

表8-13. TPS6508641 Settings Summary—General Purpose LDOs

DEFAULT

VOLTAGE

POWER FAULT

MASKED

REGULATOR

SLEEP VOLTAGE

ALWAYS ON

SLP PIN

SLP_EN

LDOA1

LDOA2

LDOA3

1.8 V

No

—

1.2 V

CTL6

Yes

1.2 V

表8-14. TPS6508641 Settings Summary—VTT LDO

REGULATOR

ILIM SETTING

ENABLE PIN

POWER FAULT MASKED

VTT LDO

1.8 A

CTL3

No

表8-15. TPS6508641 Settings Summary—Load Switches

REGULATOR

SWA1

POWER GOOD VOLTAGE

SWB1_2 MERGED

POWER FAULT MASKED

3.3 V

1.8 V

Yes

No

—

SWB1

Yes

SWB2

No

表8-16. TPS6508641 Settings Summary—GPOs

GPO

GPO1

GPO2

GPO3

GPO4

POWER GOOD (PG) or I²C

STATE

OUTPUT TYPE

Open Drain

PG

I²C

PG

—

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8.6 TPS65086470 Design and Settings

The TPS65086470 device is originally intended to power a Xilinx Artix 7 platform. 图 8-14 shows an example

block diagram for this system.

TPS65086470

Xilinx Artix 7

V_IN

5 V (from LDO5)

1 V

VCCINT

VCCBRAM

VCCAUX

CSD87381P¹

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

LDOA1

LDOA2

LDOA3

SWA1

1.8 V

CSD87381P¹

1.2 V

VCCADC

Filter

5 V (from ext supply)

VMGTAVTT

VCCOa

VCCOb

2.5 V

3.3 V

5 V (from LDO5)

1.8 V (BUCK2)

1.35 œ 3.3 V

0.7 œ 1.5 V

0.5 œ 3.3 V

SWB1

SWB2

VCCO_DDR

V_IN

5 V (from LDO5)

BUCK6 Output

1.35 or 1.5 V

CSD87381P¹

BUCK6

DDR Memory

0.675 or 0.75 V

I²C CLK & DATA

VTT LDO

I²C

Main Sequence 1

Main Sequence 2

VTT_EN

CTL1

CTL2

CTL3

CTL4

CTL5

CTL6

BUCK1_2_PG

System_PG

I2C_GPO3

GPO1

GPO2

GPO3

GPO4

SWA1_SWB1_EN

SWB2_EN

I2C_GPO4

DDR_SEL

(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.

图8-14. TPS65086470 Power Map Example

图 8-15 and 图 8-16 show the power-up and power-down sequences. Regulators and GPOs are enabled by

combination of CTL pins and regulator power good signals.

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5.6 V

VSYS

LDO5/LDO3P3

I²C Available

CTL1

1 V

BUCK1

(VCC_INT)

1.8 V

BUCK2

(VCC_AUX)

GPO1

(BUCK1/2 PG)

CTL2

1.2 V

BUCK3

(VMGTAVTT)

2.5 V

BUCK4

(VCCOa)

3.3 V

BUCK5

(VCCOb)

1.5 V if CTL6 = ”0‘

1.35 V if CTL6 = ”1‘

BUCK6

(VCCO_DDR)

Disabled if CTL3 = ”0‘

0.75 V if CTL6 = ”0‘ & CTL3 = ”1‘

0.675 V if CTL6 = ”1‘ & CTL3 = ”1‘

2.5 ms

VTT LDO

GPO2

(System PG)

PG of all BUCKs + VTT LDO

图8-15. TPS65086470 Power-Up Sequence

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CTL2

GPO2

(System PG)

VTT LDO

BUCK6

(VCCO_DDR)

BUCK5

(VCCOb)

4 ms

BUCK4

(VCCOa)

BUCK3

(VMGTAVTT)

CTL1

GPO1

(BUCK1/2 PG)

BUCK2

(VCC_AUX)

4 ms

BUCK1

(VCC_INT)

图8-16. TPS65086470 Power-Down Sequence

If CTL1 and CTL2 are set low at the same time, both sequences will occur simultaneously. If CTL1 is set low

before CTL2, GPO1 and GPO2 will go low and remaining bucks will be disabled as their PG enable is lost. For

example, as BUCK2 is disabled after 4 ms, BUCK3 will start it's 4 ms delay. As such it is recommended to not

set CTL1 low before CTL2.

Additionally, CTL4 can be used to enable SWA1 and SWB1. CTL5 can be used to enable SWB2. LDOA2 and

LDOA3 are controlled only by I²C.

A summary of the part number specific settings can be seen in 节8.6.1.

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8.6.1 TPS65086470 OTP Summary

The following tables list the TPS65086470 device settings for the buck regulators (表 8-17), general purpose

LDOs (表 8-18), VTT LDO (表 8-19), load switches (表 8-20), and GPOs (表 8-21). LDOA1 is not used in

sequence so all registers with LDOA1_SWB2 will function as LDOA1. Additionally, SWB1 and SWB2 are not

merged so all registers with SWB2_LDOA1 will function as SWB2. All values which can be modified by I²C after

power on are shown in italics. Additional details (such as GPO power good inputs) can be found in the register

map.

表8-17. TPS65086470 Settings Summary—Buck Regulators

SLEEP

VOLTAGE

POWER FAULT

MASKED

FORCE

PWM

REGULATOR

DEFAULT VOLTAGE

STEP SIZE

SLP PIN

SLP_EN

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

1 V

1.8 V

1.2 V

2.5 V

3.3 V

1.35 V

10 mV

25 mV

CTL6

No

Yes

No

1.8 V

1.2 V

2.5 V

3.3 V

1.5 V

表8-18. TPS65086470 Settings Summary—General Purpose LDOs

DEFAULT

VOLTAGE

POWER FAULT

MASKED

REGULATOR

SLEEP VOLTAGE

ALWAYS ON

SLP PIN

SLP_EN

LDOA1

LDOA2

LDOA3

1.8 V

No

—

Yes

—

No

0.7 V

CTL6

0.7 V

表8-19. TPS65086470 Settings Summary—VTT LDO

REGULATOR

ILIM SETTING

ENABLE PIN

POWER FAULT MASKED

VTT LDO

0.95 A

CTL3

No

表8-20. TPS65086470 Settings Summary—Load Switches

REGULATOR

SWA1

POWER GOOD VOLTAGE

SWB1_2 MERGED

POWER FAULT MASKED

3.3 V

1.8 V

Yes

—

No

SWB1

SWB2

表8-21. TPS65086470 Settings Summary—GPOs

GPO

GPO1

GPO2

GPO3

GPO4

POWER GOOD (PG) OR I²C

STATE

OUTPUT TYPE

Open drain

PG

I²C

—

Low

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8.7 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set by an

external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the

desired system load. The buck converters include integrated power stage and require a minimum number of pins

for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these

features allow use of inductors in small form factor, thus reducing total-system cost and size.

BUCK1 –BUCK6 have selectable auto- and forced-pulse width modulation (PWM) mode through the

BUCKx_MODE bit in the BUCKxCTRL register. In default auto mode, the VR automatically switches between

PWM and pulsed frequency modulation (PFM) depending on the output load to maximize efficiency.

All controllers and converters can be used with the default V_OUTor can have their voltage dynamically changed

at any time. This means that the rails can be default programmed for any available V_OUTby OTP programming

at the factory, so the device starts up with the default voltage, or during operation the rail can be configured by

I²C to another operating V_OUTwhile the rail is enable or disabled. There are two step sizes or ranges available

for V_OUTselection : 10-mV and 25-mV steps. The step-size range must be selected prior to use and must be

programmed in the OTP at the factory. It is not subject to change during operation.

For the 10-mV step-size range V_OUToptions, see 表 8-22. For the 25-mV step-size range V_OUToptions, see 表

8-23.

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表8-22. 10-mV Step-Size V_OUTRange

VID BITS

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

V_OUT

0

VID BITS

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

V_OUT

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

1.11

1.12

1.13

1.14

1.15

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

1.24

1.25

VID BITS

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

V_OUT

1.26

1.27

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

1.38

1.39

1.40

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

1.56

1.57

1.58

1.59

1.60

1.61

1.62

1.63

1.64

1.65

1.66

1.67

0.41

0.42

0.43

0.44

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

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VID BITS

表8-23. 25-mV Step-Size V_OUTRange

V_OUT

(Converters)

V_OUT

VID BITS

V_OUT

VID BITS

V_OUT

(Controllers)

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

2.000

2.025

2.050

2.075

2.100

2.125

2.150

2.175

2.200

2.225

2.250

2.275

2.300

2.325

2.350

2.375

2.400

2.425

2.450

2.475

2.500

2.525

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

2.550

2.575

2.600

2.625

2.650

2.675

2.700

2.725

2.750

2.775

2.800

2.825

2.850

2.875

2.900

2.925

2.950

2.975

3.000

3.025

3.050

3.075

3.100

3.125

3.150

3.175

3.200

3.225

3.250

3.275

3.300

3.325

3.350

3.375

3.400

3.425

3.450

3.475

3.500

3.525

3.550

3.575

0.425

0.450

0.475

0.500

0.525

0.550

0.575

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

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8.7.1 Controller Overview

The controllers are fast-reacting, high-frequency, scalable output power controllers capable of driving two

external N-MOSFETs. They are D-CAP2 controller scheme that optimizes transient responses at high load

currents for such applications as CORE and DDR supplies. The output voltage is compared with internal

reference voltage after divider resistors. The PWM comparator determines the timing to turn on the high-side

MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage. Because the

device does not have a dedicated oscillator for control loop on board, switching cycle is controlled by the

adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by feed-forwarding the

input and output voltage into the on-time one-shot timer.

The D-CAP2 control scheme has an injected ripple from the SW node that is added to the reference voltage to

simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP^™mode control.

Thus, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used with the controllers.

VDD

V_REFœ V_{TH_PG}

+

UV

PGOOD

FAULT

EN

œ

PGOOD

+

DCHG

VFB

OV

V_REF+ V_{TH_PG}

œ

+

Control Logic

œ

+

PWM

Ramp Generator

REF

BOOTx

DRVHx

SWx

SS Ramp Comp

HS

VSYS

XCON

œ

OC

DRV5V_x_x

œ

50 µA

+

ILIM

LS

DRVLx

œ

NOC

+

PGNDSNSx

One-Shot

GND

+

ZC

œ

PMIC Internal Signals

External Inputs/Outputs

图8-17. Controller Block Diagram

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8.7.2 Converter Overview

The PMIC synchronous step-down DCDC converters include a unique hysteretic PWM controller scheme which

enables a high switching frequency converter, excellent transient and AC load regulation as well as operation

with cost-competitive external components. The converter topology supports forced PWM mode as well as

power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent current

consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In forced PWM

mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows filtering of the switch

noise by external filter components. The PMIC device offers fixed output voltage options featuring smallest

solution size by using only three external components per converter.

A significant advantage of PMIC compared to other hysteretic PWM controller topologies is its excellent AC load

transient regulation capability. When the output voltage falls below the threshold of the error comparator, a

switch pulse is initiated, and the high-side switch is turned on. The high-side switch remains turned on until a

minimum ON-time of t_ONminexpires and the output voltage trips the threshold of the error comparator or the

inductor current reaches the high-side switch current limit. When the high-side switch turns off, the low-side

switch rectifier is turned on and the inductor current ramps down until the high-side switch turns on again or the

inductor current reaches zero. In forced PWM mode operation, negative inductor current is allowed to enable

continuous conduction mode even at no load condition.

PVINx

Current

Limit Comparator

VREF

0.40 V

Bandgap

High-Side

Limit

MODE or EN

MODE

Softstart

VIN

FB

Gate Driver

Anti

Shoot-Through

Control

Logic

Minimum ON Time

Minimum OFF Time

LXx

EN

VREF

+

FBx

œ

Error

Comparator

Low-Side

Limit

Integrated

Feedback

Network

Zero (Negative)

Current Limit Comparator

PGND/Thermal Pad

PMIC Internal Signals

External Inputs/Outputs

图8-18. Converter Block Diagram

8.7.3 DVS

BUCK1–BUCK6 support dynamic voltage scaling (DVS) for maximum system efficiency. The VR outputs can

slew up and down in 25-mV steps for the converters, and either 10-mV or 25-mV steps for the controllers, using

the 7-bit voltage ID (VID) defined in 节7.7 and 节7.8. DVS slew rate is minimum 2.5 mV/µs. In order to meet the

minimum slew rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV or at 6-µs interval per 25-

mV steps. When DVS is active, the VR is forced into PWM mode, unless BUCKx_DECAY = 1, to ensure the

output keeps track of VID code with minimal delay. Additionally, PGOOD is masked when DVS is in progress. 图

8-19 shows an example of slew down and up from one VID to another (step size of

10 mV).

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VID

Number of Steps × 3 µs

V_OUT

图8-19. DVS Timing Diagram I (BUCKx_DECAY = 0)

As shown in 图 8-20, if a BUCKx_VID[6:0] is set to 7b000 0000, its output voltage will slew down to 0.5 V first,

and then will drift down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] is set to a value

(neither 7b000 0000 nor 7b000 0001) when its output voltage is less than 0.5 V, the VR will ramp up to 0.5 V first

with soft-start kicking in, then will slew up to target voltage in the slew rate mentioned previously. It must be

noted that a fixed 200 µs of soft-start time is reserved for V_OUTto reach 0.5 V. In this case, however, the SMPS

is not forced into PWM mode as it otherwise could cause V_OUTto droop momentarily if V_OUTmight have been

drifting above 0.5 V for any reason.

VID

Number of

Steps × 3 µs

V_OUT

Load and Time

Dependent

200 µs

图8-20. DVS Timing Diagram II (BUCKx_DECAY = 0)

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8.7.4 Decay

In addition to DVS, BUCK1–BUCK6 can decay down to a lower voltage when BUCKx_DECAY bit in

BUCKxCTRL register is set to 1. Decay mode is only used in a downward direction of VID. The VR does not

control slew rate. As both high-side and low-side FETs stop switching, the output voltage ramps down naturally,

dictated by current drawn from the load and output filtering capacitance. When the VR is in the middle of decay

down its PGOOD is masked until V_OUTfalls below the over-voltage (OV) threshold of the set VID value. 图 8-21

shows two cases that differ from each other as to whether V_OUThas reached the target voltage corresponding to

a new VID when the VR is commanded to slew back up to a higher voltage. In case that V_OUThas not decayed

down below VID as denoted case 2, the VR will wait for VID to catch up, and then V_OUTwill start ramping up to

keep up with the VID ramp.

VID

V_OUT

case 2

case 1

图8-21. Decay Down to a Lower V_OUTand Slew Up

VID

V_OUT

case 2

200 us

case 1

图8-22. Decay Down to 0 V and Slew Up

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8.7.5 Current Limit

The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the

current limit is programmable by an external resistor at the ILIMx pin. 方程式 1 shows the calculation for a

desired resistor value, depending on specific application conditions. I_LIMREFis the current source out of the ILIMx

pin that is typically 50 µA, and R_DSONis the maximum channel resistance of the low-side FET. The scaling factor

is 1.3 to take into account all errors and temperature variations of R_DSON, I_LIMREF, and R_ILIM. Finally, 8 is another

scaling factor associated with I_LIMREF

.

I_ripple(min)

≈

’

÷

◊

R_DSONì 8 ì 1.3 ì I

-

∆

LIM

2

«

I_LIMREF

R_ILIM

=

(1)

where

• I_LIMis the target current limit. An appropriate margin must be allowed when determining I_LIMfrom maximum

output DC load current.

• I_ripple(min)is the minimum peak-to-peak inductor ripple current for a given V_OUT

.

V_OUT(V

- V_OUT)

IN(MIN)

I_ripple(min)

=

L_maxì V

ì f_sw(max)

IN(MIN)

(2)

where

• L_maxis maximum inductance

• f_sw(max)is maximum switching frequency

• V_IN(MIN)minimum input voltage to the external power stage

The buck converter limit inductor peak current cycle-by-cycle to I_{IND_LIM}is specified in 节7.8.

The current limit circuit also protects against reverse current going back into the low side FET from the load.

When operating in Force PWM mode, the inductor current is expected to go negative so it is important to ensure

that the R_ILIMvalue is sufficient to account for this. If operating in PFM, this can be neglected. The equation for

Force PWM minimum R_ILIMvalue is:

I

≈

∆

«

’

÷

◊

ripple(max)

R_DSONì 8 ì 1.3 ì

2

R_ILIM

í

I_LIMREF

(3)

(4)

where

• I_ripple(max)is the maximum peak-to-peak inductor ripple current for a given V_OUT

.

V_OUT(V

- V_OUT)

IN(MAX)

I_ripple(max)

=

L_minì V

ì f_sw(min)

IN(MAX)

where

• L_minis minimum inductance

• f_sw(min)is minimum switching frequency

• V_IN(MAX)maximum input voltage to the external power stage

If R_ILIMis too low for the chosen inductor and voltage conditions, then the ripple current at no load will trigger the

negative current limit, forcing the low side FET to turn off. This will eventually result in the output voltage

increasing above target regulation point due to irregular duty cycle created by current limit being triggered.

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8.8 LDOs and Load Switches

8.8.1 VTT LDO

Typically powered from the BUCK6 output, the VTT LDO tracks FBVOUT6 and regulates it's output to

FBVOUT6 / 2. The LDO current limit is OTP dependent, and it is designed specifically to power DDR memory.

The LDO core is a transconductance amplifier with large gain, and it drives a current output stage that either

sources or sinks current depending on the deviation of the VTTFB pin voltage from the target regulation voltage.

8.8.2 LDOA1–LDOA3

The TPS650864 device integrates three general purpose LDOs. LDOA1 is powered from a 5-V supply through

the DRV5V_2_A1 pin and it can be factory configured to be an Always-On rail (stay on even in case of

emergency shutdown) as long as a valid power supply is available at VSYS. See 表 8-24 for LDOA1 output

voltage options. LDOA2 and LDOA3 share a power input pin (PVINLDOA2_A3). The output regulation voltages

are set by writing to LDOAx_VID[3:0] bits (Reg 0x9A, 0x9B, and 0xAE). See 表 8-25 for LDOA2 and LDOA3

output voltage options. LDOA1 is controlled by the LDOA1_SWB2_CTRL register.

表8-24. LDOA1 Output Voltage Options

VID BITS

0000

V_OUT

1.35

1.5

VID BITS

V_OUT

VID BITS

V_OUT

VID BITS

1100

V_OUT

2.85

0100

1.8

1000

2.3

0001

0101

1.9

1001

2.4

1101

3.0

0010

1.6

0110

2.0

1010

2.5

1110

3.3

0011

1.7

0111

2.1

1011

2.6

1111

Not Used

表8-25. LDOA2 and LDOA3 Output Voltage Options

VID BITS

0000

V_OUT

0.70

0.75

0.80

0.85

VID BITS

V_OUT

0.90

0.95

1.00

1.05

VID BITS

V_OUT

1.10

1.15

1.20

1.25

VID BITS

1100

V_OUT

1.30

1.35

1.40

1.50

0100

1000

0001

0101

1001

1101

0010

0110

1010

1110

0011

0111

1011

1111

8.8.3 Load Switches

The PMIC features three general-purpose load switches. SWA1 has its own power input pin (PVINSWA1), while

SWB1 and SWB2 share one power input pin (PVINSWB1_B2). All switches have built-in slew rate control during

start-up to limit the inrush current.

8.9 Power Goods (PGOOD or PG) and GPOs

The device provides information on status of VRs through four GPO pins along with Power Good Status

registers defined in 节8.13.50 and 节8.13.51. Power Good information of any individual VR and load switch can

be assigned to be part of the PGOOD tree as defined from 节 8.13.40 to 节 8.13.47. PGOOD assertion delays

are programmable from 0 ms to 15 ms for GPO1, 5 ms to 100 ms for GPO3, and 0 ms to 100 ms for GPO2 and

GPO4, respectively, as are defined in 节8.13.21 and 节8.13.34.

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BUCK1_PG

BUCK1_MSK (bit)

BUCK2_PG

BUCK2_MSK (bit)

BUCK3_PG

BUCK3_MSK (bit)

BUCK4_PG

BUCK4_MSK (bit)

BUCK5_PG

BUCK5_MSK (bit)

BUCK6_PG

BUCK6_MSK (bit)

SWA1_PG

SWA1_MSK (bit)

LDOA2_PG

LDOA2_MSK (bit)

LDOA3_PG

Selectable

Rising Edge

Delay

GPOx_PG

LDOA3_MSK (bit)

SWB1_PG

SWB1_MSK (bit)

SWB2_LDOA1_PG

SWB2_LDOA1_MSK (bit)

GPOx

(Output)

0

1

GPOx_LVL

GPOx_CTL

VTT_PG

VTT_MSK (bit)

CTL1

CTL1_MSK (bit)

CTL2

CTL2_MSK (bit)

CTL3/SLPENB1

CTL3_MSK (bit)

CTL4

CTL4_MSK (bit)

CTL5

CTL5_MSK (bit)

CTL6/SLPENB2

CTL6_MSK (bit)

图8-23. Power Good Tree

Alternatively, the GPOs can be used as general purpose outputs controlled by the user through I²C. Refer to 节

8.13.37 for details on controlling the GPOs in I²C control mode. When configured as push-pull, LDO3P3 is used

for logic-level high.

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8.10 Power Sequencing and VR Control

The device has three different ways of sequencing the rails during power up and power down:

• Rail enabled by CTLx pin

• Rail enabled by Power Good (PG) of previously enabled rail

• Rail enabled by I²C software command

A delay can be added from any CTLx pin or PG to the enable of the subjected enabled rail. This creates a very

flexible device capable of many sequence options. If a rail cannot be sequenced automatically, any rail can be

enabled or disabled through an I²C command.

8.10.1 CTLx Sequencing

The device has six control-input pins (CTL1–CTL6) to control six SMPS regulators, three LDO regulators, and

three load switches. This allows the user to define up to six distinctive groups, to which each VR can be

assigned for highly flexible power sequencing. Of the six CTLx pins, CTL3 and CTL6 can be configured

alternatively to active-low sleep enable pins. For instance, if a system level SLEEP state is defined such that

BUCK1 output regulation voltage is lower than in the normal mode, then BUCK1 SLEEP state can be assigned

to CTL3 or CTL6. By being pulled low, either CTL3 or CTL6 can be used to put BUCK1 into SLEEP state, and

BUCK1 will regulate its output at a voltage defined by BUCK1_SLP_VID[6:0] in 节 8.13.23. For a demonstration

of this feature, 图8-24 shows how BUCK1 is enabled from the CTL1 pin.

8.10.2 PG Sequencing

Any rail can be sequenced by the Power Good of a prior rail. This can be combined with the CTLx method to

allow for further sequence control and create more distinctive groups of enables than the six from CTLx. This

also allows some of the CTLx pins to be freed up for other purposes such as logic input gates. For a

demonstration of this feature, 图8-24 shows how the BUCK5 is enabled from the BUCK4 PG.

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VSYS

5.6 V

LDO5/LDO3P3

LDOA1/GPO1

I²C Available

CTL1

BUCK1

BUCK2

BUCK6

CTL2

2 ms

4 ms

BUCK3

BUCK4

BUCK5

GPO4

CTL4

PG of all

BUCKs

LDOA2

LDOA3

GPO3

CTL5

16 ms

PG of BUCKs and LDOs

SWA1

SWB1

SWB2

CTL6

2 ms

8 ms

VTT

图8-24. Generic Power-Up Sequence Example

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8.10.3 Enable Delay

A delay can be added to the enable of any rail after the desired CTLx and PGs are met. This allows for the

option to create additional timing groups from either CTLx pins or internal PGs. For a demonstration of this

feature, 图8-24 shows how BUCK2 and BUCK6 are enabled after BUCK1 is enabled from CTL1 pin.

8.10.4 Power-Up Sequence

When a valid power supply is detected at the VSYS pin as V_SYScrosses above V_{SYS_UVLO_5V}

+

V_{SYS_UVLO+5V_HYS}, the power-up sequence is initiated by driving one of the control input pins high, followed by

the rest of pins in order. 图 8-24 is an example where CTL1–CTL4 are defined to control four groups of VRs,

while GPO3 and GPO4 are defined to provide a PGOOD status of two groups. The control input pins do not

necessarily have to be pulled up in a staggered manner. For instance, if CTL2 is pulled up from the preceding

group of VRs before PGOOD has been asserted at GPO1, the BUCK4 enable will be delayed until the PGOOD

is asserted.

For the specific sequencing of a TPS650864 device, see 表5-1.

8.10.5 Power-Down Sequence

The power-down sequence can follow the CTLx pins, or be controlled with the I²C commands. If the internal PGs

are used for sequencing or if some rails need to ramp down before others a delay can be added to the

deassertion low of the internal enable of the subjected rail. This delay can be independent of the power-up delay

option. Thus, power-up and power-down sequences can be different or similar to match the specific application

sequences required.

Refer to 图 8-25 for an example of a power-down sequence demonstrating the delay disable of BUCK1 and

BUCK2.

For the specific sequencing of a TPS650864 device, see 表5-1.

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CTL6

VTT

CTL5

SWA1

SWB1

SWB2

CTL4

GPO3

LDOA2

LDOA3

CTL2

GPO4

BUCK6

BUCK5

BUCK4

CTL1

BUCK6

BUCK2

BUCK1

2 ms

4 ms

图8-25. Generic Power-Down Sequence Example

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8.10.6 Sleep State Entry and Exit

Normal State

Sleep State

0 V

Normal State

1.8 V

1.8V

CTL6

CTL1-CTL4

GPO1-GPO4

BUCK1

BUCK1_VID

BUCK1_DECAY = 1

BUCK1_SLP_VID

BUCK1_DECAY = 0

图8-26. Sleep State Entry and Exit Sequence Example

图8-26 shows an example where BUCK1 is defined to enter Sleep State in response to CTL6 going low.

备注

All PGOODs from GPO1–GPO4 can stay asserted during the entry and the exit. Depending on status

of the BUCK1_DECAY bit defined in the BUCK1CTRL register, BUCK1 output will either decay or slew

down to a new voltage defined in BUCK1_SLP_VID[6:0].

8.10.7 Emergency Shutdown

5.4 V

VSYS

GPOx

444 ns (nominal with 1 œ % variation)

BUCKx

LDOAx

SWx

VTT

图8-27. Emergency Shutdown Sequence

When V_SYScrosses below V_{SYS_UVLO_5V}, all Power Good pins will be deasserted, and after 444 ns (nominal) of

delay all VRs will shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure timely

decay of all VR outputs. Other conditions that will cause emergency shutdown are the die temperature rising

above the critical temperature threshold (T_CRIT), deassertion of Power Good of any rail (configurable), or failure

of any rail to reach power good within 10 ms of being enabled (configurable). If PMIC was shutdown by UVLO, it

will wait until VSYS rises above V_{SYS_UVLO_5V}+ V_{SYS_UVLO_5V_HYS}before reloading the default OTP and

checking the state of the CTLx pins. If PMIC was shutdown by temperature, it will wait until temperature drops

below T_CRIT– T_{CRIT_HYS}before reloading OTP and checking the state of the CTLx pins. If the PMIC was

shutdown by power fault, it will reload OTP after disabling all rails and check the state of the CTLx pins once

OTP has finished reloading.

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8.11 Device Functional Modes

8.11.1 Off Mode

When power supply at the VSYS pin is less than V_{SYS_UVLO_5V}(5.4-V nominal) + V_{SYS_UVLO_5V_HYS}(0.2-V

nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than

V_{SYS_UVLO_3V}(3.6-V nominal) + V_{SYS_UVLO_3V_HYS}(0.15-V nominal) while it is still less than V_{SYS_UVLO_5V}

+

V_{SYS_UVLO_5V_HYS}, then the internal band-gap reference (VREF pin) along with LDO3P3 are enabled and

regulated at target values.

8.11.2 Standby Mode

When power supply at the VSYS pin rises above V_{SYS_UVLO_5V}+ V_{SYS_UVLO_5V_HYS}, the device enters standby

mode, where all internal reference and regulators (LDO3P3 and LDO5) are up and running, and I²C interface

and CTL pins are ready to respond. All default registers defined in 节8.13 should have by now been loaded from

one-time programmable (OTP) memory. Quiescent current consumption in standby mode is specified in 节7.5.

8.11.3 Active Mode

The device proceeds to active mode when any output rail is enabled either through an input pin as discussed in

节 8.10 or by writing to EN bits through I²C. Output regulation voltage can also be changed by writing to VID bits

defined in 节8.13.

8.12 I²C Interface

The I²C interface is a 2-wire serial interface developed by NXP^™(formerly Philips Semiconductor) (see I²C-Bus

Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line

(SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C

compatible devices connect to the I²C bus through open drain I/O pins, DATA and CLK. A master device, usually

a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL

signal and device addresses. The master also generates specific conditions that indicate the START and STOP

of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The PMIC works as a slave and supports the following data transfer modes, as defined in the I²C-Bus

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (1 Mbps). The interface

adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending

on the instantaneous application requirements. Register contents are loaded when V_SYShigher than

V_{SYS_UVLO_5V}is applied to the PMIC. The I²C interface is running from an internal oscillator that is automatically

enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred to as

F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred

to as H/S-mode.

The PMIC device supports 7-bit addressing; however, 10-bit addressing and general call address are not

supported. The default device address is 0x5E.

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8.12.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high (see 图 8-28). All I²C-compatible devices should recognize a

start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see

图 8-29). All devices recognize the address sent by the master and compare it to their internal fixed addresses.

Only the slave device with a matching address generates an acknowledge (see 图 8-30), by pulling the SDA line

low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that

the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from

the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to

high while the SCL line is high (see 图 8-28). This releases the bus and stops the communication link with the

addressed slave. All I²C-compatible devices must recognize the stop condition. Upon the receipt of a stop

condition, all devices know that the bus is released, and they wait for a start condition followed by a matching

address.

SDA

SCL

S

P

START

STOP

Condition

图8-28. START and STOP Conditions

SDA

SCL

Data Valid

Change of Data Allowed

图8-29. Bit Transfer on the I²C Bus

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Data Output at

Transmitter

Not ACK

Data Output at

Receiver

ACK

SCL from Master

S

1

2

8

9

START

Condition

Clock pulse for ACK

图8-30. Acknowledge on the I²C Bus

Generate ACK Signal

SDA

MSB

ACK Signal From Slave

Address

R/W

SCL

1

2

7

8

9

1

2

3-8

9

ACK

Byte Complete, Interrupt

Within Slave

Clock Line Held Low While

Interrupts Are Serviced

S or Sr

P or Sr

START or

Repeated START Condition

STOP or

Repeated START Condition

图8-31. I²C Bus Protocol

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SCL

SDA

A6

A5

A4

A0 R /W ACK

R7

R6

R5

R0 ACK

0

D7

D6

D5

D0 ACK

0

START

Slave Address

Register Address

Data

STOP

图8-32. I²C Interface WRITE to TPS650864 in F/S Mode

SCL

SDA

W

R/

A6

A0

ACK

0

R7

R0 ACK

0

A6

A0

ACK D7

0

D0 ACK

W

R/

0

1

0

Master

Drives ACK

and Stop

Slave Drives

the Data

Slave Address

START

Slave Address

Register Address

STOP

Repeated

START

图8-33. I²C Interface READ from TPS650864 in F/S Mode (Only Repeated START is Supported)

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8.13 Register Maps

8.13.1 Register Map Summary

Do not attempt to write a RESERVED R/W bit to the opposite value. When the reset value of a bit register is

0bX, it means the bit value is coming from the OTP memory.

表8-26. Register Map Summary

Address

00h

01h

02h

03h

04h

05h

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

40h

41h

42h

43h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Fh

A0h

A1h

A2h

A3h

A4h

A5h

Name

DEVICEID1

Short Description

Device ID code indicating revision

Interrupt statuses

DEVICEID2

IRQ

IRQ_MASK

Interrupt masking

PMIC_STAT

PMIC temperature indicator

Shutdown root cause indicator bits

SHUTDNSRC

BUCK1CTRL

BUCK2CTRL

BUCK3DECAY

BUCK3VID

BUCK1 decay control and voltage select

BUCK2 decay control and voltage select

BUCK3 decay control

BUCK3 voltage select

BUCK3SLPCTRL

BUCK4CTRL

BUCK5CTRL

BUCK6CTRL

LDOA2CTRL

LDOA3CTRL

DISCHCTRL1

DISCHCTRL2

DISCHCTRL3

PG_DELAY1

BUCK3 voltage select for sleep state

BUCK4 control

BUCK5 control

BUCK6 control

LDOA2 control

LDOA3 control

Discharge resistors for each rail control

System Power Good on GPO3 (if GPO3 is programmed to be system PG)

Software force shutdown

FORCESHUTDN

BUCK1SLPCTRL

BUCK2SLPCTRL

BUCK4VID

BUCK1 voltage select for sleep state

BUCK2 voltage select for sleep state

BUCK4 voltage select

BUCK4SLPVID

BUCK5VID

BUCK4 voltage select for sleep state

BUCK5 voltage select

BUCK5SLPVID

BUCK6VID

BUCK5 voltage select for sleep state

BUCK6 voltage select

BUCK6SLPVID

LDOA2VID

BUCK6 voltage select for sleep state

LDOA2 voltage select

LDOA3VID

LDOA3 voltage select

BUCK123CTRL

PG_DELAY2

BUCK1, 2, and 3 disable and PFM/PWM mode control

System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be system PG)

SWs and VTT I²C disable bits

SWVTT_DIS

I2C_RAIL_EN1

I2C_RAIL_EN2/GPOCTRL

PWR_FAULT_MASK1

PWR_FAULT_MASK2

GPO1PG_CTRL1

GPO1PG_CTRL2

I²C Enable control of individual rails

I²C Enable control of individual rails and I²C controlled GPOs, high or low

Power fault masking for individual rails

Power good tree control for GPO1

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表8-26. Register Map Summary (continued)

Address

A6h

Name

Short Description

GPO4PG_CTRL1

GPO4PG_CTRL2

GPO2PG_CTRL1

GPO2PG_CTRL2

GPO3PG_CTRL1

GPO3PG_CTRL2

MISCSYSPG

Power good tree control for GPO4

Power good tree control for GPO2

Power good tree control for GPO3

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

B0h

Power good tree control with CTL3 and CTL6 for GPO

Discharge resistor setting for VTT LDO

LDOA1 and SWB2 control for discharge, voltage selection, and enable

Power good statuses for individual rails

Power fault statuses for individual rails

Critical temperature indicators

VTT_DISCH_CTRL

LDOA1_SWB2_CTRL

PG_STATUS1

B1h

PG_STATUS2

B2h

PWR_FAULT_STATUS1

PWR_FAULT_STATUS2

TEMPCRIT

B3h

B4h

B5h

TEMPHOT

Hot temperature indicators

Complex bit access types are encoded to fit into small table cells. 表 8-27 shows the codes that are used for

access types in this section.

表8-27. Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

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8.13.2 DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]

图8-34. DEVICEID1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

PART_

NUMBER[7] NUMBER[6] NUMBER[5] NUMBER[4] NUMBER[3]

NUMBER[2]

NUMBER[1] NUMBER[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

1

R

0

1

R

0

1

R

0

R

0

R

0

R

0

1

0

R

表8-28. DEVICEID1 Register Descriptions

Bit

Field

Type Reset

Description

7:4

PART_NUMBER[7:4]

PART_NUMBER[3:0]

R

X

Device part number ID

0000: TPS65086x0x

0001: TPS65086x1x

...

1111: TPS65086xFx

3:0

X

Device part number ID

0000: TPS65086xx0

0001: TPS65086xx1

...

1111: TPS65086xxF

8.13.3 DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]

图8-35. DEVICEID2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

OTP_

PART_

REVID[1]

REVID[0]

VERSION[1] VERSION[0] NUMBER[11] NUMBER[10] NUMBER[9] NUMBER[8]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

1

0

1

0

R

0

1

0

1

R

0

R

1

R

0

R

0

R

表8-29. DEVICEID2 Register Descriptions

Bit

7:6

5:4

Field

Type Reset

Description

REVID[1:0]

R

X

Silicon revision ID

OTP_VERSION[1:0]

OTP variation ID

00: A

01: B

10: C

11: D

3:0

PART_NUMBER[11:8]

R

X

Device part number ID

0100: TPS650864xx

64

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8.13.4 IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]

图8-36. IRQ Register

Bit

Bit Name

7

FAULT

0

6

5

4

3

SHUTDN

0

2

1

0

DIETEMP

0

RESERVED RESERVED RESERVED

RESERVED RESERVED

TPS650864

Access

0

R/W

R

R/W

R

R/W

表8-30. IRQ Register Descriptions

Bit

Field

Type Reset

Description

7

FAULT

R/W

0

Fault interrupt. Asserted when either condition occurs: power fault of any rail,

or die temperature crosses over the critical temperature threshold (T_CRIT). The

user can read Reg. 0xB2–0xB6 to determine what has caused the interrupt.

0: Not asserted

1: Asserted. Host to write 1b to clear.

3

0

SHUTDN

DIETEMP

R/W

0

Asserted when PMIC shuts down. To clear indicator, SHUTDNSRC must be

cleared first, see 节8.13.7

0: Not asserted.

1: Asserted. Host to write 1b to clear.

Die temp interrupt. Asserted when PMIC die temperature crosses above the

hot temperature threshold (T_HOT).

0: Not asserted.

1: Asserted. Host to write 1b to clear.

8.13.5 IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]

图8-37. IRQ_MASK Register

Bit

Bit Name

7

MFAULT

1

6

5

4

3

msHUTDN

1

2

1

0

RESERVED RESERVED RESERVED

RESERVED RESERVED MDIETEMP

TPS650864

Access

1

R/W

R

R/W

R

R/W

表8-31. IRQ_MASK Register Descriptions

Bit

Field

Type Reset

Description

7

MFAULT

R/W

1

FAULT interrupt mask.

0: Not masked.

1: Masked.

3

0

msHUTDN

MDIETEMP

PMIC shutdown event interrupt mask

0: Not masked.

1: Masked.

Die temp interrupt mask.

0: Not masked.

1: Masked.

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8.13.6 PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]

图8-38. PMICSTAT Register

Bit

Bit Name

7

6

5

4

3

2

1

0

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SDIETEMP

TPS650864

Access

0

R

表8-32. PMICSTAT Register Descriptions

Bit

Field

SDIETEMP

Type Reset

Description

0

R

0

PMIC die temperature status.

0: PMIC die temperature is below T_HOT

.

1: PMIC die temperature is above T_HOT

.

8.13.7 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]

图8-39. SHUTDNSRC Register

Bit

Bit Name

7

6

5

4

3

COLDOFF

0

2

UVLO

0

1

0

CRITTEMP

0

RESERVED RESERVED RESERVED RESERVED

PWR_FAULT

TPS650864

Access

0

R

R/W

表8-33. SHUTDNSRC Register Descriptions

Bit

Field

Type Reset

Description

3

COLDOFF

R/W

0

Set by PMIC cleared by host. Host to write 1b to clear.

0: Cleared

1: N/A. Not enabled for existing OTPs.

2

1

UVLO

R/W

0

Set by PMIC cleared by host. Host to write 1b to clear.

0: Cleared

1: PMIC was shut down due to a UVLO event (V_SYScrosses below 5.4 V).

Assertion of this bit sets the SHUTDN bit in 节8.13.4.

PWR_FAULT

CRITTEMP

R/W

0

Set by PMIC cleared by host. Host to write 1b to clear.

0: Cleared

1: PMIC was shut down due to an unmasked power fault event. Assertion of

this bit sets the SHUTDN bit in 节8.13.4. The source of the power fault can be

determined from the PWR_FAULT registers (0xB2 and 0xB3). Overcurrent

protection will limit I_OUTand typically cause a power fault as V_OUTdroops.

0

Set by PMIC cleared by host. Host to write 1b to clear.

0: Cleared

1: PMIC was shut down due to the rise of PMIC die temperature above critical

temperature threshold (T_CRIT). Assertion of this bit sets the SHUTDN bit in 节

8.13.4.

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8.13.8 BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]

图8-40. BUCK1CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK1_

VID[6]

BUCK1_

VID[5]

BUCK1_

VID[4]

BUCK1_

VID[3]

BUCK1_

VID[2]

BUCK1_

VID[1]

BUCK1_

VID[0]

BUCK1_

DECAY

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

R/W

表8-34. BUCK1CTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK1_VID[6:0]

R/W

X

This field sets the BUCK1 regulator output regulation voltage in

normal mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK1_DECAY

R/W

X

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

8.13.9 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]

图8-41. BUCK2CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK2_

VID[6]

BUCK2_

VID[5]

BUCK2_

VID[4]

BUCK2_

VID[3]

BUCK2_

VID[2]

BUCK2_

VID[1]

BUCK2_

VID[0]

BUCK2_

DECAY

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-35. BUCK2CTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK2_VID[6:0]

R/W

X

This field sets the BUCK2 regulator output regulation voltage in

normal mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK2_DECAY

R/W

X

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

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8.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]

图8-42. BUCK3DECAY Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK3_

DECAY

SPARE

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-36. BUCK3DECAY Register Descriptions

Bit

7:1

0

Field

Type Reset

Description

SPARE

R/W

X

Unused. Typically mirror BUCK3_VID by default in OTP.

BUCK3_DECAY

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

8.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]

图8-43. BUCK3VID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK3_

VID[6]

BUCK3_

VID[5]

BUCK3_

VID[4]

BUCK3_

VID[3]

BUCK3_

VID[2]

BUCK3_

VID[1]

BUCK3_

VID[0]

RESERVED

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

R

0

1

0

1

0

R/W

表8-37. BUCK3VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK3_VID[6:0]

R/W

X

This field sets the BUCK3 regulator output regulation voltage in

normal mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

68

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8.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]

图8-44. BUCK3SLPCTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP BUCK3_SLP

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

_ EN

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-38. BUCK3SLPCTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK3_SLP_VID[6:0]

R/W

X

This field sets the BUCK3 regulator output regulation voltage in

sleep mode if BUCK3_SLP_EN = 1b.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK3_SLP_EN

R/W

X

BUCK3 sleep mode enable. BUCK3 is factory configured to

switch to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0: Disable. Uses BUCK3_VID in all cases.

1: Enabled. Uses BUCK3_SLP_VID when assigned sleep pin is

low.

8.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]

图8-45. BUCK4CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK4_SLP BUCK4_SLP

_ EN[1]

BUCK4_

MODE

RESERVED RESERVED

BUCK4_DIS

_ EN[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

1

0

1

0

1

0

1

R/W

表8-39. BUCK4CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:4

BUCK4_SLP_EN

R/W

X

BUCK4 sleep mode enable. BUCK4 is factory configured to switch

to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/

SLPENB2 pin.

00: Disable. Uses BUCK4_VID in all cases.

11: Enabled. Uses BUCK4_SLP_VID when assigned sleep pin is

low.

01,10: Reserved. Do not write these values.

3:2

1

RESERVED

R/W 11

Reserved bits. Always write to 11.

BUCK4_MODE

R/W

X

This field sets the BUCK4 regulator operating mode.

0: Automatic mode

1: Forced PWM mode

0

BUCK4_DIS

R/W

X

BUCK4 Disable Bit. Writing 0 to this bit forces BUCK4 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

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8.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]

图8-46. BUCK5CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK5_SLP BUCK5_SLP

BUCK5_

MODE

RESERVED RESERVED

BUCK5_DIS

_EN[1]

_EN[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

1

0

1

0

1

R/W

表8-40. BUCK5CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:4

BUCK5_SLP_EN

R/W

X

BUCK5 sleep mode enable. BUCK5 is factory configured to

switch to sleep mode voltage either by CTL3/SLPENB1 pin or by

CTL6/SLPENB2 pin.

00: Disable. Uses BUCK5_VID in all cases.

11: Enabled. Uses BUCK5_SLP_VID when assigned sleep pin is

low.

01,10: Reserved. Do not write these values.

3:2

1

RESERVED

R/W 11

Reserved bits. Always write to 11.

BUCK5_MODE

R/W

X

This field sets the BUCK5 regulator operating mode.

0: Automatic mode

1: Forced PWM mode

0

BUCK5_DIS

R/W

X

BUCK5 Disable Bit. Writing 0 to this bit forces BUCK5 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

8.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]

图8-47. BUCK6CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK6_SLP BUCK6_SLP

BUCK6_

MODE

RESERVED RESERVED

BUCK6_DIS

EN[1]

EN[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

1

0

1

0

1

0

1

0

1

R/W

表8-41. BUCK6CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:4

BUCK6_SLP_EN

R/W

X

BUCK6 sleep mode enable. BUCK6 is factory configured to switch

to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/

SLPENB2 pin.

00: Disable. Uses BUCK6_VID in all cases.

11: Enabled. Uses BUCK6_SLP_VID when assigned sleep pin is

low.

01,10: Reserved. Do not write these values.

3:2

1

RESERVED

R/W 11

R/W

Reserved bits. Always write to 11.

BUCK6_MODE

X

This field sets the BUCK6 regulator operating mode.

0: Automatic mode

1: Forced PWM mode

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表8-41. BUCK6CTRL Register Descriptions (continued)

Bit

Field

Type Reset

Description

0

BUCK6_DIS

R/W

X

BUCK6 Disable Bit. Writing 0 to this bit forces BUCK6 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

8.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]

图8-48. LDOA2CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2_SLP LDOA2_SLP

RESERVED RESERVED

RESERVED RESERVED RESERVED LDOA2_DIS

_EN[1]

_EN[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-42. LDOA2CTRL Register Descriptions

Bit

Field

Type Reset

Description

5:4

LDOA2_SLP_EN

R/W

X

LDOA2 sleep mode enable. LDOA2 is factory configured to switch

to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/

SLPENB2 pin.

00: Disable. Uses LDOA2_VID in all cases.

11: Enabled. Uses LDOA2_SLP_VID when assigned sleep pin is

low.

01,10: Reserved. Do not write these values.

3:1

0

RESERVED

LDOA2_DIS

R/W 110

R/W

Reserved bits. Always write to '110'.

X

LDOA2 Disable Bit. Writing 0 to this bit forces LDOA2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

8.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]

图8-49. LDOA3CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA3_SLP LDOA3_SLP

RESERVED RESERVED

RESERVED RESERVED RESERVED LDOA3_DIS

_EN[1]

_EN[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-43. LDOA3CTRL Register Descriptions

Bit

Field

LDOA3_SLP_EN

Type Reset

Description

5:4

R/W

X

LDOA3 sleep mode enable. LDOA3 is factory configured to switch

to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/

SLPENB2 pin.

00: Disable. Uses LDOA3_VID in all cases.

11: Enabled. Uses LDOA3_SLP_VID when assigned sleep pin is

low.

01,10: Reserved. Do not write these values.

3:1

RESERVED

R/W 110

Reserved bits. Always write to '110'.

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表8-43. LDOA3CTRL Register Descriptions (continued)

Bit

Field

Type Reset

Description

0

LDOA3_DIS

R/W

X

LDOA3 Disable Bit. Writing 0 to this bit forces LDOA3 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

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8.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

图8-50. DISCHCTRL1 Register

Bit

7

6

5

4

3

2

1

0

BUCK4_

DISCHG[1]

BUCK4_

DISCHG[0]

BUCK3_

DISCHG[1]

BUCK3_

DISCHG[0]

BUCK2_

DISCHG[1]

BUCK2_

DISCHG[0]

BUCK1_

DISCHG[1]

BUCK1_

DISCHG[0]

Bit Name

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-44. DISCHCTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7:6

BUCK4_DISCHG[1:0]

BUCK3_DISCHG[1:0]

BUCK2_DISCHG[1:0]

BUCK1_DISCHG[1:0]

R/W

X

BUCK4 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5:4

3:2

1:0

BUCK3 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK2 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

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8.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

图8-51. DISCHCTRL2 Register

Bit

7

6

5

4

3

2

1

0

LDOA2_

DISCHG[1]

LDOA2_

DISCHG[0]

SWA1_

DISCHG[1]

SWA1_

DISCHG[0]

BUCK6_

DISCHG[1]

BUCK6_

DISCHG[0]

BUCK5_

DISCHG[1]

BUCK5_

DISCHG[0]

Bit Name

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-45. DISCHCTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7:6

LDOA2_DISCHG[1:0]

SWA1_DISCHG[1:0]

BUCK6_DISCHG[1:0]

BUCK5_DISCHG[1:0]

R/W

X

LDOA2 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5:4

3:2

1:0

SWA1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK6 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

BUCK5 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

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8.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

图8-52. DISCHCTRL3 Register

Bit

7

6

5

4

3

2

1

0

SWB2_

DISCHG[1]

SWB2_

DISCHG[0]

SWB1_

DISCHG[1]

SWB1_

DISCHG[0]

LDOA3_

DISCHG[1]

LDOA3_

DISCHG[0]

Bit Name

RESERVED RESERVED

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-46. DISCHCTRL3 Register Descriptions

Bit

Field

Type Reset

Description

5:4

SWB2_DISCHG[1:0]

SWB1_DISCHG[1:0]

LDOA3_DISCHG[1:0]

R/W

X

SWB2 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

3:2

1:0

SWB1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

LDOA3 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

8.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]

Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to GPO3

pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC can be

programmed for system PG, level shifter or I²C controller GPO.

图8-53. PG_DELAY1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

GPO3_PG_ GPO3_PG_ GPO3_PG_

DELAY[2]

RESERVED RESERVED RESERVED RESERVED RESERVED

DELAY[1]

DELAY[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

0

R

0

R

0

R

1

0

1

0

1

—

R/W

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表8-47. PG_DELAY1 Register Descriptions

Bit

Field

Type Reset

Description

2:0

GPO3_PG_DELAY[2:0]

R/W

X

Programmable delay Power Good or level shifter for GPO3 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation.

000: 2.5 ms

001: 5.0 ms

010: 10 ms

011: 15 ms

100: 20 ms

101: 50 ms

110: 75 ms

111: 100 ms

—: Bits not used. If GPO3 is controlled by I²C rather than PG and

is not used internally for VTT LDO enable, these bits have no

impact. Default is set to 0b.

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8.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register

(offset = 91h) [reset = 0000 0000]

图8-54. FORCESHUTDN Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SDWN

0

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

TPS650864

Access

0

R

R/W

表8-48. FORCESHUTDN Register Descriptions

Bit

Field

SDWN

Type Reset

Description

0

R/W

0

Forces reset of the PMIC and reset of all registers. The bit is self-clearing.

PMIC does not generate I²C ACK for this command because it goes into

emergency shutdown.

0: No action.

1: PMIC initiates emergency shutdown.

8.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]

图8-55. BUCK1SLPCTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK1_

SLP_ EN

SLP_ VID[6] SLP_ VID[5] SLP_ VID[4] SLP_ VID[3] SLP_ VID[2] SLP_ VID[1] SLP_ VID[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

R/W

表8-49. BUCK1SLPCTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK1_SLP_VID[6:0]

R/W

X

This field sets the BUCK1 regulator output regulation voltage in

sleep mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK1_SLP_EN

R/W

X

BUCK1 sleep mode enable. BUCK1 is factory configured to

switch to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0: Disable. Uses BUCK1_VID in all cases.

1: Enabled. Uses BUCK1_SLP_VID when assigned sleep pin is

low.

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8.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]

图8-56. BUCK2SLPCTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP BUCK2_SLP

_ VID[6]

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

_ EN

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-50. BUCK2SLPCTRL Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK2_SLP_VID[6:0]

R/W

X

This field sets the BUCK2 regulator output regulation voltage in

sleep mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK2_SLP_EN

R/W

X

BUCK2 sleep mode enable. BUCK2 is factory configured to

switch to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0: Disable. Uses BUCK2_VID in all cases.

1: Enabled. Uses BUCK2_SLP_VID when assigned sleep pin is

low.

8.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]

图8-57. BUCK4VID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK4_

VID[6]

BUCK4_

VID[5]

BUCK4_

VID[4]

BUCK4_

VID[3]

BUCK4_

VID[2]

BUCK4_

VID[1]

BUCK4_

VID[0]

BUCK4_

DECAY

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-51. BUCK4VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK4_VID[6:0]

R/W

X

This field sets the BUCK4 regulator output regulation voltage in

normal mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK4_DECAY

R/W

X

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

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8.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]

图8-58. BUCK4SLPVID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP BUCK4_SLP

_ VID[6]

RESERVED

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

R

1

0

1

0

1

0

1

0

1

0

R/W

表8-52. BUCK4SLPVID Register Descriptions

Bit

Field

BUCK4_SLP_VID[6:0]

Type Reset

Description

7:1

R/W

X

This field sets the BUCK4 regulator output regulation voltage in

sleep mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

8.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]

图8-59. BUCK5VID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK5_

VID[6]

BUCK5_

VID[5]

BUCK5_

VID[4]

BUCK5_

VID[3]

BUCK5_

VID[2]

BUCK5_

VID[1]

BUCK5_

VID[0]

BUCK5_

DECAY

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-53. BUCK5VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK5_VID[6:0]

R/W

X

This field sets the BUCK5 regulator output regulation voltage in

normal mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK5_DECAY

R/W

X

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

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8.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]

图8-60. BUCK5SLPVID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP BUCK5_SLP

_ VID[6]

RESERVED

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

R

0

1

0

1

0

1

0

R/W

表8-54. BUCK5SLPVID Register Descriptions

Bit

Field

BUCK5_SLP_VID[6:0]

Type Reset

Description

7:1

R/W

X

This field sets the BUCK5 regulator output regulation voltage in

sleep mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

8.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]

图8-61. BUCK6VID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK6_

VID[6]

BUCK6_

VID[5]

BUCK6_

VID[4]

BUCK6_

VID[3]

BUCK6_

VID[2]

BUCK6_

VID[1]

BUCK6_

VID[0]

BUCK6_

DECAY

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-55. BUCK6VID Register Descriptions

Bit

Field

Type Reset

Description

7:1

BUCK6_VID[6:0]

R/W

X

This field sets the BUCK6 regulator output regulation voltage in

normal mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK6_DECAY

R/W

X

Decay Bit

0: The output slews down to a lower voltage set by the VID bits.

1: The output decays down to a lower voltage set by the VID bits.

Decay rate depends on total capacitance and load present at the

output.

80

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8.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]

图8-62. BUCK6SLPVID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP BUCK6_SLP

_ VID[6]

RESERVED

_ VID[5]

_ VID[4]

_ VID[3]

_ VID[2]

_ VID[1]

_ VID[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

R

0

1

0

1

0

1

0

R/W

表8-56. BUCK6SLPVID Register Descriptions

Bit

Field

BUCK6_SLP_VID[6:0]

Type Reset

Description

7:1

R/W

X

This field sets the BUCK6 regulator output regulation voltage in

sleep mode.

See 表8-22 and 表8-23 for 10-mV and 25-mV step ranges for

V_OUToptions.

8.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]

图8-63. LDOA2VID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2_SLP LDOA2_SLP LDOA2_SLP LDOA2_SLP

_VID[3]

LDOA2_

VID[3]

LDOA2_

VID[3]

LDOA2_

VID[1]

LDOA2_

VID[0]

_VID[2]

_VID[1]

_VID[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-57. LDOA2VID Register Descriptions

Bit

Field

Type Reset

Description

7:4

LDOA2_SLP_VID[3:0]

R/W

X

This field sets the LDOA2 regulator output regulation voltage in

sleep mode.

See 表8-25 for V_outoptions.

3:0

LDOA2_VID[3:0]

R/W

X

This field sets the LDOA2 regulator output regulation voltage in

normal mode.

See 表8-25 for V_outoptions.

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8.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]

图8-64. LDOA3VID Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA3_SLP LDOA3_SLP LDOA3_SLP LDOA3_SLP

_ VID[3]

LDOA3_

VID[3]

LDOA3_

VID[3]

LDOA3_

VID[1]

LDOA3_

VID[0]

_ VID[2]

_ VID[1]

_ VID[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-58. LDOA3VID Register Descriptions

Bit

Field

Type Reset

Description

7:4

LDOA3_SLP_VID[3:0]

R/W

X

This field sets the LDOA3 regulator output regulation voltage in

sleep mode.

See 表8-25 for V_outoptions.

3:0

LDOA3_VID[3:0]

R/W

X

This field sets the LDOA3 regulator output regulation voltage in

normal mode.

See 表8-25 for V_outoptions.

8.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]

图8-65. BUCK123CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BUCK3

_MODE

BUCK2

_MODE

BUCK1

_MODE

BUCK3

_DIS

BUCK2

_DIS

BUCK1

_DIS

RESERVED RESERVED

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

R

1

0

1

0

1

R/W

表8-59. BUCK123CTRL Register Descriptions

Bit

Field

Type Reset

Description

5

BUCK3_MODE

R/W

X

This field sets the BUCK3 regulator operating mode.

0: Automatic mode

1: Forced PWM mode

4

3

2

BUCK2_MODE

BUCK1_MODE

BUCK3_DIS

This field sets the BUCK2 regulator operating mode.

0: Automatic mode

1: Forced PWM mode

This field sets the BUCK1 regulator operating mode.

0: Automatic mode

1: Forced PWM mode

BUCK3 Disable Bit. Writing 0 to this bit forces BUCK3 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

1

BUCK2_DIS

R/W

X

BUCK2 Disable Bit. Writing 0 to this bit forces BUCK2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

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表8-59. BUCK123CTRL Register Descriptions (continued)

Bit

Field

Type Reset

Description

0

BUCK1_DIS

R/W

X

BUCK1 Disable Bit. Writing 0 to this bit forces BUCK1 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable

1: Enable

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8.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]

Programmable Power Good delay for GPO1, GPO2, and GPO4 pins, measured from the moment when all VRs

assigned to respective GPO reach their regulation range to Power Good assertion. This is an optional register as

the PMIC can be programmed for system PG, level shifter or I²C controller GPO.

图8-66. PG_DELAY2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

GPO2_PG_ GPO2_PG_ GPO2_PG_ GPO4_PG_ GPO4_PG_ GPO4_PG_ GPO1_PG_ GPO1_PG_

DELAY[2]

DELAY[1]

DELAY[0]

DELAY[2]

DELAY[1]

DELAY[0]

DELAY[1]

DELAY[0]

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

—

0

—

0

—

0

—

0

—

R/W

表8-60. PG_DELAY2 Register Descriptions

Bit

Field

Type Reset

Description

7:5

GPO2_PG_DELAY[2:0]

R/W

X

Programmable delay Power Good or level shifter for GPO2 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation.

000: 0 ms

001: 5.0 ms

010: 10 ms

011: 15 ms

100: 20 ms

101: 50 ms

110: 75 ms

111: 100 ms

—: Bits not used. If GPO2 is controlled by I²C rather than PG and

is not used internally for VTT LDO enable, these bits have no

impact. Default is set to 0b.

4:2

GPO4_PG_DELAY[2:0]

R/W

X

Programmable delay Power Good or level shifter for GPO4 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation.

000: 0 ms

001: 5.0 ms

010: 10 ms

011: 15 ms

100: 20 ms

101: 50 ms

110: 75 ms

111: 100 ms

—: Bits not used. If GPO4 is controlled by I²C rather than PG,

these bits have no impact. Default is set to 0b.

1:0

GPO1_PG_DELAY[1:0]

R/W

X

Programmable delay Power Good or level shifter for GPO1 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation.

00: 0 ms

01: 5.0 ms

10: 10 ms

11: 15 ms

—: Bits not used. If GPO1 is controlled by I²C rather than PG,

these bits have no impact. Default is set to 0b.

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8.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]

图8-67. SWVTT_DIS Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWB2_LDOA

1_DIS

SWB1_DIS

SWA1_DIS

VTT_DIS

Reserved

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

R/W

表8-61. SWVTT_DIS Register Descriptions

Bit

Field

Type Reset

Description

7

SWB2_LDOA1_DIS

R/W

X

SWB2 or LDOA1 Disable Bit. Writing 0 to this bit forces

SWB2 or LDOA1 to turn off regardless of any control input

pin (CTL1–CTL6) status. OTP setting selects either

SWB2 or LDOA1.

0: Disable.

1: Enable.

SWB2 for: TPS65086470

LDOA1 for: TPS6508640, TPS65086401, and

TPS6508641

6

5

SWB1_DIS

SWA1_DIS

R/W

X

SWB1 Disable Bit. Writing 0 to this bit forces SWB1 to turn

off regardless of any control input pin (CTL1–CTL6)

status.

0: Disable.

1: Enable.

SWA1 Disable Bit. Writing 0 to this bit forces SWA1 to turn

off regardless of any control input pin (CTL1–CTL6)

status.

0: Disable.

1: Enable.

4

VTT_DIS

Reserved

VTT Disable Bit. Writing 0 to this bit forces VTT to turn off

regardless of any control input pin (CTL1–CTL6) status.

0: Disable.

1: Enable.

3:0

R/W 0000

Reserved bits. Always write to 0000.

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8.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]

图8-68. I2C_RAIL_EN1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2_EN

SWA1_EN

BUCK6_EN BUCK5_EN BUCK4_EN BUCK3_EN BUCK2_EN BUCK1_EN

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

R/W

表8-62. I2C_RAIL_EN1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_EN

R/W

X

LDOA2 I²C Enable

0: LDOA2 is enabled or disabled by one of the control input pins

or internal PG signal.

1: LDOA2 is forced on unless LDOA2_DIS = 0b.

6

5

4

3

2

1

0

SWA1_EN

BUCK6_EN

BUCK5_EN

BUCK4_EN

BUCK3_EN

BUCK2_EN

BUCK1_EN

SWA1 I²C Enable

0: SWA1 is enabled or disabled by one of the control input pins

or internal PG signal.

1: SWA1 is forced on unless SWA1_DIS = 0b.

BUCK6 I²C Enable

0: BUCK6 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK6 is forced on unless BUCK6_DIS = 0b.

BUCK5 I²C Enable

0: BUCK5 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK5 is forced on unless BUCK5_DIS = 0b.

BUCK4 I²C Enable

0: BUCK4 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK4 is forced on unless BUCK4_DIS = 0b.

BUCK3 I²C Enable

0: BUCK3 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK3 is forced on unless BUCK3_DIS = 0b.

BUCK2 I²C Enable

0: BUCK2 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK2 is forced on unless BUCK2_DIS = 0b.

BUCK1 I²C Enable

0: BUCK1 is enabled or disabled by one of the control input pins

or internal PG signal.

1: BUCK1 is forced on unless BUCK1_DIS = 0b.

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8.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h)

[reset = X]

图8-69. I2C_RAIL_EN2/GPOCTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWB2_LDOA

1_EN

GPO4_LVL

GPO3_LVL

GPO2_LVL

0

GPO1_LVL

VTT_EN

SWB1_EN

LDOA3_EN

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

—

0

—

0

1

—

R/W

表8-63. I2C_RAIL_EN2/GPOCTRL Register Descriptions

Bit

Field

Type Reset

Description

7

GPO4_LVL

R/W

X

The field is to set GPO4 pin output if the pin is factory-

configured as an I²C controlled open-drain general-purpose

output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

—: Bit not used in this version; GPO4 is controlled by GPO4 PG

tree. Default is set to 0b.

6

5

4

GPO3_LVL

GPO2_LVL

GPO1_LVL

VTT_EN

The field is to set GPO3 pin output if the pin is factory-

configured as either an I²C controlled open-drain or a push-pull

general-purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

—: Bit not used in this version; GPO3 is controlled by GPO3 PG

tree. Default is set to 0b.

The field is to set GPO2 pin output if the pin is factory-

configured as either an I²C controlled open-drain or a push-pull

general-purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

—: Bit not used in this version; GPO2 is controlled by GPO2 PG

tree. Default is set to 0b.

The field is to set GPO1 pin output if the pin is factory-

configured as either an I²C controlled open-drain or a push-pull

general-purpose output.

0: The pin is driven to logic low.

1: The pin is driven to logic high.

—: Bit not used in this version; GPO1 is controlled by GPO1 PG

tree. Default is set to 0b.

3

2

R/W

X

VTT LDO I²C Enable

0: VTT LDO is enabled or disabled by one of the control input

pins or internal PG signals.

1: VTT LDO is forced on unless VTT_DIS = 0b.

SWB2_LDOA1_EN

SWB2 or LDOA1 I²C Enable. Internal setting selects either

SWB2 or LDOA1.

0: SWB2 or LDOA1 is enabled or disabled by one of the control

input pins or internal PG signals.

1: SWB2 or LDOA1 is forced on unless SWB2_LDOA1_DIS =

0b.

SWB2 for: TPS65086470

LDOA1 for: TPS6508640, TPS65086401, and TPS6508641

1

SWB1_EN

R/W

X

SWB1 I²C Enable

0: SWB1 is enabled or disabled by one of the control input pins

or internal PG signals.

1: SWB1 is forced on unless SWB1_DIS = 0b.

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表8-63. I2C_RAIL_EN2/GPOCTRL Register Descriptions (continued)

Bit

Field

Type Reset

Description

0

LDOA3_EN

R/W

X

LDOA3 I²C Enable

0: LDOA3 is enabled or disabled by one of the control input pins

or internal PG signals.

1: LDOA3 is forced on unless LDOA3_DIS = 0b.

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8.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]

图8-70. PWR_FAULT_MASK1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2_

FLTmsK

SWA1_

FLTmsK

BUCK6_

FLTmsK

BUCK5_

FLTmsK

BUCK4_

FLTmsK

BUCK3_

FLTmsK

BUCK2_

FLTmsK

BUCK1_

FLTmsK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

R/W

表8-64. PWR_FAULT_MASK1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_FLTmsK

SWA1_FLTmsK

BUCK6_FLTmsK

BUCK5_FLTmsK

BUCK4_FLTmsK

BUCK3_FLTmsK

BUCK2_FLTmsK

BUCK1_FLTmsK

R/W

X

LDOA2 Power Fault Mask. When masked, power fault from

LDOA2 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

6

5

4

3

2

1

0

SWA1 Power Fault Mask. When masked, power fault from SWA1

does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK6 Power Fault Mask. When masked, power fault from

BUCK6 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK5 Power Fault Mask. When masked, power fault from

BUCK5 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK4 Power Fault Mask. When masked, power fault from

BUCK4 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK3 Power Fault Mask. When masked, power fault from

BUCK3 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK2 Power Fault Mask. When masked, power fault from

BUCK2 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

BUCK1 Power Fault Mask. When masked, power fault from

BUCK1 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

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8.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]

图8-71. PWR_FAULT_MASK2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA1_

FLTmsK

VTT_

FLTmsK

SWB2_

FLTmsK

SWB1_

FLTmsK

LDOA3_

FLTmsK

RESERVED RESERVED RESERVED

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-65. PWR_FAULT_MASK2 Register Descriptions

Bit

6

Field

Type Reset

Description

RESERVED

R/W

0

1

X

Reserved bit. Always write to 0b.

Reserved bit. Always write to 1b.

5

4

LDOA1_FLTmsK

VTT_FLTmsK

LDOA1 Power Fault Mask. When masked, power fault from

LDOA1 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

3

2

1

0

R/W

X

VTT LDO Power Fault Mask. When masked, power fault from

VTT LDO does not cause PMIC to shutdown.

0: Not Masked

1: Masked

SWB2_FLTmsK

SWB1_FLTmsK

LDOA3_FLTmsK

SWB2 Power Fault Mask. When masked, power fault from

SWB2 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

SWB1 Power Fault Mask. When masked, power fault from

SWB1 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

LDOA3 Power Fault Mask. When masked, power fault from

LDOA3 does not cause PMIC to shutdown.

0: Not Masked

1: Masked

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8.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]

图8-72. GPO1PG_CTRL1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2

_msK

SWA1

_msK

BUCK6

_msK

BUCK5

_msK

BUCK4

_msK

BUCK3

_msK

BUCK2

_msK

BUCK1

_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-66. GPO1PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_msK

R/W

X

0: LDOA2 PG is part of Power Good tree of GPO1 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

6

5

4

3

2

1

0

SWA1_msK

BUCK6_msK

BUCK5_msK

BUCK4_msK

BUCK3_msK

BUCK2_msK

BUCK1_msK

0: SWA1 PG is part of Power Good tree of GPO1 pin.

1: SWA1 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK6 PG is part of Power Good tree of GPO1 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK5 PG is part of Power Good tree of GPO1 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK4 PG is part of Power Good tree of GPO1 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK3 PG is part of Power Good tree of GPO1 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK2 PG is part of Power Good tree of GPO1 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: BUCK1 PG is part of Power Good tree of GPO1 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

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8.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]

图8-73. GPO1PG_CTRL2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWB2_LDO

A1_msK

CTL5_msK

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

SWB1_msK LDOA3_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

R/W

表8-67. GPO1PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_msK

R/W

X

0: CTL5 pin status is part of Power Good tree of GPO1 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

6

5

4

3

2

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

0: CTL4 pin status is part of Power Good tree of GPO1 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO1 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO1 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO1 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO1 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO1 pin

and is ignored.

SWB2_LDOA1_msK

0: SWB2_LDOA1 PG is part of Power Good tree of GPO1 pin.

1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO1

pin and is ignored.

SWB2 for: TPS65086470

LDOA1 for:TPS6508640, TPS65086401, and TPS6508641

1

0

SWB1_msK

LDOA3_msK

R/W

X

0: SWB1 PG is part of Power Good tree of GPO1 pin.

1: SWB1 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

0: LDOA3 PG is part of Power Good tree of GPO1 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO1 pin and

is ignored.

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8.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]

图8-74. GPO4PG_CTRL1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWA1

_msK

BUCK6

_msK

BUCK5

_msK

BUCK4

_msK

BUCK3

_msK

BUCK2

_msK

BUCK1

_msK

LDOA2_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

R/W

表8-68. GPO4PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_msK

SWA1_msK

BUCK6_msK

BUCK5_msK

BUCK4_msK

BUCK3_msK

BUCK2_msK

BUCK1_msK

R/W

X

0: LDOA2 PG is part of Power Good tree of GPO4 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

6

5

4

3

2

1

0

0: SWA1 PG is part of Power Good tree of GPO4 pin.

1: SWA1 PG is NOT part of Power Good tree of GPO4 pin and

is ignored.

0: BUCK6 PG is part of Power Good tree of GPO4 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK5 PG is part of Power Good tree of GPO4 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK4 PG is part of Power Good tree of GPO4 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK3 PG is part of Power Good tree of GPO4 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK2 PG is part of Power Good tree of GPO4 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: BUCK1 PG is part of Power Good tree of GPO4 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

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8.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]

图8-75. GPO4PG_CTRL2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWB2_LDO

A1_msK

CTL5_msK

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

SWB1_msK LDOA3_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

R/W

表8-69. GPO4PG_CTRL2 Register Descriptionsr

Bit

Field

Type Reset

Description

7

CTL5_msK

R/W

X

0: CTL5 pin status is part of Power Good tree of GPO4 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

6

5

4

3

2

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

0: CTL4 pin status is part of Power Good tree of GPO4 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO4 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO4 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO4 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO4 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO4 pin

and is ignored.

SWB2_LDOA1_msK

0: SWB2_LDOA1 PG is part of Power Good tree of GPO4 pin.

1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO4

pin and is ignored.

SWB2 for: TPS65086470

LDOA1 for: TPS6508640, TPS65086401, and TPS6508641

1

0

SWB1_msK

LDOA3_msK

R/W

X

0: SWB1 PG is part of Power Good tree of GPO4 pin.

1: SWB1 PG is NOT part of Power Good tree of GPO4 pin and

is ignored.

0: LDOA3 PG is part of Power Good tree of GPO4 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO4 pin and

is ignored.

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8.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]

图8-76. GPO2PG_CTRL1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWA1

_msK

BUCK6

_msK

BUCK5

_msK

BUCK4

_msK

BUCK3

_msK

BUCK2

_msK

BUCK1

_msK

LDOA2_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

R/W

表8-70. GPO2PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_msK

SWA1_msK

BUCK6_msK

BUCK5_msK

BUCK4_msK

BUCK3_msK

BUCK2_msK

BUCK1_msK

R/W

X

0: LDOA2 PG is part of Power Good tree of GPO2 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

6

5

4

3

2

1

0

0: SWA1 PG is part of Power Good tree of GPO2 pin.

1: SWA1 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK6 PG is part of Power Good tree of GPO2 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK5 PG is part of Power Good tree of GPO2 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK4 PG is part of Power Good tree of GPO2 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK3 PG is part of Power Good tree of GPO2 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK2 PG is part of Power Good tree of GPO2 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: BUCK1 PG is part of Power Good tree of GPO2 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

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8.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]

图8-77. GPO2PG_CTRL2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWB2_LDO

A1_msK

LDOA3_

msK

CTL5_msK

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

SWB1_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

R/W

表8-71. GPO2PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_msK

R/W

X

0: CTL5 pin status is part of Power Good tree of GPO2 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO2 pin

and is ignored.

6

5

4

3

2

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

0: CTL4 pin status is part of Power Good tree of GPO2 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO2 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO2 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO2 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO2 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO2 pin

and is ignored.

SWB2_LDOA1_msK

0: SWB2_LDOA1 PG is part of Power Good tree of GPO2 pin.

1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO2

pin and is ignored.

SWB2 for: TPS65086470

LDOA1 for: TPS6508640, TPS65086401, and TPS6508641

1

0

SWB1_msK

LDOA3_msK

R/W

X

0: SWB1 PG is part of Power Good tree of GPO2 pin.

1: SWB1 PG is NOT part of Power Good tree of GPO2 pin and

is ignored.

0: LDOA3 PG is part of Power Good tree of GPO2 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO2 pin and

is ignored.

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8.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]

图8-78. GPO3PG_CTRL1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2

_msK

SWA1

_msK

BUCK6

_msK

BUCK5

_msK

BUCK4

_msK

BUCK3

_msK

BUCK2

_msK

BUCK1

_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-72. GPO3PG_CTRL1 Register Descriptions

Bit

Field

Type Reset

Description

7

LDOA2_msK

R/W

X

0: LDOA2 PG is part of Power Good tree of GPO3 pin.

1: LDOA2 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

6

5

4

3

2

1

0

SWA1_msK

BUCK6_msK

BUCK5_msK

BUCK4_msK

BUCK3_msK

BUCK2_msK

BUCK1_msK

0: SWA1 PG is part of Power Good tree of GPO3 pin.

1: SWA1 PG is NOT part of Power Good tree of GPO3 pin and is

ignored.

0: BUCK6 PG is part of Power Good tree of GPO3 pin.

1: BUCK6 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK5 PG is part of Power Good tree of GPO3 pin.

1: BUCK5 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK4 PG is part of Power Good tree of GPO3 pin.

1: BUCK4 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK3 PG is part of Power Good tree of GPO3 pin.

1: BUCK3 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK2 PG is part of Power Good tree of GPO3 pin.

1: BUCK2 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: BUCK1 PG is part of Power Good tree of GPO3 pin.

1: BUCK1 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

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8.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]

图8-79. GPO3PG_CTRL2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

SWB2_LDO

A1_msK

CTL5_msK

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

SWB1_msK LDOA3_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-73. GPO3PG_CTRL2 Register Descriptions

Bit

Field

Type Reset

Description

7

CTL5_msK

R/W

X

0: CTL5 pin status is part of Power Good tree of GPO3 pin.

1: CTL5 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

6

5

4

3

2

CTL4_msK

CTL2_msK

CTL1_msK

VTT_msK

0: CTL4 pin status is part of Power Good tree of GPO3 pin.

1: CTL4 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

0: CTL2 pin status is part of Power Good tree of GPO3 pin.

1: CTL2 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

0: CTL1 pin status is part of Power Good tree of GPO3 pin.

1: CTL1 pin status is NOT part of Power Good tree of GPO3 pin

and is ignored.

0: VTT LDO PG is part of Power Good tree of GPO3 pin.

1: VTT LDO PG is NOT part of Power Good tree of GPO3 pin

and is ignored.

SWB2_LDOA1_msK

0: SWB2_LDOA1 PG is part of Power Good tree of GPO3 pin.

1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO3

pin and is ignored.

SWB2 for: TPS65086470

LDOA1 for: TPS6508640, TPS65086401, and TPS6508641

1

0

SWB1_msK

LDOA3_msK

R/W

X

0: SWB1 PG is part of Power Good tree of GPO3 pin.

1: SWB1 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

0: LDOA3 PG is part of Power Good tree of GPO3 pin.

1: LDOA3 PG is NOT part of Power Good tree of GPO3 pin and

is ignored.

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8.13.48 MISCSYSPG Register (offset = ACh) [reset = X]

图8-80. MISCSYSPG Register

Bit

Bit Name

7

6

5

4

3

2

1

0

GPO1_

CTL3_msK

GPO1_

CTL6_msK

GPO4_

CTL3_msK

GPO4_

CTL6_msK

GPO2_

CTL3_msK

GPO2_

CTL6_msK

GPO3_

CTL3_msK

GPO3_

CTL6_msK

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

表8-74. MISCSYSPG Register Descriptions

Bit

Field

Type Reset

Description

7

GPO1_CTL3_msK

GPO1_CTL6_msK

GPO4_CTL3_msK

GPO4_CTL6_msK

GPO2_CTL3_msK

GPO2_CTL6_msK

GPO3_CTL3_msK

GPO3_CTL6_msK

R/W

X

0: CTL3 pin status is part of Power Good tree of GPO1 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO1 pin.

6

5

4

3

2

1

0

0: CTL6 pin status is part of Power Good tree of GPO1 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO1 pin.

0: CTL3 pin status is part of Power Good tree of GPO4 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO4 pin.

0: CTL6 pin status is part of Power Good tree of GPO4 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO4 pin.

0: CTL3 pin status is part of Power Good tree of GPO2 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO2 pin.

0: CTL6 pin status is part of Power Good tree of GPO2 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO2 pin.

0: CTL3 pin status is part of Power Good tree of GPO3 pin.

1: CTL3 pin status is NOT part of Power Good tree of GPO3pin.

0: CTL6 pin status is part of Power Good tree of GPO3 pin.

1: CTL6 pin status is NOT part of Power Good tree of GPO3 pin.

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8.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]

图8-81. VTT_DISCH_CTRL Register

Bit

Bit Name

7

6

5

4

3

2

1

0

VTT_

DISCHG

RESERVED RESERVED RESERVED

RESERVED RESERVED RESERVED RESERVED

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-75. VTT_DISCH_CTRL Register Descriptions

Bit

7:5

4

Field

Type Reset

Description

RESERVED

VTT_DISCHG

R/W

X

Reserved bits. Always write to match OTP settings.

0: no discharge

1: 100 Ω

3:0

RESERVED

R/W

X

Reserved bits. Always write to match OTP settings.

8.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]

图8-82. LDOA1_SWB2_CTRL Register

Bit

7

6

5

4

3

2

1

0

LDOA1_

DISCHG[1]

LDOA1_

DISCHG[0]

LDOA1_SWB2_

SDWN_CONFIG

LDOA1_

VID[3]

LDOA1_

VID[2]

LDOA1_

VID[1]

LDOA1_

VID[0]

LDOA1_

SWB2_EN

Bit Name

TPS6508640

TPS65086401

TPS6508641

TPS65086470

Access

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R/W

表8-76. LDOA1_SWB2_CTRL Register Descriptions

Bit

Field

LDOA1_DISCHG[1:0]

Type Reset

Description

7:6

R/W

X

LDOA1 discharge resistance

00: no discharge

01: 100 Ω

10: 200 Ω

11: 500 Ω

5

LDOA1_SWB2_SDWN_CO R/W

NFIG

X

Control for Disabling LDOA1 or SWB2 (OTP dependent) during

Emergency Shutdown. When LDOA1 is used in sequence and

SWB1 and SWB2 are not merged, this will control SWB2.

0: LDOA1 or SWB2 will turn off during Emergency Shutdown for

factory-programmable duration of 1 ms, 5 ms, 10 ms, or 100 ms.

1: LDOA1 or SWB2 is controlled by LDOA1_SWB2_EN bit only.

LDOA1 for: TPS65086470

SWB2 for: TPS6508640

Unused for: TPS65086401 and TPS6508641

4:1

0

LDOA1_VID[3:0]

R/W

X

This field sets the LDOA1 regulator output regulation voltage.

See 表8-24 for V_OUToptions.

LDOA1_SWB2_EN

LDOA1 or SWB2 Enable Bit.

0: Disable.

1: Enable.

LDOA1 for: TPS65086470

SWB2 for: TPS6508640

Unused for: TPS65086401 and TPS6508641

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8.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]

图8-83. PG_STATUS1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2_

PGOOD

SWA1_

PGOOD

BUCK6_

PGOOD

BUCK5_

PGOOD

BUCK4_

PGOOD

BUCK3_

PGOOD

BUCK2_

PGOOD

BUCK1_

PGOOD

TPS650864

Access

0

R

表8-77. PG_STATUS1 Register Descriptions

Bit

Field

LDOA2_PGOOD

Type Reset

Description

7

R

0

LDOA2 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

6

5

4

3

2

1

0

SWA1_PGOOD

BUCK6_PGOOD

BUCK5_PGOOD

BUCK4_PGOOD

BUCK3_PGOOD

BUCK2_PGOOD

BUCK1_PGOOD

SWA1 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK6 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK5 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK4 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK3 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK2 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

BUCK1 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

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8.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]

图8-84. PG_STATUS2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDO5

_PGOOD

LDOA1

_PGOOD

VTT

_PGOOD

SWB2

_PGOOD

SWB1

_PGOOD

LDOA3

_PGOOD

RESERVED RESERVED

TPS650864

Access

0

R

表8-78. PG_STATUS2 Register Descriptions

Bit

Field

LDO5_PGOOD

Type Reset

Description

5

R

0

LDO5 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

4

3

2

1

0

LDOA1_PGOOD

VTT_PGOOD

LDOA1 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

VTT LDO Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

SWB2_PGOOD

SWB1_PGOOD

LDOA3_PGOOD

SWB2 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

SWB1 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

LDOA3 Power Good status.

0: The output is not in target regulation range.

1: The output is in target regulation range.

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8.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]

图8-85. PWR_FAULT_STATUS1 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA2_

PWRFLT

SWA1_

PWRFLT

BUCK6_

PWRFLT

BUCK5_

PWRFLT

BUCK4_

PWRFLT

BUCK3_

PWRFLT

BUCK2_

PWRFLT

BUCK1_

PWRFLT

TPS650864

Access

0

R/W

表8-79. PWR_FAULT_STATUS1 Register Descriptions

Bit

Field

LDOA2_PWRFLT

Type Reset

Description

7

R

0

This fields indicates that LDOA2 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

6

5

4

3

2

1

0

SWA1_PWRFLT

BUCK6_PWRFLT

BUCK5_PWRFLT

BUCK4_PWRFLT

BUCK3_PWRFLT

BUCK2_PWRFLT

BUCK1_PWRFLT

This fields indicates that SWA1 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK6 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK5 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK4 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK3 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK2 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK1 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

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8.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]

图8-86. PWR_FAULT_STATUS2 Register

Bit

Bit Name

7

6

5

4

3

2

1

0

LDOA1_

PWRFLT

VTT_

PWRFLT

SWB2_

_PWRFLT

SWB1_

PWRFLT

LDOA3_

PWRFLT

RESERVED RESERVED RESERVED

TPS650864

Access

0

R

R/W

表8-80. PWR_FAULT_STATUS2 Register Descriptions

Bit

Field

LDOA1_PWRFLT

Type Reset

Description

4

R/W

0

This fields indicates that LDOA1 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

3

2

1

0

VTT_PWRFLT

This fields indicates that VTT LDO has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

SWB2_PWRFLT

SWB1_PWRFLT

LDOA3_PWRFLT

This fields indicates that SWB2 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that SWB1 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

This fields indicates that LDOA3 has lost its regulation.

0: No Fault.

1: Power fault has occurred. The host to write 1 to clear.

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8.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]

Asserted when an internal temperature sensor detects rise of die temperature above the CRITICAL temperature

threshold (T_CRIT). There are 5 temperature sensors across the die.

图8-87. TEMPCRIT Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BOTTOM-

RIGHT

_CRIT

TOP-RIGHT

_CRIT

TOP-LEFT

_CRIT

RESERVED RESERVED RESERVED

DIE_CRIT

VTT_CRIT

TPS650864

Access

0

R

R/W

表8-81. TEMPCRIT Register Descriptions

Bit

Field

Type Reset

Description

4

DIE_CRIT

R/W

0

Temperature of rest of die has exceeded T_CRIT

0: Not asserted.

1: Asserted. The host to write 1 to clear.

.

3

2

VTT_CRIT

Temperature of VTT LDO has exceeded T_CRIT

0: Not asserted.

.

1: Asserted. The host to write 1 to clear.

TOP-RIGHT_CRIT

TOP-LEFT_CRIT

Temperature of die Top-Right has exceeded T_CRIT. Top-Right corner of die from

top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

1

0

R/W

0

Temperature of die Top-Left has exceeded T_CRIT.Top-Left corner of die from top

view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

BOTTOM-RIGHT_CRIT

Temperature of die Bottom-Right has exceeded T_CRIT. Bottom-Right corner of

die from top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

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8.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]

Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature

threshold (T_HOT). There are 5 temperature sensors across the die.

图8-88. TEMPHOT Register

Bit

Bit Name

7

6

5

4

3

2

1

0

BOTTOM-

RIGHT

_HOT

TOP-RIGHT

_HOT

TOP-LEFT

_HOT

RESERVED RESERVED RESERVED

DIE_HOT

VTT_HOT

TPS650864

Access

0

R

R/W

表8-82. TEMPHOT Register Descriptions

Bit

Field

Type Reset

Description

4

DIE_HOT

R/W

0

Temperature of rest of die has exceeded T_HOT

0: Not asserted.

1: Asserted. The host to write 1 to clear.

.

3

2

VTT_HOT

Temperature of VTT LDO has exceeded T_HOT

0: Not asserted.

.

1: Asserted. The host to write 1 to clear.

TOP-RIGHT_HOT

TOP-LEFT_HOT

Temperature of Top-Right has exceeded T_HOT. Top-Right corner of die from top

view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

1

0

R/W

0

Temperature of Top-Left has exceeded THOT. Top-Left corner of die from top

view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

BOTTOM-RIGHT_HOT

Temperature of Bottom-Right has exceeded T_HOT. Bottom-Right corner of die

from top view given pin1 is in Top-Left corner.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

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8.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]

Asserted when overcurrent condition is detected from a LSD FET.

图8-89. OC_STATUS Register

Bit

7

6

5

4

3

2

1

0

BUCK6

_OC

BUCK2

_OC

BUCK1

_OC

Bit Name

RESERVED RESERVED RESERVED RESERVED RESERVED

TPS650864

Access

0

R

R/W

表8-83. OC_STATUS Register Descriptions

Bit

Field

Type Reset

Description

2

BUCK6_OC

BUCK2_OC

BUCK1_OC

R/W

0

BUCK6 LSD FET overcurrent has been detected.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

1

0

BUCK2 LSD FET overcurrent has been detected.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

BUCK1 LSD FET overcurrent has been detected.

0: Not asserted.

1: Asserted. The host to write 1 to clear.

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9 Applications, Implementation, and Layout

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TPS650864 for Xilinx MPSoCs and FPGAs can be used in a variety of ways which is outlined in the

following sections. 节 9.2 discusses the design procedure for the general case. Specific OTP information can be

found starting with 节 8.6. In general, the PMIC is controlled by the state of the six CTL which can accept up to

3.6 V inputs. How these control pins are set varies based on application. Some examples would be using the PG

of external rails, looping GPOs back into CTL pins, connecting a locking push-button, using a push-button circuit,

using an embedded controller (such as the msP430G2121), or controlled by the MPSoC itself.

9.2 Typical Application

This section describes the general application information and provides a more detailed description on the PMIC

that powers a generic multicore-processor application. An example system block diagram for the device

powering an SoC and the rest of platform is shown in 图 9-1. The functional block diagram in 图 8-1 outlines the

typical external components necessary for proper device functionality.

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PMIC

Example SoC

PLATFORM

V_IN

BUCK1

EXT FET

V_IN

VCORE

VGPU

BUCK2

BUCK3 3A

BUCK4 3A

BUCK5 3A

BUCK6

EXT FET

5V Supply

VCCIO

VCPU1

Note: An LDO or

Buck Can Supply

the VPP Rail if

VCPU2

Needed for DDR.

V_IN

EXT FET

VDDQ, VDD1&2

VTT LDO ±0.5A

VTT

DDR

LDO5V or

5V Supply

VSUPP1

VSUPP2

VSUPP3

VSUPP4

VSUPP5

VSUPP6

LDOA1 0.2A

LDOA2 0.6A

LDOA3 0.6A

SWA1 0.3A

SWB1 0.3A

SWB2 0.3A

LDO5

1.8V

Input up to 3.3V

LDO5V

V_SYS

V_IN

5V Supply

PG_5V

LDO3P3

IRQB

GPO1 – GPO4

SDA

CTL1 – CTL6

SCL

图9-1. Typical Application Example

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9.2.1 Design Requirements

The PMIC requires decoupling caps on the supply pins. Follow the values for recommended capacitance on

these supplies given in 节 7. The controllers, converter, LDOs, and some other features can be adjusted to meet

specific application needs. 节 9.2.2 describes how to design and adjust the external components to achieve

desired performance.

9.2.2 Detailed Design Procedure

9.2.2.1 Controller Design Procedure

Designing the controller can be broken down into the following steps:

1. Design the output filter.

2. Select the FETs.

3. Select the bootstrap capacitor.

4. Select the input capacitors.

5. Set the current limits.

Controllers BUCK1, BUCK2, and BUCK6 require a 5-V supply and capacitors at their corresponding DRV5V_x_x

pins. For most applications, the DRV5V_x_x input should come from the LDO5P0 pin to ensure uninterrupted

supply voltage; a 2.2-µF, X5R, 20%, 10-V, or similar capacitor must be used for decoupling.

V_SYS

DRVHx

BOOT1

LDO5V

DRV5V_x_x

V_OUT

L_OUT

SWx

C_OUT

Controller

DRVLx

PGNDSNSx

Control

from SOC

FBVOUTx

R_ILIM

ILIMx

<FBGND2>⁽¹⁾

PowerPAD^TM

A. <FBGND2> is only present for BUCK2.

图9-2. Controller Diagram

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9.2.2.1.1 Selecting the Inductor

Placement of an inductor is required between the external FETs and the output capacitors. Together, the inductor

and output capacitors make the double-pole that contributes to stability. In addition, the inductor is directly

responsible for the output ripple, efficiency, and transient performance. As the inductance used increases, the

ripple current decreases, which typically results in an increased efficiency. However, with an increase in

inductance used, the transient performance decreases. Finally, the inductor selected must be rated for

appropriate saturation current, core losses, and DC resistance (DCR).

Equation 5 shows the calculation for the recommended inductance for the controller.

V_OUTì (V - V_OUT

_INì f_swì I_OUT(MAX)ì K_IND

)

IN

L =

V

(5)

where

• V_OUTis the typical output voltage

• V_INis the typical input voltage

• f_SWis the typical switching frequency when loaded, 1 MHz unless otherwise noted

• I_OUT(MAX)is the maximum load current

• K_INDis the ratio of I_Lrippleto the I_OUT(MAX). For this application, TI recommends that K_INDis set to a value from

0.2 to 0.4. Higher values have improved transient performance, lower values have improved efficiency

With the chosen inductance value, the peak current for the inductor in steady state operation, I_L(max), can be

calculated using Equation 6. The rated saturation current of the inductor must be higher than the I_L(max)current.

(V -V_OUT) ì V_OUT

2 ì V_INì f_swì L

IN

I_L(MAX)= I_OUT(MAX)

+

(6)

9.2.2.1.2 Selecting the Output Capacitors

TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple. The

output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide

variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on the

output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage

ripple in PFM mode. To achieve specified regulation performance and low output voltage ripple, the DC-bias

characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops

with increasing DC bias voltage.

TI recommends the use of small ceramic capacitors placed between the inductor and load with many vias to the

PGND plane for the output capacitors of the BUCK controllers. This solution typically provides the smallest and

lowest cost solution available for D-CAP2 controllers.

The selection of the output capacitor is typically driven by the output transient response. Equation 7 and

Equation 8 provide a rough estimate of the minimum required capacitance to ensure proper transient response.

Because the transient response is significantly affected by the board layout, some experimentation is expected

in order to confirm that values derived in this section are applicable to any particular use case. These are not

meant to be an absolute requirement, but rather a rough starting point. Alternatively, some known combination

values from which to begin are provided in 表 9-1. V_UNDERand V_OVERvalues should be greater than or equal to

3% of V_OUTsetting in order for equations to be meaningful. The equations provide some margin so that actual

capacitance requirement may be lower than calculated.

2

I_TRAN(MAX)ì L

C_OUT

>

(V_IN- V_OUT) ì V_UNDER

(7)

where

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• I_TRAN(max)is the maximum load current step

• L is the chosen inductance

• V_INis the maximum input voltage

• V_OUTis the minimum programmed output voltage

• V_UNDERis the maximum allowable undershoot from programmed voltage

I_TRAN(MAX)²ìL

C_OUT

>

V_OUTì V_OVER

(8)

where

• V_OVERis the maximum allowable overshoot from programmed voltage

Another key performance factor can be the ripple voltage while in pulsed frequency modulation mode, also

known as discontinuous conduction mode. At light load, the controller will disable the low side FET once it

detects a zero-crossing event on the inductor current. It will stay disabled until V_OUTcrosses below the set VID

threshold. This architecture allows significant power savings at light load conditions by minimizing power loss

through the low side FET and through switching. The disadvantage is that there is higher voltage ripple since the

ripple current is only positive. Additionally, for even higher efficiency, T_ON(PFM)for this device is typically 80%

longer than T_ON(PWM), which can be calculated by dividing the duty cycle by the switching frequency. An estimate

for the required capacitance for a given allowable ripple voltage at light load is shown in Equation 9. ESR of the

output capacitor is neglected here because ceramic capacitors, which typically have low ESR, are

recommended. V_OVERshould not be set lower than 3% of V_OUTvalue.

T_{ON_EXT}²ì V_OUTì V - V

(

)

IN

OUT

C_OUT

>

2ì V ìƒ_SW²ì V_OVERìL

IN

(9)

where

• T_{ON_EXT}is the PFM on time extension constant, 1.8 unless otherwise noted in the part number specific

section

• V_OUTis the maximum programmed output voltage

• V_INis the maximum input voltage

• f_SWis the typical switching frequency when loaded, 1 MHz unless otherwise noted

• V_OVERis the maximum allowable overshoot from programmed voltage

• L is the chosen inductance

In cases where the transient current change is very low and ripple voltage allowance is large, the DC stability

may become important. DCAP2 is a very stable architecture so this value is likely to be the smallest of those

calculated. Equation 10 approximates the amount of capacitance necessary to maintain DC stability. Again, this

is provided as a starting point; actual values will vary on a board-to-board case.

V_OUTì 50 ms

C_OUT

>

V

ì f_SWì L

IN

(10)

where

• V_OUTis the maximum programmed output voltage

• 50 µs is based on internal ramp setup

• V_INis the minimum input voltage

• f_SWis the typical switching frequency

• L is the chosen inductance

Choosing the maximum valuable between Equation 7, Equation 8, Equation 9, and Equation 10 is recommended

as a starting point to get the desired performance. All equations are estimates and have not been validated at all

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variable corners. Removing excess capacitance or adding extra capacitance may be necessary during board

evaluation. Testing can typically be performed on the evaluation module or on prototype boards.

表9-1. Known LC Combinations for 1 µs Load Rise and Fall Time

I_{TRAN(max) (A)}

L (µH)

0.47

0.33

0.22

V_OUT(V)

V_UNDER(V)

V_OVER(V)

C_OUT(µF)

110

3.5

4

1

0.05

220

5

1.35

1

0.068

0.05

0.068

0.06

220

8

440

20

1

0.05

0.16

550

9.2.2.1.3 Selecting the FETs

This controller is designed to drive two NMOS FETs. Typically, lower R_DSONvalues are better for improving the

overall efficiency of the controller, however higher gate charge thresholds will result in lower efficiency so the two

need to be balanced for optimal performance. As the R_DSONfor the low-side FET decreases, the minimum

current limit increases; therefore, ensure selection of the appropriate values for the FETs, inductor, output

capacitors, and current limit resistor. TI's CSD85301Q2, CSD87331Q3D, CSD87381P, CSD87588N, and

CSD87350Q5D devices are recommended for the controllers, depending on the required maximum current.

9.2.2.1.4 Bootstrap Capacitor

To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a capacitor

must be connected between the SWx pins and the respective BOOTx pins. TI recommends placing ceramic

capacitors with the value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402, 10-V capacitor is used

for the controllers.

TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and turnoff of

the FETs must be slowed to reduce voltage ringing on the switch node, which is a common practice for controller

design.

9.2.2.1.5 Setting the Current Limit

The current-limiting resistor value must be chosen based on Equation 1.

9.2.2.1.6 Selecting the Input Capacitors

Due to the nature of the switching controller with a pulsating input current, a low ESR input capacitor is required

for best input-voltage filtering and also for minimizing the interference with other circuits caused by high input-

voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x pin to handle the

transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is recommended for most

applications. To achieve the low ESR requirement, a ceramic capacitor is recommended. However, the voltage

rating and DC-bias characteristic of ceramic capacitors must be considered. For better input-voltage filtering, the

input capacitor can be increased without any limit.

备注

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS and

PGND pins of the FETs. The preferred capacitors for the controllers are two Murata GRM21BR61E226ME44:

22-µF, 0805, 25-V, ±20%, or similar capacitors.

9.2.2.2 Converter Design Procedure

Designing the converter has only two steps: design the output filter and select the input capacitors.

图9-3 shows a diagram of the converter.

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L_OUT

V_OUT

PVINx

LXx

VIN_BUCK345_ANA

C_IN

FBx

Converter

Control from SOC

图9-3. Converter Diagram

9.2.2.2.1 Selecting the Inductor

Internal parameters for the converters are optimized for either a 0.47 µH or 1 µH inductor, however it is possible

to use other inductor values as long as they are chosen carefully and thoroughly tested. The equations from 节

9.2.2.1.1 can be utilized again with the parameters changed to match those of the converters. Switching

frequency estimates can be found in 节7.15.

9.2.2.2.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values are recommended because they provide the lowest output voltage

ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside from the wide

variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on the

output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage

ripple in PFM mode. To achieve specified regulation performance and low output voltage ripple, the DC-bias

characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops

with increasing DC-bias voltage.

For the output capacitors of the BUCK converters, TI recommends placing small ceramic capacitors between the

inductor and load with many vias to the PGND plane. This solution typically provides the smallest and lowest-

cost solution available.

The minimum output capacitance recommended is 22 µF for stability. Equation 7 and Equation 8 can be used to

estimate the required output capacitance for a given load transient. Note that V_INwill be different for the

converters and that the switching frequency can be estimated using 节 7.15. Equation 9 can be neglected for

converters as there is no on time extension and the V_IN- V_OUTterm is typically smaller.

9.2.2.2.3 Selecting the Input Capacitors

Due to the nature of the switching converter with a pulsating input current, a low ESR input capacitor is required

for best input-voltage filtering and for minimizing the interference with other circuits caused by high input-voltage

spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for most applications. A

ceramic capacitor is recommended to achieve the low ESR requirement. However, the voltage rating and DC-

bias characteristic of ceramic capacitors must be considered. The input capacitor can be increased without any

limit for better input-voltage filtering.

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备注

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10-µF, 0402, 10-V, ±20%, or

similar capacitor.

9.2.2.3 LDO Design Procedure

The VTT LDO must handle the fast load transients from the DDR memory for termination. Therefore, it is

recommended to use ceramic capacitors to maintain a high amount of capacitance with low ESR on the VTT

LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the GRM188R60J226MEA0 from

Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred input capacitor for the VTT LDO is the

CL05A106MP5NUNC from Samsung (10-µF, 0402, 10-V, ±20%, or similar capacitor).

The remaining LDOs must have input and output capacitors chosen based on the values in 节7.9.

9.2.3 Application Curves

FET = CSD87588N

L = PIMB062D-R22ms

L = PIFE32251B-R47ms

C_OUT= 4 × 22 µF

C_OUT= 2 × 300 µF + 1 × 22 µF

图9-5. BUCK3 Converter Load Transient

图9-4. BUCK2 Controller Load Transient

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9.2.4 Layout

9.2.4.1 Layout Guidelines

For a detailed description regarding layout recommendations, refer to the TPS65086x Design Guide and to the

TPS65086x Schematic and Layout Checklist. For all switching power supplies, the layout is an important step in

the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done,

the regulator can have stability problems and EMI issues. Therefore, use wide and short traces for the main

current path and for the power ground tracks. The input capacitors, output capacitors, and inductors must be

placed as close as possible to the device. Use a common-ground node for power ground and use a different,

isolated node for control ground to minimize the effects of ground noise. Connect these ground nodes close to

the AGND pin by one or two vias. Use of the design guide is highly encouraged in addition to the following list of

other basic requirements:

• Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.

• To ensure proper sensing based on FET R_DSON, PGNDSNSx must not connect to PGND until very close to

the PGND pin of the FET.

• All inductors, input and output capacitors, and FETs for the converters and controller must be on the same

board layer as the IC.

• To achieve the best regulation performance, place feedback connection points near the output capacitors and

minimize the control feedback loop as much as possible.

• Bootstrap capacitors must be placed close to the device.

• The internal reference regulators must have their input and output capacitors placed close to the device pins.

• Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with DRVLx,

which provides optimal driver loops.

9.2.4.2 Layout Example

BUCK2

VREF Capacitor

VTT

BUCK6

BUCK3

BUCK5

BUCK4

BUCK1

图9-6. EVM Layout Example With All Components on the Top Layer

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9.2.5 VIN 5-V Application

The PMIC can be operated by a 5-V input voltage to the system because the power path of the controller does

not go through the device itself. The concept is simple: supply the controller VINs with the 5-V input, and supply

the VSYS with a 5.8-V step-up of the 5 V with a boost or charge pump. The 5.8 V is recommended because the

UVLO of the internal LDO5 is at 5.6 V and the device measures the voltage at VSYS and determines the

optimum internal compensation and controller settings thus, it is ideal the VSYS be close to the VIN of the

controllers.

PMIC

Example SoC

PLATFORM

V_IN

BUCK1

EXT FET

V_IN

VCORE

BUCK2

BUCK3 3.5A

BUCK4 3A

BUCK5 3A

BUCK6

EXT FET

VGPU

VCCIO

5V Supply

VCPU1

Note: An LDO or Buck

Can Supply the VPP

Rail if Needed for DDR.

VCPU2

V_IN

EXT FET

VDDQ, VDD1&2

VTT LDO ±0.5A

VTT

DDR

LDO5V or

5V Supply

LDOA1 0.2A

LDOA2 0.6A

LDOA3 0.6A

SWA1 0.3A

SWB1 0.3A

SWB2 0.3A

LDO5

VSUPP1

VSUPP2

VSUPP3

VSUPP4

VSUPP5

VSUPP6

1.8V

Input up to 3.3V

Supply Diode Needed if

Pre-bias is Not Supported

Charge Pump or

Boost

LDO5V

V_SYS

VSYS = Vout -

Vf

V_IN

40 mA –

mA

5V

5 V

PG_5V

LDO3P3

CTL1

IRQB

GPO1

GPO2

GPO3

GPO4

DATA

SCLK

CTL2

CTL3

CTL4

CTL5

CTL6

图9-7. VIN 5-V Application

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9.2.5.1 Design Requirements

The PMIC requires a step-up voltage from the 5-V input to 5.8 V for the VSYS supply. TI recommends keeping

the VSYS near 5.8 V for optimization of the controllers.

Depending on the application use cases, the supply current to the VSYS can require from 40 mA with the drivers

being supplied by the 5-V input to 440 mA with the drivers being supplied by the LDO5 and the LDOA1 being

operated at max loading. This means that a charge pump may be used in some applications like the 5-V input

but in others, a small boost may be required.

A Schottky diode from the 5-V input to the VSYS is recommended to ensure the VSYS is biased and the internal

reference LDOs are on before the step-up regulator is enabled or fully ramped up. If the step-up cannot tolerate

pre-bias condition then, 2 diodes may be needed to prevent the initial 5-V supply biasing the output of the step-

up.

9.2.5.2 Design Procedure

To design a 5-V input application, first provide a step-up voltage from the 5-V input to the VSYS. Design the

step-up to output a voltage near 5.8 V. Next, route the 5-V input to the controller and converter VINs. Thus, all

power paths (all high currents) are routed through the controllers or directly to the converters. None of the high

currents are required from the step-up supply. After the input stage is complete, the rest of the system can be

designed as normal following the typical application procedure, using 5 V as the input value to the controllers.

9.2.5.3 Application Curves

100%

95%

90%

85%

80%

75%

70%

65%

Vout = 1 V

Vout = 1.8 V

60%

Vout = 2.5 V

Vout = 3.3 V

55%

50%

0.1

0.2 0.3 0.40.5 0.7 1

Iout (A)

2

3

4 5 6 7

D010

FET = CSD87381P L = PIMB061H-R47 ms

图9-8. BUCK1 Efficiency at V_IN= 5 V

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9.3 Power Supply Coupling and Bulk Capacitors

This device is designed to work with several different input voltages. The minimum voltage on the VSYS pin is

5.6 V for the device to start up; however, this is a low power rail. The input to the FETs must be from 4.5 V to 21

V as long as the proper BOM choices are made. Input to the converters should be between 3.3 V and 5 V. For

the device to output maximum power, the input power must be sufficient. For the controllers, VIN must be able to

supply sufficient input current for the output power of the application. For the converters, PVINx must be able to

typically supply 2 A.

A best practice here is to determine power usage by the system and back-calculate the necessary power input

based on expected efficiency values.

9.4 Do's and Don'ts

• Connect the LDO5V output to the DRV5V_x_x inputs for situations where an external 5-V supply is not

initially available or is not available the entire time PMIC is on. If the external 5-V supply is always present,

then DRV5V_x_x can be directly connected to remove the V5ANA-to-LDO5P0 load switch R_DSON

.

• Ensure that none of the control pins are potentially floating.

• Include 0-Ωresistors on the DRVH or BOOT pins of controllers on prototype boards, which allows for slowing

the controllers if the system is unable to handle the noise generated by the large switching or if switching

voltage is too large due to layout.

• Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here causes

reference circuits to regulate incorrectly.

• Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may turn on

the HS FET passing the input to the output until VSYS is biased.

• Do not change the values of the reserved bits when writing I²C. This can have unexpected consequences.

Expected values for each OTP are shown in the register map.

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10 Device and Documentation Support

10.1 Device Support

10.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

10.1.2 Development Support

For documentation related to device development see the following:

• Texas Instruments, TPS65086x Schematic and Layout Checklist

• Texas Instruments, TPS65086x Design Guide

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, CSD85301Q2 20 V Dual N-Channel NexFET™ Power MOSFETs data sheet

• Texas Instruments, CSD87331Q3D Synchronous Buck NexFET^™Power Block data sheet

• Texas Instruments, CSD87588N Synchronous Buck NexFET™ Power Block II data sheet

• Texas Instruments, CSD87381P Synchronous Buck NexFET™ Power Block II data sheet

• Texas Instruments, CSD87350Q5D Synchronous Buck NexFET™ Power Block data sheet

• Texas Instruments, MSP430G2121 Mixed Signal Microcontroller data sheet

• Texas Instruments, Power management integrated buck controllers for distant point-of-load applications white

paper

• Texas Instruments, TPS65086x Evaluation Module user's guide

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

D-CAP2^™, D-CAP^™, and NexFET^™are trademarks of Texas Instruments.

NXP^™is a trademark of NXP Semiconductors.

TI E2E^™is a trademark of Texas Instruments.

Xilinx^®and Zynq^®are registered trademarks of Xilinx.

所有商标均为其各自所有者的财产。

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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型号：	TPS6508641RSKT
厂家：	TEXAS INSTRUMENTS
描述：	用于 Xilinx MPSoC 和 FPGA 的可配置多轨 PMIC \| RSK \| 64 \| -40 to 85 集成电源管理电路
文件：	总129页 (文件大小：2651K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS6508641RSKT [TI]

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