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TPS6508700

ZHCSGZ6 –OCTOBER 2017

适用于 AMD™ 系列 17h 型 10h-1Fh 处理器的 TPS6508700 PMIC

1 器件概述

1.1 特性

1

• 5.6V 至 21V 的宽输入电压范围

• 三个可变输出电压同步

• 带有 BUCK6 的 LDO 作为输入电压

• 三个具有压摆率控制功能的负载开关

降压控制器，采用 DCAP2™拓扑

– 输出电流高达 300mA，压降小于标称输入电压的

– 使用外部 FET 的可扩展输出电流，支持可选电流

限制

– 针对 BUCK2 和 BUCK6 进行 I²C 动态电压调节

(DVS) 控制，针对 BUCK1 进行外部反馈

1.5%

– 输入电压为 1.8V 时，R_DSON< 96mΩ

• 5V 固定输出电压 LDO (LDO5)

– 用于 SMPS 的栅极驱动器和 LDOA1 的电源

– 可自动切换至 5V 降压以实现更高效率

• 工厂 OTP 编程提供的内置时序功能

– 用于 G3'、G3、S5 和 S0 状态选择的 CTL1、

CTL4 和 CTL5

– 用于 PG_S0 和 PG_S5 的 GPO1 和 GPO2

– 漏极开路中断输出引脚

• I²C 接口支持：

• 三个可变输出电压同步降压转换器，采用 DCS-

Control 拓扑技术并支持 I²C DVS 功能

– 输入电压范围为 4.5V 至 5.5V

– 输出电压范围为 0.425V 至 3.575V

– 输出电流高达 3A

• 三个具有可调节输出电压的 LDO 稳压器

– LDOA1：可通过 I²C 选择的输出电压（1.35V 至

3.3V），输出电流高达 200mA

– 标准模式（100kHz）

– 快速模式（400kHz）

– 快速模式+（1MHz）

– LDOA2 和 LDOA3：I²C 可选输出电压为 0.7V 至

1.5V，输出电流高达 600mA

1.2 应用

•

2、3 或 4 电芯锂离子电池供电产品（NVDC 或非

NVDC）

•

平板电脑、超极本和笔记本电脑

移动 PC 和移动网络设备

•

墙供电设计，特别是 12V 电源

1.3 说明

TPS6508700 器件是一款单芯片电源管理 IC (PMIC)，专为笔记本电脑和一体式台式机的 AMD™系列 17h

型 10h-1Fh 处理器而设计。TPS6508700 器件可提供 5.6V 至 21V 的输入电压范围，用途广泛。该器件非

常适合使用 2S、3S 或 4S 锂离子电池组的 NVDC 和非 NVDC 电源架构。该 D-CAP2™和 DCS-Control™

高频稳压器采用小型电感和电容，以减小解决方案体积。D-CAP2 和 DCS-Control 拓扑具有出色的瞬态响应

性能，特别适用于具有快速负载开关的处理器内核和系统内存电压轨。I²C 接口可通过嵌入式控制器 (EC) 或

片上系统 (SoC) 进行轻松控制。PMIC 采用带散热焊盘的 8mm × 8mm 单行 VQFN 封装，因此散热性能良

好，电路板布线简单。

器件信息⁽¹⁾

封装

器件型号

封装尺寸（标称值）

TPS6508700

VQFN (64)

8.00mm x 8.00mm

(1) 有关详细信息，请参阅机械封装和可订购信息部分。

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SWCS134

TPS6508700

ZHCSGZ6 –OCTOBER 2017

www.ti.com.cn

1.4 功能框图

LDO5V

LDO1

VIN

BOOT1

DRVH1

LDOA1

1.35 œ 3.3 V

200 mA

CTL1

SW1

V1

CTL2

VSET

EN

BUCK1

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL1

CTL3/SLPENB1

CTL4

Control

Inputs

EN

VSET

FBVOUT1

PGNDSNS1

CTL5

ILIM1

CTL6/SLPENB2

VPULL

VIN

BOOT2

DRVH2

CLK

SoC

&

I²C CTL

SW2

DATA

System

VPULL

V2

VSET

EN

BUCK2

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL2

Control

Outputs

FBVOUT2

PGNDSNS2

IRQB

GP01

GPO2

GPO3

GPO4

FBGND2

ILIM2

Internal

Interrupt

Events

3.3V œ 5V

PVIN3

LX3

TEST CTL

OTP

BUCK3

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

V3

FB3

<PGND_BUCK3>

REGISTERS

3 A

3.3V œ 5V

PVIN4

LX4

BUCK4

VSET 0.425 ꢀ 3.575 V

0.41 œ 1.67 V

LDO5P0

V5ANA

LDO5P0

Digital Core

V4

V5

3.3V œ 5V

EN

FB4

(DVS)

3 A

<PGND_BUCK4>

3.3V œ 5V

PVIN5

LX5

BUCK5

œ

VSET

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

4.7V

+

EN

FB5

STDBY

LDO5V

3 A

<PGND_BUCK5>

VIN

REFSYS

LDO3P3

BOOT6

DRVH6

Thermal

Monitoring

VSYS

5.6Vœ21V

LDO3P3

SW6

DRVL6

Thermal Shutdown

VDDQ

VSET

EN

BUCK6

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VREF

AGND

Bandgap

FBVOUT6

PGNDSNS6

ILIM6

PVIN_VTT

VTT

VTT_LDO

VDDQ/2

EN

VTTFB

LDOA2

0.7 ꢀ 1.5 V

600 mA

LDOA3

0.7 ꢀ 1.5 V

600 mA

LOAD SWA1

LOAD SWB1

LOAD SWB2

图 1-1. PMIC 功能框图

2

器件概述

TPS6508700

www.ti.com.cn

ZHCSGZ6 –OCTOBER 2017

内容

1

器件概述.................................................... 1

4.16 Typical Characteristics .............................. 17

Detailed Description ................................... 18

5.1 Overview ............................................ 18

5.2 Functional Block Diagram........................... 19

5.3 SMPS Voltage Regulators .......................... 20

5.4 LDO Regulators and Load Switches ................ 26

1.1 特性 ................................................... 1

1.2 应用 ................................................... 1

1.3 说明 ................................................... 1

1.4 功能框图 .............................................. 2

修订历史记录............................................... 3

Pin Configuration and Functions..................... 4

3.1 Pin Functions ......................................... 4

Specifications ............................................ 7

4.1 Absolute Maximum Ratings .......................... 7

4.2 ESD Ratings.......................................... 7

4.3 Recommended Operating Conditions ................ 8

4.4 Thermal Information .................................. 8

5

2

3

5.5

Power Good Information (PGOOD or PG) and GPO

Pins.................................................. 27

Power Sequencing and Voltage-Rail Control ....... 29

5.6

4

5.7 Device Functional Modes ........................... 31

5.8 I²C Interface ......................................... 32

5.9 Register Maps....................................... 35

Applications, Implementation, and Layout........ 82

6.1 Application Information.............................. 82

6.2 Typical Application .................................. 82

6

7

4.5

Electrical Characteristics: Total Current

Consumption.......................................... 8

Electrical Characteristics: Reference and Monitoring

System................................................ 9

4.6

6.3

Power Supply Coupling and Bulk Capacitors....... 91

6.4 Do's and Don'ts ..................................... 91

器件和文档支持 .......................................... 92

7.1 器件支持 ............................................ 92

7.2 文档支持............................................. 92

7.3 接收文档更新通知 ................................... 92

7.4 社区资源............................................. 92

7.5 商标.................................................. 92

7.6 静电放电警告 ........................................ 92

7.7 术语表 ............................................... 92

机械、封装和可订购信息................................ 92

4.7

4.8

Electrical Characteristics: Buck Controllers......... 10

Electrical Characteristics: Synchronous Buck

Converters........................................... 11

4.9 Electrical Characteristics: LDOs .................... 12

4.10 Electrical Characteristics: Load Switches........... 14

4.11 Digital Signals: I²C Interface ........................ 15

4.12 Digital Input Signals (CTLx)......................... 15

4.13 Digital Output Signals (IRQB, GPOx) ............... 15

4.14 Timing Requirements ............................... 15

4.15 Switching Characteristics ........................... 16

8

2 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2017 年 10 月

*

初始发行版

修订历史记录

3

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ZHCSGZ6 –OCTOBER 2017

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3 Pin Configuration and Functions

Figure 3-1 shows the 64-pin RSK plastic quad-flatpack no-lead package with exposed thermal pad.

FBGND2

FBVOUT2

DRVH2

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VTTFB

2

VTT

3

PVINVTT

ILIM6

SW2

4

BOOT2

5

FBVOUT6

DRVH6

SW6

PGNDSNS2

DRVL2

6

7

DRV5V_2_A1

LDOA1

8

BOOT6

PGNDSNS6

DRVL6

Thermal

Pad

9

LX3

10

11

12

13

14

15

16

PVIN3

DRV5V_1_6

DRVL1

FB3

CTL1

PGNDSNS1

BOOT1

SW1

CTL6/SLPENB2

IRQB

GPO1

DRVH1

Not to scale

The thermal pad must be connected to the system power ground plane.

Figure 3-1. 64-pin RSK VQFN (Top View)

3.1 Pin Functions

Pin Functions

NAME

SMPS REGULATORS

I/O

DESCRIPTION

NO.

Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor

or input capacitor of load.

1

FBGND2

I

4

Pin Configuration and Functions

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Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor

or input capacitor of load.

2

FBVOUT2

I

3

4

5

6

7

DRVH2

SW2

O

I

High-side gate driver output for BUCK2 controller.

Switch node connection for BUCK2 controller.

BOOT2

I

Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin.

Power GND sense connection for BUCK2. Connect to ground terminal of external low-side FET.

Low-side gate driver output for BUCK2 controller.

PGNDSNS2

DRVL2

I

O

5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (typical) ceramic

capacitor. Shorted on board to LDO5P0 pin.

8

DRV5V_2_A1

I

10

11

12

20

21

22

23

24

25

LX3

PVIN3

FB3

O

I

Switch node connection for BUCK3 converter.

Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.

Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor.

Switch node connection for BUCK5 converter.

I

LX5

O

I

PVIN5

FB5

Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.

Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor.

Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor.

Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.

Switch node connection for BUCK4 converter.

I

FB4

I

PVIN4

LX4

I

O

Remote feedback sense for BUCK1 controller. Connect to external feedback near either output

capacitor or input capacitor of load. Recommend a 4.7-pF feedforward capacitor.

29

30

FBVOUT1

ILIM1

I

Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of

external low-side FET.

33

34

35

36

37

DRVH1

SW1

O

I

High-side gate driver output for BUCK1 controller.

Switch node connection for BUCK1 controller.

BOOT1

I

Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin.

Power GND sense connection for BUCK1. Connect to ground terminal of external low-side FET.

Low-side gate driver output for BUCK1 controller.

PGNDSNS1

DRVL1

I

O

5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (typical) ceramic

capacitor. Shorted on board to LDO5P0 pin.

38

DRV5V_1_6

I

39

40

41

42

43

DRVL6

PGNDSNS6

BOOT6

O

I

Low-side gate driver output for BUCK6 controller.

Power GND sense connection for BUCK6. Connect to ground terminal of external low-side FET.

Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin.

Switch node connection for BUCK6 controller.

I

SW6

I

DRVH6

O

High-side gate driver output for BUCK6 controller.

Remote feedback sense for BUCK6 controller. Connect to positive terminal of output capacitor or input

capacitor of load.

44

45

64

FBVOUT6

ILIM6

I

Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of

external low-side FET.

Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of

external low-side FET.

ILIM2

LDO AND LOAD SWITCHES

9

LDOA1

O

LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.

Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating

when not in use.

17

SWB1

Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical) ceramic capacitor to

improve transient performance. Connect to ground when not in use.

18

19

31

PVINSWB1_B2

SWB2

I

Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating

when not in use.

O

Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating

when not in use.

SWA1

Pin Configuration and Functions

5

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Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve

transient performance. Connect to ground when not in use.

32

PVINSWA1

I

Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic capacitor. Connect to

ground when not in use.

46

47

48

49

50

PVINVTT

VTT

Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic capacitors. Leave floating

when not in use.

O

I

Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor. Leave floating

when not in use.

VTTFB

Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not

in use.

LDOA3

O

I

Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.

Connect to ground when not in use.

PVINLDOA2_A3

Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not

in use.

51

54

56

LDOA2

LDO3P3

LDO5P0

O

Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.

Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with

a 4.7-µF (typical) ceramic capacitor.

External 5-V supply input to internal load switch that connects this pin to LDO5P0 pin. Bypass this pin

with an optional ceramic capacitor to improve transient performance.

57

V5ANA

I

INTERFACE

Active-high enable pin for BUCK4, BUCK5, and BUCK6. Connect to AND of GPIO_G3 and EN_S5 for

typical sequencing.

13

CTL1

14

15

CTL6/SLPENB2

IRQB

I

Active-high unused control signal. Sleep state control for BUCK6 (masked).

Open-drain output interrupt pin. Refer to Section 5.9.3 for definitions.

O

PG_S5 output indicates S5 power state has been reached. Open drain output, pull up to appropriate

voltage rail.

16

26

27

28

GPO1

GPO2

GPO3

GPO4

O

PG_S0 output indicates S0 power state has been reached. Open drain output, pull up to appropriate

voltage rail.

General purpose output that is configured to push-pull output at 3.3V and controlled by I²C. Default state

is low.

General purpose output that is configured to open-drain output and controlled by I²C. Default state is

high.

I²C clock

O

I

58

59

CLK

DATA

I/O I²C data

Active-high LDOA2 and LDOA3 enable. Tie to GND unless using this pin to disable LDOA2 and LDOA3

60

61

62

63

CTL2

CTL3/SLPENB1

CTL4

I

after enabling them by I²C.

Active-high VTT LDO enable and sleep state control for BUCK1-BUCK5 (masked), LDOA2, and LDOA3.

Active-high enable pin for BUCK1 and BUCK3. Connect to OR of CTL1 input and inverted GPIO_G3 for

typical sequencing. SWA1, SWB1, and SWB2 can also use CTL4 if configured by I²C after boot.

CTL5

Active-high enable pin for BUCK2. Connect to EN_S0 for typical sequencing.

REFERENCE

Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic capacitor between this

pin and quiet ground.

53

VREF

AGND

VSYS

O

—

I

Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF

capacitor.

52

55

System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF

(typical) ceramic capacitor.

THERMAL PAD

Thermal pad

—

Connect to PCB ground plane using multiple vias for good thermal and electrical performance.

6

Pin Configuration and Functions

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4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

ANALOG

Input voltage from battery, VSYS

–0.3

–5

28

7

V

PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6

V5ANA

6

PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2

DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6

SW1, SW2, SW6, transient for less than 5 ns.

LX3, LX4, LX5

0.3

34

28

7

-0.3

–2

LX3, LX4, LX5, transient for less than 20 ns.

Differential voltage, BOOTx to SWx

9

–0.3

5.5

VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6,

PVINVTT, VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1

–0.3

3.6

3.3

V

PVINLDOA2_A3, LDOA2, LDOA3

DIGITAL IO

DATA, CLK, GPO1-GPO3

CTL1-CTL6, GPO4, IRQB

CHIP

–0.3

3.6

7

V

Storage temperature, T_stg

–40

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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Specifications

7

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4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

13

MAX

UNIT

ANALOG

VSYS

5.6

–0.3

–1

21

1.3

V

v

VREF

PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1

PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2

DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6

DRVL1, DRVL2, DRVL6

5

5.5

0.3

26.5

5.5

V

SW1, SW2, SW6

21

LX3, LX4, LX5

–1

5.5

FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5

LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1

PVINVTT

–0.3

3.6

3.3

FBVOUT6

/ 2

VTT, VTTFB

–0.3

V

PVINSWA1, SWA1

–0.3

3.3

3.6

1.8

1.5

V

PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2

LDOA2, LDOA3

DIGITAL IO

DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB

CHIP

–0.3

3.3

V

Operating ambient temperature, T_A

Operating junction temperature, T_J

–40

27

85

°C

125

4.4 Thermal Information

TPS6508700

RSK (VQFN)

64 PINS

25.8

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

11.3

4.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

4.4

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4.5 Electrical Characteristics: Total Current Consumption

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PMIC shutdown current that includes

I_Qfor references, LDO5, LDO3P3,

and digital core

V_SYS= 13 V, all functional output rails are

disabled

I_SD

65

µA

8

Specifications

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4.6 Electrical Characteristics: Reference and Monitoring System

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REFERENCE

V_REF

Band-gap reference voltage

Band-gap reference voltage accuracy

Band-gap output capacitor

1.25

V

–0.5%

0.047

0.5%

C_VREF

0.1

5.4

0.22

µF

V

V_{SYS_UV}

LO_5V

VSYS UVLO threshold for LDO5

V_SYSfalling

5.24

5.56

V_{SYS_UV}

LO_5V_H

YS

VSYS UVLO threshold hysteresis for V_SYSrising above

200

3.6

mV

V

LDO5

V_{SYS_UVLO_5V}

V_{SYS_UV}

LO_3V

VSYS UVLO threshold for LDO3P3

V_SYSfalling

3.45

3.75

V_{SYS_UV}

LO_3V_H

YS

VSYS UVLO threshold hysteresis for V_SYSrising above

150

mV

LDO3P3

V_{SYS_UVLO_3V}

T_CRIT

Critical threshold of die temperature

Hysteresis of T_CRIT

T_Jrising

130

110

145

10

160

120

°C

T_{CRIT_H}

YS

T_Jfalling

T_Jrising

T_HOT

Hot threshold of die temperature

Hysteresis of T_HOT

115

10

T_{HOT_HY}

S

T_Jfalling

LDO5

V_IN

Input voltage at V_SYSpin

DC output voltage

5.6

4.9

13

5

21

5.1

V

V_OUT

I_OUT

I_OCP

I_OUT= 10 mA

DC output current

100

180

mA

Overcurrent protection

Measured with output shorted to ground

V_OUTrising

200

Power good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

94%

4%

V_{TH_PG_}

HYS

Power good deassertion hysteresis

V_OUTrising or falling

V_IN= 13 V, I_OUT= 0 A

I_Q

Quiescent current

20

µA

µF

C_OUT

External output capacitance

2.7

4.7

10

1

V5ANA-to-LDO5P0 LOAD SWITCH

V_IN= 5 V, measured from V5ANA pin to LDO5P0

pin at I_OUT= 200 mA

R_DSON

V_{TH_PG}

On resistance

Ω

V

Power good threshold for external 5-

V supply

V_V5ANArising

V_V5ANAfalling

4.7

V_{TH_HYS}Power good threshold hysteresis for

_PG

100

mV

µA

external 5-V supply

Switch disabled,

V_V5ANA= 5 V, V_LDO5= 0 V

I_LKG

Leakage current

10

21

LDO3P3

V_IN

Input voltage at V_SYSpin

DC output voltage

5.6

–3%

70

13

V

V_OUT

I_OUT= 10 mA

3.3

V_IN= 13 V,

I_OUT= 10 mA

DC output voltage accuracy

3%

40

I_OUT

I_OCP

DC output current

mA

Overcurrent protection

Measured with output shorted to ground

V_OUTrising

Power good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

92%

3%

V_{TH_PG_}

HYS

Power good deassertion hysteresis

V_OUTfalling

Specifications

9

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Electrical Characteristics: Reference and Monitoring System (continued)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN= 13 V,

I_OUT= 0 A

I_Q

Quiescent current

20

µA

C_OUT

External output capacitance

2.2

4.7

10

µF

4.7 Electrical Characteristics: Buck Controllers

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BUCK1

Power input voltage for external HSD

FET

V_IN

5.6

13

21

V

V_FBVOU

T1

Internal reference regulation voltage

Low-side output valley current limit

T_A= 25°C

0.392

0.4

0.408

I_{LIM_LSD}accuracy (programmed by external

resistor R_LIM

–15%

15%

)

I_LIMREFSource current out of ILIM1 pin

45

0.2

50

55

µA

V

V_LIM

Voltage at ILIM1 pin

V_LIM= R_LIM× I_LIMREF

V_OUTrising

2.25

105.5%

89.5%

108% 110.5%

Power good deassertion threshold in

percentage of target V_FB

V_{TH_PG}

V_OUTfalling

92%

3

94.5%

Source, IDRVH = –50 mA

Sink, IDRVH = 50 mA

Source, IDRVL = –50 mA

Sink, IDRVL = 50 mA

Ω

R_{DSON_}

DRVH

Driver DRVH resistance

Driver DRVL resistance

2

3

Ω

R_{DSON_}

DRVL

0.4

100

Ω

C_BOOT

Bootstrap capacitance

nF

R_{ON_BO}

OT

Bootstrap switch ON resistance

20

Ω

BUCK2, BUCK6

Power input voltage for external HSD

FET

V_IN

5.6

0.41

1

13

21

1.67

V

VID step size = 10 mV, BUCKx_VID[6:0]

progresses from 0000001b to 1111111b

DC output voltage VID range and

options

VID step size = 25 mV, BUCKx_VID[6:0]

progresses from 0000001b to 1111111b

3.575

BUCK2 output voltage default

BUCK6 output voltage default

Set by BUCK2_VID[6:0], 10-mV step size selected

Set by BUCK6_VID[6:0], 25-mV step size selected

0.8

3.3

V

V_OUT

V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V

I_OUT= 100 mA to 7 A

DC output voltage accuracy

–2%

–30

2%

40

Total output voltage accuracy (DC

plus ripple) in DCM

I_OUT= 10 mA, V_OUT≤ 1 V

mV

Step size = 10 mV

Step size = 25 mV

2.5

5

3.125

6.25

mV/µs

SR(V_OU

Output DVS slew rate

)

T

Low-side output valley current limit

I_{LIM_LSD}accuracy (programmed by external

resistor R_LIM

–15%

15%

)

I_LIMREFSource current out of ILIM1 pin

T_A= 25°C

45

50

55

µA

V

V_LIM

Voltage at ILIM1 pin

V_LIM= R_LIM× I_LIMREF

0.2

2.25

ΔV_OUT

ΔV_IN

/

V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,

I_OUT= 7 A

Line regulation

–0.5%

0.5%

10

Specifications

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Electrical Characteristics: Buck Controllers (continued)

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN= 13 V, V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5,

3.3 V, I_OUT= 0 A to 7 A,

referenced to V_OUTat I_OUT= I_{OUT_MAX}

ΔV_OUT

ΔI_OUT

/

Load regulation

0%

1%

V_OUTrising

105.5%

89.5%

108% 110.5%

Power good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_OUTfalling

92%

3

94.5%

Source, IDRVH = –50 mA

Sink, IDRVH = 50 mA

Source, IDRVL = –50 mA

Sink, IDRVL = 50 mA

BUCKx_DIS[1:0] = 01b

BUCKx_DIS[1:0] = 10b

BUCKx_DIS[1:0] = 11b

Ω

R_{DSON_}

DRVH

Driver DRVH resistance

Driver DRVL resistance

2

3

Ω

R_{DSON_}

DRVL

0.4

100

200

500

100

Ω

R_DIS

Output auto-discharge resistance

Ω

C_BOOT

Bootstrap capacitance

nF

R_{ON_BO}

OT

Bootstrap switch ON resistance

20

Ω

4.8 Electrical Characteristics: Synchronous Buck Converters

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

BUCK3, BUCK4, BUCK5

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN

Power input voltage

4.5

5

5.5

V

DC output voltage VID range and

options

VID step size = 25 mV, BUCKx_VID[6:0]

progresses from 0000001b to 1111111b

0.425

3.575

BUCK3 output voltage default

BUCK4 output voltage default

BUCK5 output voltage default

Set by BUCK3_VID[6:0], 25-mV step size

Set by BUCK4_VID[6:0], 25-mV step size

Set by BUCK5_VID[6:0], 25-mV step size

1.8

0.8

1.8

V

V_OUT

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 1.5 A

–2%

–2.5%

–30

2%

2.5%

40

DC output voltage accuracy

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 100 mA

Total output voltage accuracy (DC

plus ripple) in DCM

I_OUT= 10 mA, V_OUT≤ 1 V

mV

SR(V_OU

Output DVS slew rate

5

6.25

35

mV/µs

)

T

I_OUT

Continuous DC output current

3

7

A

I_{IND_LIM}HSD FET current limit

4.3

I_Q

Quiescent current

V_IN= 5 V, V_OUT= 1 V

µA

ΔV_OUT

ΔV_IN

/

V_OUT= 1, 1.2, 1.35, 1.5, 1.8,

2.5, 3.3 V, I_OUT= 1.5 A

Line regulation

–0.5%

–0.2%

0.5%

2%

V_IN= 5 V, V_OUT= 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,

I_OUT= 0 A to 3 A, referenced to V_OUTat I_OUT= 1.5

A

ΔV_OUT

ΔI_OUT

Load regulation

V_OUTrising

V_OUTfalling

108%

92%

Power good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_{TH_HYS}Power good reassertion hysteresis

V_OUTrising or falling

3%

entering back into V_{TH_PG}

_PG

BUCKx_DIS[1:0] = 01b

BUCKx_DIS[1:0] = 10b

BUCKx_DIS[1:0] = 11b

100

200

500

R_DIS

Output auto-discharge resistance

Ω

Specifications

11

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4.9 Electrical Characteristics: LDOs

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LDOA1

V_IN

Input voltage

4.5

5

5.5

V

DC output voltage

Accuracy

Set by LDOA1_VID[3:0]

3.3

V_OUT

I_OUT

I_OUT= 0 to 200 mA

–2%

2%

V

DC output current

200

mA

ΔV_OUT

ΔV_IN

/

Line regulation

I_OUT= 40 mA

–0.5%

0.5%

2%

ΔV_OUT

ΔI_OUT

Load regulation

I_OUT= 10 mA to 200 mA

–2%

500

I_OCP

Overcurrent protection

V_IN= 5 V, Measured with output shorted to ground

mA

µs

V_OUTrising

V_OUTfalling

108%

92%

Power good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Measured from EN = H to reach 95% of final

value,

C_OUT= 4.7 µF

t_STARTU

P

Start-up time

500

I_Q

Quiescent current

External output capacitance

ESR

I_OUT= 0 A

23

µA

µF

mΩ

Ω

2.7

4.7

10

C_OUT

100

LDOA1_DIS[1:0] = 01b

LDOA1_DIS[1:0] = 10b

LDOA1_DIS[1:0] = 11b

100

190

450

R_DIS

Output auto-discharge resistance

Ω

LDOA2 and LDOA3

V_OUT

+

V_IN

Power input voltage

V_DROP

1.8

1.98

V

(1)

LDOA2 DC output voltage

LDOA3 DC output voltage

DC output voltage accuracy

DC output current

Set by LDOA2_VID[3:0]

Set by LDOA3_VID[3:0]

I_OUT= 0 to 600 mA

1.5

1.2

V

V_OUT

–2%

3%

I_OUT

600

mA

mV

V_OUT= 0.99 × V_{OUT_NOM}

I_OUT= 600 mA

,

V_DROP

Dropout voltage

Line regulation

350

0.5%

2%

ΔV_OUT

ΔV_IN

/

I_OUT= 300 mA

–0.5%

ΔV_OUT

ΔI_OUT

Load regulation

I_OUT= 10 mA to 600 mA

–2%

0.65

I_OCP

Overcurrent protection

Measured with output shorted to ground

V_OUTrising

1.25

108%

92%

A

Power good assertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_OUTfalling

t_STARTU

P

Measured from EN = H to reach 95% of final

value, C_OUT= 4.7 µF

Start-up time

500

µs

I_Q

Quiescent current

I_OUT= 0 A

20

µA

(1) It must be equal to or greater than 1.62 V.

12

Specifications

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Electrical Characteristics: LDOs (continued)

over recommended input voltage range, T_A= –40°C to +85°C and T_A= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LDOA2 and LDOA3 (continued)

f = 1 kHz, V_IN= 1.8 V, V_OUT= 1.2 V,

I_OUT= 300 mA,

C_OUT= 2.2 µF – 4.7 µF

48

dB

PSRR

Power supply rejection ratio

f = 10 kHz, V_IN= 1.8 V, V_OUT= 1.2 V,

I_OUT= 300 mA,

30

C_OUT= 2.2 µF – 4.7 µF

External output capacitance

ESR

2.2

4.7

10

µF

C_OUT

100

mΩ

LDOAx_DIS[1:0] = 01b

LDOAx_DIS[1:0] = 10b

LDOAx_DIS[1:0] = 11b

80

180

475

R_DIS

Output auto-discharge resistance

Ω

VTT LDO

V_IN

Power input voltage

DC output voltage

1.2

3.3

10

V

V_OUT

V_IN= 1.2 V, Measured at VTTFB pin

V_IN/ 2

Relative to V_IN/ 2, I_OUT≤ 10 mA,

1.1 V ≤ V_IN≤ 1.35 V

–10

DC output voltage accuracy

mV

mA

Relative to V_IN/ 2, I_OUT≤ 500 mA,

1.1 V ≤ V_IN≤ 1.35 V

–25

–500

–4%

0.95

25

500

4%

I_OUT

DC output current

Load regulation

sink(–) and source(+)

ΔV_OUT

/

1.1 V ≤ V_IN≤ 1.35 V,

I_OUT= –500 mA to 500 mA

ΔI_OUT

I_OCP

Overcurrent protection

Measured with output shorted to ground

V_OUTrising

A

110%

95%

Power good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

V_OUTfalling

V_{TH_HYS}Power good reassertion hysteresis

5%

entering back into V_{TH_PG}

_PG

I_Q

Total ground current

V_IN= 1.2 V, I_OUT= 0 A

V_IN= 1.2 V, disabled

240

1

µA

µF

kΩ

Ω

I_LKG

C_IN

C_OUT

OFF leakage current

External input capacitance

External output capacitance

10

35

VTT_DIS = 0b

VTT_DIS = 1b

1000

60

R_DIS

Output auto-discharge resistance

80

100

Specifications

13

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4.10 Electrical Characteristics: Load Switches

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SWA1

V_IN

Input voltage range

DC output current

0.5

1.5

3.3

V

I_OUT

300

mA

V_IN= 1.8 V, measured from PVINSWA1 pin to

SWA1 pin at I_OUT= I_OUT,MAX

60

93

R_DSON

ON resistance

mΩ

V_IN= 3.3 V, measured from PVINSWA1 pin to

SWA1 pin at I_OUT= I_OUT,MAX

100

165

V_OUTrising

V_OUTfalling

108%

92%

Power good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Power good reassertion hysteresis

entering back into V_{TH_PG}

V_{TH_HYS_PG}

I_INRUSH

V_OUTrising or falling

2%

Inrush current upon turnon

V_IN= 3.3 V, C_OUT= 0.1 µF

V_IN= 3.3 V, I_OUT= 0 A

10

mA

µA

10.5

9

I_Q

Quiescent current

V_IN= 1.8 V, I_OUT= 0 A

Switch disabled, V_IN= 1.8 V

Switch disabled, V_IN= 3.3 V

7

370

900

I_LKG

Leakage current

nA

µF

10

C_OUT

External output capacitance

0.1

100

200

500

SWA1_DIS[1:0] = 01

SWA1_DIS[1:0] = 10

SWA1_DIS[1:0] = 11

R_DIS

Output auto-discharge resistance

Ω

SWB1, SWB2

V_IN

Input voltage range

0.5

1.5

3.3

V

I_OUT

DC current per channel

400

mA

V_IN= 1.8 V, measured from PVINSWB1_B2 pin to

SWB1/SWB2 pin at I_OUT= I_OUT,MAX

68

75

92

mΩ

R_DSON

ON resistance per channel

V_IN= 3.3 V, measured from PVINSWB1_B2 pin to

SWB1/SWB2 pin at I_OUT= I_OUT,MAX

125

V_OUTrising

V_OUTfalling

108%

92%

Power good deassertion threshold in

percentage of target V_OUT

V_{TH_PG}

Power good reassertion hysteresis

entering back into V_{TH_PG}

V_{TH_HYS_PG}

I_INRUSH

V_OUTrising or falling

2%

Inrush current upon turning on

V_IN= 3.3 V, C_OUT= 0.1 µF

V_IN= 3.3 V, I_OUT= 0 A

10

mA

µA

10.5

9

I_Q

Quiescent current

V_IN= 1.8 V, I_OUT= 0 A

Switch disabled, V_IN= 1.8 V

Switch disabled, V_IN= 3.3 V

7

460

I_LKG

Leakage current

nA

µF

10

1150

C_OUT

External output capacitance

0.1

100

200

500

SWBx_DIS[1:0] = 01

SWBx_DIS[1:0] = 10

SWBx_DIS[1:0] = 11

R_DIS

Output auto-discharge resistance

Ω

14

Specifications

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4.11 Digital Signals: I²C Interface

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

Low-level output voltage

High-level input voltage

Low-level input voltage

Leakage current

TEST CONDITIONS

V_{PULL_UP}= 1.8 V

MIN

TYP

MAX UNIT

V_OL

V_IH

V_IL

0.4

V

1.2

0.4

0.3

8.5

2.5

1

V

I_LKG

V_{PULL_UP}= 1.8 V

Standard mode

Fast mode

0.01

µA

R_PULL-

UP

Pullup resistance

kΩ

Fast mode plus

C_OUT

Total load capacitance per pin

50

pF

4.12 Digital Input Signals (CTLx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

High-level input voltage

Low-level input voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IH

V_IL

0.85

V

0.4

V

4.13 Digital Output Signals (IRQB, GPOx)

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

Low-level output voltage

Leakage current

TEST CONDITIONS

I_OL< 2 mA

V_{PULL_UP}= 1.8 V

MIN

TYP

MAX UNIT

V_OL

I_LKG

0.4

V

0.35

µA

4.14 Timing Requirements

over recommended free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

MIN

NOM

MAX UNIT

I²C INTERFACE

Clock frequency (standard mode)

100

400

kHz

ns

f_CLK

Clock frequency (fast mode)

Clock frequency (fast mode plus)

Rise time (standard mode)

Rise time (fast mode)

1000

300

t_r

ns

Rise time (fast mode plus)

Rise time (standard mode)

Rise time (fast mode)

120

ns

300

ns

t_f

300

ns

Rise time (fast mode plus)

120

ns

Specifications

15

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4.15 Switching Characteristics

over operating free-air temperature range and over recommended input voltage range (typical values are at T_A= 25°C)

(unless otherwise noted)

PARAMETER

BUCK CONTROLLERS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Measured from enable going high to when output

reaches 90% of target value.

t_PG

Total turnon time

550

850

µs

T_ON,MINMinimum on-time of DRVH

50

15

30

ns

DRVH off to DRVL on

DRVL off to DRVH on

T_DEAD

f_SW

Driver dead-time

Continuous-conduction mode,

V_IN= 13 V, V_OUT≥ 1 V

Switching frequency

1000

kHz

BUCK CONVERTERS

Measured from enable going high to when output

reaches 90% of target value.

t_PG

Total turnon time

250

1.6

1.7

1.9

2

1000

µs

Continuous-conduction mode, V_OUT= 1 V, I_OUT

1 A

=

MHz

Continuous-conduction mode, V_OUT= 1.05 V, I_OUT

= 1 A

Continuous-conduction mode, V_OUT= 1.24 V, I_OUT

= 1 A

f_SW

Switching frequency

Continuous-conduction mode, V_OUT= 1.35 V, I_OUT

= 1 A

Continuous-conduction mode, V_OUT= 1.8 V, I_OUT

= 1 A

2.5

LDOAx

Measured from enable going high to when output

reaches 95% of final value,

V_OUT= 1.2 V, C_OUT= 4.7 µF

t_STARTU

P

Start-up time

180

22

µs

VTT LDO

t_STARTU

P

Measured from enable going high to PG assertion,

V_OUT= 0.675 V, C_OUT= 40 µF

SWA1

Measured from enable going high to reach 95% of

final value,

V_IN= 3.3 V, C_OUT= 0.1 µF

0.85

0.63

ms

t_TURN-

ON

Turnon time

Measured from enable going high to reach 95% of

final value,

V_IN= 1.8 V, C_OUT= 0.1 µF

SWB1_2

Measured from enable going high to reach 95% of

final value,

V_IN= 3.3 V, C_OUT= 0.1 µF

1.1

ms

t_TURN-

ON

Turnon time

Measured from enable going high to reach 95% of

final value,

0.82

V_IN= 1.8 V, C_OUT= 0.1 µF

16

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4.16 Typical Characteristics

Measurements done at 25°C.

图 4-1. BUCK2 Controller Start Up to 1 V by I²C

图 4-2. Converter Start Up to 1 V by I²C

100%

95%

90%

85%

80%

75%

70%

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

65%

Vout = 1 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

Vout = 1 V

60%

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

55%

50%

0.1

0.2 0.3 0.40.5 0.7

1

2

3

4

5 6 7

0.1

0.2 0.3 0.40.5 0.7

1

2

3

4 5 6 7

Iout (A)

D011

D012

图 4-3. BUCK6 Efficiency at V_IN= 13 V

图 4-4. BUCK6 Efficiency at V_IN= 18 V

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

Vout = 1 V

Vout = 1.8 V

Vout = 2.5 V

Vout = 3.3 V

50%

0.1

0.2

0.3 0.4 0.5 0.7

Iout (A)

1

2

3

D009

图 4-5. Converter Efficiency at V_IN= 5 V

Specifications

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5 Detailed Description

5.1 Overview

The TPS6508700 power-management integrated circuit (PMIC) provides all the required power supplies

for the AMD Family 17h Models 10h-1Fh Processors. The PMIC has the following integrated components:

three step-down controllers (BUCK1, BUCK2, and BUCK6), three step-down converters (BUCK3, BUCK4,

and BUCK5), a sink or source LDO (VTT LDO), three low-voltage V_INLDOs (LDOA1–LDOA3), and three

load switches (SWA1, SWB1, and SWB2). With on-chip, one-time programmable (OTP) memory,

configuration of each rail for the default output value, power-up sequence, fault handling, and power good

mapping into a GPO pin are all conveniently flexible. All voltage rails (VRs) have a built-in discharge

resistor, and the value can be changed using the DISCHCNT1–DISCHCNT3 and LDOA1_CTRL registers.

When enabling a VR, the PMIC automatically disconnects the discharge resistor for that rail without any

I²C command. 表 5-1 lists the key characteristics of the voltage rails.

表 5-1. Summary of Voltage Regulators

INPUT VOLTAGE (V)

OUTPUT VOLTAGE RANGE (V)

CURRENT

(mA)

RAIL

BUCK1

TYPE

MIN

MAX

MIN

TYP

MAX

5 V by external

feedback

Step-down controller

4.5

21

Scalable

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

LDOA1

LDOA2

LDOA3

SWA1

Step-down controller

Step-down converter

Step-down controller

LDO

4.5

1.62

0.5

21

5.5

21

0.41

0.425

1

0.8

1.8

0.8

1.8

3.3

1.5

1.2

1.5

1.67

3.575

3.3

Scalable

3000

Scalable

200⁽¹⁾

600

5.5

1.98

3.3

1.35

0.7

LDO

1.5

LDO

0.7

1.5

600

Load switch

300

SWB1/SWB2

Load switch

300

Sink and Source

LDO

VTT

BUCK6 output

V_BUCK6/ 2

(1) When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, max current is limited by max I_OUTof LDO5.

18

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5.2 Functional Block Diagram

LDO5V

LDO1

VIN

BOOT1

DRVH1

LDOA1

1.35 œ 3.3 V

200 mA

CTL1

CTL2

SW1

V1

VSET

EN

BUCK1

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL1

CTL3/SLPENB1

Control

CTL4

EN

VSET

FBVOUT1

Inputs

PGNDSNS1

CTL5

ILIM1

CTL6/SLPENB2

VPULL

VIN

BOOT2

DRVH2

CLK

SoC

&

System

I²C CTL

SW2

DATA

V2

VSET

EN

BUCK2

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

DRVL2

Control

Outputs

FBVOUT2

PGNDSNS2

IRQB

GP01

GPO2

GPO3

GPO4

FBGND2

ILIM2

Internal

Interrupt

Events

3.3V œ 5V

PVIN3

LX3

TEST CTL

OTP

BUCK3

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VSET

EN

V3

FB3

<PGND_BUCK3>

REGISTERS

3 A

3.3V œ 5V

PVIN4

LX4

BUCK4

VSET 0.425 ꢀ 3.575 V

0.41 œ 1.67 V

LDO5P0

V5ANA

LDO5P0

Digital Core

V4

3.3V œ 5V

EN

FB4

(DVS)

3 A

<PGND_BUCK4>

3.3V œ 5V

PVIN5

LX5

BUCK5

œ

VSET

0.425 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

4.7V

+

V5

EN

FB5

STDBY

LDO5V

3 A

<PGND_BUCK5>

VIN

REFSYS

LDO3P3

BOOT6

DRVH6

Thermal

Monitoring

VSYS

5.6Vœ21V

LDO3P3

SW6

DRVL6

Thermal Shutdown

VDDQ

VSET

EN

BUCK6

1 ꢀ 3.575 V

0.41 œ 1.67 V

(DVS)

VREF

AGND

Bandgap

FBVOUT6

PGNDSNS6

ILIM6

PVIN_VTT

VTT

VTT_LDO

VDDQ/2

EN

VTTFB

LDOA2

0.7 ꢀ 1.5 V

600 mA

LDOA3

0.7 ꢀ 1.5 V

600 mA

LOAD SWA1

LOAD SWB1

LOAD SWB2

图 5-1. PMIC Functional Block Diagram

Detailed Description

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5.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with a programmable current limit

(set by an external resistor at ILIMx pin), which allows for optimal selection of external passive

components based on the desired system load. The buck converters include an integrated power stage

and require a minimum number of pins for power input, inductor, and output voltage feedback input.

Combined with high-frequency switching, all these features allow the use of inductors in a small form

factor, reducing total-system cost and size.

BUCK1–BUCK6 have selectable auto-PWM and forced-PWM mode through the BUCKx_MODE bit in the

BUCKxCTRL register. In default auto-PWM mode, the VR automatically switches between pulse width

modulation (PWM) and pulse frequency modulation (PFM) depending on the output load to maximize

efficiency.

All controllers and converters can be set to the default output voltage (V_OUT) or dynamically voltage

changing at any time. This feature means that the rails can be programmed for any V_OUTby the factory,

therefore the device starts up with the default voltage, or during operation the rail can be programmed to

another operating V_OUTwhile the rail is enable or disabled. Two step sizes, or ranges, are available for

V_OUTselection: 10-mV steps and 25-mV steps. The step-size range must be selected prior to use and

must be programmed by the factory. The step-size range is not subject to programming or change during

operation.

表 5-2 lists the options for the 10-mV step-size range V_OUT. 表 5-3 lists the options for the 25-mV step-size

range V_OUT

.

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表 5-2. 10-mV Step-Size V_OUTRange

VID BITS

0000000b

0000001b

0000010b

0000011b

0000100b

0000101b

0000110b

0000111b

0001000b

0001001b

0001010b

0001011b

0001100b

0001101b

0001110b

0001111b

0010000b

0010001b

0010010b

0010011b

0010100b

0010101b

0010110b

0010111b

0011000b

0011001b

0011010b

0011011b

0011100b

0011101b

0011110b

0011111b

0100000b

0100001b

0100010b

0100011b

0100100b

0100101b

0100110b

0100111b

0101000b

0101001b

0101010b

V_OUT

0

VID BITS

0101011b

0101100b

0101101b

0101110b

0101111b

0110000b

0110001b

0110010b

0110011b

0110100b

0110101b

0110110b

0110111b

0111000b

0111001b

0111010b

0111011b

0111100b

0111101b

0111110b

0111111b

1000000b

1000001b

1000010b

1000011b

1000100b

1000101b

1000110b

1000111b

1001000b

1001001b

1001010b

1001011b

1001100b

1001101b

1001110b

1001111b

1010000b

1010001b

1010010b

1010011b

1010100b

1010101b

V_OUT

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

1.11

1.12

1.13

1.14

1.15

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

1.24

1.25

VID BITS

1010110b

1010111b

1011000b

1011001b

1011010b

1011011b

1011100b

1011101b

1011110b

1011111b

1100000b

1100001b

1100010b

1100011b

1100100b

1100101b

1100110b

1100111b

1101000b

1101001b

1101010b

1101011b

1101100b

1101101b

1101110b

1101111b

1110000b

1110001b

1110010b

1110011b

1110100b

1110101b

1110110b

1110111b

1111000b

1111001b

1111010b

1111011b

1111100b

1111101b

1111110b

1111111b

—

V_OUT

1.26

1.27

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

1.38

1.39

1.40

1.41

1.42

1.43

1.44

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

1.56

1.57

1.58

1.59

1.60

1.61

1.62

1.63

1.64

1.65

1.66

1.67

—

0.41

0.42

0.43

0.44

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

Detailed Description

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表 5-3. 25-mV Step-Size V_OUTRange

V_OUT

(Converters)

V_OUT

VID BITS

V_OUT

VID BITS

V_OUT

(Controllers)

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

0000000b

0000001b

0000010b

0000011b

0000100b

0000101b

0000110b

0000111b

0001000b

0001001b

0001010b

0001011b

0001100b

0001101b

0001110b

0001111b

0010000b

0010001b

0010010b

0010011b

0010100b

0010101b

0010110b

0010111b

0011000b

0011001b

0011010b

0011011b

0011100b

0011101b

0011110b

0011111b

0100000b

0100001b

0100010b

0100011b

0100100b

0100101b

0100110b

0100111b

0101000b

0101001b

0101010b

0

0101011b

0101100b

0101101b

0101110b

0101111b

0110000b

0110001b

0110010b

0110011b

0110100b

0110101b

0110110b

0110111b

0111000b

0111001b

0111010b

0111011b

0111100b

0111101b

0111110b

0111111b

1000000b

1000001b

1000010b

1000011b

1000100b

1000101b

1000110b

1000111b

1001000b

1001001b

1001010b

1001011b

1001100b

1001101b

1001110b

1001111b

1010000b

1010001b

1010010b

1010011b

1010100b

1010101b

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

2.000

2.025

2.050

2.075

2.100

2.125

2.150

2.175

2.200

2.225

2.250

2.275

2.300

2.325

2.350

2.375

2.400

2.425

2.450

2.475

2.500

2.525

1010110b

1010111b

1011000b

1011001b

1011010b

1011011b

1011100b

1011101b

1011110b

1011111b

1100000b

1100001b

1100010b

1100011b

1100100b

1100101b

1100110b

1100111b

1101000b

1101001b

1101010b

1101011b

1101100b

1101101b

1101110b

1101111b

1110000b

1110001b

1110010b

1110011b

1110100b

1110101b

1110110b

1110111b

1111000b

1111001b

1111010b

1111011b

1111100b

1111101b

1111110b

1111111b

—

2.550

2.575

2.600

2.625

2.650

2.675

2.700

2.725

2.750

2.775

2.800

2.825

2.850

2.875

2.900

2.925

2.950

2.975

3.000

3.025

3.050

3.075

3.100

3.125

3.150

3.175

3.200

3.225

3.250

3.275

3.300

3.325

3.350

3.375

3.400

3.425

3.450

3.475

3.500

3.525

3.550

3.575

—

0.425

0.450

0.475

0.500

0.525

0.550

0.575

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

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5.3.1 Controller Overview

The controllers are fast-reacting, high-frequency, scalable output-power controllers capable of driving two

external N-MOSFETs. The controllers use the D-CAP2 control scheme that optimizes transient responses

at high load currents for such applications as CORE and DDR supplies. The output voltage is compared

with and internal reference voltage after divider resistors. The PWM comparator determines the timing to

turn on the high-side MOSFET. The PWM comparator response maintains a very small PWM output ripple

voltage. Because the device does not have a dedicated oscillator for the on-board control loop, the

switching cycle is controlled by the adaptive on-time circuit. The on-time is controlled to meet the target

switching frequency by feed-forwarding the input and output voltage into the on-time one-shot timer.

The D-CAP2 control scheme has an injected ripple from the SW node that is added on to the reference

voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP

mode control. Therefore, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be

used with the controllers. 图 5-2 shows the block diagram for the controller

VDD

V_REFœ V_{TH_PG}

+

UV

PGOOD

FAULT

EN

œ

PGOOD

+

DCHG

VFB

OV

V_REF+ V_{TH_PG}

œ

+

Control Logic

œ

+

PWM

Ramp Generator

REF

BOOTx

DRVHx

SWx

SS Ramp Comp

HS

VSYS

XCON

œ

OC

DRV5V_x_x

œ

50 µA

+

ILIM

LS

DRVLx

œ

NOC

+

PGNDSNSx

One-Shot

GND

+

ZC

œ

PMIC Internal Signals

External Inputs/Outputs

图 5-2. Controller Block Diagram

Detailed Description

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5.3.2 Converter Overview

The PMIC synchronous step-down DC-DC converters include a unique, hysteretic PWM-controller scheme

which enables a high switching-frequency converter, excellent transient and AC load regulation as well as

operation with cost-competitive external components. The controller topology supports forced PWM mode

as well as power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent

current consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In

forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows

filtering of the switch noise by external filter components. The PMIC device offers fixed output voltage

options featuring a small solution size by using only three external components per converter.

A significant advantage of a PMIC over other hysteretic PWM controller topologies is the excellent AC

load transient regulation capability of PMICs. When the output voltage falls below the threshold of the

error comparator, a switch pulse is initiated, and the high-side switch is turned on. The switch remains

turned on until a minimum on-time (t_ONmin) expires and the output voltage trips the threshold of the error

comparator, or until the inductor current reaches the current limit of the high-side switch. When the high-

side switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until

the high-side switch turns on again or the inductor current reaches zero. In forced PWM mode operation,

negative inductor current is allowed to enable continuous conduction mode even at no load condition.

PVINx

Current

Limit Comparator

VREF

0.40 V

Bandgap

High-Side

Limit

MODE or EN

MODE

Softstart

VIN

FB

Gate Driver

Anti

Shoot-Through

Control

Logic

Minimum ON Time

Minimum OFF Time

LXx

EN

VREF

+

FBx

œ

Error

Low-Side

Limit

Integrated

Feedback

Network

Comparator

Zero (Negative)

Current Limit Comparator

PGND/Thermal Pad

PMIC Internal Signals

External Inputs/Outputs

图 5-3. Converter Block Diagram

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5.3.3 Dynamic Voltage Scaling

The buck regulators (BUCK1 through BUCK6) support dynamic voltage scaling (DVS) for maximum

system efficiency. The VR outputs can slew up and slew down in either 10-mV or 25-mV steps using the

7-bit voltage ID (VID) defined in Section 4.7 and Section 4.8. The DVS slew rate is 2.5 mV/µs (minimum).

To meet the minimum slew rate, VID progresses to the next code at 3-µs (nominal) interval per 10-mV or

at 6-µs interval per 25-mV steps. When DVS is active, the VR is forced into PWM mode, unless the

BUCKx_DECAY bit is 1b, to ensure the output keeps track of the VID code with minimal delay.

Additionally, the PGOOD bits (in the PG_STATUS1 and PG_STATUS2 registers) are masked when DVS

is in progress. 图 5-4 shows an example of slew down and slew up from one VID to another (step size of

10 mV).

VID

Number of Steps × 3 µs

V_OUT

图 5-4. DVS Timing Diagram I (BUCKx_DECAY = 0b)

When DVS is enabled and the BUCKx_VID[6:0] bit is set to any setting except 0b or 1b, the slew rate of

the voltage is as shown in 图 5-4.

As shown in 图 5-5, if a BUCKx_VID[6:0] bit is set to 0000000b, the output voltage of that buck slews

down to 0.5 V first, and then drifts down to 0 V as the SMPS stops switching. Subsequently, if a

BUCKx_VID[6:0] bit is set to a value (neither 0000000b nor 0000001b) when the output voltage of that

buck is less than 0.5 V, the VR ramps up to 0.5 V first and the soft-start time begins. The output voltage

then slews up to the target voltage of the previously mentioned slew rate.

注

A fixed 200 µs of soft-start time is reserved for the output voltage to reach 0.5 V. In this case,

however, the SMPS is not forced into PWM mode as it otherwise could cause the output

voltage to droop momentarily if the output voltage might have been drifting above 0.5 V for

any reason.

VID

Number of

Steps × 3 µs

V_OUT

Load and Time

Dependent

200 µs

图 5-5. DVS Timing Diagram II (BUCKx_DECAY = 0b)

Detailed Description

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5.3.4 Current Limit

The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the

current limit is programmable by an external resistor at the ILIMx pin. 公式 1 shows the calculation for a

desired resistor value, depending on specific application conditions. The I_LIMREFcurrent is the current

source out of the ILIMx pin that is typically 50 µA, and R_DSONis the maximum channel resistance of the

low-side FET. The scaling factor is 1.3 to consider all errors and temperature variations of R_DSON, I_LIMREF

,

and R_ILIM. Finally, 8 is another scaling factor associated with the I_LIMREFcurrent.

I_ripple(min)

≈

’

÷

◊

R_DSONì 8 ì 1.3 ì I

-

∆

LIM

2

«

R_ILIM

=

I_LIMREF

where

•

I_LIMis the target current limit. An appropriate margin must be allowed when determining the value of I_LIM

from the maximum DC load current of the output.

•

I_ripple(min)is the minimum peak-to-peak inductor ripple current for a given output voltage.

(1)

V_OUT(V

- V_OUT)

IN(MIN)

I_ripple(min)

=

L_maxì V

ì f_sw(max)

IN(MIN)

where

•

L_maxis the maximum inductance.

f_sw(max)is the maximum switching frequency.

V_IN(MIN)is the minimum input voltage to the external power stage.

(2)

The inductor of the buck converter limits the peak current. This current limiting is done on a cycle-by-cycle

basis to the current limit (I_{IND_LIM}), which is specified in Section 4.8.

5.4 LDO Regulators and Load Switches

5.4.1 VTT LDO

Powered from the BUCK6 output, the VTT LDO tracks the V_BUCK6voltage by regulating its output to a half

of its input. The LDO current limit is OTP dependent, and it is designed specifically to power DDR

memory. The LDO core is a transconductance amplifier with large gain, and it drives a current output

stage that either sources or sinks current depending on the deviation of VTTFB pin voltage from the target

regulation voltage.

5.4.2 LDOA1–LDOA3

The TPS6508700 device integrates three general-purpose LDOs. LDOA1 is powered from a 5-V supply

through the DRV5V_2_A1 pin and it can be factory configured as an always-on rail as long as a valid

power supply is available at the VSYS pin. For LDOA1 output voltage options, see 表 5-4. LDOA2 and

LDOA3 share a power input pin (PVINLDOA2_A3). The output regulation voltages are set by writing to the

LDOAx_VID[3:0] bits (registers 0x9A, 0x9B, and 0xAE). For LDOA2 and LDOA3 output voltage options,

See 表 5-5.

表 5-4. LDOA1 Output Voltage Options

VID Bits

0000b

0001b

0010b

0011b

V_OUT

1.35

1.5

VID Bits

0100b

0101b

0110b

0111b

V_OUT

1.8

VID Bits

1000b

1001b

1010b

1011b

V_OUT

2.3

VID Bits

1100b

1101b

1110b

1111b

V_OUT

2.85

1.9

2.4

3.0

1.6

2.0

2.5

3.3

1.7

2.1

2.6

Not Used

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表 5-5. LDOA2 and LDOA3 Output Voltage Options

VID Bits

0000b

0001b

0010b

0011b

V_OUT

0.70

0.75

0.80

0.85

VID Bits

0100b

0101b

0110b

0111b

V_OUT

0.90

0.95

1.00

1.05

VID Bits

1000b

1001b

1010b

1011b

V_OUT

1.10

1.15

1.20

1.25

VID Bits

V_OUT

1.30

1.35

1.40

1.50

1100b

1101b

1110b

1111b

5.4.3 Load Switches

The PMIC features three general-purpose load switches. The SWA1 switch has a dedicated power input

pin (PVINSWA1). The SWB1 and SWB2 pins share one power input pin (PVINSWB1_B2). All switches

have built-in slew-rate control during startup to limit the inrush current.

5.5 Power Good Information (PGOOD or PG) and GPO Pins

The device provides information on status of VRs through four GPO pins along with the power-good status

registers defined in Section 5.9.47 and Section 5.9.48. Power good information of any individual VR and

load switch can be assigned to be part of the PGOOD tree as defined from Section 5.9.37 to

Section 5.9.44. PGOOD assertion delays are programmable from 0 ms to 15 ms for GPO1, 0 ms to 100

ms for GPO2 and GPO4, and 2.5 ms to 100 ms for GPO3 as defined in Section 5.9.19 and Section 5.9.31

(respectively).

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BUCK1_PG

BUCK1_PG_MASK

BUCK2_PG

BUCK2_PG_MASK

BUCK3_PG

BUCK3_PG_MASK

BUCK4_PG

BUCK4_PG_MASK

BUCK5_PG

BUCK5_PG_MASK

BUCK6_PG

BUCK6_PG_MASK

SWA1_PG

SWA1_PG_MASK

LDOA2_PG

LDOA2_PG_MASK

Selectable MS

Rising

LDOA3_PG

SYSTEM PG

LDOA3_PG_MASK

Edge

Delay

SWB1_PG

SWB1_PG_MASK

SWB2/LDOA1_PG

SWB2/LDOA1_PG_MASK

VTT_PG

VTT_PG_MASK

CTRL1

CTRL1_MASK

CTRL2

CTRL2_MASK

CTRL3/SLPENB1

CTRL3_MASK

CTRL4

CTRL4_MASK

CTRL5

CTRL5_MASK

CTRL6/SLPENB2

CTRL6_MASK

图 5-6. Power Good Tree

Alternatively, the GPOs can be used as general-purpose outputs controlled by the user through I²C. For

more information on controlling the GPOs in I²C control mode, see Section 5.9.34.

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5.6 Power Sequencing and Voltage-Rail Control

When a valid power source is available at the VSYS pin (VSYS ≥ 5.6 V), the internal analog blocks,

including LDO5 and LDO3P3, are enabled. The device then has three ways of sequencing the rails during

power up and power down:

•

Rail enabled by CTLx pin

Rail enabled by power good, (PG) of the previously enabled rail

Rail enabled by I²C software command

5.6.1 Power-Up and Power-Down Sequencing

The power-up and power-down sequence uses the CTL1, CTL4, and CTL5 pins to enable and disable

regulators as required by the system. 图 5-7 shows the sequencing of these enables in a typical power-up

and power-down sequence.

Detailed Description

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–

G3'

G3

S5

S0

S5

G3

VSYS

5.6 V

LDO5

LDO3P3

LDOA1

I²C Available

CTL4

(GPIO_G3 OR

EN_S5)

BUCK1

(VDD_5_S5)

2 ms

BUCK3

(VDD_18_S5)

CTL1

(GPIO_G3 AND

EN_S5)

BUCK6

(VDD33_S5)

BUCK5

(VDD_AUD_S5)

BUCK4

(VDDP_S5)

5 ms

GPO1

(PG_S5)

CTL5

(EN_S0)

BUCK2

(VDDP)

5 ms

GPO2

(PG_S0)

(1) CTLx are control signals from the discrete digital from the processor to enable the rails.

(2) The power fault is masked for 10 ms when the regulator is enabled.

图 5-7. Power-Up and Power-Down Sequence

表 5-6 lists the system power states.

表 5-6. System Power States

STATE

G3’

GPIO_G3

EN_S5

CTL4

CTL5

1

0

1

0

1

0

1

0

1

G3’

G3 state

S5 state

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5.6.2 Emergency Shutdown

图 5-8 shows the emergency shutdown sequence.

5.4 V

VSYS

GPOx

444 ns (nominal with ± 1 œ % variation)

BUCKx

LDOAx

SWx

VTT

图 5-8. Emergency Shutdown Sequence

When the V_SYSvoltage crosses below V_{SYS_UVLO_5V}, all power good pins are deasserted, and after 444 ns

(nominal) of delay, all VRs shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to

ensure timely decay of all VR outputs. Other conditions that cause emergency shutdown are the die

temperature rising above the critical temperature threshold (T_CRIT), and deassertion of the power good of

any rail (configurable).

5.7 Device Functional Modes

5.7.1 Off Mode

When the power supply at the VSYS pin is less than V_{SYS_UVLO_5V}(5.4-V nominal) + V_{SYS_UVLO_5V_HYS}(0.2-

V nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater

than V_{SYS_UVLO_3V}(3.6-V nominal) + V_{SYS_UVLO_3V_HYS}(0.15-V nominal) while the supply voltage is still less

than V_{SYS_UVLO_5V}+ V_{SYS_UVLO_5V_HYS}, then the internal band-gap reference (VREF pin) along with

LDO3P3 are enabled and regulated at target values.

5.7.2 Standby Mode

When the power supply at the VSYS pin rises above V_{SYS_UVLO_5V}+ V_{SYS_UVLO_5V_HYS}, the device enters

standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are up and running, and

I²C interface and CTL pins are ready to respond. All default registers defined in Section 5.9.1 should have

been loaded from one-time programmable (OTP) memory by now. Quiescent current consumption in

standby mode is specified in Section 4.5.

5.7.3 Active Mode

The device proceeds to active mode when any output rail is enabled through an input pin as discussed in

节 5.6 or by writing to EN bits through I²C. The output regulation voltage can also be changed by writing to

the VID bits defined in Section 5.9.1.

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5.8 I²C Interface

The I²C interface is a 2-wire serial interface. The bus consists of a data line (SDA) and a clock line (SCL)

with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C

compatible devices connect to the I²C bus through open drain I/O pins, DATA, and CLK. A master device,

usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for

generating the SCL signal and device addresses. The master also generates specific conditions that

indicate the START and STOP of data transfer. A slave device receives data, transmits data, or both on

the bus under control of the master device.

The TPS6508700 device works as a slave and supports the following data transfer modes, as defined in

the I²C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode

(1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents

are loaded when the V_SYSvoltage is higher than V_{SYS_UVLO_5V}and is applied to the TPS6508700 device.

The I²C interface is running from an internal oscillator that is automatically enabled when access to the

interface is avaialble.

The data transfer protocol for fast and standard modes are exactly the same, therefore, they are referred

to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it

is referred to as H/S-mode.

The TPS6508700 device supports 7-bit addressing; however, 10-bit addressing and a general call address

are not supported. The default device address is 0x5E.

5.8.1 F/S-Mode Protocol

The master initiates a data transfer by generating a start condition. The start condition is a high-to-low

transition that occurs on the SDA line while SCL is high (see 图 5-9). All I²C-compatible devices should

recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read-write direction

bit, R/W, on the SDA line. During all transmissions, the master ensures that data is valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse (see

图 5-10). All devices recognize the address sent by the master and compare it to their internal fixed

addresses. Only the slave device with a matching address generates an acknowledge (see 图 5-11) by

pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this

acknowledge, the master identifies that the communication link with a slave has been established.

The master generates additional SCL cycles to either transmit data to the slave (R/W bit is 0b) or receive

data from the slave (R/W bit is 1b). In either case, the receiver must acknowledge the data sent by the

transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on

which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge

can continue as long as required.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from

low to high while the SCL line is high (see 图 5-9). This process releases the bus and stops the

communication link with the addressed slave. All I²C-compatible devices must recognize the stop

condition. Upon receiving a stop condition, all devices identify that the bus is released, and wait for a start

condition followed by a matching address.

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SDA

SCL

S

P

START

STOP

Condition

图 5-9. START and STOP Conditions

SDA

SCL

Data Valid

Change of Data Allowed

图 5-10. Bit Transfer on the I²C Bus

Data Output at

Transmitter

Not ACK

Data Output at

Receiver

ACK

SCL from Master

1

2

8

9

S

START

Clock pulse for ACK

Condition

图 5-11. Acknowledge on the I²C Bus

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Generate ACK Signal

ACK Signal From Slave

SDA

MSB

Address

R/W

7

SCL

1

2

8

9

1

2

3-8

9

ACK

Byte Complete, Interrupt

Within Slave

Clock Line Held Low While

Interrupts Are Serviced

S or Sr

P or Sr

START or

STOP or

Repeated START Condition

图 5-12. I²C Bus Protocol

SCL

SDA

A6

A5

A4

A0 R /W ACK

R7

R6

R5

R0 ACK

0

D7

D6

D5

D0 ACK

0

START

Slave Address

Register Address

Data

STOP

图 5-13. I²C Interface WRITE to TPS6508700 in F/S Mode

SCL

SDA

W

R/

A6

A0

ACK

0

R7

R0 ACK

0

A6

A0

ACK D7

0

D0 ACK

0

W

R/

0

1

Master

Drives ACK

and Stop

Slave Drives

the Data

Slave Address

START

Slave Address

Register Address

STOP

Repeated

START

图 5-14. I²C Interface READ From TPS6508700 in F/S Mode

(Only Repeated START is Supported)

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5.9 Register Maps

5.9.1 Register Map Summary

Table 5-7 lists the memory-mapped registers for the TPS6508700. All register offset addresses not listed

in Table 5-7 should be considered as reserved locations and the register contents should not be modified.

Table 5-7. Register Map Summary

Offset

1h

Acronym

DEVICEID

Short Description

Device ID code indicating revision

Section

Go

2h

IRQ

Interrupt statuses

3h

IRQ_MASK

Interrupt masking

4h

PMICSTAT

PMIC temperature indicator

Shutdown root cause indicator bits

BUCK2 decay control and voltage select

BUCK3 decay control

5h

SHUTDNSRC

BUCK2CTRL

BUCK3DECAY

BUCK3VID

21h

22h

23h

24h

25h

26h

27h

28h

29h

40h

41h

42h

BUCK3 voltage select

BUCK3SLPCTRL

BUCK4CTRL

BUCK5CTRL

BUCK6CTRL

LDOA2CTRL

LDOA3CTRL

DISCHCTRL1

DISCHCTRL2

DISCHCTRL3

BUCK3 voltage select for SLEEP state

BUCK4 control

BUCK5 control

BUCK6 control

LDOA2 control

LDOA3 control

Discharge resistors for each rail control

System Power Good on GPO3 (if GPO3 is programmed to be system

PG)

43h

PG_DELAY1

Go

91h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

FORCESHUTDN

BUCK2SLPCTRL

BUCK4VID

Software force shutdown

Go

BUCK2 voltage select for SLEEP state

BUCK4 voltage select

BUCK4SLPVID

BUCK5VID

BUCK4 voltage select for SLEEP state

BUCK5 voltage select

BUCK5SLPVID

BUCK6VID

BUCK5 voltage select for SLEEP state

BUCK6 voltage select

BUCK6SLPVID

LDOA2VID

BUCK6 voltage select for SLEEP state

LDOA2 voltage select

LDOA3VID

LDOA3 voltage select

BUCK123CTRL

BUCK1, 2, and 3 disable and PFM/PWM mode control

System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be

system PG)

9Dh

PG_DELAY2

Go

9Fh

A0h

A1h

A2h

A3h

A4h

A5h

A6h

A7h

A8h

SWVTT_DIS

SWs and VTT I²C disable bits

I²C enable control of individual rails

Go

I2C_RAIL_EN1

I2C_RAIL_EN2/GPOCTRL I²C enable control of individual rails and I²C controlled GPOs, high or low

PWR_FAULT_MASK1

PWR_FAULT_MASK2

GPO1PG_CTRL1

GPO1PG_CTRL2

GPO4PG_CTRL1

GPO4PG_CTRL2

GPO2PG_CTRL1

Power fault masking for individual rails

Power good tree control for GPO1

Power good tree control for GPO4

Power good tree control for GPO2

Detailed Description

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Table 5-7. Register Map Summary (continued)

Offset

Acronym

Short Description

Section

Go

A9h

AAh

ABh

ACh

AEh

B0h

B1h

B2h

B3h

B4h

B5h

B6h

GPO2PG_CTRL2

GPO3PG_CTRL1

GPO3PG_CTRL2

MISCSYSPG

Power good tree control for GPO2

Power good tree control for GPO3

Go

Power good tree control for GPO3

Go

Power Good tree control with CTL3 and CTL6 for GPO

LDOA1 control for discharge, voltage selection, and enable

Power Good statuses for individual rails

Power fault statuses for individual rails

Critical temperature indicators

Go

LDOA1CTRL

Go

PG_STATUS1

Go

PG_STATUS2

Go

PWR_FAULT_STATUS1

PWR_FAULT_STATUS2

TEMPCRIT

Go

TEMPHOT

Hot temperature indicators

Go

OC_STATUS

Overcurrent fault status

Go

Complex bit access types are encoded to fit into small table cells. Table 5-8 shows the codes that are

used for access types in this section.

Table 5-8. Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-nh

Value after reset or the default

value

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5.9.2 DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]

DEVICEID is shown in Figure 5-15 and described in Table 5-9.

Return to Summary Table.

Figure 5-15. DEVICEID Register

7

6

5

4

3

2

1

0

REVID[1:0]

R-0h

OTP_VERSION[1:0]

R-1h

PART_NUMBER[3:0]

R-0h

Table 5-9. DEVICEID Field Descriptions

Bit

Field

Type

Reset

Description

7-6

REVID[1:0]

R

0h

Silicon revision ID

5-4

OTP_VERSION[1:0]

R

1h

OTP variation ID

0h = A

1h = B

2h = C

3h = D

3-0

PART_NUMBER[3:0]

R

0h

Device part number ID

0h = TPS6508700

1h = TPS6508701

Fh = TPS650870F

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5.9.3 IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]

IRQ is shown in Figure 5-16 and described in Table 5-10.

Return to Summary Table.

Figure 5-16. IRQ Register

7

6

5

4

3

2

1

0

FAULT

R/W-0h

RESERVED

R-0h

SHUTDN

R/W-0h

RESERVED

R-0h

DIETEMP

R/W-0h

Table 5-10. IRQ Field Descriptions

Bit

Field

Type

Reset

Description

7

FAULT

R/W

0h

Fault interrupt. Asserted when either condition occurs: SYS <

UVLO, power fault of any rail, or die temperature crosses over

the critical temperature threshold (T_CRIT). The user can read

registers 0xB2 through 0xB6 to determine what has caused the

interrupt.

0h = Not asserted

1h = Asserted. Host to write 1 to clear.

6-4

3

RESERVED

SHUTDN

R

0h

R/W

Asserted when PMIC shuts down. To clear indicator,

SHUTDNSRC must be cleared first, see Section 5.9.6

0h = Not asserted.

1h = Asserted. Host to write 1 to clear.

2-1

0

RESERVED

DIETEMP

R

0h

R/W

Die temp interrupt. Asserted when PMIC die temperature

crosses above the hot temperature threshold (T_HOT).

0h = Not asserted.

1h = Asserted. Host to write 1 to clear.

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5.9.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]

IRQ_MASK is shown in Figure 5-17 and described in Table 5-11.

Return to Summary Table.

Figure 5-17. IRQ_MASK Register

7

6

5

4

3

2

1

0

MFAULT

R/W-1h

RESERVED

R-7h

MSHUTDN

R/W-1h

RESERVED

R-3h

MDIETEMP

R/W-1h

Table 5-11. IRQ_MASK Field Descriptions

Bit

Field

Type

Reset

Description

7

MFAULT

R/W

1h

FAULT interrupt mask.

0h = Not masked.

1h = Masked.

6-4

3

RESERVED

MSHUTDN

R

7h

1h

R/W

PMIC shutdown event interrupt mask

0h = Not masked.

1h = Masked.

2-1

0

RESERVED

MDIETEMP

R

3h

1h

R/W

Die temp interrupt mask.

0h = Not masked.

1h = Masked.

5.9.5 PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]

PMICSTAT is shown in Figure 5-18 and described in Table 5-12.

Return to Summary Table.

Figure 5-18. PMICSTAT Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

SDIETEMP

R-0h

Table 5-12. PMICSTAT Field Descriptions

Bit

7-1

0

Field

Type

R

Reset

0h

Description

RESERVED

SDIETEMP

R

0h

PMIC die temperature status.

0h = PMIC die temperature is below T_HOT

.

1h = PMIC die temperature is above T_HOT

.

Detailed Description

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5.9.6 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]

SHUTDNSRC is shown in Figure 5-19 and described in Table 5-13.

Return to Summary Table.

Figure 5-19. SHUTDNSRC Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

COLDOFF

R/W-0h

UVLO

R/W-0h

PWRFLT

R/W-0h

CRITTEMP

R/W-0h

Table 5-13. SHUTDNSRC Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

COLDOFF

R/W

0h

Set by PMIC cleared by host. Host to write 1 to clear. This bit is

always 0h for TPS6508700.

0h = Cleared

1h = PMIC was shut down by pulling down CTL1 pin.

2

1

0

UVLO

R/W

0h

Set by PMIC cleared by host. Host to write 1 to clear.

0h = Cleared

1h = PMIC was shut down due to a UVLO event (V_SYScrosses

below 5.4 V). Assertion of this bit sets the SHUTDN bit in

Section 5.9.3.

PWRFLT

CRITTEMP

Set by PMIC cleared by host. Host to write 1 to clear.

0h = Cleared

1h = PMIC was shut down due to a power fault on a rail with

power fault not masked. Assertion of this bit sets the SHUTDN

bit in Section 5.9.3.

Set by PMIC cleared by host. Host to write 1 to clear.

0h = Cleared

1h = PMIC was shut down due to the rise of PMIC die

temperature above critical temperature threshold (T_CRIT).

Assertion of this bit sets the SHUTDN bit in Section 5.9.3.

40

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5.9.7 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]

BUCK2CTRL is shown in Figure 5-20 and described in Table 5-14.

Return to Summary Table.

Figure 5-20. BUCK2CTRL Register

7

6

5

4

3

2

1

0

BUCK2_VID[6:0]

BUCK2_DECA

Y

R/W-28h

R/W-0h

Table 5-14. BUCK2CTRL Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK2_VID[6:0]

R/W

28h

This field sets the BUCK2 regulator output regulation voltage in

normal mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK2_DECAY

R/W

0h

Decay bit

0h = The output slews down to a lower voltage set by the VID

bits.

1h = The output decays down to a lower voltage set by the VID

bits. Decay rate depends on total capacitance and load present

at the output.

5.9.8 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]

BUCK3DECAY is shown in Figure 5-21 and described in Table 5-15.

Return to Summary Table.

Figure 5-21. BUCK3DECAY Register

7

6

5

4

3

2

1

0

RESERVED

BUCK3_DECA

Y

R/W-38h

R/W-0h

Table 5-15. BUCK3DECAY Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

38h

Reserved bits are don't care bits, can be 1h or 0h.

Decay bit

0

BUCK3_DECAY

R/W

0h

0h = The output slews down to a lower voltage set by the VID

bits.

1h = The output decays down to a lower voltage set by the VID

bits. Decay rate depends on total capacitance and load present

at the output.

Detailed Description

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5.9.9 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]

BUCK3VID is shown in Figure 5-22 and described in Table 5-16.

Return to Summary Table.

Figure 5-22. BUCK3VID Register

7

6

5

4

3

2

1

0

BUCK3_VID[6:0]

R/W-38h

RESERVED

R/W-0h

Table 5-16. BUCK3VID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK3_VID[6:0]

R/W

38h

This field sets the BUCK3 regulator output regulation voltage in

normal mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

RESERVED

R/W

0h

5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]

BUCK3SLPCTRL is shown in Figure 5-23 and described in Table 5-17.

Return to Summary Table.

Figure 5-23. BUCK3SLPCTRL Register

7

6

5

4

3

2

1

0

BUCK3_SLP_VID[6:0]

BUCK3_SLP_E

N

R/W-38h

R/W-0h

Table 5-17. BUCK3SLPCTRL Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK3_SLP_VID[6:0]

R/W

38h

This field sets the BUCK3 regulator output regulation voltage in

sleep mode. BUCK3_SLP_VID bits are copied to BUCK3_VID

bits upon enters sleep mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK3_SLP_EN

R/W

0h

BUCK3 sleep mode enable. BUCK3 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

42

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5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]

BUCK4CTRL is shown in Figure 5-24 and described in Table 5-18.

Return to Summary Table.

Figure 5-24. BUCK4CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

BUCK4_SLP_EN[1:0]

R/W-0h

RESERVED

R/W-3h

BUCK4_MODE

R/W-0h

BUCK4_DIS

R/W-1h

Table 5-18. BUCK4CTRL Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Description

RESERVED

BUCK4_SLP_EN[1:0]

R/W

0h

BUCK4 sleep mode enable. BUCK4 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.

3-2

1

RESERVED

R/W

3h

0h

Reserved as 3h. 0h, 1h, and 2h will result in BUCK4 regulation

ignoring BUCK4_VID and BUCK4_SLP_VID values.

BUCK4_MODE

This field sets the BUCK4 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode

0

BUCK4_DIS

R/W

1h

BUCK4 disable bit. Writing 0 to this bit forces BUCK4 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

Detailed Description

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5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]

BUCK5CTRL is shown in Figure 5-25 and described in Table 5-19.

Return to Summary Table.

Figure 5-25. BUCK5CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

BUCK5_SLP_EN[1:0]

R/W-0h

RESERVED

R/W-3h

BUCK5_MODE

R/W-0h

BUCK5_DIS

R/W-1h

Table 5-19. BUCK5CTRL Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Description

RESERVED

BUCK5_SLP_EN[1:0]

R/W

0h

BUCK5 sleep mode enable. BUCK5 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.

3-2

1

RESERVED

R/W

3h

0h

Reserved as 3h. 0h, 1h, and 2h will result in BUCK5 regulation

ignoring BUCK5_VID and BUCK5_SLP_VID values.

BUCK5_MODE

This field sets the BUCK5 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode

0

BUCK5_DIS

R/W

1h

BUCK5 disable bit. Writing 0 to this bit forces BUCK5 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

44

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5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]

BUCK6CTRL is shown in Figure 5-26 and described in Table 5-20.

Return to Summary Table.

Figure 5-26. BUCK6CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

BUCK6_SLP_EN[1:0]

R/W-0h

RESERVED

R/W-3h

BUCK6_MODE

R/W-0h

BUCK6_DIS

R/W-1h

Table 5-20. BUCK6CTRL Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Description

RESERVED

BUCK6_SLP_EN[1:0]

R/W

0h

BUCK6 sleep mode enable. BUCK6 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.

3-2

1

RESERVED

R/W

3h

0h

Reserved as 3h. 0h, 1h, and 2h will result in BUCK6 regulation

ignoring BUCK6_VID and BUCK6_SLP_VID values.

BUCK6_MODE

This field sets the BUCK6 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode

0

BUCK6_DIS

R/W

1h

BUCK6 disable bit. Writing 0 to this bit forces BUCK6 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

Detailed Description

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5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]

LDOA2CTRL is shown in Figure 5-27 and described in Table 5-21.

Return to Summary Table.

Figure 5-27. LDOA2CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

LDOA2_SLP_EN[1:0]

R/W-0h

RESERVED

R/W-6h

LDOA2_DIS

R/W-0h

Table 5-21. LDOA2CTRL Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Description

RESERVED

LDOA2_SLP_EN[1:0]

R/W

0h

LDOA2 sleep mode enable. LDOA2 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.

3-1

0

RESERVED

LDOA2_DIS

R/W

6h

0h

Reserved as 3h. 0h, 1h, and 2h will result in LDOA2 regulation

ignoring LDOA2_VID and LDOA2_SLP_VID values.

LDOA2 disable bit. Writing 0 to this bit forces LDOA2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

46

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5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]

LDOA3CTRL is shown in Figure 5-28 and described in Table 5-22.

Return to Summary Table.

Figure 5-28. LDOA3CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

LDOA3_SLP_EN[1:0]

R/W-3h

RESERVED

R/W-6h

LDOA3_DIS

R/W-0h

Table 5-22. LDOA3CTRL Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Description

RESERVED

LDOA3_SLP_EN[1:0]

R/W

3h

LDOA3 sleep mode enable. LDOA3 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.

3-1

0

RESERVED

LDOA3_DIS

R/W

6h

0h

Reserved as 3h. 0h, 1h, and 2h will result in LDOA3 regulation

ignoring LDOA3_VID and LDOA3_SLP_VID values.

LDOA3 disable bit. Writing 0h to this bit forces LDOA3 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

Detailed Description

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5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]

DISCHCTRL1 is shown in Figure 5-29 and described in Table 5-23.

Return to Summary Table.

All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.

Figure 5-29. DISCHCTRL1 Register

7

6

5

4

3

2

1

0

BUCK4_DISCHG[1:0]

R/W-1h

BUCK3_DISCHG[1:0]

R/W-1h

BUCK2_DISCHG[1:0]

R/W-1h

BUCK1_DISCHG[1:0]

R/W-1h

Table 5-23. DISCHCTRL1 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

BUCK4_DISCHG[1:0]

R/W

1h

BUCK4 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

5-4

3-2

1-0

BUCK3_DISCHG[1:0]

BUCK2_DISCHG[1:0]

BUCK1_DISCHG[1:0]

R/W

1h

BUCK3 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

BUCK2 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

BUCK1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

48

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5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]

DISCHCTRL2 is shown in Figure 5-30 and described in Table 5-24.

Return to Summary Table.

All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.

Figure 5-30. DISCHCTRL2 Register

7

6

5

4

3

2

1

0

LDOA2_DISCHG[1:0]

R/W-1h

SWA1_DISCHG[1:0]

R/W-1h

BUCK6_DISCHG[1:0]

R/W-1h

BUCK5_DISCHG[1:0]

R/W-1h

Table 5-24. DISCHCTRL2 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

LDOA2_DISCHG[1:0]

R/W

1h

LDOA2 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

5-4

3-2

1-0

SWA1_DISCHG[1:0]

BUCK6_DISCHG[1:0]

BUCK5_DISCHG[1:0]

R/W

1h

SWA1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

BUCK6 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

BUCK5 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

Detailed Description

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5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]

DISCHCTRL3 is shown in Figure 5-31 and described in Table 5-25.

Return to Summary Table.

All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.

Figure 5-31. DISCHCTRL3 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

SWB2_DISCHG[1:0]

R/W-1h

SWB1_DISCHG[1:0]

R/W-1h

LDOA3_DISCHG[1:0]

R/W-1h

Table 5-25. DISCHCTRL3 Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Description

RESERVED

SWB2_DISCHG[1:0]

SWB1_DISCHG[1:0]

LDOA3_DISCHG[1:0]

R/W

1h

SWB2 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

3-2

1-0

R/W

1h

SWB1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

LDOA3 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

50

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5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]

PG_DELAY1 is shown in Figure 5-32 and described in Table 5-26.

Return to Summary Table.

Programmable power good delay for GPO3 pin, measured from the moment when all VRs assigned to

GPO3 pin reach their regulation range to power good assertion. This register is optional as the PMIC can

be programmed for system PG, level shifter or I²C controller GPO.

Figure 5-32. PG_DELAY1 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

GPO3_PG_DELAY[2:0]

R/W-0h

Table 5-26. PG_DELAY1 Field Descriptions

Bit

7-3

2-0

Field

Type

R

Reset

0h

Description

RESERVED

GPO3_PG_DELAY[2:0]

R/W

0h

Programmable delay power good or level shifter for GPO3 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation.

Register not used (GPO3 controlled by I²C)

0h = 2.5 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

4h = 20 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms

Detailed Description

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5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset

= 0h]

FORCESHUTDN is shown in Figure 5-33 and described in Table 5-27.

Return to Summary Table.

Figure 5-33. FORCESHUTDN Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

SDWN

R/W-0h

Table 5-27. FORCESHUTDN Field Descriptions

Bit

7-1

0

Field

Type

R

Reset

0h

Description

RESERVED

SDWN

R/W

0h

Forces reset of the PMIC and reset of all registers. The bit is

self-clearing.

0h = No action.

1h = PMIC is forced to shut down.

52

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5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]

BUCK2SLPCTRL is shown in Figure 5-34 and described in Table 5-28.

Return to Summary Table.

Figure 5-34. BUCK2SLPCTRL Register

7

6

5

4

3

2

1

0

BUCK2_SLP_VID[6:0]

BUCK2_SLP_E

N

R/W-28h

R/W-0h

Table 5-28. BUCK2SLPCTRL Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK2_SLP_VID[6:0]

R/W

28h

This field sets the BUCK2 regulator output regulation voltage in

sleep mode. Mapping between bits and output voltage is defined

as in Section 5.9.7.

0

BUCK2_SLP_EN

R/W

0h

BUCK2 sleep mode enable. BUCK2 is factory configured to

change to sleep mode voltage either by CTL3/SLPENB1 pin or

by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]

BUCK4VID is shown in Figure 5-35 and described in Table 5-29.

Return to Summary Table.

Figure 5-35. BUCK4VID Register

7

6

5

4

3

2

1

0

BUCK4_VID[6:0]

BUCK4_DECA

Y

R/W-10h

R/W-0h

Table 5-29. BUCK4VID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK4_VID[6:0]

R/W

10h

This field sets the BUCK4 regulator output regulation voltage in

normal mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK4_DECAY

R/W

0h

Decay bit

0h = The output slews down to a lower voltage set by the VID

bits.

1h = The output decays down to a lower voltage set by the VID

bits. Decay rate depends on total capacitance and load present

at the output.

Detailed Description

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5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]

BUCK4SLPVID is shown in Figure 5-36 and described in Table 5-30.

Return to Summary Table.

Figure 5-36. BUCK4SLPVID Register

7

6

5

4

3

2

1

0

BUCK4_SLP_VID[6:0]

R/W-10h

RESERVED

R-0h

Table 5-30. BUCK4SLPVID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK4_SLP_VID[6:0]

R/W

10h

This field sets the BUCK4 regulator output regulation voltage in

sleep mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

RESERVED

R

0h

5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]

BUCK5VID is shown in Figure 5-37 and described in Table 5-31.

Return to Summary Table.

Figure 5-37. BUCK5VID Register

7

6

5

4

3

2

1

0

BUCK5_VID[6:0]

BUCK5_DECA

Y

R/W-38h

R/W-0h

Table 5-31. BUCK5VID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK5_VID[6:0]

R/W

38h

This field sets the BUCK5 regulator output regulation voltage in

normal mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK5_DECAY

R/W

0h

Decay bit

0h = The output slews down to a lower voltage set by the VID

bits.

1h = The output decays down to a lower voltage set by the VID

bits. Decay rate depends on total capacitance and load present

at the output.

54

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5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]

BUCK5SLPVID is shown in Figure 5-38 and described in Table 5-32.

Return to Summary Table.

Figure 5-38. BUCK5SLPVID Register

7

6

5

4

3

2

1

0

BUCK5_SLP_VID[6:0]

R/W-74h

RESERVED

R-0h

Table 5-32. BUCK5SLPVID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK5_SLP_VID[6:0]

R/W

74h

This field sets the BUCK5 regulator output regulation voltage in

sleep mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

RESERVED

R

0h

5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]

BUCK6VID is shown in Figure 5-39 and described in Table 5-33.

Return to Summary Table.

Figure 5-39. BUCK6VID Register

7

6

5

4

3

2

1

0

BUCK6_VID[6:0]

BUCK6_DECA

Y

R/W-74h

R/W-0h

Table 5-33. BUCK6VID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK6_VID[6:0]

R/W

74h

This field sets the BUCK6 regulator output regulation voltage in

normal mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

BUCK6_DECAY

R/W

0h

Decay bit

0h = The output slews down to a lower voltage set by the VID

bits.

1h = The output decays down to a lower voltage set by the VID

bits. Decay rate depends on total capacitance and load present

at the output.

Detailed Description

55

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5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]

BUCK6SLPVID is shown in Figure 5-40 and described in Table 5-34.

Return to Summary Table.

Figure 5-40. BUCK6SLPVID Register

7

6

5

4

3

2

1

0

BUCK6_SLP_VID[6:0]

R/W-74h

RESERVED

R-0h

Table 5-34. BUCK6SLPVID Field Descriptions

Bit

Field

Type

Reset

Description

7-1

BUCK6_SLP_VID[6:0]

R/W

74h

This field sets the BUCK6 regulator output regulation voltage in

normal mode.

See 表 5-2 and 表 5-3 for 10-mV and 25-mV step ranges for

V_OUToptions.

0

RESERVED

R

0h

5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]

LDOA2VID is shown in Figure 5-41 and described in Table 5-35.

Return to Summary Table.

Figure 5-41. LDOA2VID Register

7

6

5

4

3

2

1

0

LDOA2_SLP_VID[3:0]

R/W-Fh

LDOA2_VID[3:0]

R/W-Fh

Table 5-35. LDOA2VID Field Descriptions

Bit

Field

Type

Reset

Description

7-4

LDOA2_SLP_VID[3:0]

R/W

Fh

This field sets the LDOA2 regulator output regulation voltage in

sleep mode.

See 表 5-5 for V_OUToptions.

3-0

LDOA2_VID[3:0]

R/W

Fh

This field sets the LDOA2 regulator output regulation voltage in

normal mode.

See 表 5-5 for V_OUToptions.

56

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5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]

LDOA3VID is shown in Figure 5-42 and described in Table 5-36.

Return to Summary Table.

Figure 5-42. LDOA3VID Register

7

6

5

4

3

2

1

0

LDOA3_SLP_VID[3:0]

R/W-Ah

LDOA3_VID[3:0]

R/W-Ah

Table 5-36. LDOA3VID Field Descriptions

Bit

Field

Type

Reset

Description

7-4

LDOA3_SLP_VID[3:0]

R/W

Ah

This field sets the LDOA3 regulator output regulation voltage in

sleep mode.

See 表 5-5 for V_OUToptions.

3-0

LDOA3_VID[3:0]

R/W

Ah

This field sets the LDOA3 regulator output regulation voltage in

normal mode.

See 表 5-5 for V_OUToptions.

Detailed Description

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5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]

BUCK123CTRL is shown in Figure 5-43 and described in Table 5-37.

Return to Summary Table.

Figure 5-43. BUCK123CTRL Register

7

6

5

4

3

2

1

0

SPARE

R/W-0h

BUCK3_MODE BUCK2_MODE BUCK1_MODE

R/W-0h R/W-0h R/W-0h

BUCK3_DIS

R/W-1h

BUCK2_DIS

R/W-1h

BUCK1_DIS

R/W-1h

Table 5-37. BUCK123CTRL Field Descriptions

Bit

Field

Type

Reset

Description

7-6

SPARE

R/W

0h

Spare bits.

5

4

3

2

BUCK3_MODE

BUCK2_MODE

BUCK1_MODE

BUCK3_DIS

R/W

0h

1h

This field sets the BUCK3 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode

This field sets the BUCK2 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode

This field sets the BUCK1 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode

BUCK3 disable bit. Writing 0 to this bit forces BUCK3 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

1

0

BUCK2_DIS

BUCK1_DIS

R/W

1h

BUCK2 disable bit. Writing 0 to this bit forces BUCK2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

BUCK1 disable bit. Writing 0 to this bit forces BUCK1 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

58

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5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]

PG_DELAY2 is shown in Figure 5-44 and described in Table 5-38.

Return to Summary Table.

Programmable Power Good delay for GPO1, GPO2, and GPO4 pins, measured from the moment when

all VRs assigned to respective GPO reach their regulation range to Power Good assertion. This is an

optional register as the PMIC can be programmed for system PG, level shifter or I²C controller GPO.

Figure 5-44. PG_DELAY2 Register

7

6

5

4

3

2

1

0

GPO2_PG_DELAY[2:0]

R/W-1h

GPO4_PG_DELAY[2:0]

R/W-0h

GPO1_PG_DELAY[1:0]

R/W-1h

Table 5-38. PG_DELAY2 Field Descriptions

Bit

Field

Type

Reset

Description

7-5

GPO2_PG_DELAY[2:0]

R/W

1h

Programmable delay power good or level shifter for GPO2 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation.

0h = 0 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

4h = 20 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms

4-2

GPO4_PG_DELAY[2:0]

R/W

0h

Programmable delay power good or level shifter for GPO4 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation

0h = 0 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

4h = 20 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms

1-0

GPO1_PG_DELAY[1:0]

R/W

1h

Programmable delay power good or level shifter for GPO1 pin.

Measured from the moment when all rails grouped to this pin

reach their regulation range. All values have ±10% variation

0h = 0 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

Detailed Description

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5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]

SWVTT_DIS is shown in Figure 5-45 and described in Table 5-39.

Return to Summary Table.

Figure 5-45. SWVTT_DIS Register

7

6

5

4

3

2

1

0

SWB2_DIS

R/W-0h

SWB1_DIS

R/W-0h

SWA1_DIS

R/W-0h

VTT_DIS

R/W-0h

RESERVED

R/W-0h

Table 5-39. SWVTT_DIS Field Descriptions

Bit

Field

Type

Reset

Description

7

SWB2_DIS

SWB1_DIS

SWA1_DIS

VTT_DIS

R/W

0h

SWB2 disable bit. Writing 0h to this bit forces SWB2 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

6

R/W

0h

SWB1 disable bit. Writing 0 to this bit forces SWB1 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

5

SWA1 disable bit. Writing 0 to this bit forces SWA1 to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

4

VTT Disable Bit. Writing 0 to this bit forces VTT to turn off

regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

3-0

Reserved

Reserved, Keep bit set to 0h at all times. Do not write to 1h.

60

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5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]

I2C_RAIL_EN1 is shown in Figure 5-46 and described in Table 5-40.

Return to Summary Table.

Figure 5-46. I2C_RAIL_EN1 Register

7

6

5

4

3

2

1

0

LDOA2_EN

R/W-1h

SWA1_EN

R/W-0h

BUCK6_EN

R/W-0h

BUCK5_EN

R/W-0h

BUCK4_EN

R/W-0h

BUCK3_EN

R/W-0h

BUCK2_EN

R/W-0h

BUCK1_EN

R/W-0h

Table 5-40. I2C_RAIL_EN1 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

LDOA2_EN

SWA1_EN

BUCK6_EN

BUCK5_EN

BUCK4_EN

BUCK3_EN

BUCK2_EN

BUCK1_EN

R/W

1h

LDOA2 I²C enable

0h = LDOA2 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = LDOA2 is forced on unless LDOA2_DIS = 0.

SWA1 I²C enable

R/W

0h

0h = SWA1 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = SWA1 is forced on unless SWA1_DIS = 0.

BUCK6 I²C enable

0h = BUCK6 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = BUCK6 is forced on unless BUCK6_DIS = 0.

BUCK5 I²C enable

0h = BUCK5 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = BUCK5 is forced on unless BUCK5_DIS = 0.

BUCK4 I²C enable

0h = BUCK4 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = BUCK4 is forced on unless BUCK4_DIS = 0.

BUCK3 I²C enable

0h = BUCK3 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = BUCK3 is forced on unless BUCK3_DIS = 0.

BUCK2 I²C enable

0h = BUCK2 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = BUCK2 is forced on unless BUCK2_DIS = 0.

BUCK1 I²C enable

0h = BUCK1 is enabled or disabled by one of the control input

pins or internal PG signal.

1h = BUCK1 is forced on unless BUCK1_DIS = 0.

Detailed Description

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5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register

(offset = A1h) [reset = 89h]

I2C_RAIL_EN2/GPOCTRL is shown in Figure 5-47 and described in Table 5-41.

Return to Summary Table.

Figure 5-47. I2C_RAIL_EN2/GPOCTRL Register

7

6

5

4

3

2

1

0

GPO4_LVL

R/W-1h

GPO3_LVL

R/W-0h

GPO2_LVL

R/W-0h

GPO1_LVL

R/W-0h

VTT_EN

R/W-1h

SWB2_EN

R/W-0h

SWB1_EN

R/W-0h

LDOA3_EN

R/W-1h

Table 5-41. I2C_RAIL_EN2/GPOCTRL Field Descriptions

Bit

Field

Type

Reset

Description

7

GPO4_LVL

GPO3_LVL

R/W

1h

The field is to set GPO4 pin output if the pin is factory-

configured as an open-drain general-purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.

6

R/W

0h

The field is to set GPO3 pin output if the pin is factory-

configured as either an open-drain or a push-pull general-

purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.

5

4

GPO2_LVL

GPO1_LVL

The field is to set GPO2 pin output if the pin is factory-

configured as either an open-drain or a push-pull general-

purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.

The field is to set GPO1 pin output if the pin is factory-

configured as either an open-drain or a push-pull general-

purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.

3

2

1

0

VTT_EN

R/W

1h

0h

1h

VTT LDO I²C enable

0h = VTT LDO is enabled or disabled by one of the control input

pins or internal PG signals.

1h = VTT LDO is forced on unless VTT_DIS = 0.

SWB2 I²C enable

SWB2_EN

SWB1_EN

LDOA3_EN

0h = SWB2 is enabled or disabled by one of the control input

pins or internal PG signals.

1h = SWB2 is forced on unless SWB2_DIS = 0.

SWB1 I²C enable

0h = SWB1 is enabled or disabled by one of the control input

pins or internal PG signals.

1h = SWB1 is forced on unless SWB1_DIS = 0.

LDOA3 I²C enable

0h = LDOA3 is enabled or disabled by one of the control input

pins or internal PG signals.

1h = LDOA3 is forced on unless LDOA3_DIS = 0.

62

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5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]

PWR_FAULT_MASK1 is shown in Figure 5-48 and described in Table 5-42.

Return to Summary Table.

Figure 5-48. PWR_FAULT_MASK1 Register

7

6

5

4

3

2

1

0

LDOA2_FLTMS SWA1_FLTMS BUCK6_FLTM BUCK5_FLTM BUCK4_FLTM BUCK3_FLTM BUCK2_FLTM BUCK1_FLTM

K

SK

R/W-1h

R/W-0h

Table 5-42. PWR_FAULT_MASK1 Field Descriptions

Bit

Field

Type

Reset

Description

7

LDOA2_FLTMSK

SWA1_FLTMSK

BUCK6_FLTMSK

BUCK5_FLTMSK

BUCK4_FLTMSK

BUCK3_FLTMSK

BUCK2_FLTMSK

BUCK1_FLTMSK

R/W

1h

LDOA2 power fault mask. When masked, power fault from

LDOA2 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

6

5

4

3

2

1

0

R/W

0h

SWA1 power fault mask. When masked, power fault from SWA1

does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

BUCK6 power fault mask. When masked, power fault from

BUCK6 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

BUCK5 power fault mask. When masked, power fault from

BUCK5 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

BUCK4 power fault mask. When masked, power fault from

BUCK4 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

BUCK3 power fault mask. When masked, power fault from

BUCK3 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

BUCK2 power fault mask. When masked, power fault from

BUCK2 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

BUCK1 power fault mask. When masked, power fault from

BUCK1 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

Detailed Description

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5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]

PWR_FAULT_MASK2 is shown in Figure 5-49 and described in Table 5-43.

Return to Summary Table.

Figure 5-49. PWR_FAULT_MASK2 Register

7

6

5

4

3

2

1

0

RESERVED

LDOA1_FLTMS VTT_FLTMSK SWB2_FLTMS SWB1_FLTMS LDOA3_FLTMS

K

R-1h

R/W-1h

Table 5-43. PWR_FAULT_MASK2 Field Descriptions

Bit

7-5

4

Field

Type

R

Reset

1h

Description

RESERVED

LDOA1_FLTMSK

R/W

1h

LDOA1 power fault mask. When masked, power fault from

LDOA1 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

3

2

1

0

VTT_FLTMSK

R/W

1h

VTT LDO Power Fault Mask. When masked, power fault from

VTT LDO does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

SWB2_FLTMSK

SWB1_FLTMSK

LDOA3_FLTMSK

SWB2 power fault mask. When masked, power fault from SWB2

does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

SWB1 power fault mask. When masked, power fault from SWB1

does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

LDOA3 power fault mask. When masked, power fault from

LDOA3 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

64

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5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]

GPO1PG_CTRL1 is shown in Figure 5-50 and described in Table 5-44.

Return to Summary Table.

Figure 5-50. GPO1PG_CTRL1 Register

7

6

5

4

3

2

1

0

LDOA2_MSK

R/W-1h

SWA1_MSK

R/W-1h

BUCK6_MSK

R/W-0h

BUCK5_MSK

R/W-0h

BUCK4_MSK

R/W-0h

BUCK3_MSK

R/W-0h

BUCK2_MSK

R/W-1h

BUCK1_MSK

R/W-0h

Table 5-44. GPO1PG_CTRL1 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

LDOA2_MSK

SWA1_MSK

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W

1h

0h = LDOA2 PG is part of power good tree of GPO1 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO1 pin

and is ignored.

R/W

1h

0h

1h

0h

0h = SWA1 PG is part of power good tree of GPO1 pin.

1h = SWA1 PG is NOT part of power good tree of GPO1 pin and

is ignored.

0h = BUCK6 PG is part of power good tree of GPO1 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO1 pin

and is ignored.

0h = BUCK5 PG is part of power good tree of GPO1 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO1 pin

and is ignored.

0h = BUCK4 PG is part of power good tree of GPO1 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO1 pin

and is ignored.

0h = BUCK3 PG is part of power good tree of GPO1 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO1 pin

and is ignored.

0h = BUCK2 PG is part of power good tree of GPO1 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO1 pin

and is ignored.

0h = BUCK1 PG is part of power good tree of GPO1 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO1 pin

and is ignored.

Detailed Description

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5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]

GPO1PG_CTRL2 is shown in Figure 5-51 and described in Table 5-45.

Return to Summary Table.

Figure 5-51. GPO1PG_CTRL2 Register

7

6

5

4

3

2

1

0

CTL5_MSK

R/W-1h

CTL4_MSK

R/W-0h

CTL2_MSK

R/W-1h

CTL1_MSK

R/W-0h

VTT_MSK

R/W-1h

SWB2_MSK

R/W-1h

SWB1_MSK

R/W-1h

LDOA3_MSK

R/W-1h

Table 5-45. GPO1PG_CTRL2 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

CTL5_MSK

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W

1h

0h = CTL5 pin status is part of power good tree of GPO1 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO1

pin and is ignored.

R/W

0h

1h

0h

1h

0h = CTL4 pin status is part of power good tree of GPO1 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO1

pin and is ignored.

0h = CTL2 pin status is part of power good tree of GPO1 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO1

pin and is ignored.

0h = CTL1 pin status is part of power good tree of GPO1 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO1

pin and is ignored.

0h = VTT LDO PG is part of power good tree of GPO1 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO1 pin

and is ignored.

SWB2_MSK

SWB1_MSK

LDOA3_MSK

0h = SWB2 pin status is part of power good tree of GPO1 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO1

pin and is ignored.

0h = SWB1 PG is part of power good tree of GPO1 pin.

1h = SWB1 PG is NOT part of power good tree of GPO1 pin and

is ignored.

0h = LDOA3 PG is part of power good tree of GPO1 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO1 pin

and is ignored.

66

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5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]

GPO4PG_CTRL1is shown in Figure 5-52 and described in Table 5-46.

Return to Summary Table.

Figure 5-52. GPO4PG_CTRL1 Register

7

6

5

4

3

2

1

0

LDOA2_MSK

R/W-0h

SWA1_MSK

R/W-0h

BUCK6_MSK

R/W-0h

BUCK5_MSK

R/W-0h

BUCK4_MSK

R/W-0h

BUCK3_MSK

R/W-0h

BUCK2_MSK

R/W-0h

BUCK1_MSK

R/W-0h

Table 5-46. GPO4PG_CTRL1 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

LDOA2_MSK

SWA1_MSK

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W

0h

0h = LDOA2 PG is part of power good tree of GPO4 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO4 pin

and is ignored.

R/W

0h

0h = SWA1 PG is part of power good tree of GPO4 pin.

1h = SWA1 PG is NOT part of power good tree of GPO4 pin and

is ignored.

0h = BUCK6 PG is part of power good tree of GPO4 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO4 pin

and is ignored.

0h = BUCK5 PG is part of power good tree of GPO4 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO4 pin

and is ignored.

0h = BUCK4 PG is part of power good tree of GPO4 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO4 pin

and is ignored.

0h = BUCK3 PG is part of power good tree of GPO4 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO4 pin

and is ignored.

0h = BUCK2 PG is part of power good tree of GPO4 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO4 pin

and is ignored.

0h = BUCK1 PG is part of power good tree of GPO4 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO4 pin

and is ignored.

Detailed Description

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5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]

GPO4PG_CTRL2 is shown in Figure 5-53 and described in Table 5-47.

Return to Summary Table.

Figure 5-53. GPO4PG_CTRL2 Register

7

6

5

4

3

2

1

0

CTL5_MSK

R/W-0h

CTL4_MSK

R/W-0h

CTL2_MSK

R/W-0h

CTL1_MSK

R/W-0h

VTT_MSK

R/W-0h

SWB2_MSK

R/W-0h

SWB1_MSK

R/W-0h

LDOA3_MSK

R/W-0h

Table 5-47. GPO4PG_CTRL2 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

CTL5_MSK

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W

0h

0h = CTL5 pin status is part of power good tree of GPO4 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO4

pin and is ignored.

R/W

0h

0h = CTL4 pin status is part of power good tree of GPO4 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO4

pin and is ignored.

0h = CTL2 pin status is part of power good tree of GPO4 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO4

pin and is ignored.

0h = CTL1 pin status is part of power good tree of GPO4 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO4

pin and is ignored.

0h = VTT LDO PG is part of power good tree of GPO4 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO4 pin

and is ignored.

SWB2_MSK

SWB1_MSK

LDOA3_MSK

0h = SWB2 pin status is part of power good tree of GPO4 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO4

pin and is ignored.

0h = SWB1 PG is part of power good tree of GPO4 pin.

1h = SWB1 PG is NOT part of power good tree of GPO4 pin and

is ignored.

0h = LDOA3 PG is part of power good tree of GPO4 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO4 pin

and is ignored.

68

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5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]

GPO2PG_CTRL1 is shown in Figure 5-54 and described in Table 5-48.

Return to Summary Table.

Figure 5-54. GPO2PG_CTRL1 Register

7

6

5

4

3

2

1

0

LDOA2_MSK

R/W-1h

SWA1_MSK

R/W-1h

BUCK6_MSK

R/W-0h

BUCK5_MSK

R/W-0h

BUCK4_MSK

R/W-0h

BUCK3_MSK

R/W-0h

BUCK2_MSK

R/W-0h

BUCK1_MSK

R/W-0h

Table 5-48. GPO2PG_CTRL1 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

LDOA2_MSK

SWA1_MSK

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W

1h

0h = LDOA2 PG is part of power good tree of GPO2 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO2 pin

and is ignored.

R/W

1h

0h

0h = SWA1 PG is part of power good tree of GPO2 pin.

1h = SWA1 PG is NOT part of power good tree of GPO2 pin and

is ignored.

0h = BUCK6 PG is part of power good tree of GPO2 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO2 pin

and is ignored.

0h = BUCK5 PG is part of power good tree of GPO2 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO2 pin

and is ignored.

0h = BUCK4 PG is part of power good tree of GPO2 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO2 pin

and is ignored.

0h = BUCK3 PG is part of power good tree of GPO2 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO2 pin

and is ignored.

0h = BUCK2 PG is part of power good tree of GPO2 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO2 pin

and is ignored.

0h = BUCK1 PG is part of power good tree of GPO2 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO2 pin

and is ignored.

Detailed Description

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5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]

GPO2PG_CTRL2 is shown in Figure 5-55 and described in Table 5-49.

Return to Summary Table.

Figure 5-55. GPO2PG_CTRL2 Register

7

6

5

4

3

2

1

0

CTL5_MSK

R/W-0h

CTL4_MSK

R/W-0h

CTL2_MSK

R/W-1h

CTL1_MSK

R/W-0h

VTT_MSK

R/W-1h

SWB2_MSK

R/W-1h

SWB1_MSK

R/W-1h

LDOA3_ MSK

R/W-1h

Table 5-49. GPO2PG_CTRL2 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

CTL5_MSK

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W

0h

0h = CTL5 pin status is part of power good tree of GPO2 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO2

pin and is ignored.

R/W

0h

1h

0h

1h

0h = CTL4 pin status is part of power good tree of GPO2 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO2

pin and is ignored.

0h = CTL2 pin status is part of power good tree of GPO2 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO2

pin and is ignored.

0h = CTL1 pin status is part of power good tree of GPO2 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO2

pin and is ignored.

0h = VTT LDO PG is part of power good tree of GPO2 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO2 pin

and is ignored.

SWB2_MSK

SWB1_MSK

LDOA3_MSK

0h = SWB2 pin status is part of power good tree of GPO2 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO2

pin and is ignored.

0h = SWB1 PG is part of power good tree of GPO2 pin.

1h = SWB1 PG is NOT part of power good tree of GPO2 pin and

is ignored.

0h = LDOA3 PG is part of power good tree of GPO2 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO2 pin

and is ignored.

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5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]

GPO3PG_CTRL1 is shown in Figure 5-56 and described in Table 5-50.

Return to Summary Table.

Figure 5-56. GPO3PG_CTRL1 Register

7

6

5

4

3

2

1

0

LDOA2_MSK

R/W-0h

SWA1_MSK

R/W-0h

BUCK6_MSK

R/W-0h

BUCK5_MSK

R/W-0h

BUCK4_MSK

R/W-0h

BUCK3_MSK

R/W-0h

BUCK2_MSK

R/W-0h

BUCK1_MSK

R/W-0h

Table 5-50. GPO3PG_CTRL1 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

LDOA2_MSK

SWA1_MSK

BUCK6_MSK

BUCK5_MSK

BUCK4_MSK

BUCK3_MSK

BUCK2_MSK

BUCK1_MSK

R/W

0h

0h = LDOA2 PG is part of power good tree of GPO3 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO3 pin

and is ignored.

R/W

0h

0h = SWA1 PG is part of power good tree of GPO3 pin.

1h = SWA1 PG is NOT part of power good tree of GPO3 pin and

is ignored.

0h = BUCK6 PG is part of power good tree of GPO3 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO3 pin

and is ignored.

0h = BUCK5 PG is part of power good tree of GPO3 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO3 pin

and is ignored.

0h = BUCK4 PG is part of power good tree of GPO3 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO3 pin

and is ignored.

0h = BUCK3 PG is part of power good tree of GPO3 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO3 pin

and is ignored.

0h = BUCK2 PG is part of power good tree of GPO3 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO3 pin

and is ignored.

0h = BUCK1 PG is part of power good tree of GPO3 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO3 pin

and is ignored.

Detailed Description

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5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]

GPO3PG_CTRL2 is shown in Figure 5-57 and described in Table 5-51.

Return to Summary Table.

Figure 5-57. GPO3PG_CTRL2 Register

7

6

5

4

3

2

1

0

CTL5_MSK

R/W-0h

CTL4_MSK

R/W-0h

CTL2_MSK

R/W-0h

CTL1_MSK

R/W-0h

VTT_MSK

R/W-0h

SWB2_MSK

R/W-0h

SWB1_MSK

R/W-0h

LDOA3_MSK

R/W-0h

Table 5-51. GPO3PG_CTRL2 Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

CTL5_MSK

CTL4_MSK

CTL2_MSK

CTL1_MSK

VTT_MSK

R/W

0h

0h = CTL5 pin status is part of power good tree of GPO3 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO3

pin and is ignored.

R/W

0h

0h = CTL4 pin status is part of power good tree of GPO3 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO3

pin and is ignored.

0h = CTL2 pin status is part of power good tree of GPO3 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO3

pin and is ignored.

0h = CTL1 pin status is part of power good tree of GPO3 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO3

pin and is ignored.

0h = VTT LDO PG is part of power good tree of GPO3 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO3 pin

and is ignored.

SWB2_MSK

SWB1_MSK

LDOA3_MSK

0h = SWB2 pin status is part of power good tree of GPO3 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO3

pin and is ignored.

0h = SWB1 PG is part of power good tree of GPO3 pin.

1h = SWB1 PG is NOT part of power good tree of GPO3 pin and

is ignored.

0h = LDOA3 PG is part of power good tree of GPO3 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO3 pin

and is ignored.

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5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]

MISCSYSPG is shown in Figure 5-58 and described in Table 5-52.

Return to Summary Table.

Figure 5-58. MISCSYSPG Register

7

6

5

4

3

2

1

0

GPO1_CTL3_

MSK

GPO1_

CTL6_MSK

GPO4_CTL3_

MSK

GPO4_

CTL6_MSK

GPO2_CTL3_

MSK

GPO2_CTL6_

MSK

GPO3_CTL3_

MSK

GPO3_CTL6_

MSK

R/W-1h

Table 5-52. MISCSYSPG Field Descriptions

Bit

Field

Type

Reset

Description

7

GPO1_CTL3_MSK

GPO1_CTL6_MSK

GPO4_CTL3_MSK

GPO4_CTL6_MSK

GPO2_CTL3_MSK

GPO2_CTL6_MSK

GPO3_CTL3_MSK

GPO3_CTL6_MSK

R/W

1h

0h = CTL3 pin status is part of power good tree of GPO1 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO1

pin.

6

5

4

3

2

1

0

R/W

1h

0h = CTL6 pin status is part of power good tree of GPO1 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO1

pin.

0h = CTL3 pin status is part of power good tree of GPO4 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO4

pin.

0h = CTL6 pin status is part of power good tree of GPO4 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO4

pin.

0h = CTL3 pin status is part of power good tree of GPO2 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO2

pin.

0h = CTL6 pin status is part of power good tree of GPO2 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO2

pin.

0h = CTL3 pin status is part of power good tree of GPO3 pin.

1h = CTL3 pin status is NOT part of power good tree of

GPO13pin.

0h = CTL6 pin status is part of power good tree of GPO3 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO3

pin.

Detailed Description

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5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]

LDOA1CTRL is shown in Figure 5-59 and described in Table 5-53.

Return to Summary Table.

Figure 5-59. LDOA1CTRL Register

7

6

5

4

3

2

1

0

LDOA1_DISCHG[1:0]

LDOA1_SDWN

_CONFIG

LDOA1_VID[3:0]

LDOA1_EN

R/W-1h

R/W-Eh

R/W-1h

Table 5-53. LDOA1CTRL Field Descriptions

Bit

Field

Type

Reset

Description

7-6

LDOA1_DISCHG[1:0]

R/W

1h

LDOA1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

5

LDOA1_SDWN_CONFIG

R/W

1h

Control for Disabling LDOA1 during Emergency Shutdown

0h = LDOA1 will turn off during Emergency Shutdown for

factory-programmable duration of 1 ms, 5 ms, 10 ms, or 100 ms.

1h = LDOA1 is controlled by LDOA1_EN bit only.

4-1

0

LDOA1_VID[3:0]

LDOA1_EN

R/W

Eh

1h

This field sets the LDOA1 regulator output regulation voltage.

See 表 5-4 for V_OUToptions.

LDOA1 Enable Bit.

0h = Disable.

1h = Enable.

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5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]

PG_STATUS1 is shown in Figure 5-60 and described in Table 5-54.

Return to Summary Table.

Figure 5-60. PG_STATUS1 Register

7

6

5

4

3

2

1

0

LDOA2_PGOO SWA1_PGOOD BUCK6_PGOO BUCK5_PGOO BUCK4_PGOO BUCK3_PGOO BUCK2_PGOO BUCK1_PGOO

D

R-0h

Table 5-54. PG_STATUS1 Field Descriptions

Bit

Field

Type

Reset

Description

7

LDOA2_PGOOD

SWA1_PGOOD

BUCK6_PGOOD

BUCK5_PGOOD

BUCK4_PGOOD

BUCK3_PGOOD

BUCK2_PGOOD

BUCK1_PGOOD

R

0h

LDOA2 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

6

5

4

3

2

1

0

R

0h

SWA1 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

BUCK6 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

BUCK5 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

BUCK4 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

BUCK3 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

BUCK2 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

BUCK1 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

Detailed Description

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5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]

PG_STATUS2 is shown in Figure 5-61 and described in Table 5-55.

Return to Summary Table.

Figure 5-61. PG_STATUS2 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

LDO5_PGOOD LDOA1_PGOO VTT_PGOOD SWB2_PGOOD SWB1_PGOOD LDOA3_PGOO

D

R-0h

Table 5-55. PG_STATUS2 Field Descriptions

Bit

7-6

5

Field

Type

R

Reset

0h

Description

RESERVED

LDO5_PGOOD

LDOA1_PGOOD

VTT_PGOOD

R

0h

LDO5 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

4

3

2

1

0

R

0h

LDOA1 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

VTT LDO Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

SWB2_PGOOD

SWB1_PGOOD

LDOA3_PGOOD

SWB2 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

SWB1 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

LDOA3 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

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5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]

PWR_FAULT_STATUS1 is shown in Figure 5-62 and described in Table 5-56.

Return to Summary Table.

Figure 5-62. PWR_FAULT_STATUS1 Register

7

6

5

4

3

2

1

0

LDOA2_PWRF SWA1_PWRFL BUCK6_PWRF BUCK5_PWRF BUCK4_PWRF BUCK3_PWRF BUCK2_PWRF BUCK1_PWRF

LT

T

LT

R/W-0h

Table 5-56. PWR_FAULT_STATUS1 Field Descriptions

Bit

Field

Type

Reset

Description

7

LDOA2_PWRFLT

SWA1_PWRFLT

BUCK6_PWRFLT

BUCK5_PWRFLT

BUCK4_PWRFLT

BUCK3_PWRFLT

BUCK2_PWRFLT

BUCK1_PWRFLT

R

0h

This fields indicates that LDOA2 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

6

5

4

3

2

1

0

R

0h

This fields indicates that SWA1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK6 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK5 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK4 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK3 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK2 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that BUCK1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

Detailed Description

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5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]

PWR_FAULT_STATUS2 is shown in Figure 5-63 and described in Table 5-57.

Return to Summary Table.

Figure 5-63. PWR_FAULT_STATUS2 Register

7

6

5

4

3

2

1

0

RESERVED

LDOA1_PWRF VTT_PWRFLT SWB2_PWRFL SWB1_PWRFL LDOA3_PWRF

LT

T

LT

R-0h

R/W-0h

Table 5-57. PWR_FAULT_STATUS2 Field Descriptions

Bit

7-5

4

Field

Type

R

Reset

0h

Description

RESERVED

LDOA1_PWRFLT

R/W

0h

This fields indicates that LDOA1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

3

4

3

0

VTT_PWRFLT

R/W

0h

This fields indicates that VTT LDO has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

SWB2_PWRFLT

SWB1_PWRFLT

LDOA3_PWRFLT

This fields indicates that SWB2 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that SWB1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

This fields indicates that LDOA3 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

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5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]

TEMPCRIT is shown in Figure 5-64 and described in Table 5-58.

Return to Summary Table.

Asserted when an internal temperature sensor detects rise of die temperature above the CRITICAL

temperature threshold (T_CRIT). There are 5 temperature sensors across the die.

Figure 5-64. TEMPCRIT Register

7

6

5

4

3

2

1

0

RESERVED

DIE_CRIT

VTT_CRIT

TOP-

BOTTOM-

RIGHT_CRIT

LEFT_CRIT

RIGHT_CRIT

R-0h

R/W-0h

Table 5-58. TEMPCRIT Field Descriptions

Bit

7-5

4

Field

Type

R

Reset

0h

Description

RESERVED

DIE_CRIT

R/W

0h

Temperature of rest of die has exceeded T_CRIT

.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

3

2

VTT_CRIT

R/W

0h

Temperature of VTT LDO has exceeded T_CRIT

.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

TOP-RIGHT_CRIT

Temperature of die Top-Right has exceeded T_CRIT. Top-Right

corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

1

0

TOP-LEFT_CRIT

R/W

0h

Temperature of die Top-Left has exceeded T_CRIT.Top-Left

corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

BOTTOM-RIGHT_CRIT

Temperature of die Bottom-Right has exceeded T_CRIT. Bottom-

Right corner of die from top view given pin1 is in Top-Left

corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

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5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]

TEMPHOT is shown in Figure 5-65 and described in Table 5-59.

Return to Summary Table.

Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature

threshold (T_HOT). There are 5 temperature sensors across the die.

Figure 5-65. TEMPHOT Register

7

6

5

4

3

2

1

0

RESERVED

DIE_HOT

VTT_HOT

TOP-

BOTTOM-

RIGHT_HOT

LEFT_HOT

RIGHT_HOT

R-0h

R/W-0h

Table 5-59. TEMPHOT Field Descriptions

Bit

7-5

4

Field

Type

R

Reset

0h

Description

RESERVED

DIE_HOT

R/W

0h

Temperature of rest of die has exceeded T_HOT

.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

3

2

VTT_HOT

R/W

0h

Temperature of VTT LDO has exceeded T_HOT

.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

TOP-RIGHT_HOT

Temperature of Top-Right has exceeded T_HOT. Top-Right corner

of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

1

0

TOP-LEFT_HOT

R/W

0h

Temperature of Top-Left has exceeded THOT. Top-Left corner

of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

BOTTOM-RIGHT_HOT

Temperature of Bottom-Right has exceeded T_HOT. Bottom-Right

corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

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5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]

OC_STATUS is shown in Figure 5-66 and described in Table 5-60.

Return to Summary Table.

Asserted when overcurrent condition is detected from a LSD FET.

Figure 5-66. OC_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

BUCK6_OC

R/W-0h

BUCK2_OC

R/W-0h

BUCK1_OC

R/W-0h

Table 5-60. OC_STATUS Field Descriptions

Bit

7-3

2

Field

Type

R

Reset

0h

Description

RESERVED

BUCK6_OC

R/W

0h

BUCK6 LSD FET overcurrent has been detected.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

1

0

BUCK2_OC

BUCK1_OC

R/W

0h

BUCK2 LSD FET overcurrent has been detected.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

BUCK1 LSD FET overcurrent has been detected.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

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6 Applications, Implementation, and Layout

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

6.1 Application Information

The TPS6508700 device can be used in several different applications from computing, industrial

interfacing and much more. 节 6.2 describes the general application information and provides a more

detailed description on the TPS6508700 device that powers the AMD system. 图 6-2 shows the functional

block diagram for the device, which outlines the typical external connections required for proper device

functionality.

6.2 Typical Application

3.3 V_EC

(LDOA1)

100 kꢀ

EN_S5

CTL4

100 kꢀ

GPIO_G3

CTL1

EN_S0

CTL5

图 6-1. CTL Pin Implementation Option

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V_IN

PMIC

AMD SoC

PLATFORM

VDD_5

LDO5 V

5 V

BUCK1 (8 A)

EXT FET

V_IN

VDD_5_S5

LS

BUCK2 (4 A)

BUCK3 (3 A)

EXT FET

VDDP

VDD_18

V_IN(5.4 V to 21 V)

VDD_18_S5

VDDP_S5

BUCK4 (1 A)

BUCK5 (0.25 A)

BUCK6 (8 A/15 A)

VTT LDO ±0.5 A

LDOA1 0.2 A

VDD_AUD_S5

V_IN

LS

VDD_33

EXT FET

VDD33_S5

3.3V_G3

VINLDO up to 2 V

LDOA2 0.6 A

LDOA3 0.6 A

VSUPP1

VSUPP2

VING1 up to 3.3 V

VING2 up to 3.3 V

SWA1 0.3 A

SWB1 0.4 A

SWB2 0.4 A

VSUPP3

VSUPP4

VSUPP5

V_SYS

LDO5 V

LDO5

PG_5 V

LDO3P3

EN_S5

CTL1

IRQB

CTL2

GPO1 (PG_S5)

GPO2 (PG_S0)

GPO3

GPIO_G3

CTL3

CTL4

GPO4

CTL5

CTL6

EN_S0

DATA

SCLK

图 6-2. Typical Application Example

6.2.1 Design Requirements

The TPS6508700 device requires decoupling capacitors on the supply pins. Follow the values for

recommended capacitance on these supplies given in Section 4. The controllers, converter, LDOs, and

some other features can be adjusted to meet specific application needs. 节 6.2.2 describes how to design

and adjust the external components to achieve the desired performance. In most cases, the controller and

converter designs should be copied directly from the AMD reference design. If significant changes must

be made, some guidelines are provided in 节 6.2.2.

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6.2.2 Detailed Design Procedure

6.2.2.1 Controller Design Procedure

Designing the controller can be broken down into the following steps:

1. Design the output filter

2. Select the FETs

3. Select the bootstrap capacitor

4. Select the input capacitors

5. Set the current limits

The BUCK1, BUCK2, and BUCK6 controllers require a 5-V supply and capacitors at their corresponding

DRV5V_x_x pins. For most applications, the DRV5V_x_x input must come from the LDO5P0 pin to ensure

uninterrupted supply voltage. A 2.2-µF, X5R, 20%, 10-V, or similar capacitor must be used for decoupling.

V_SYS

DRVHx

BOOT1

LDO5V

DRV5V_x_x

V_OUT

L_OUT

SWx

C_OUT

Controller

DRVLx

PGNDSNSx

Control

from SOC

FBVOUTx

R_ILIM

ILIMx

<FBGND2>⁽¹⁾

PowerPAD^TM

图 6-3. Controller Diagram

6.2.2.1.1 Controller With External Feedback Resistor

For BUCK1, the voltage can be set using external feedback resistor. For all other bucks, the voltage is set

by the default OTP settings and no resistor divider is required. For BUCK1, The internal voltage reference

is set to 0.4 V.The output voltage is set with a resistor divider from the output node to the FB pin. TI

recommends using a 1% tolerance or better to get accurate number. Use 公式 3 to calculate the value of

R2.

R2 = R1 (0.4 / V_O– 0.4)

(3)

To set the output voltage to 5 V, use a value of 294 kΩ for R1 and 25.5 kΩ for R2.

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V_SYS

DRVHx

BOOT1

LDO5V

DRV5V_x_x

L_OUT

V_OUT

SWx

C_OUT

Controller

C_FF

DRVLx

PGNDSNSx

Control

from SOC

FBVOUTx

R_ILIM

ILIMx

<FBGND2>⁽¹⁾

PowerPAD^TM

图 6-4. Controller Diagram With External Feedback Resistor

6.2.2.1.2 Selecting the Inductor

Placement of an inductor is required between the external FETs and the output capacitors. Together, the

inductor and output capacitors make the double-pole that contributes to stability. Additionally, the inductor

is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used

increases, the ripple current decreases, which typically results in increased efficiency. However, as the

inductance used increases, the transient performance decreases. Finally, the inductor selected must be

rated for appropriate saturation current, core losses, and DC resistance (DCR).

Use 公式 4 to calculate the recommended inductance for the controller.

V_OUTì (V - V_OUT

_INì f_swì I_OUT(MAX)ì K_IND

)

IN

L =

V

where

•

V_OUTis the typical output voltage.

V_INis the typical input voltage.

f_SWis the typical switching frequency.

I_OUT(MAX)is the maximum load current.

K_INDis the ratio of I_Lrippleto the I_OUT(MAX). For this application, TI recommends that K_INDis set to a value

from 0.2 to 0.4.

(4)

With the chosen inductance value, the peak current for the inductor in steady state operation, I_L(MAX), can

be calculated using 公式 5. The rated saturation current of the inductor must be higher than the I_L(MAX)

current.

(V -V_OUT) ì V_OUT

2 ì V_INì f_swì L

IN

I_L(MAX)= I_OUT(MAX)

+

(5)

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6.2.2.1.3 Selecting the Output Capacitors

TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple.

The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from

their wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on

the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize

the voltage ripple in PFM mode. To achieve the specified regulation performance and low output-voltage

ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of

ceramic capacitors drops with increasing DC bias voltage.

TI recommends using small ceramic capacitors placed between the inductor and load with many vias to

the power ground (PGND) plane for the output capacitors of the buck controllers. This solution typically

provides the smallest and lowest cost solution available for D-CAP2 controllers.

The selection of the output capacitor is typically driven by the output transient response. 公式 6 provides a

rough estimate of the minimum required capacitance to ensure proper transient response. Because the

transient response is significantly affected by the board layout, some experimentation is expected to

confirm that values derived in this section are applicable to any particular use case. 公式 6 is not meant to

be an absolute requirement, but rather a rough starting point. Alternatively, some known combination

values from which to begin are provided in 表 6-1.

2

I_TRAN(MAX)ì L

C_OUT

>

(V_IN- V_OUT) ì V_UNDER

where

•

I_TRAN(MAX)is the maximum load current step.

L is the chosen inductance.

V_OUTis the minimum programmed output voltage.

V_INis the maximum input voltage.

V_UNDERis the minimum allowable undershoot from the programmable voltage.

(6)

In cases where the transient current change is very low, the DC stability may become important. Use 公式

7 to calculate the approximate amount of capacitance required to maintain DC stability. Again, this

equation is provided as a starting point; actual values will vary on a board-to-board case.

V_OUTì 50 ms

C_OUT

>

V

ì f_SWì L

IN

where

•

V_OUTis the maximum programmed output voltage

50 µs is based on internal ramp setup

V_INis the minimum input voltage

f_SWis the typical switching frequency

L is the chosen inductance

(7)

The maximum valuable between 公式 6 and 公式 7 must be selected. 表 6-1 lists some known inductor-

capacitor combinations.

表 6-1. Known LC Combinations

I_{TRAN(max) (A)}

L (µH)

0.47

0.33

0.22

V_OUT(V)

V_UNDER(V)

0.05

C_OUT(µF)

110

3.5

4

1

0.05

220

5

1.35

1

0.068

0.06

220

8

440

20

1

0.16

550

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6.2.2.1.4 Selecting the FETs

This controller is designed to drive two NMOS FETs. Typically, lower R_DSONvalues are better for

improving the overall efficiency of the controller; however, higher gate-charge thresholds result in lower

efficiency so the twovalues must be balanced for optimal performance. As the R_DSONfor the low-side FET

decreases, the minimum current limit increases; therefore, appropriately select the values for the FETs,

inductor, output capacitors, and current limit resistor. TI's CSD87331Q3D, CSD87381P, and CSD87588N

devices are recommended for the controllers, depending on the required maximum current.

6.2.2.1.5 Bootstrap Capacitor

To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a

capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends

placing ceramic capacitors with a value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402,

10-V capacitor is used for the controllers.

TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and

turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common

practice for controller design.

6.2.2.1.6 Setting the Current Limit

The current-limiting resistor value must be chosen based on 公式 1.

6.2.2.1.7 Selecting the Input Capacitors

Because of the nature of the switching controller with a pulsating input current, a low-ESR input capacitor

is required for best input-voltage filtering and also for minimizing the interference with other circuits caused

by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x

pin to support the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is

recommended for most applications. To achieve the low-ESR requirement, a ceramic capacitor is

recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be

considered. For better input-voltage filtering, the input capacitor can be increased without any limit.

注

Use the correct capacitance value for the ceramic capacitor after derating to achieve the

recommended input capacitance.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS

and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata

GRM21BR61E226ME44: 22-µF, 0805, 25-V, ±20%, or similar capacitors.

6.2.2.2 Converter Design Procedure

Designing the converter has only two steps: design the output filter and select the input capacitors.

The converter must be supplied by a 5-V source. 图 6-5 shows a diagram of the converter.

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L_OUT

V_OUT

PVINx

LXx

VIN_BUCK345_ANA

C_IN

FBx

Converter

Control from SOC

图 6-5. Converter Diagram

6.2.2.2.1 Selecting the Inductor

Placement of an inductor between the external FETs and the output capacitors is required. Together, the

inductor and output capacitors form a double pole in the control loop that contributes to stability.

Additionally, the inductor is directly responsible for the output ripple, efficiency, and transient performance.

As the inductance used increases, the ripple current decreases, which typically results in an increase in

efficiency. However, with an increase in inductance used, the transient performance decreases. Finally,

the inductor selected must be rated for appropriate saturation current, core losses, and DCR.

注

Internal parameters for the converters are optimized for a 0.47-µH inductor for BUCK3 and a

1-µH inductor for BUCK4 and BUCK5; however, using other inductor values is possible as

long as they are chosen carefully and thoroughly tested.

V_OUTì (V - V_OUT

_INì f_swì I_OUT(MAX)ì K_IND

)

IN

L =

V

(8)

With the chosen inductance value and the peak current for the inductor in steady state operation, I_L(MAX)

can be calculated using 公式 9. The rated saturation current of the inductor must be higher than the I_L(MAX)

current.

(V -V_OUT) ì V_OUT

2 ì V_INì f_swì L

IN

I_L(MAX)= I_OUT(MAX)

+

(9)

6.2.2.2.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values are recommended because they provide the lowest output

voltage ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside

from the wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on

the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize

the voltage ripple in PFM mode. To achieve the specified regulation performance and low output-voltage

ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of

ceramic capacitors drops with increasing DC-bias voltage.

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For the output capacitors of the buck converters, TI recommends placing small ceramic capacitors

between the inductor and load with many vias to the PGND plane. This solution typically provides the

smallest and lowest-cost solution available for D-CAP2 controllers.

The output capacitance must equal or exceed the minimum capacitance listed for BUCK3, BUCK4, and

BUCK5 (assuming quality layout techniques are followed).

6.2.2.2.3 Selecting the Input Capacitors

Because of the nature of the switching converter with a pulsating input current, a low-ESR input capacitor

is required for the best input-voltage filtering and for minimizing the interference with other circuits caused

by high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for

most applications. A ceramic capacitor is recommended to achieve the low-ESR requirement. However,

the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. The input

capacitor can be increased without any limit for better input-voltage filtering.

注

Use the correct capacitance value for the ceramic capacitor after derating to achieve the

recommended input capacitance.

The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10-µF, 0402, 10-V,

±20%, or similar capacitor.

6.2.2.3 LDO Design Procedure

The VTT LDO must support the fast load transients from the DDR memory for termination. Therefore, TI

recommends using ceramic capacitors to maintain a high amount of capacitance with low ESR on the VTT

LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the GRM188R60J226MEA0

from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred input capacitor for the VTT

LDO is the CL05A106MP5NUNC from Samsung (10-µF, 0402, 10-V, ±20%, or similar capacitor).

The remaining LDOs must have input and output capacitors chosen based on the values in Section 4.9.

6.2.3 Application Curves

图 6-6. BUCK2 Load Transient

图 6-7. BUCK2 Load Transient

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6.2.4 Layout

6.2.4.1 Layout Guidelines

For all switching power supplies, the layout is an important step in the design, especially at high peak

currents and high switching frequencies. If the layout is not carefully done, the regulator can have stability

problems and EMI issues. Therefore, use wide and short traces for the main current path and for the

power ground (PGND) tracks. The input capacitors, output capacitors, and inductors must be placed as

close as possible to the device. Use a common-ground node for the power ground and use a different,

isolated node for the control ground to minimize the effects of ground noise. Connect these ground nodes

close to the AGND pin by one or two vias. Use of the design guide is highly recommended in addition to

following these other basic requirements:

•

Do not allow the AGND, PGNDSNSx, or FBGND2 pin to connect to the thermal pad on the top layer.

To ensure proper sensing based on the FET R_DSON, the PGNDSNSx pin must not connect to the board

ground or to the PGND pin of the FET.

•

All inductors, input and output capacitors, and FETs for the converters and controller must be on the

same board layer as the device.

To achieve the best regulation performance, place feedback connection points near the output

capacitors and minimize the control feedback loop as much as possible.

•

Bootstrap capacitors must be placed close to the device.

The internal reference regulators must have their input and output capacitors placed close to the

device pins.

•

Route the DRVHx and SWx pins as a differential pair. Ensure that a power-ground path is routed in

parallel with the DRVLx pin, which provides optimal driver loops.

6.2.4.2 Layout Example

BUCK2

VREF Capacitor

VTT

BUCK6

BUCK3

BUCK5

BUCK4

BUCK1

图 6-8. EVM Layout Example With All Components on the Top Layer

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6.3 Power Supply Coupling and Bulk Capacitors

This device is designed to work with several different input voltages. The minimum voltage on the VSYS

pin is 5.6 V for the device to start up; however, this is a low power rail. The input to the FETs must be

from 4.5 V to 21 V as long as the proper bill of materials (BOM) choices are made. The input to the

converters must be 5 V. For the device to output maximum power, the input power must be sufficient. For

the controllers, V_INmust be able to supply sufficient input current for the output power of the application.

For the converters, the PVINx converter must be able to supply 2 A (typical).

As a best practice, determine the power usage by the system and back-calculate the necessary power

input based on the expected efficiency values.

6.4 Do's and Don'ts

•

Connect the LDO5V output to the DRV5V_x_x inputs. This output initially supplies 5 V for the drivers

from the VSYS pin and then switches to using the 5-V buck converter when available for optimal

efficiency.

•

Ensure that none of the control pins are potentially floating.

Include 0-Ω resistors on the DRVH or BOOT pins of the controllers on prototype boards, which allows

for slowing the controllers if the system is unable to handle the noise generated by the large switching

or if switching voltage is too large because of layout.

•

Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here

causes reference circuits to regulate incorrectly.

Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may

turn on the HS FET passing the input to the output until VSYS is biased.

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产品主页链接: TPS6508700

TPS6508700

ZHCSGZ6 –OCTOBER 2017

www.ti.com.cn

7 器件和文档支持

7.1 器件支持

7.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构

成此类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

7.2 文档支持

7.2.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《CSD87331Q3D 同步降压 NexFET™ 电源块》数据表

德州仪器 (TI)，《CSD87381P 同步降压 NexFET™ 电源块 II》数据表

德州仪器 (TI)，《CSD87588N 同步降压 NexFET™ 电源块 II》数据表

7.3 接收文档更新通知

要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

7.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术

规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区为了促进工程师之间的合作，我们创建了 TI 工程师对工程师 (E2E) 社区。在 e2e.ti.com

中，您可以提问、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信

息。

7.5 商标

DCAP2, D-CAP2, DCS-Control, NexFET, E2E are trademarks of Texas Instruments.

AMD is a trademark of Advanced Micro Devices.

All other trademarks are the property of their respective owners.

7.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

7.7 术语表

TI 术语表

这份术语表列出并解释术语、缩写和定义。

8 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另

行通知和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

92

机械、封装和可订购信息

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产品主页链接: TPS6508700

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS6508700RSKR
厂家：	TEXAS INSTRUMENTS
描述：	适用于 AMD™ 系列 17h 模型 10h-1Fh 处理器的 PMIC \| RSK \| 64 \| -40 to 85 集成电源管理电路
文件：	总100页 (文件大小：2404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS6508700RSKR [TI]

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