TPS65131TRGERQ1 [TI]
具有双路正负输出（750mA 典型值）的汽车类双电源转换器 | RGE | 24 | -40 to 105;
| 型号： | TPS65131TRGERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双路正负输出（750mA 典型值）的汽车类双电源转换器 | RGE | 24 | -40 to 105 开关 输出元件 转换器 |
| 文件： | 总34页 (文件大小：2379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
TPS65131-Q1 正负输出直流/直流转换器
1 特性
3 说明
1
•
•
适用于汽车电子 应用
AEC-Q100 在测试指南中包括以下结果：
TPS65131-Q1 器件作为双输出直流/直流转换器，可产
生高达 15V 的正输出电压和低至 -15V 的负输出电
压，输出电流通常为 200mA，具体值取决于输入电压
与输出电压比。凭借高达 85% 的总体效率，此器件非
常适合于便携式电池供电类设备。输入电压范围为
2.7V 至 5.5V，因此允许诸如 3.3V 和 5V 的电压轨为
TPS65131-Q1 器件供电。TPS65131-Q1 器件采用带
有散热垫的 QFN-24 封装。由于只需少量较小的外部
组件，因此总体解决方案尺寸可以非常小。
–
器件温度 2 级：–40°C 至 105°C 的环境运行温
度范围
–
已在 -40°C 至 125°C 的结温范围内测试电气特
性
–
–
器件 HBM ESD 分类等级 H1C
器件 CDM ESD 分类等级 C4B
•
•
•
高达 15V 和低至 -15V 的双向可调输出电压
对升压和逆变器主开关具有 2A 典型开关电流限制
高转换效率
此转换器采用定频 PWM 控制拓扑运行，而且在启用
省电模式后，它在轻负载电流的情况下使用脉冲跳跃模
式。在运行时，典型的总体器件静态电流只有
500µA。在关断状态下，器件一般消耗 0.2µA。独立使
能引脚可实现针对两个输出的加电和断电排序。为了尽
可能地实现故障情况下的高可靠性，此器件有一个内部
电流限制、过压保护和热关断。
–
–
–
正输出轨高达 91%
负输出轨高达 85%
低负载状态下的省电模式
•
•
针对加电和断电排序的独立使能输入
用于外部 PFET 的控制输出可支持在关断时完全断
电
•
•
•
•
•
•
2.7V 至 5.5V 输入电压范围
最低 1.25MHz 的定频 PWM 操作
热关断
根据 AEC-Q100 温度 2 级要求，TPS65131-Q1 器件
符合汽车 应用的要求。该器件在 –40°C 至 125°C 的
器件结温范围内接受了电气特性测试。该器件还具有最
低关断电流、小巧的解决方案尺寸、带散热垫的封装以
及良好的效率和保护 特性，适合汽车和工业 应用。
在两个输出上的过压保护
0.2µA 典型关断电流
小型 4mm x 4mm QFN-24 封装 (RGE)
器件信息(1)
器件型号
封装
封装尺寸（标称值）
2 应用范围
超薄四方扁平无引线
(VQFN) (24)
•
•
小尺寸至中等尺寸有机发光二极管 (OLED) 显示器
(TFT) LCD、CCD 偏置电源
TPS65131-Q1
4mm x 4mm
(1) 如需了解所有可用封装，请参阅可订购产品附录。
应用电路原理图
L1
4.7 µH
D1
VI
VPOS
C4
Q1
C1
4.7 µF
R1
22 µF
C9
VPOS
FBP
INP
BSW
VREF
R2
C8
220 nF
R4
R3
TPS65131-Q1
FBN
INN
VIN
C10
VNEG
R7
100 Ω
ENP
PSP
ENN
PSN
VNEG
OUTN
CN
C3
100 nF
C2
4.7 µF
D2
L2
4.7 µH
C5
22 µF
C6 C7
10nF 4.7nF
CP
AGND
PGND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBB2
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
9
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 26
12.1 器件支持................................................................ 26
12.2 商标....................................................................... 26
12.3 静电放电警告......................................................... 26
12.4 Glossary................................................................ 26
13 机械、封装和可订购信息....................................... 26
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (October 2014) to Revision E
Page
•
•
•
•
已更改 特性项标条目文本从“...通过认证..”改为“...测试指南..”并且 HBM 分类等级从“H2”改为“H1C”...................................... 1
Moved Tstg spec to the Abs Max Ratings table per new data sheet standard ....................................................................... 5
Changed "Handling Ratings" to "ESD Ratings" and HBM Value From "±2 kV" to "±1000 V"................................................ 5
Changed Electrical Characteristics condition statement to "This specification applies over the full recommended
input voltage range VI = 2.7 V to 5.5 V and over the temperature range TJ = –40°C to 125°C unless otherwise
noted. Typical values apply for VI = 3.6 V and TJ = 25°C.".................................................................................................... 6
•
•
Changed The specification applies over the full recommended input voltage range VI = 2.7 V to 5.5 V and over the
temperature range TJ = –40 °C to 125°C unless otherwise noted. Typical values apply for VI = 3.6 V and TJ = 25°........... 7
已添加 Analog Supply Input Filter description ..................................................................................................................... 16
Changes from Revision C (March 2014) to Revision D
Page
•
•
•
•
•
•
•
•
•
•
•
•
全局编辑更改，数据表使用了全新的格式 ............................................................................................................................... 1
已更改 最大效率从 89% 改为 91% 以及从 81% 改为 85% .................................................................................................... 1
已删除 “最低 1.25MHz”........................................................................................................................................................... 1
已更改 1µA 关断电流至典型的 0.2µA ..................................................................................................................................... 1
Relocated and renamed the pin Functions table ................................................................................................................... 4
Added thermal pad to pin Functions Table............................................................................................................................. 4
Added Thermal Pad to Absolute Maximum Ratings. Added min./max. values where missing.............................................. 5
Added V(VIN), V(INN), VNEG, VPOS, V(ENN), V(ENP), V(PSN) to Recommended Operating Conditions table .................................... 5
Changed symbol names to JEDEC compliance..................................................................................................................... 6
Added frequency and duty cycles to Switching Characteristics table. Removed from Electrical Characteristics table ......... 7
已添加 Rectifier Diode Selection Guide................................................................................................................................ 15
已添加 P-MOSFET Selection Guide..................................................................................................................................... 15
2
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
Changes from Revision B (February 2013) to Revision C
Page
•
•
•
•
•
•
•
•
•
已添加 “已在 -40°C 至 125°C 的结温范围内测试电气特性”.................................................................................................... 1
Deleted TA table row............................................................................................................................................................... 5
Changed INN to VINN, added pin names VIN and INN............................................................................................................. 5
Added pin name VPOS .......................................................................................................................................................... 5
Added pin name VNEG .......................................................................................................................................................... 5
Changed INP to VINP, added pin name INP ............................................................................................................................. 5
Changed "between pins OUTN to VINN" to "between pins OUTN to INN".............................................................................. 5
Added operating junction temperature ................................................................................................................................... 5
Added "In applications where high power dissipation and/or poor package thermal resistance is present, the
maximum ambient temperature may require derating. See Thermal Information for details."............................................... 5
•
•
Deleted "virtual" from "Operating virtual junction temperature range".................................................................................... 5
Changed Electrical Characteristics condition statement to "This specification applies over the full recommended
input voltage range VI = 2.7 V to 5.5 V and over the temperature range TJ = TA = –40°C to 125°C unless otherwise
noted. Typical values apply for VI = 3.6 V and TJ = TA = 25°C."............................................................................................ 6
•
•
•
•
•
•
•
•
•
•
Changed ILIM,min = 1800 mA to 1700 mA ................................................................................................................................ 6
Deleted VPOS = 5 V (105°C) row............................................................................................................................................. 6
Changed rDS(on)P,max (VPOS = 5 V) = 300 mΩ to 390 mΩ ......................................................................................................... 6
Changed rDS(on)P,max (VPOS = 10 V) = 200 mΩ to 230 mΩ ....................................................................................................... 6
Changed ILIMP,min = 1800 mA to 1700 mA............................................................................................................................... 6
Changed ILIMP,max = 2200 mA to 2250 mA.............................................................................................................................. 6
Added TA = –40°C to 85°C ..................................................................................................................................................... 6
Changed minimum f = 1250 kHz to 1150 kHz........................................................................................................................ 7
Editorially updated Block Diagram.......................................................................................................................................... 9
已更改 "The maximum recommended junction temperature (TJ) of the TPS65131-Q1 is 125°C." to "The
recommended device junction temperature range, TJ, is -40°C to 125°C." ......................................................................... 16
•
•
已更改 RθJA = 37.8°C/W to RθJA = 34.1°C/W ........................................................................................................................ 16
已更改 "Specified regulator operation is ensured to a maximum ambient temperature TA of 105°C." to "The
recommended operating ambient temperature range for the device is TA = –40°C to 105°C."........................................... 16
•
已更改 "Therefore, the maximum power dissipation is about 1058 mW" to "Use 公式 13 to calculate the maximum
power dissipation, PDmax, as a function of TA. In this equation, use TJ = 125°C to operate the device within the
recommended temperature range, use TJ = T(TS) to determine the absolute maximum threshold when the device
might go into thermal shutdown." ......................................................................................................................................... 16
•
已更改 公式 13...................................................................................................................................................................... 16
Changes from Revision A (November 2012) to Revision B
Page
•
将 CDM ESD 等级从 C3B 改为 C4B。................................................................................................................................... 1
Changes from Original (May 2012) to Revision A
Page
•
•
•
器件将从预览推进到生产 ........................................................................................................................................................ 1
Added thermal information table values. ................................................................................................................................ 6
Added VPOS = 5 V (105°C) row and values to Electrical Characteristics table....................................................................... 6
Copyright © 2012–2017, Texas Instruments Incorporated
3
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
5 Pin Configuration and Functions
24-pin VQFN With PowerPAD™ Package
RGE Package
place
place
(Top View)
(Bottom View)
19 20 21 22 23 24
24 23 22 21 20 19
18
17
16
15
14
13
1
2
3
4
5
6
CN
VREF
FBN
INP
1
2
3
4
5
6
18
17
16
15
14
13
INP
PGND
PGND
VIN
CN
PGND
PGND
VIN
VREF
FBN
Thermal Pad
Thermal Pad
VNEG
OUTN
OUTN
VNEG
OUTN
OUTN
INN
INN
INN
INN
12 11 10
9
8
7
7
8
9
10 11 12
NC – No internal Connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
AGND
BSW
CN
NO.
19
—
O
Analog ground pin
Gate-control pin for external battery switch. This pin goes low when ENP is set high.
7
18
I/O Compensation pin for inverting converter control
I/O Compensation pin for boost converter control
CP
21
ENN
ENP
FBN
10
I
I
Enable pin for the negative-output voltage (0 V: disabled, VIN: enabled)
Enable pin for the positive-output voltage (0 V: disabled, VIN: enabled)
Feedback pin for the negative-output voltage divider
Feedback pin for the positive-output voltage divider
Inverting converter switch pin
8
16
I
FBP
22
I
INN
5, 6
1, 24
12, 20
13, 14
2, 3
11
O
O
—
INP
Boost converter switch pin
NC(1)
OUTN
PGND
PSN
PSP
Not connected
I/O Inverting converter switch output
—
Power ground pin
I
I
I
I
I
Power-save mode enable for inverter stage (0 V: disabled, VIN: enabled)
Power-save mode enable for boost converter stage (0 V: disabled, VIN: enabled)
Control supply input
9
VIN
4
VNEG
VPOS
15
Negative-output voltage-sense input
23
Positive-output voltage-sense input
Reference output voltage. Bypass this pin with a 220-nF capacitor to ground. Connect the lower resistor of the
negative-output voltage divider to this pin.
VREF
17
O
Thermal pad
Thermal pad for thermal performance, connect to PGND(1)
(1) NC - No internal connection
4
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature, unless otherwise noted
(1)
VALUE
UNIT
MIN
–0.3
–0.3
MAX
(2)
Input voltage range at pins VIN, INN
6
V
V
(2)
Voltage at pin VPOS
17
(2)
Voltage at pin VNEG
–17 V(VIN) + 0.3
–0.3 V(VIN) + 0.3
V
(2)
Voltage at pins ENN, ENP, FBP, FBN, CN, CP, PSP, PSN, BSW
V
(2)
Input voltage at pin INP
–0.3
–0.3
–0.3
–40
–65
17
24
V
(2)
Differential voltage between pins OUTN to INN
V
Thermal pad(2)
0.3
150
150
V
TJ
Operating junction temperature
Storage temperature range
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground pin, unless otherwise noted.
6.2 ESD Ratings
VALUE
±1000
±750
UNIT
V
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature, unless otherwise noted
MIN
MAX
UNIT
VI , V(VIN)
V(INN)
,
Application input voltage range, input voltage range at VIN and INN pins
2.7
5.5
V
VPOS
VNEG
Adjustable output voltage range for the boost converter
Adjustable output voltage range for the inverting converter
Enable signals voltage
VI + 0.5
–15
15
–2
V
V
V
V(ENN)
V(ENP)
,
0
5.5
V(PSN)
,
Power-save mode enable signals voltage
0
5.5
V
V(PSP)
TA
TJ
Operating free-air temperature range(1)
Operating junction temperature range
–40
–40
105
125
°C
°C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
require derating. See Thermal Information for details.
Copyright © 2012–2017, Texas Instruments Incorporated
5
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
6.4 Thermal Information
TPS65131-Q1
THERMAL METRIC(1)
RGE PACKAGE
UNIT
24 PINS
34.1
36.8
12.2
0.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
12.3
2.8
RθJCbot
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
This specification applies over the full recommended input voltage range VI = 2.7 V to 5.5 V and over the temperature range
TJ = –40°C to 125°C unless otherwise noted. Typical values apply for VI = 3.6 V and TJ = 25°C.
PARAMETER
DC-DC STAGE (V(VPOS), V(VNEG)
TEST CONDITIONS
MIN
TYP
MAX UNIT
)
Vref
Reference voltage
Iref = 10 µA
1.2
1.213
50
1.225
V
nA
nA
V
I(FBP)
I(FBN)
V(FBP)
V(FBN)
Positive feedback input bias current
Negative feedback input bias current
Positive feedback regulation voltage
Negative feedback regulation voltage
Total output dc accuracy
V(FBP) = Vref
V(FBN) = 0.1 Vref
50
1.189
1.213
0
1.237
0.024
–0.024
V
3%
V(VIN) = 3.6 V
440
330
1950
230
170
1950
620
530
rDS(on)(N)
I(LIM-N)
rDS(on)(P)
Inverter switch on-resistance
Inverter switch current limit
Boost switch on-resistance
Boost switch current limit
mΩ
mA
mΩ
mA
V(VIN) = 5 V
V(VIN) = 3.6 V
1700
2200
390
V(POS) = 5 V
V(POS) = 10 V
230
I(LIM-P)
CONTROL STAGE
V(VIN) = 3.6 V, V(POS) = 8 V
1700
1.4
2250
High-level input voltage, ENP, ENN,
PSP, PSN
VIH
VIL
V
V
Low-level input voltage, ENP, ENN,
PSP, PSN
0.4
0.1
ENP, ENN, PSP, PSN connected
to GND or VIN
Input current, ENP, ENN, PSP, PSN
0.01
µA
R(BSW)
Output resistance
VIN
27
300
100
100
kΩ
V(VIN) = 3.6 V, I(POS) = I(NEG) = 0,
ENP = ENN = PSP = PSN =
500
120
120
VPOS
VNEG
IQ
Quiescent current
µA
µA
V(VIN)
,
V(POS) = 8 V, V(NEG) = –5 V
ENN = ENP = LOW, TA = –40°C to
85°C
ISD
Shutdown supply current
0.2
1.5
2.7
V(UVLO)
T(TS)
Undervoltage lockout threshold
Thermal shutdown
2.1
2.35
150
5
V
°C
°C
T(TS-HYS)
Thermal shutdown hysteresis
Junction temperature decreasing
6
Copyright © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
6.6 Switching Characteristics
The specification applies over the full recommended input voltage range VI = 2.7 V to 5.5 V and over the temperature range
TJ = –40 °C to 125°C unless otherwise noted. Typical values apply for VI = 3.6 V and TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY
f
Oscillator frequency
1150
1380
1500
kHz
DUTY CYCLE
D(MAX-P)
Maximum-duty-cycle, boost converter
87.5%
87.5%
12.5%
12.5%
Maximum-duty-cycle, inverting
converter
D(MAX-N)
D(MIN-P)
D(MIN-N)
Minimum-duty-cycle, boost converter
Minimum-duty-cycle, inverting
converter
6.7 Typical Characteristics
At 25°C, unless otherwise noted.
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
VPOS = 10.5 V
VNEG = -10 V
VNEG = -15 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VPOS = 15 V
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D001
D002
图 1. Boost Converter (VPOS) Maximum Output Current vs
图 2. Inverting Converter (VPOS) Output Current vs Input
Input Voltage
Voltage
340
330
320
310
300
290
280
270
260
250
240
1.2
VI = 5.5 V
VI = 3.3 V
1
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D004
D003
VI = 3.6 V
图 4. Quiescent Current (Into VIN and INN) Over Input
图 3. Shutdown Current (Into VIN and INN) Over Input
Voltage
Voltage
版权 © 2012–2017, Texas Instruments Incorporated
7
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
7 Parameter Measurement Information
表 1. List of Components
REFERENCE
SETUP
VALUE, DESCRIPTION
4.7 µF, ceramic, 6.3 V, X5R
0.1 µF, ceramic, 10 V, X5R
4 x 4.7 µF, ceramic, 25 V, X7R
10 nF, ceramic, 16 V, X7R
4.7 nF, 50 V, C0G
220 nF, ceramic, 6.3 V, X5R
1 MΩ
C1, C2
C3
C4, C5
C6
—
C7
C8
VPOS = 10.5 V
VPOS = 15 V
VPOS = 10.5 V
VPOS = 15 V
VNEG = –10 V
VNEG = –15 V
VNEG = –10 V
VNEG = –15 V
R1
R2
R3
R4
975 kΩ
130 kΩ
85.8 kΩ
1 MΩ
1.3 MΩ
121.2 kΩ
104.8 kΩ
R7
D1, D2
L1, L2
Q1
100 Ω
Schottky, 1 A, 20 V, Onsemi
MBRM120
—
4.7 µH, Epcos B82462-G4472
MOSFET, p-channel, 12 V, 4 A,
Vishay Si2323DS
D1
L1
VI
Q1
V
POS
C1
C4
R1
R2
INP
VPOS
FBP
BSW
VREF
TPS65131-Q1
C8
R4
R3
INN
FBN
R7
VIN
VNEG
ENP
PSP
ENN
PSN
AGND
VNEG
OUTN
CN
C2
C3
D2
C5
L2
CP
C7
C6
PGND
Copyright © 2017, Texas Instruments Incorporated
图 5. Parameter Measurement Setup
8
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
8 Detailed Description
8.1 Overview
The TPS65131-Q1 is a dual-output dc-dc converter that generates two adjustable output voltages. One output
voltage is positive (boost converter), the other is negative (inverting converter). The positive output is adjustable
up to 15 V, the negative output is adjustable down to –15 V. The device operates with an input voltage range of
2.7 V to 5.5 V. Both converters (positive and negative output) work independently of each other. They share a
common clock and a common voltage reference. A fixed-frequency, pulse-width-modulated (PWM) regulator
controls both outputs separately. In general, each converter operates in continuous-conduction mode (CCM). To
improve efficiency at light loads, the converters can operate in discontinuous-conduction mode (DCM). When the
power-save mode is enabled, the converters automatically transition between CCM and DCM operation: As the
load current decreases, the converter enters DCM mode. Power-save mode is individually configurable for both
outputs. The transition as a function of the load current works independently for each converter.
8.2 Functional Block Diagram
INP
VIN
VPOS
VIN
VPOS
Date
/ontrol
VIN
ENP
PSP
CP
.oost /onverter /ontrol
FBP
+
-
VREF
BSW
+
-
VIN
VIN
Çemperature
hscillator
/ontrol
Vref
ENN
PSN
VNEG
FBN
Lnverting /onverter /ontrol
CN
-
+
INN
VIN
Date
/ontrol
INN
OUTN
PGND
AGND
Copyright © 2017, Texas Instruments Incorporated
版权 © 2012–2017, Texas Instruments Incorporated
9
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
8.3 Feature Description
8.3.1 Power Conversion
Both converters operate in a fixed-frequency, PWM control scheme. The on-time of the internal switches varies
depending on the input-to-output voltage ratio and the load. During the on-time, the inductors connected to the
converters charge with current. In the remaining time, the off-time with a time period set by the fixed operating
frequency, the inductors discharge into the output capacitors through the rectifier diodes. Usually at higher loads,
the inductor currents are continuous. At lighter loads, the boost converter uses an additional internal switch to
allow current to flow back to the input. This avoids inductor current becoming discontinuous in the boost
converter. At the inverting converter, during light loads, the inductor current can become discontinuous. In this
case, the control circuit of the inverting controller output automatically takes care of these changing conditions to
operate always with an optimum control setup.
8.3.2 Control
The controller circuits of both converters employ a fixed-frequency, multiple-feedforward controller topology.
These circuits monitor input voltage, output voltage, and voltage drop across the switches. Changes in the
operating conditions of the converters directly affect the duty cycle and must not take the indirect and slow way
through the output voltage-control loops. A self-learning control corrects measurement errors in this feedforward
system. An external capacitor damps the output to avoid output-voltage steps due to output changes of this self-
learning control system.
The voltage loops, determined by the error amplifiers, must only handle small signal errors. The error amplifiers
feature internal compensation. Their inputs are the feedback voltages on the FBP and FBN pins. The device
uses a comparison of these voltages with the internal reference voltage to generate an accurate and stable
output voltage.
8.3.3 Output Rails Enable or Disable
Both converters can be enabled or disabled individually. Applying a logic HIGH signal at the enable pins (ENP for
the boost converter, ENN for the inverting converter) enables the corresponding output. After enabling, internal
circuitry, necessary to operate the specific converter, then turns on, followed by the Soft Start.
Applying a low signal at the enable ENP or ENN pin shuts down the corresponding converter. When both enable
pins are low, the device enters shutdown mode, where all internal circuitry turns off. The device now consumes
shutdown current flowing into the VIN pin. The output loads of the converters can be disconnected from the
input, see Load Disconnect.
8.3.4 Load Disconnect
The device supports completely disconnecting the load when the converters are disabled. For the inverting
converter, the device turns off the internal PMOS switch. If the inverting converter is turned off, no dc current
path remains which could discharge the battery or supply.
This is different for the boost converter. The external rectifying diode, together with the boost inductor, form a dc
current path which could discharge the battery or supply if any load connects to the output. The device has no
internal switch to prevent current from flowing. For this reason, the device offers a PMOS gate control output
(BSW) to enable and disable a PMOS switch in this dc current path, ideally directly between the boost inductor
and battery. To be able to fully disconnect the battery, the forward direction of the parasitic backgate diode of this
switch must point to the battery or supply. The external PMOS switch, which connects to BSW, turns on when
the boost converter is enabled and turns off when the boost converter is disabled.
8.3.5 Soft Start
Both converters have implemented soft-start functions. When each converter is enabled, the implemented switch
current limit ramps up slowly to its nominal programmed value in typically 1 ms. The device includes this function
to limit the input current during start-up to avoid high peak input currents, which could interfere with other
systems connected to the same battery or supply.
If the application includes the Load Disconnect PMOS switch, a current flows from the input to the output of the
boost converter at the moment the PMOS switch becomes conducting.
10
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
Feature Description (接下页)
8.3.6 Overvoltage Protection
Both built-in converters (boost and inverter) have implemented individual overvoltage protection. If the feedback
voltage under normal operation exceeds the nominal value by typically 5%, the corresponding converter shuts
down immediately to protect any connected circuitry from possible damage.
8.3.7 Undervoltage Lockout
An undervoltage lockout prevents the device from starting up and operating if the supply voltage at the VIN pin is
lower than the undervoltage lockout threshold. For this case, the device automatically shuts down both
converters when the supply voltage at VIN falls below this threshold. Nevertheless, parts of the control circuits
remain active, which is different than device shutdown using EN inputs. The device includes the undervoltage
lockout function to prevent device malfunction.
8.3.8 Overtemperature Shutdown
The device automatically shuts down both converters if the implemented internal temperature sensor detects a
chip temperature above the thermal shutdown temperature. It automatically starts operating again when the chip
temperature falls below this threshold plus hysteresis threshold. The built-in hysteresis avoids undefined
operation caused by ringing from shutdown and prevents operating at a temperature close to the
overtemperature shutdown threshold.
8.4 Device Functional Modes
8.4.1 Power-Save Mode
The power-save mode can improve efficiency at light loads. In power-save mode, the converter only operates
when the output voltage falls below an device internally set threshold voltage. The converter ramps up the output
voltage with one or several operating pulses and goes again into power-save mode once the inductor current
becomes discontinuous.
The PSN and PSP logic level selects between power-save mode and continuous-conduction mode. If the specific
pins (PSP for the boost converter, PSN for the inverting converter) are HIGH, the power-save mode for the
corresponding converter operates at light loads. Similary, a LOW on the PSP pin or PSN pin disables the power-
save mode for the corresponding converter.
版权 © 2012–2017, Texas Instruments Incorporated
11
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS656131-Q1 boost converter output voltage, VPOS, and the inverting converter output voltage, VNEG
,
require external components to set the required output voltages. The valid output voltage ranges are as shown in
Recommended Operating Conditions). The passages below show typical application examples with different
output voltage settings and guidance for external component choices.
9.2 Typical Applications
9.2.1 TPS65131-Q1 With VPOS = 10.5 V, VNEG = –10 V
L1
4.7 µH
D1
VI
VPOS
Q1
C4
22 µF
C1
4.7 µF
R1
C9
VPOS
FBP
INP
BSW
VREF
R2
C8
220 nF
R4
R3
TPS65131-Q1
FBN
INN
VIN
C10
VNEG
R7
100 Ω
ENP
PSP
ENN
PSN
VNEG
OUTN
CN
C3
100 nF
C2
4.7 µF
D2
L2
4.7 µH
C5
22 µF
C6 C7
10nF 4.7nF
CP
AGND
PGND
Copyright © 2017, Texas Instruments Incorporated
图 6. Typical Application Schematic With VPOS = 10.5 V, VNEG = –10 V
9.2.1.1 Design Requirements
This design example uses the following parameters:
表 2. Design Parameters
Design Parameter
Example Value
Input voltage range
2.7 V to 5.5 V
R1 = 1 MΩ
R2 = 130 kΩ
C9 = 6.8 pF
Boost converter output
voltage, VPOS
10.5 V
12
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
表 2. Design Parameters (接下页)
Design Parameter
Example Value
R3 = 1 MΩ
R4 = 121.2 kΩ
C10 = 7.5 pF
Inverting converter output
voltage, VNEG
–10 V
In this example, the converters operate with power-save mode both enabled and disabled (see Power-Save
Mode).
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Programming the Output Voltage
9.2.1.2.1.1 Boost Converter
An external resistor divider adjusts the output voltage of the TPS65131-Q1 boost converter stage. Connect this
divider to the FBP pin. The typical value of the voltage at the FBP pin is the reference voltage, which is 1.213 V.
The maximum recommended output voltage at the boost converter is 15 V. To achieve appropriate accuracy, the
current through the feedback divider should be about 100 times higher than the current into the FBP pin. Typical
current into the FBP pin is 0.05 µA, and the voltage across R2 is 1.213 V. Based on those values, the
recommended value for R2 should be lower than 200 kΩ in order to set the divider current at 5 µA or higher.
Calculate the value of resistor R1, as a function of the needed output voltage (VPOS), with 公式 1:
≈
∆
«
’
VPOS
R1= R2ì
-1
÷
◊
V
ref
(1)
In this example, with R2 = 130 kΩ, choose R1 = 1 MΩ to set VPOS = 10.5 V.
9.2.1.2.1.2 Inverting Converter
An external resistor divider adjusts the output voltage of the TPS65131-Q1 inverting converter stage. Connect
this divider to the FBN pin. Unlike the feedback divider at the boost converter, the reference point of the feedback
divider is not GND, but Vref. So the typical value of the voltage at the FBN pin is 0 V. The minimum
recommended output voltage at the inverting converter is –15 V. Feedback divider current considerations are
similar to the considerations for the boost converter. For the same reasons, the feedback divider current should
be in the range of 5 µA or higher. The voltage across R4 is 1.213 V. Based on those values, the recommended
value for R4 should be lower than 200 kΩ in order to set the divider current at the required value.
Calculate the value of resistor R3, as a function of the needed output voltage (VNEG), with 公式 2:
≈
∆
«
’
÷
VNEG
V
R3 = -R4ì
ref ◊
(2)
In this example, with R4 = 121.2 kΩ kΩ, choose R3 = 1 MΩ to set VNEG = –10 V.
9.2.1.2.2 Inductor Selection
An inductive converter normally requires two main passive components to store energy during the conversion.
Therefore, each converter requires an inductor and a storage capacitor. To select the right inductor, it is
recommended to keep the possible peak inductor current below the current-limit threshold of the power switch in
the chosen configuration. For example, the current-limit threshold of the switch for the boost converter and for the
inverting converters is nominally 1950 mA. The highest peak current through the switches and the inductor
depends on the output load (IPOS, INEG), the input voltage (VI), and the output voltages (VPOS, VNEG). Use 公式 3
to estimate the peak inductor current in the boost converter, I(L-P). 公式 4 shows the corresponding formula for the
inverting converter, I(L-N)
.
VPOS
I(L-P)
=
ìIPOS
V ì0.64
I
(3)
(4)
V - VNEG
I
I(L-N)
=
ìINEG
V ì0.64
I
版权 © 2012–2017, Texas Instruments Incorporated
13
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the
losses in the inductor, as well as output voltage ripple and EMI. But in the same way, output voltage regulation
gets slower, causing higher voltage changes during fast load changes. In addition, a larger inductor usually
increases the total system cost. Keep those parameters in mind and calculate the possible inductor value with 公
式 5 for the boost converter (L1) and 公式 6 for the inverting converter (L2).
V ì V
- V
I
(
)
I
POS
L1=
DI(L-P) ì f ì VPOS
(5)
V ì VNEG
I
L2 =
DI(L-N) ì f ì V
- V
I
NEG
(6)
The parameter f is the switching frequency. For the boost converter, ΔI(L-P) is the ripple current in the inductor,
that is, 20% of I(L-P). Accordingly, for the inverting converter, ΔI(L-N) is the ripple current in the inductor, that is,
20% of I(L-N). VI is the input voltage, which is 3.3 V in this example. So, the calculated inductance value for the
boost inductor is 5.1 µH and for the inverting converter inductor is 5.1 µH. With these calculated values and the
calculated currents, it is possible to choose a suitable inductor.
In typical applications, the recommendation is to choose a 4.7-µH inductor. The device is optimized to work with
inductance values between 3.3 µH and 6.8 µH. Nevertheless, operation with higher inductance values may be
possible in some applications. Perform detailed stability analysis in this case. Be aware of the possibility that load
transients and losses in the circuit can lead to higher currents than estimated in 公式 3 and 公式 4. Also, the
losses caused by magnetic hysteresis and conductor resistance are a major parameter for total circuit efficiency.
The following table shows inductors from different suppliers used with the TPS65131-Q1 converter:
表 3. List of Inductors
VENDOR(1)
INDUCTOR SERIES
B8246284-G4
7447789XXX
744031XXX
VLF3010
EPCOS
Wurth Elektronik
TDK
VLF4012
Cooper Electronics Technologies
SD12
(1) See Third-party Products Disclaimer
9.2.1.2.3 Capacitor Selection
9.2.1.2.3.1 Input Capacitor
As a recommendation, choose an input capacitors of at least 4.7 µF for the input of the boost converter (INP)
and accordingly for the input of the inverting converter (INN). This improves transient behavior of the regulators
and EMI behavior of the total power-supply circuit. Choose a ceramic capacitor or a tantalum capacitor. For the
use of a tantalum capcitor, an additonal, smaller ceramic capacitor (100 nF) in parallel is required. Place the
input capacitor(s) close to the input pins.
9.2.1.2.3.2 Output Capacitors
One of the major parameters necessary to define the capacitance value of the output capacitor is the maximum
allowed output voltage ripple of the converter. Two parameters, which are the capacitance and the equivalent
series resitance (ESR), affect this ripple. It is possible to calculate the minimum capacitance needed for the
defined ripple, supposing that the ESR is zero. Use 公式 7 for the boost-converter output capacitor (C4min) and
公式 8 for the inverting-converter output capacitor (C5min).
IPOS ì V
- V
I
(
)
POS
C4min =
C5min =
f ì DVPOS ì VPOS
INEG ì VNEG
f ì DVNEG ì V
(7)
- V
I
NEG
(8)
14
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
The parameter f is the switching frequency. ΔVPOS and ΔVNEG are the maximum allowed ripple voltages for each
converter.
Choosing a ripple voltage in the range of 10 mV requires a minimum capacitance of 12 µF. The total ripple is
larger due to the ESR of the output capacitor. Use 公式 9 for the boost converter and 公式 10 for the inverting
converter to calculate this additional ripple component.
DV
= IPOS ìR(ESR-C4)
(ESR-P)
(9)
DV
= INEG ìR(ESR-C5)
(ESR-N)
(10)
In this example, an additional ripple of 2 mV is the result of using a typical ceramic capacitor with an ESR in the
10-mΩ range. The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the
ESR of the capacitor. In this example, the total ripple is 10 mV.
Load transients can create additional ripple. When the load current increases rapidly, the output capacitor must
provide the additional current until the inductor current increases by the control loop which sets a higher on-time
(duty cycle) of the main switch. The higher duty cycle results in longer inductor charging periods. The inductance
itself also limits the rate of increase of the inductor current. When the load current decreases rapidly, the output
capacitor must store the excess energy (stored in the inductor) until the regulator has decreased the inductor
current by reducing the duty cycle. The recommendation is to use higher capacitance values, as the foregoing
calculations show.
9.2.1.2.4 Rectifier Diode Selection
Both converters (the boost and inverting converter) require rectifier diodes, D1 and D2. As a recommendation, to
reduce losses, use Schottky diodes. The forward current rating needed is equal to the maximum output current.
Consider that the maximum currents, IPOSmax and INEGmax, might differ for VPOS and VNEG when choosing the
diodes.
9.2.1.2.5 External P-MOSFET Selection
During shutdown, when connected to a power supply, a path from the power supply to the positive output
conducts through the inductor and an external diode. Optionally, in oder to fully disconnect the positive output
VPOS during shutdown, add an external p-MOSFET (Q1). The BSW pin controls the gate of the p-MOSFET.
When choosing a proper p-MOSFET, the VGS and VGD voltage ratings must cover the input voltage range, the
drain current rating must not be lower than the maximum input current flowing into the application, and conditions
of the p-MOSFET operating area must fit.
If there is no intention to use an external p-MOSFET, leave the BSW pin floating.
9.2.1.2.6 Stabilizing the Control Loop
9.2.1.2.6.1 Feedforward Capacitors
As a recommendation, to speed up the control loop, place feedforward capacitors in the feedback divider, parallel
to R1 (boost converter) and R3 (inverting converter). 公式 11 shows how to calculate the appropriate value for
the boost converter, and 公式 12 for the inverting converter.
6.8 ꢀs
C9 =
(11)
(12)
7.5 ꢀs
C10 =
R3
In this application example, C9 = 6.8 pF and C10 = 7.5 pF match the choices of R1 and R3.
To avoid coupling noise into the control loop from the feedforward capacitors, it is possible to place a series
resistor to limit the bandwidth of the feedforward effect. Any value between 10 kΩ and 100 kΩ is suitable. The
higher the resistance, the lower the noise coupled into the control loop system.
版权 © 2012–2017, Texas Instruments Incorporated
15
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
9.2.1.2.6.2 Compensation Capacitors
The device features completely internally compensated control loops for both converters. The internal
feedforward system has built-in error correction which requires external capacitors. As a recommendation, use a
10-nF capacitor at the CP pin of the boost converter and a 4.7-nF capacitor at the CN pin of the inverting
converter.
9.2.1.3 Analog Supply Input Filter
To ensure a noise free voltage supply of the IC, it is recommended to add an RC or LC filter between IIN and
VIN pins.
9.2.1.3.1 RC-Filter
For most applications an RC filter can be used with a resistance value of 100 Ω minimum and capacitor value of
0.1 µF as in the application example 图 6.
9.2.1.3.2 LC-Filter
For applications where input voltages VI with a fast rising edge (slew rate ≥ 275 mV/µs) are expected, it is
recommended to replace the resistor R7 with a ferrite bead to minimize the delay between the signals on IIN and
VIN. A ferrite bead with the lowest possible DCR and a proper current rating should be selected -
BLM18KG101TN1 for example. A conservative approach for the current rating specification is to set it at 1.5
times or twice the maximum input current.
表 4. List of Ferrite Beads
VENDOR
FERRITE BEAD SERIES
Murata
BLMxKG
9.2.1.4 Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues, such as thermal coupling, airflow, added
heatsinks and convection surfaces, and the presence of heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance follow.
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow to the system
The recommended device junction temperature range, TJ, is –40°C to 125°C. The thermal resistance of the 24-
pin QFN, 4–mm × 4–mm package (RGE) is RθJA = 34.1°C/W. The recommended operating ambient temperature
range for the device is TA = –40°C to 105°C. Use 公式 13 to calculate the maximum power dissipation, PDmax,
as a function of TA. In this equation, use TJ = 125°C to operate the device within the recommended temperature
range, use TJ = T(TS) to determine the absolute maximum threshold when the device might go into thermal
shutdown. If the maximum ambient temperature of the application is lower, more heat dissipation is possible.
TJ - TA
RqJA
PD max =
(13)
16
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
9.2.1.5 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VPOS = 10.5 V PSM OFF
VPOS = 10.5 V PSM ON
VPOS = 10.5 V PSM OFF
VPOS = 10.5 V PSM ON
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
D005
D006
Power-save mode
on and off
VI = 3.3 V
VPOS = 10.5 V
Power-save mode
on and off
VI = 5 V
VPOS = 10.5 V
图 7. Boost Converter (VPOS) Efficiency vs Output Current
图 8. Boost Converter (VPOS) Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
VNEG = -10 V PSM OFF
10
VNEG = -10 V PSM OFF
10
VNEG = -10 V PSM ON
VNEG = -10 V PSM ON
0
0.001
0
0.001
0.01
0.1
1
0.01
0.1
1
Output Current (A)
Output Current (A)
D007
Power-save mode
on and off
D008
Power-save mode
on and off
VI = 3.3 V
VNEG = –10 V
VI = 5 V
VNEG = –10 V
图 9. Inverting Converter (VNEG) Efficiency vs Output
图 10. Inverting Converter (VNEG) Efficiency vs Output
Current
Current
版权 © 2012–2017, Texas Instruments Incorporated
17
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
11
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
VPOS = 10.5 V PSM OFF
VPOS = 10.5 V PSM ON
VPOS = 10.5 V PSM OFF
VPOS = 10.5 V PSM ON
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Output Current (A)
Output Current (A)
D009
D010
VI = 3.3 V
VPOS = 10.5 V
Power-save mode
on and off
VI = 5 V
VPOS = 10.5 V
Power-save mode
on and off
图 11. Boost Converter (VPOS) Output Voltage vs Output
图 12. Boost Converter (VPOS) Output Voltage vs Output
Current
Current
-9.5
-9.6
-9.5
-9.6
-9.7
-9.7
-9.8
-9.8
-9.9
-9.9
-10
-10
-10.1
-10.2
-10.3
-10.1
-10.2
-10.3
VNEG = -10 V PSM OFF
-10.4
VNEG = -10 V PSM OFF
-10.4
VNEG = -10 V PSM ON
VNEG = -10 V PSM ON
-10.5
-10.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
D011
D012
VI = 3.3 V
VNEG = –10 V
Power-save mode
on and off
VI = 5 V
VNEG = –10 V
Power-save mode
on and off
图 13. Inverting Converter (VNEG) Output Voltage vs Output
图 14. Inverting Converter (VNEG) Output Voltage vs Output
Current
Current
Output Voltage 50 mV/div
Inductor Current 200 mA/div
Output Voltage 10 mV/div
Inductor Current 200 mA/div
Time = 400 ns/div
Time = 20 ꢀs/div
VI = 3.3 V
VPOS = 10.5 V
IPOS = 200 mA
Power-save mode
off
VI = 3.3 V
VPOS = 10.5 V
IPOS = 20 mA
Power-save mode
on
图 15. Boost Converter (VPOS) Output Ripple
图 16. Boost Converter (VPOS) Output Ripple
18
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
Output Voltage 10 mV/div
Inductor Current 100 mA/div
Time = 40 ꢀs/div
Output Voltage 10 mV/div
Inductor Current 100 mA/div
Time = 1 ꢀs/div
VI = 3.3 V
VNEG = –10 V
INEG = 200 mA
Power-save mode
off
VI = 3.3 V
VNEG = –10 V
INEG = 20 mA
Power-save mode
on
图 17. Inverting Converter (VNEG) Output Ripple
图 18. Inverting Converter (VNEG) Output Ripple
Output Current 20 mA/div
Offset = 200 mA
Output Current 20 mA/div
Offset = 150 mA
Output Voltage 50 mV/div
Output Voltage 100 mV/div
Time = 1 ms/div
Time = 1 ms/div
VI = 3.3 V
VPOS = 10.5 V
VI = 3.3 V
VNEG = –10 V
IPOS = 200 mA to 250 mA
INEG = 150 mA to 200 mA
图 19. Boost Converter (VPOS) Load Transient Response
图 20. Inverting Converter (VNEG) Load Transient Response
Input Voltage 500 mV/div
Offset = 3 V
Input Voltage 500 mV/div
Offset = 3 V
Output Voltage 200 mV/div
Output Voltage 500 mV/div
Time = 2 ms/div
Time = 2 ms/div
VI = 3 V to 3.6 V
VPOS = 10.5 V
IPOS = 150 mA
VI = 3 V to 3.6 V
VNEG = –10 V
INEG = 100 mA
图 21. Boost Converter (VPOS) Line Transient Response
图 22. Inverting (VNEG) Converter Line Transient Response
版权 © 2012–2017, Texas Instruments Incorporated
19
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
Input Voltage 2 V/div
Input Voltage 2 V/div
Output Voltage 5 V/div
Output Voltage 5 V/div
Inductor Current 1 A/div
Inductor Current 500 mA/div
Voltage at Switching Pin 10 V/div
Voltage at Switching Pin 10 V/div
Time = 200 ꢀs/div
Time = 400 ꢀs/div
VI = 3.3 V
VPOS = 10.5 V
IPOS = 46 mA
VI = 3.3 V
VNEG = –10 V
INEG = 150 mA
图 23. Boost Converter (VPOS) Start-Up Into Load
图 24. Inverting Converter (VNEG) Start-Up Into Load
Enabling Boost Converter
2 V/div
Output Voltage, Boost Converter
5 V/div
Enabling Inverter Converter
2 V/div
Output Voltage, Inverting Converter
10 V/div
Time = 1 ms/div
VI = 3.3 V
VPOS = 10.5 V
VNEG = –10 V
IPOS = INEG= 160 mA
图 25. Boost and Inverting Converter Start-Up Into Load
9.2.2 TPS65131-Q1 With VPOS = 5.5 V, VNEG = –5 V
9.2.2.1 Design Requirements
The design procedure for this setup is similar to the first example, see Detailed Design Procedure. Change the
feedback dividers to set the output voltage, see Programming the Output Voltage. Further, choose the feed-
forward capacitors according to Feedforward Capacitors. 表 5 shows the components being changed. See 图 6.
表 5. Design Parameters
Design Parameter
Example Value
Input voltage range
2.7 V to 5.5 V
R1 = 390 kΩ
R2 = 110 kΩ
C9 = 18 pF
Boost converter output
voltage, VPOS
5.5 V
–5 V
R3 = 620 kΩ
R4 = 150 kΩ
C10 = 12 pF
Inverting converter output
voltage, VNEG
20
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
In this example, the converters are operated with power-save mode both enabled and disabled (see Power-Save
Mode).
9.2.2.2 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VPOS = 5.5 V PSM OFF
VPOS = 5.5 V PSM ON
VPOS = 5.5 V PSM OFF
VPOS = 5.5 V PSM ON
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
D013
D014
VI = 3.3 V
VPOS = 5.5 V
Power-save mode
on and off
VI = 5 V
VPOS = 5.5 V
Power-save mode
on and off
图 26. Boost Converter (VPOS) Efficiency vs Output Current
图 27. Boost Converter (VPOS) Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
VNEG = -5 V PSM OFF
10
VNEG = -5 V PSM OFF
10
VNEG = -5 V PSM ON
VNEG = -5 V PSM ON
0
0.001
0
0.001
0.01
0.1
1
0.01
0.1
1
Output Current (A)
Output Current (A)
D015
Power-save mode
on and off
D016
Power-save mode
on and off
VI = 3.3 V
VNEG = –5 V
VI = 5 V
VNEG = –5 V
图 28. Inverting Converter (VNEG) Efficiency vs Output
图 29. Inverting Converter (VNEG) Efficiency vs Output
Current
Current
版权 © 2012–2017, Texas Instruments Incorporated
21
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
6
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5
6
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5
VPOS = 5.5 V PSM OFF
VPOS = 5.5 V PSM ON
VPOS = 5.5 V PSM OFF
VPOS = 5.5 V PSM ON
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Output Current (A)
D017
D018
VI = 3.3 V
VPOS = 5.5 V
Power-save mode
on and off
VI = 5 V
VPOS = 5.5 V
Power-save mode
on and off
图 30. Boost Converter (VPOS) Output Voltage vs Output
图 31. Boost Converter (VPOS) Output Voltage vs Output
Current
Current
-4.5
-4.5
VNEG = -5 V PSM OFF
VNEG = -5 V PSM ON
VNEG = -5 V PSM OFF
VNEG = -5 V PSM ON
-4.6
-4.7
-4.8
-4.9
-5
-4.6
-4.7
-4.8
-4.9
-5
-5.1
-5.2
-5.3
-5.4
-5.5
-5.1
-5.2
-5.3
-5.4
-5.5
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Output Current (A)
Output Current (A)
D019
D020
VI = 3.3 V
VNEG = –5 V
Power-save mode
on and off
VI = 3.3 V
VNEG = –5 V
Power-save mode
on and off
图 32. Inverting Converter (VNEG) Output Voltage vs Output
图 33. Inverting Converter (VNEG) Output Voltage vs Output
Current
Current
9.2.3 TPS65131-Q1 With VPOS = 15 V, VNEG = –15 V
9.2.3.1 Design Requirements
The design procedure for this setup is similar to the first example, see Detailed Design Procedure. Change the
feedback dividers to set the output voltage, see Programming the Output Voltage. Further, choose the
feedforward capacitors according to Feedforward Capacitors. 表 6 shows the components being changed. See
图 6.
表 6. Design Parameters
Design Parameter
Example Value
Input voltage range
2.7 V to 5.5 V
R1 = 975 kΩ
R2 = 85.8 kΩ
C9 = 6.8 pF
Boost converter output
voltage, VPOS
15 V
R3 = 1.3 MΩ
R4 = 104.8 kΩ
C10 = 5.6 pF
Inverting converter output
voltage, VNEG
–15 V
22
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
In this example, the converters operate with power-save mode both enabled and disabled (see Power-Save
Mode).
9.2.3.2 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VPOS = 15 V PSM OFF
VPOS = 15 V PSM ON
VPOS = 15 V PSM OFF
VPOS = 15 V PSM ON
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
D021
D022
VI = 3.3 V
VPOS = 15 V
Power-save mode
on and off
VI = 5 V
VPOS = 15 V
Power-save mode
on and off
图 34. Boost Converter (VPOS) Efficiency vs Output Current
图 35. Boost Converter (VPOS) Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
VNEG = -15 V PSM OFF
10
VNEG = -15 V PSM OFF
10
VNEG = -15 V PSM ON
VNEG = -15 V PSM ON
0
0.001
0
0.001
0.01
0.1
1
0.01
0.1
1
Output Current (A)
Output Current (A)
D023
Power-save mode
on and off
D024
Power-save mode
on and off
VI = 3.3 V
VNEG = –15 V
VI = 5 V
VNEG = –15 V
图 36. Inverting Converter (VNEG) Efficiency vs Output
图 37. Inverting Converter (VNEG) Efficiency vs Output
Current
Current
版权 © 2012–2017, Texas Instruments Incorporated
23
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
15.5
15.4
15.3
15.2
15.1
15
15.5
15.4
15.3
15.2
15.1
15
VPOS = 15 V PSM OFF
VPOS = 15 V PSM ON
VPOS = 15 V PSM OFF
VPOS = 15 V PSM ON
14.9
14.8
14.7
14.6
14.5
14.9
14.8
14.7
14.6
14.5
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
D025
D026
VI = 3.3 V
VPOS = 15 V
Power-save mode
on and off
VI = 5 V
VPOS = 15 V
Power-save mode
on and off
图 38. Boost Converter (VPOS) Output Voltage vs Output
图 39. Boost Converter (VPOS) Output Voltage vs Output
Current
Current
-14.5
-14.5
VNEG = -15 V PSM OFF
VNEG = -15 V PSM ON
-14.6
-14.7
-14.8
-14.9
-15
-14.6
-14.7
-14.8
-14.9
-15
-15.1
-15.2
-15.3
-15.4
-15.5
-15.1
-15.2
-15.3
-15.4
-15.5
VNEG = -15 V PSM OFF
VNEG = -15 V PSM ON
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current (A)
Output Current (A)
D027
D028
VI = 3.3 V
VNEG = –15 V
Power-save mode
on and off
VI = 5 V
VNEG = –15 V
Power-save mode
on and off
图 40. Inverting Converter (VNEG) Output Voltage vs Output
图 41. Inverting Converter (VNEG) Output Voltage vs Output
Current
Current
24
版权 © 2012–2017, Texas Instruments Incorporated
TPS65131-Q1
www.ti.com.cn
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
10 Power Supply Recommendations
The TPS65131-Q1 input voltage ranges from 2.7 V to 5.5 V. Consequently, the supply can come, for example,
from a 3.3-V or 5-V rail. If the device starts into load during the Soft Start phase, the drawn input current can be
higher than during post-start operation. Consider the application requirements when selecting the power supply.
To avoid unintended toggling of the Undervoltage Lockout, connect the TPS65131-Q1 via a low-impedance path
to the power supply.
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. Improper layout might show the symptoms of poor line or load regulation, ground
and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. Therefore, use wide
and short traces for the main current paths and for the power ground tracks. The input capacitors (C1, C2, C3),
output capacitors (C4, C5), the inductors (L1, L2), and the rectifying diodes (D1, D2) should be placed as close
as possible to the IC to keep parasitic inductances low. Use a wide PGND plane. Connect the analog ground pin
(AGND) to the PGND plane. Further, connect the PGND plane with the exposed thermal pad. Place the feedback
dividers as close as possible to the control pin (boost converter) or the VREF pin (inverting converter) of the IC.
图 42 provides an layout example which is recommended to be followed.
11.2 Layout Example
C8
R4
R3
C10
C7
AGND
NC
19
20
12
NC
PGND
L2
D2
C6
R2
11 PSN
CP 21
22
10
9
ENN
PSP
ENP
BSW
FBP
VPOS 23
8
C9
R1
PGND
C4
24
7
INP
C5
D1
U1
R7
VNEG
C3
VI
PGND
C2
VPOS
L1
C1
Q1
图 42. TPS65131-Q1 Layout Recommendation
版权 © 2012–2017, Texas Instruments Incorporated
25
TPS65131-Q1
ZHCSAI3E –MAY 2012–REVISED MARCH 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 商标
PowerPAD is a trademark of Texas Instruments.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件提供的最新数据。这些数据会在无通知且不对本
文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧导航栏。
26
版权 © 2012–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65131TRGERQ1
ACTIVE
VQFN
RGE
24
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
2U65131
Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65131TRGERQ1
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGE 24
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TPS65131TRGERQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明