TPS65149RSHR [TI]

用于使用 ASG/GIP 技术的 LCD 面板的 LCD 偏置解决方案 | RSH | 56 | -40 to 85;


型号：	TPS65149RSHR
厂家：	TEXAS INSTRUMENTS
描述：	用于使用 ASG/GIP 技术的 LCD 面板的 LCD 偏置解决方案 \| RSH \| 56 \| -40 to 85 CD
文件：	总50页 (文件大小：964K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TI Information — Selective Disclosure

TPS65149

www.ti.com

SLVSAC1 –SEPTEMBER 2010

LCD Bias Solution for Monitors

Check for Samples: TPS65149

The device integrates a boost converter to generate

the source driver supply voltage (V_AVDD), positive and

negative charge pump controllers to generate gate

FEATURES

•

3 V to 6 V Input Voltage Range

Boost Converter With 4 A Switch Current Limit

Boost Converter Output Voltages up to 18 V

Boost Converter Overvoltage Protection

driver ON (V_GH

)

and OFF (V_GL

)

voltages,

programmable V_COMgenerator, and an 8-channel

level shifter in a single IC. The positive charge pump

controller supports temperature compensation to

reduce V_GHat high temperatures.

Selectable Switching Frequency (640 kHz or

1.2 MHz)

In addition to the above functions, the TPS65149

generates two signals to discharge the display panel

during power-down, plus an additional active-low

XAO reset output.

•

Programmable Boost Converter Soft-Start

Temperature-Compensated Positive Charge

Pump Controller

•

Negative Charge Pump Controller

Eight Channel Level Shifter

Two Panel Discharge Signals

XAO Reset Signal

Supply sequencing during power-up can be controlled

by an externally generated enable signal.

V_IN

Boost

Converter

V_AVDD

Digitally Programmable V_COMBuffer

Thermal Shutdown

Negative

V_GL

Charge Pump

56-Pin 7×7 mm QFN Package

Positive

Charge Pump

(Temp. Compensated)

V_GH

APPLICATIONS

•

LCD Monitors using ASG/GIP Technology

I²C

Programmable

VCOM

V_COM

DESCRIPTION

OUT

Level

Shifters

The TPS65149 provides a highly integrated LCD bias

solution, primarily intended for monitor applications

using ASG/GIP technology.

V_DET

DISCHARGE

Reset

XAO

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TI Information — Selective Disclosure

TPS65149

SLVSAC1 –SEPTEMBER 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

T_A

ORDERING

PACKAGE

PACKAGE MARKING

–40°C to 85°C

TPS65149RSHR

56-Pin 7×7 QFN

TPS65149

(1) The device is supplied taped and reeled, with 3000 devices per reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

FBN, VL, WP, SCL, SDA, FBP, RESETIN, CLKIN1, CLKIN2, CLKIN3, CLKIN4, CLKIN5,

CLKIN6, FBPH, FREQ, COMP, RHVS, FB, SS, GD, VIN, DRVN, VDET, STVIN, RNTC,

RSET, EN, XAO

DVRO, AVDD, SW, HVS

DRVP, VGH

Pin Voltage⁽²⁾

VGL1, VGL2

–20

DSCHG1, DSCHRG2, STVOUT, RESETOUT, CLKOUT1, CLKOUT2, CLKOUT3,

CLKOUT4, CLKOUT5, CLKOUT6

–20 to 40

Human Body Model

200

ESD Rating

Machine Model

Charged Device Model

Continuous Power Dissipation

Ambient temperature

500

P_D

See Thermal Table

–40 to 85

–40 to 150

–65 to 150

300

°C

T_A

T_J

Junction temperature

T_STG

Storage temperature

Lead temperature (soldering, 10 seconds)

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) With respect to the AGND and LGND pins.

THERMAL INFORMATION

TPS65149

THERMAL METRIC⁽¹⁾

QFN

56 PINS

27.4

20.4

7.1

UNITS

q_JA

Junction-to-ambient thermal resistance

q_JC(top)

q_JB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.5

y_JB

7.0

q_JC(bottom)

2.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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SLVSAC1 –SEPTEMBER 2010

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

V_IN

Input voltage range

7⁽¹⁾

–3

V_AVDD

V_GH

V_GL1

V_GL2

V_DET

I_SET

C_L

Boost converter output voltage range

Level shifter positive supply voltage range

Level shifter negative supply voltage range

Panel discharge threshold voltage

Programmable V_COMset current

V_Ldecoupling capacitance

–15

0.1

100

0.5

220

°C

–40

T_A

Operating ambient temperature

Operating junction temperature

T_J

125

(1) Or V_IN+ 1 V, whichever is lower.

ELECTRICAL CHARACTERISTICS

V_IN= 5 V; V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= V_GL2= –10 V, T_A= –40°C to 85°C; FREQ = high. Typical values are at 25°C

(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

POWER SUPPLY

I_IN

V_INsupply current

Device not switching, V_FB= V_L+5%

0.75

0.04

I_SUP

I_GH

Positive supply current

STVIN = 0 V, RESETIN = 0 V, CLKIN1-CLKIN6 = 0 V

0.26

I_GL1

I_GL2

V_UVLO

V_HYS

V_L

0.035

0.046

2.5

Negative supply current

UVLO threshold

V_INrising

V_INfalling

I_L= 100 µA

UVLO hysteresis

0.25

External reference voltage

1.215

250

1.24 1.265

I_L

Reference voltage maximum output current V_L= 1.24 V ±2%

µA

CONTROL SIGNALS (EN, HVS, FREQ, WP)

V_IH

High input voltage threshold

Low input voltage threshold

Pull-up resistor

EN, HVS, FREQ, WP rising

EN, HVS, FREQ, WP falling

EN, FREQ

2.0

V_IL

0.5

R_PULL-UP

R_PULL-DOWN

kΩ

Pull-down resistor

HVS, WP

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TPS65149

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ELECTRICAL CHARACTERISTICS (continued)

V_IN= 5 V; V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= V_GL2= –10 V, T_A= –40°C to 85°C; FREQ = high. Typical values are at 25°C

(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

BOOST CONVERTER (AVDD)

V_AVDD

Output voltage

I_AVDD= 0.5 A

V_AVDDrising

V_AVDDfalling

18⁽¹⁾

V_OVP

Overvoltage threshold

Overvoltage hysteresis

18.0

19.0

0.3

2.6

0.36

20.0

V_OVP(HYS)

V_AVDDrising, during power-up

V_FBfalling, during normal operation

V_FBrising

V_SCP(AVDD)

Short-circuit threshold voltage

Power good threshold

Short circuit timer

% of

V_REF

V_FB(PG)

V_FBfalling

91.7

OFF time

t_SCP(AVDD)

ON time

V_FB

I_FB

Feedback regulation voltage

Feedback input bias current

Switch ON resistance

1.228

–100

1.240 1.252

100

V_FB= 1.24V

r_DS(ON)

I_LIM

I_LK

V_IN= 5V, I_SW= I_LIM

0.13

4.6

0.18

5.6

Switch current limit

4.0

Switch leakage current

EN = 0V, V_SW= 18.5V

V_SS= 1.24V

µA

I_SS

Soft-start capacitor charge current

4.4

FREQ connected to V_IN

FREQ connected to 0V

V_IN= 4 V to 6 V, I_AVDD= 0.5 A

I_AVDD= 0.1 A to 0.5 A

HVS = 5 V, RHVS = 0 V

900

470

1200 1500

f_SW

Oscillator frequency

kHz

640

0.01

0.2

790

Line regulation

%/V

%/A

Load regulation

R_HVS

HVS switch ON resistance

400

500

600

GATE DRIVE (Isolation Switch)

I_GD

Gate drive sink current

Gate drive internal pull-up resistance

EN = 5 V, V_GD= TBD V

EN = 0 V, I_GD= TBD mA

µA

R_GD

kΩ

POSITIVE CHARGE PUMP CONTROLLER (VGH)

V_DRVP

Base drive voltage range

With external pull-up resistor

Normal operation, sinking, V_FBP= 1.575 V,

V_DRVP= 28 V

2.5

µA

I_DRVP

Base drive sink current

Short-circuit operation, sinking, V_FBP= 0 V, V_DRVP= 28 V

Lower limit; V_RNTC= 2 V, V_FBPH= 1.75 V

Lower limit; V_RNTC= 1.5 V, V_FBPH= 1.75 V

Lower limit; V_RNTC= 1.0 V, V_FBPH= 1.75 V

V_FBPrising, during power-up

1.663

1.425

1.178

1.75 1.838

1.50 1.575

1.24 1.302

124

V_FBP

Feedback regulation voltage

V_FBP(SCP)

Short circuit threshold voltage

Power good threshold

V_FBPfalling, during normal operation

V_FBPrising

340

97.5

% of

V_REF

V_FBP(PG)

V_FBPfalling

92.5

t_SCP(VGH)

I_FBP

I_RNTC

I_FBPH

Short circuit timer

Starts from boost converter power good

V_RNTC= 1 V, V_FBPH= 1.75 V, V_FBP= 1.24 V

V_RNTC= 1.5 V, matched to I_FBPH; T_A= 25 °C

V_FBPH= 1.75 V, trimnmed; at T_A= 25 °C

I_GH= 1 mA to 50 mA

FBP input bias current

RNTC output current

FBPH output current

Load regulation

–100

190

100

200

210

205

µA

195

µA

0.05

%/mA

(1) Limited by overvoltage protection function.

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SLVSAC1 –SEPTEMBER 2010

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 5 V; V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= V_GL2= –10 V, T_A= –40°C to 85°C; FREQ = high. Typical values are at 25°C

(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

NEGATIVE CHARGE PUMP CONTROLLER (VGL)

I_DRVN

Base drive current

Normal operation, sourcing, V_FBN= 25 mV, V_DRVN= 0.7V

2.5

µA

Short-circuit operation, sourcing, V_FBN= 1.116 V,

V_DRVN= 0.7 V

200

300

480

V_FBN

I_FBN

Feedback regulation voltage

FBN input bias current

I_DRVN= 1 mA, sourcing

V_FBN= 0 V

–15

–100

100

V_FBNfalling, during start-up

V_FBNrising, during normal operation

V_FBNfalling

794

817

2.8

V_FBN(SCP)

Short circuit threshold voltage

% of

V_REF

V_FBN(PG)

Power good threshold

Load regulation

V_FBNrising

7.5

I_GL1= 1 mA to 50 mA

0.05

%/mA

PROGRAMMABLE VCOM

SET_VR

SET_ZSE

SET_FSE

SET voltage resolution

Bits

LSB

V/V

SET zero-scale error

SET full-scale error

V_AVDDto V_SETvoltage ratio

Differential nonlinearity

0.165

0.8

Bits

DNL

t_WRITE

EEPROM write time

100

N_WRITE

Number of specified EEPROM write cycles

1000

cycles

THERMAL SHUTDOWN

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

138

°C

T_HYS

LEVEL SHIFTERS (CLK1 to CLK6)

V_UVLO

V_IH

UVLO threshold

V_GHrising.

5.0

0.5

7.5

10.0

1.5

Level shifter high level input threshold

Level shifter low level input threshold

High side ON resistance

V_CLKINxrising

V_IL

V_CLKINxfalling

I_CLKOUTx= 10 mA, sourcing

I_CLKOUTx= 10 mA, sinking

r_DS(ON)

Low side ON resistance

LEVEL SHIFTERS (STV, RESET)

V_IH

V_IL

Level shifter high level input threshold

V_STVIN, V_RESETINrising

1.5

Level shifter low level input threshold

High side ON resistance

V_STVIN, V_RESETINfalling

0.5

I_STVOUT, I_RESETOUT= 10 mA, sourcing

I_STVOUT, I_RESETOUT= 10 mA, sinking

r_DS(ON)

Low side ON resistance

DISCHARGE (DISCHRG1, DISCHRG2)

V_IL(DET)

V_HYS

Discharge threshold voltage

Discharge hysteresis

V_DETfalling

1.221

1.240 1.259

V_DETrising

High side ON resistance

Low side ON resistance

I_DSCHRG1, I_DSCHRG2= 10 mA, sourcing

I_DSCHRG1, I_DSCHRG2= 10 mA, sinking

r_DS(ON)

I²C INTERFACE

Bus address

4Fh

V_IL

Low level input voltage

High level input voltage

Low level output voltage

V_IN= 4 V to 6 V

Sinking 3 mA

0.7

V_IH

1.5

0.4

V_OL1

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SLVSAC1 –SEPTEMBER 2010

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DEVICE INFORMATION

PIN ASSIGNMENT

(TOP VIEW)

FBPH

COMP

AGND

CLKIN2

CLKIN3

CLKIN4

CLKIN5

CLKIN6

STVIN

RHVS

RESETIN

PGND

Exposed

Thermal Die

DSCHG1

RESETOUT

STVOUT

FREQ

CLKOUT6

CLKOUT5

CLKOUT4

CLKOUT3

VIN

XAO

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SLVSAC1 –SEPTEMBER 2010

PIN FUNCTIONS

I/O DESCRIPTION

NAME

NO.

Connecting a resistor between this pin and ground allows the maximum output voltage (i.e., at the voltage at

colder temperatures) of the positive charge pump to be set. A current of 200 µA flows out of this pin, and at

colder temperatures the positive charge pump regulates to a feedback voltage equal to this current multiplied

by the resistor connected between FBPH and ground.

FBPH

Connecting a suitable compensation network between this pin and ground allows the boost converter to be

optimized for stable operation and proper performance. A series RC network is adequate for most

applications.

COMP

AGND

Analog ground.

A capacitor connected between this pin and ground allows the start-up characteristic of the boost converter to

be controlled. Larger capacitor values lengthen the time required for the boost converter to reach full output

power capability and reduce the inrush current drawn from V_IN

A resistor connected between this pin and the FB pin allows the boost converter output voltage during high

voltage stress mode to be set.

RHVS

Boost converter feedback pin.

Power ground.

PGND

7, 8

9, 10

Boost converter switch node.

Boost converter frequency select pin. The boost converter's nominal switching frequency is 1.2 MHz when

FREQ=high and 640 kHz when FREQ=low. This pin features an internal pull-up and may be left floating if 1.2

MHz operation is desired.

FREQ

Gate drive for external isolation switch. This pin sinks a constant current when EN=high and is pulled up by a

resistor when EN=low.

Supply voltage. This pin should be decoupled using a 100 nF ceramic capacitor connected close to the VIN

pin.

VIN

XAO

Reset output. This open-drain output is pulled low when the voltage applied to the VDET pin is below the

internal reference voltage of 1.24 V.

The TPS65149 is enabled when EN=high and disabled when EN=low. Note that the panel discharge function

always works and is not disabled when EN=low.

Panel discharge detection. The TPS65149 enters discharge mode (all level shifter outputs and the two

discharge signals track V_GH) when the voltage applied to the VDET pin is below the internal reference

VDET

HVS

voltage. XAO is also pulled low when V_DET< V_REF

High voltage stress mode is selected when HVS=high and normal mode is selected when HVS=low. This pin

features an internal pull-down and may be left floating during normal operation.

This pin must be connected to the output of the boost converter. It is used for two main functions:

a) the internal reference for the programmable V_COMblock is derived from it

b) boost converter overvoltage and short-circuit conditions are detected by monitoring the voltage on it

This pin is a current sink whose current can be programmed via the I²C interface. It is typically connected to

an external resistor divider connected between AVDD and ground to generate an appropriate input voltage for

an external V_COMbuffer.

AVDD

DVRO

A resistor connected between this pin and ground sets the full-scale value of the current sink connected to

the DVRO pin. Smaller resistor values generate larger currents.

RSET

Data in the internal EEPROM can only be overwritten when WP=high. When WP=low, all write operates to

the EEPROM are prevented.

SCL

I/O I²C interface clock signal.

I/O I²C interface data signal.

SDA

N/A Not connected. Leave floating or connect to ground.

LGND

Level shifter ground connection.

Level shifter output

DSCHG2

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

CLKOUT5

CLKOUT6

STVOUT

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PIN FUNCTIONS (continued)

I/O DESCRIPTION

NAME

NO.

RESETOUT

DSCHG1

RESETIN

STVIN

Level shifter output

Level shifter input

CLKIN6

CLKIN5

CLKIN4

CLKIN3

CLKIN2

CLKIN1

Level shifter positive supply. This pin should be decoupled using a 0.1 µF to 10 µF ceramic capacitor

connected close to the VGH pin.

VGH

N/A Not connected. Leave floating or connect to ground.

Level shifter negative supply for all channels except DSCHRG2. This pin should be decoupled using a 0.1 µF

to 10 µF ceramic capacitor connected close to the VGL1 pin.

VGL1

Level shifter negative supply for DSCHRG2 channel. This pin should be decoupled using a 0.1 µF to 10 µF

ceramic capacitor connected close to the VGL2 pin.

VGL2

N/A Not connected. Leave floating or connect to ground.

FBN

Negative charge pump controller feedback pin.

This pin can be used to provide an accurate reference voltage for the negative charge pump. It cannot supply

large currents and is not intended to supply any other external circuitry. This pin should be decoupled using a

0.1 µF to 1 µF ceramic capacitor connected close to the VL pin.

DRVN

FBP

This pin provides the base drive current for an external NPN transistor used to regulate V_GL1

Positive charge pump controller feedback pin.

N/A Not connected. Leave floating or connect to ground.

This pin provides the base drive current for an external PNP transistor used to regulate V_GH

N/A Not connected. Leave floating or connect to ground.

DRVP

A thermistor-resistor network connected to this pin allows the temperature compensation characteristic of the

positive charge pump to be programmed.

RNTC

Exposed

Thermal Die

Connect to ground. The copper area of the ground plane must be large enough to ensure adequate thermal

performance.

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SLVSAC1 –SEPTEMBER 2010

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

BOOST CONVERTER

V_IN= 5 V, V_AVDD= 13.6 V, I_AVDD= 0 A to 1 A

Figure 1

Figure 2

Figure 3

Figure 4

Efficiency

V_IN= 5 V, V_AVDD= 18 V, I_AVDD= 0 A to 1 A

V_IN= 5 V, V_AVDD= 13.6 V, I_AVDD= 0 A to 0.8 A

V_IN= 3.5 V to 6.0 V, V_AVDD= 13.6 V, I_AVDD= 0.5 A

vs Load current

Frequency

vs Supply voltage

Undervoltage

Protection

f_SW=1.2MHz, L=4.7µH

V_IN= 5 V, V_AVDD= 13.6 V (10 V transient)

Figure 5

f_SW=640kHz, L=10µH

f_SW=1.2MHz, L=4.7µH

C_SS=22nF

V_IN= 5 V, V_AVDD= 13.6 V, I_AVDD= 250 mA/750 mA step

V_IN= 5 V, V_AVDD= 13.6 V, I_AVDD= 0.5 A

Figure 6

Figure 7

Figure 8

Load Transient

Response

Soft-start

Overvoltage

Protection

Duration = 75 ms

Figure 9

Duration = 75 ms

Duration = 25 ms

CCM operation

DCM operation

V_IN= 5 V, V_AVDD= 13.6 V, I_AVDD= 0.5 A

V_IN= 5 V, V_AVDD= 13.6V, I_AVDD= 0.1A

Figure 10

Figure 11

Figure 12

Figure 13

Short-Circuit

Protection

Switch Node

Waveform

POSITIVE CHARGE PUMP

f_SW= 640kHz, L = 10µH

f_SW= 1.2MHz, L = 4.7µH

Figure 14

Figure 15

Load Transient

Response

V_IN= 5V, V_AVDD= 13.6V, I_AVDD= 0.5A V_GH= 28V,

I_GH= 10 mA/50 mA step

V_IN= 4 V to 6 V, V_AVDD= 13.6 V, I_AVDD= 0.5A,

V_GH(COLD)= 28 V, V_GH(HOT)= 24 V, T_COLD= -10°C,

T_HOT= 10°C, I_GH= 25 mA

Temperature

Compensation

Figure 16

NEGATIVE CHARGE PUMP

f_SW= 640kHz, L = 10µH

f_SW= 1.2MHz, L = 4.7µH

Figure 17

Figure 18

Load Transient

Response

V_IN= 5 V, V_AVDD= 13.6 V, I_AVDD= 0.5 A, V_GL1= –10 V,

I_GL1= 10 mA/50 mA step

START-UP SEQUENCING

V_IN= 5V, V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= –10 V,

V_GL2= –6 V

Power-Up Sequence V_IN, V_AVDD, V_GH, V_GL1

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

V_IN, CLKOUTx, STVOUT,

Power-Up Sequence

V_IN= 5V, V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= –10 V,

V_GL2= –6 V

RESETOUT

V_IN= 5V, V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= –10 V,

V_GL2= –6 V

Power-Up Sequence V_IN, DSCHRG1, DSCHRG2, XAO

Power-Down

Sequence

V_IN, CLKOUTx, STVOUT,

RESETOUT

V_IN= 5V, V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= –10 V,

V_GL2= –6 V

Power-Down

Sequence

V_IN= 5V, V_AVDD= 13.6 V, V_GH= 28 V, V_GL1= –10 V,

V_GL2= –6 V

V_IN, DSCHRG1, DSCHRG2, XAO

LEVEL SHIFTERS

CLKOUTx

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Peak Output Current STVOUT, RESETOUT

V_GH= 28V, V_GL1= –10V, V_GL2= –6V, 10 nF load

DSCHRGx

CLKOUTx

Rise Time

Fall Time

STVOUT, RESETOUT

DSCHRGx

V_GH= 28 V, V_GL1= –10 V, V_GL2= –6 V, 47Ω + 10 nF load

CLKOUTx

STVOUT, RESETOUT

DSCHRGx

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BOOST CONVERTER EFFICIENCY (V_AVDD= 13.6 V)

BOOST CONVERTER EFFICIENCY (V_AVDD= 18 V)

100

FREQ = Low

FREQ = High

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

I_AVDD– Output Voltage Current – A

G001

G002

Figure 1.

Figure 2.

BOOST CONVERTER FREQUENCY vs. LOAD CURRENT

BOOST CONVERTER FREQUENCY vs. SUPPLY VOLTAGE

1400

FREQ = High

1200

1000

800

600

400

200

1200

1000

800

FREQ = Low

600

400

200

100

200

300

400

500

600

700

800

3.5

4.0

4.5

5.0

5.5

6.0

Output Current – mA

V_IN– Input Voltage – V

G003

G004

Figure 3.

Figure 4.

BOOST CONVERTER UNDERVOLTAGE PROTECTION

BOOST CONVERTER LOAD TRANSIENT RESPONSE

AV_DD

Converter Load

AV_DD

Converter O/P

I_AVDD

AV_DD

f_SW=640kHz, L=10µH

G005

G006

Figure 5.

Figure 6.

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BOOST CONVERTER LOAD TRANSIENT RESPONSE

BOOST CONVERTER SOFT-START

AV_DD

I_AVDD

G007

I_IN

f_SW=1.2MHz, L=4.7µH

G008

Figure 7.

Figure 8.

BOOST CONVERTER OVERVOLTAGE PROTECTION

BOOST CONVERTER SHORT-CIRCUIT PROTECTION

AV_DD

Short

Circuit

Duration

AV_DD

V_SW

V_GD

G009

G010

Figure 9.

Figure 10.

BOOST CONVERTER SHORT-CIRCUIT PROTECTION

BOOST CONVERTER SWITCH NODE WAVEFORM (CCM)

AV_DD

V_SW

V_GD

I_L

G011

G012

Figure 11.

Figure 12.

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BOOST CONVERTER SWITCH NODE WAVEFORM (DCM)

POSITIVE CHARGE PUMP LOAD TRANSIENT RESPONSE

V_GH

V_SW

I_GH

I_L

f_SW=640kHz, L=10µH

G014

G013

Figure 13.

Figure 14.

POSITIVE CHARGE PUMP TEMPERATURE

COMPENSATION

POSITIVE CHARGE PUMP LOAD TRANSIENT RESPONSE

28.5

V_GH(HOT)= 28 V

28.0

V_GH(COLD)= 24 V

T_COLD= –10 °C

27.5

T_HOT= 10 °C

V_GH

27.0

26.5

26.0

25.5

25.0

24.5

24.0

23.5

I_GH

f_SW=1.2MHz, L=4.7µH

-20

-15

-10

-5

Temperature – °C

G016

G015

Figure 15.

Figure 16.

NEGATIVE CHARGE PUMP LOAD TRANSIENT RESPONSE

V_GL

I_GL

f_SW=640kHz, L=10µH

f_SW=1.2MHz, L=4.7µH

G017

G018

Figure 17.

Figure 18.

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POWER-UP SEQUENCE #1

POWER-UP SEQUENCE #2

V_IN

V_CLKOUTx

AV_DD

V_GH

V_STVOUT

V_RESETOUT

V_GL

G019

G020

Figure 19.

Figure 20.

POWER-UP SEQUENCE #3

POWER-DOWN SEQUENCE #1

V_IN

V_CLKOUTx

V_DSCHG1

V_STVOUT

V_DSCHG2

V_/XAO

V_RESETOUT

G021

G022

Figure 21.

Figure 22.

POWER-DOWN SEQUENCE #2

PEAK OUTPUT CURRENT (CLKx)

544mA

V_IN

V_DSCHG1

I_CLKOUT1

V_DSCHG2

V_/XAO

564mA

G023

G024

Figure 23.

Figure 24.

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PEAK OUTPUT CURRENT (STVOUT, RESETOUT)

PEAK OUTPUT CURRENT (DSCHRGx)

258mA

488mA

I_STVOUT

I_DSCHG1

424mA

302mA

G025

G026

Figure 25.

Figure 26.

RISE TIME (CLKOUTx)

RISE TIME (STVOUT, RESETOUT)

V_CLKOUT1

V_STVOUT

Load=47Ω+10nF

G027

G028

Figure 27.

Figure 28.

RISE TIME (DSCHRGx)

FALL TIME (CLKOUTx)

V_DSCHG1

V_CLKOUT1

Load=47Ω+10nF

G030

G029

Figure 29.

Figure 30.

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FALL TIME (STVOUT, RESETOUT)

FALL TIME (DSCHRGx)

V_STVOUT

V_DSCHG1

Load=47Ω+10nF

G031

G032

Figure 31.

Figure 32.

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DETAILED DESCRIPTION

An internal block diagram of the TPS65149 is shown in Figure 33.

SS COMP

Gate

Drive

V_AVDD

V_OVP

RHVS

Boost

Converter

PGND

FREQ

HVS

DRVP

V_PG

VIN

V_IN

FBP

Internal

Bias

V_UVLO

RNTC

FBPH

Temperature

Compensation

AGND

XAO

VGL2

Buffer

DSCHG2

VGH

V_IN

Level

Shifter

Level

Shifter

DRVN

DSCHG1

VGL1

FBN

Discharge

VDET

V_GH

V_L

STVIN

RESETIN

CLKIN1

CLKIN2

CLKIN3

CLKIN4

CLKIN5

CLKIN6

LGND

STVOUT

RESETOUT

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

CLKOUT5

CLKOUT6

Level

Shifter

V_GL1

V_AVDD

EEPROM

AVDD

DVRO

I_SET

I²C

Interface

SDA

SCL

DAC

Note:

For clarity, duplicate pins not shown.

RSET

Figure 33. Internal Block Diagram

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Boost Converter

An internal block diagram of the boost converter is contained in Figure 34.

L₁

V_AVDD

V_IN

C₁

C₂

SUP

VIN

V_OVP

Gate

Drive

Bias

UVLO

Thermal SD

V_SUP

V_FB

FREQ

R₁

t_OFF

Generator

Current Limit

& Soft Start

R₂

R₃

PWM

Generator

RHVS

HVS

C₄

V_L

COMP

R₄

PGND

C₃

Figure 34. Boost Converter Internal Block Diagram

The boost converter is designed for output voltages up to 18V with a switch current limit of 4 A (guaranteed

minimum). The converter uses a current mode, quasi-constant frequency topology, and is externally

compensated for maximum flexibility. A soft-start feature limits the current drawn from V_INduring start-up, and

the converter's switching frequency can be selected between 640 kHz and 1.2 MHz.

The converter's adaptive off-time topology achieves superior transient response and operates over a wider range

of applications than conventional converters.

Design Procedure (Boost Converter)

The first step in the design procedure is to calculate the peak switch current. The simplest way to do this is to

use the curves in the typical characteristics section to estimate converter efficiency in the intended application.

Alternatively, a conservative worst-case value such as 85% can be used.

Once a value for the converter's efficiency h is available, Equation 1 can be used to calculate its duty cycle.

´ η

D = 1 -

V_AVDD

(1)

(2)

The next step is to use Equation 2 to calculate the change in inductor current per cycle.

´ D

ΔI_L=

¦ ´ L

Finally, the peak switch current can be calculated using Equation 3.

I_AVDD

ΔI_L

I_SW(PK)

- D

(3)

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The value for peak switch current calculated using Equation 3 must be lower than the minimum specified for the

device, and should be calculated under worst-case conditions (minimum V_INand maximum I_AVDD).

Inductor Selection (Boost Converter)

The boost converter in the TPS65149 has been optimized for inductors in the range 3.3 µH to 6.8 µH when using

the higher switching frequency and in the range 7 µH to 13 µH when using the lower switching frequency.

The saturation current of the inductor must be greater than the peak switch current plus an additional margin to

allow for heavy load transients. A saturation current of 130% of the value calculated using Equation 3 is

adequate for most applications.

Table 1 shows a selection of inductors suitable for use with the TPS65149.

Table 1. Boost Converter Inductor Selection

INDUCTANCE

MANUFACTURER

PART NUMBER

SIZE

DCR

ISAT

1.2 MHz OPERATION

4.7 µH

Coiltronics

Sumida

UP2B-4R7-R

CDRH12NP-4R7-M

CDRH127

14.0 × 10.4 × 6.0

12.3 × 12.3 × 4.5

12.3 × 12.3 × 8.0

17 mΩ

18 mΩ

12 mΩ

5.5 A

5.7 A

6.8 A

Sumida

640 kHz OPERATION

10 µH

Coilcraft

Sumida

DS3316P

CDRH8D43

CDRH127

13.0 × 9.4 × 5.1

8.3 × 8.3 × 4.5

70 mΩ

29 mΩ

16 mΩ

15 mΩ

3.5 A

4.0 A

5.4 A

6.7 A

12.3 × 12.3 × 8.0

CDRH127LD

Rectifier Selection (Boost Converter)

A Schottky type is recommended for the boost converter rectifier diode because its low forward voltage improves

efficiency. The diode's reverse voltage rating must be greater than 20 V, which is the maximum it will experience

(the TPS65149's overvoltage protection function prevents this voltage being any higher). The diode's average

rectified current rating must be at least as high as the maximum I_AVDD. A 2 A rating is sufficient for most

applications.

Equation 4 can be used to calculate the power dissipated in the diode. The diode must be capable of handling

this power without overheating. A power rating of 500 mW is sufficient for most applications.

P = V ´ I

AVDD

(4)

Where:

V_Fis the diode's forward voltage

I_AVDDis the average (mean) boost converter output current

Table 2 shows a selection of rectifier diodes suitable for use with the TPS65149.

Table 2. Boost Converter Rectifier Selection

CURRENT

2 A

MANUFACTURER PART NUMBER

SIZE

SMA

Vishay

SL22

SS22

20 V

0.44 V at 2 A

0.5 V at 2 A

2 A

Input Capacitor Selection (Boost Converter)

For good supply voltage filtering, low ESR capacitors are recommended. The TPS65149 has an analog supply

voltage pin (VIN) that should be decoupled with a ceramic capacitor in the range 100 nF to 1 µF, connected

close to the VIN pin.

The main boost converter (i.e. where V_INis connected to the inductor of the boost converter) should also be

decoupled. Two 10 µF or one 22 µF ceramic capacitor are adequate for most applications, however, these

values can be increased if improved filtering is required.

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Setting the Output Voltage (Boost Converter)

The output voltage of the boost converter is set by a resistor divider connected to the FB pin. The boost

converter's main error amplifier compares the feedback voltage with the internal reference voltage V_Lso that the

output is regulated at a voltage given by Equation 5.

R₁

R₂

V_AVDD= 1.24 ×

+ 1

(5)

Soft-Start (Boost Converter)

To reduce the inrush current drawn from V_INduring start-up the boost converter includes a soft-start feature.

Soft-start is controlled by a capacitor connected to the soft-start (SS) pin. During soft-start, this capacitor is

charged up by a current source and the voltage across the capacitor determines the switch current limit: the

larger the capacitor, the slower the ramp of the switch current limit and therefore the longer the soft-start time.

The maximum switch current limit is achieved when the voltage connected to the boost converter's feedback pin

(FB) reaches its power good threshold (approximately 97 percent of its nominal value).

A 22 nF soft-start capacitor is suitable for most applications.

When the EN pin is pulled low, the soft-start capacitor is discharged.

Frequency Select (FREQ)

The frequency select (FREQ) pin can be used to set the nominal boost converter switching frequency to either

640 kHz (FREQ=low) or 1.2 MHz (FREQ=high). A higher switching frequency improves the load transient

response and output voltage ripple; a lower switching frequency usually improves efficiency.

A switching frequency of 1.2 MHz is recommended for most applications unless efficiency is the primary concern.

The FREQ pin features an internal pull-up resistor that ensures the higher switching frequency is used if the pin

is left floating.

Compensation (COMP)

The boost converter uses an external compensation network connected to its COMP pin to stabilize its feedback

loop. The COMP pin is connected to the output of the boost converter's transconductance error amplifier, and a

series resistor and capacitor connected between this pin and AGND is sufficient to achieve good performance in

most applications. The capacitor primarily influences low frequency gain and the resistor primarily influences high

frequency gain. Lower output voltages require higher loop gain and therefore a larger compensation capacitor.

Good starting values, which will work for most applications running from a 5 V supply voltage, are 47 kΩ and 3.3

nF.

In some applications (e.g. those using electrolytic output capacitors), it may be necessary to include a second

compensation capacitor between the COMP pin and AGND. This has the effect of adding an additional pole in

the feedback loop's frequency response, which can be used to cancel the zero introduced by the electrolytic

output capacitor's ESR. It is recommended to include a footprint on the PCB for this optional capacitor, even if it

is not used initially.

Overvoltage Protection (Boost Converter)

The boost converter contains an overvoltage protection (OVP) feature that limits its output voltage to a safe

maximum if the FB pin is floating or shorted to ground. Overvoltage conditions are detected when the voltage

applied to the AVDD pin (V_AVDD) exceeds the overvoltage threshold (V_OVP). As soon as this happens, the boost

converter switch is turned off. It remains off until V_AVDDfalls below V_OVP(minus hysteresis), at which point the

boost converter automatically starts switching again.

NOTE

The AVDD pin must be connected to the boost converter output for the overvoltage

protection feature to operate correctly.

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Short-Circuit and Undervoltage Protection (Boost Converter)

During start-up (i.e., as soon as V_IN> V_UVLOand EN=high) the GD pin is pulled low and the boost converter's

output voltage V_AVDDis sensed. If V_AVDDdoes not rise to at least 46% of V_INwithin 5 ms the GD pin is pulled high

for 55 ms before the converter tries to start again. If the short-circuit condition persists after three failed attempts

the boost converter stops trying to restart and the GD pin is latched high. Either V_INor EN must be cycled to

recover normal operation.

During normal operation (i.e., once the boost converter has reached its power good threshold) a short circuit is

detected if the feedback voltage V_FBfalls below 30% of V_L. If this happens, the boost converter is disabled and

the GD pin is latched high. Either V_INor EN must be cycled to recover normal operation.

Undervoltage Lockout Protection (Boost Converter)

During operation, if the output of the boost converter falls below its power good threshold for longer than 55ms,

the TPS65149 will detect an undervoltage condition and turn itself off. V_INor EN must be cycled to recover

normal operation.

High Voltage Stress Mode (Boost Converter)

The TPS65149 features a special mode to support High Voltage Stress (HVS) testing during manufacturing. The

HVS mode is selected when the HVS pin is high and causes the boost converter output to be regulated to a

higher voltage than during normal operation. This is achieved by connecting an additional feedback resistor

between the FB and RHVS pins (see Figure 2). When HVS mode is enabled, the RHVS pin is switched to AGND

and the R_HVSis connected in parallel with R₂.

During HVS mode, the increase in boost converter output voltage is given by Equation 6.

R₁

DV_AVDD= 1.24 ×

R₃+ R_HVS

(6)

Where R_HVSis the r_DS(ON)of the internal MOSFET switch.

The HVS pin features an internal pull-down resistor that ensures the HVS mode is disabled if the pin is left

floating.

Gate Driver (GD)

The gate driver (GD) pin can be used to control an external isolation switch. The TPS65149 supports PMOS

devices positioned between V_INand the boost converter's inductor (see Figure 35). The GD pin is pulled low by a

10 µA current source when V_IN> V_UVLOand EN=high and features an internal pull-up resistor to turn off the

isolation switch when V_INis removed or EN is low.

If the TPS65149 is used in an application without an isolation switch, the GD pin can be left floating.

NOTE

The threshold voltage of the PMOS isolation switch must be lower than V_INfor proper

operation.

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V_IN

VIN

R_GD

GD Control

I_GD

Figure 35. Gate Drive Internal Block Diagram

Positive Charge Pump

Figure 36 shows the internal block diagram of the positive charge pump.

The positive charge pump is driven directly from the boost converter's switch node and then post-regulated by an

external PNP transistor. The controller is optimized for transistors having a DC gain (h_FE) in the range 100 to

300. The positive charge pump is temperature compensated so that its output voltage decreases at high

temperatures (see Figure 16).

V_AVDD

UVP (Normal)

1.15V*

55 ms

Disable

Timer

V_L

DRVP

Short

372mV*

124mV*

Circuit

Normal

Control

Logic

SCP (Normal)

SCP (Start-Up)

55µA

V_GH

2.5 mA

R₁₅

Error

Amplifier

V_REF

FBP

Clamp

R₁₆

RNTC

R₁₁

FBPH

R₁₀

R_NTC

R₁₂

Figure 36. Positive Charge Pump Internal Block Diagram

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Setting the Output Voltage (Positive Charge Pump)

The positive charge pump in the TPS65149 is temperature compensated such that its output voltage decreases

at high temperatures (see Figure 37). For a detailed description about how to set the output voltage see

Temperature Compensation section below.

A current of the order of 1 mA through the feedback resistor network ensures good accuracy and increases the

circuit's immunity to noise. It also ensures a minimum load on the charge pump, which reduces output voltage

ripple under no-load conditions. A good approach is to assume a value of about 1.2 k for the lower resistor (R₁₆)

and then select the upper resistor (R₁₅) to set the desired output voltage.

Note that the maximum voltage in an application is determined by the boost converter's output voltage and the

voltage drop across the diodes and PNP transistor. For a typical application in which the positive charge pump is

configured as a voltage doubler, the maximum output voltage is given by Equation 7.

V_GH(MAX)

2 ´ V

(

2 × V

- V_CE

)

(

AVDD

(7)

Where V_AVDDis the output voltage of the boost converter, V_Fis the forward voltage of each diode and V_CEis the

collector-emitter voltage of the PNP transistor (recommended to be at least 1 V, to avoid transistor saturation).

Selecting the PNP Transistor (Positive Charge Pump)

The PNP transistor used to regulate V_GHshould have a DC gain (h_FE) of at least 100 when its collector current is

equal to the charge pump's output current. The transistor should also be able to withstand voltages up to V_GH

across its collector-emitter junction (V_CE).

The power dissipated in the transistor is given by Equation 8. The transistor must be able to dissipate this power

without its junction becoming too hot. Note that the ability to dissipate power depends heavily on adequate PCB

thermal design.

^GHû

P_Q

2 ´ V

(

2 ´ V

- V

)

´ I_GH

)

(

AVDD

(8)

Where I_GHis the mean (not RMS) output current drawn from the charge pump.

A pull-up resistor is also required between the transistor's base and emitter. The value of this resistor is not

critical, but it should be large enough not to divert significant current away from the base of the transistor. A

value of 100 kΩ is suitable for most applications.

Selecting the Diodes (Positive Charge Pump)

Small-signal diodes can be used for most low current applications (<50 mA) and higher rated diodes for higher

power applications. The average current through the diode is equal to the output current, so that the power

dissipated in the diode is given by Equation 9.

P = I_GH´ V_F

(9)

The peak current through the diode occurs during start-up and for a few cycles may be as high as a few amps.

However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive current

rating is much lower. The diodes' reverse voltage rating should be equal to two times V_AVDD

Table 3. Positive Charge Pump Diode Selection

PART NUMBER

BAV99W

I_AVG

I_PK

V_R

V_F

COMPONENT SUPPLIER

NXP

150 mA

200 mA

500 mA

1 A for 1 ms

600 mA for 1s

5.5 A for 8 ms

75 V

30 V

40 V

1 V at 50 mA

0.8 V at 100 mA

0.51 at 500 mA

BAT54S

Fairchild Semiconductor

MBR0540

Selecting the Capacitors (Positive Charge Pump)

For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical

and values in the range 1 µF to 10 µF are suitable for most applications. Larger capacitors provide better

performance in applications where large load transient currents are present.

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A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a

smaller voltage drop by the end of each switching cycle, and allow higher output voltages and/or currents to be

achieved. Smaller values tend to be physically smaller and a bit cheaper. For best performance, it is

recommended to include a resistor of a few ohms (2 Ω is a good value to start with) in series with the flying

capacitor to limit peak currents occurring at the instant of switching.

Temperature Compensation (Positive Charge Pump)

The output voltage (V_GH) of the positive charge pump controller is defined by two voltages and two temperatures,

as illustrated in Figure 37. The temperature compensation scheme is optimized for use with 10 kΩ NTC

thermistors.

Positive Charge Pump

Output Voltage

V_GH(COLD)

V_GH(HOT)

T₁

T₂

Temperature

Figure 37. Positive Charge Pump Temperature Compensation

The error amplifier's non-inverting input, which is the reference voltage for V_GH, is derived from the FBPH and

RNTC pins. A higher reference voltage generates a higher V_GH

V_GH(COLD)is determined by the resistor connected to the FBPH and FBP pins:

R₁₅

R_{16 ø}

V_GH(COLD)= I_FBPH´ R₁₀

1 +

(10)

(11)

V_GH(HOT)is set by an internal clamping circuit and the resistor divider connected to the FBP pin:

R₁₅

R_{16 ø}

V_GH(HOT)= V_REF

1 +

The NTC network connected to the RNTC pin defines the temperatures T₁and T₂.

Temperature compensation can be disabled by connecting a 10 kΩ resistor between the FBPH pin and AGND

and by tying the RNTC pin directly to AGND, in which case Equation 11 should be used to calculate V_GH

Suppose a circuit with the following characteristics is required:

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Example

A Microsoft Excel spreadsheet is available that allows easy calculation of temperature compensation

components and eliminates the need for the following expressions to be calculated manually. Contact the

factory to receive a free copy.

Suppose a circuit with the following characteristics is required:

T₁= 40°C

T₂= 60°C

V_GH(COLD)= 28 V

V_GH(HOT)= 20 V

Space

1. The first step is to calculate the resistance of the NTC at temperatures T₁and T₂

At temperature T₁, R_NTC(T1)= 5302 Ω

At temperature T₂, R_NTC(T2)= 2486 Ω

Space

2. The next step is to calculate the feedback resistors R₁₅and R₁₆as follows:

V_GH(HOT)

R₁₅

R₁₆

- 1

V_REF

R₁₅

R₁₆

20V

- 1 = 15.13 V

1.24V

(12)

Suitable standard values from the E96 series would be R₁₅= 19.6 kΩ and R₁₆= 1.3 kΩ. With these values,

the current through the feedback divider is of the order of 1mA and the nominal output voltage at high

temperatures is:

R₁₅

R₁₆

V_GH(HOT)= V_REF

+ 1

19.6 kΩ

1.3 kΩ

+ 1 = 19.94 V

V_GH(HOT)= 1.24 V ´

(13)

Space

3. Now calculate V_FBPHas follows:

R₁₆

V_FBPH= V_GH(HOT)

R₁₅+ R_{16 ø}

1.3 kΩ

19.6 kΩ + 1.3 kΩ

V_FBPH= 28 V ×

= 1.742 V

(14)

Space

The value of R₁₀required to generate V_FBPHcan now be calculated, as follows:

V_FBPH

R₁₀

I_FBPH

1.742 V

200 μA

R₁₀

= 8.71 kΩ

(15)

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Two 17.4 kΩ resistors in parallel would be suitable for R₁₀, giving an output voltage at low temperatures

given by:

R₁₅

R₁₆

V_GH(COLD)= I_FBPH´ R₁₀

+ 1

17.4 kΩ

19.6 kΩ

1.3 kΩ

V_GH(COLD)= 200 μA ´

+ 1 = 28.0 V

(16)

(17)

Space

The value of R₁₂can be calculated by solving a standard quadratic equation:

-b

b²- 4 ´ a ´ c

2 ´ a

R₁₂

Where:

I_SET

a =

´ R

(

-R_{NTC T2}-1

)

NTC T1

( )

V_FBPH- V_L

200 μA

a =

´ 5.30 kΩ -2.49 kΩ -1= 0.124

(

)

1.74 V -1.24 V

Space

b = R_T1+R_T2

b = 5.30 kΩ + 2.49 kΩ = 7.79 kΩ

Space

c = R_T1´R_T2

c = 5.30 kΩ´2.49 kΩ =13.2´10⁶Ω²

Space

Using the coefficients a, b, and c we can solve for R₁₂:

7.79 kΩ + 7.79 kΩ²+ 4 × 0.124 × 13.2 × 10⁶Ω²

R₁₂

2 × 0.124

R₁₂= 64.5 kΩ

A standard value of 64.9 kΩ can be used for R₁₂.

Space

4. The final step is to calculate the value of R₁₁using Equation 11.

V_REF

R_T2´ R₁₂

R₁₁

I_RNTC

R_T2+ R₁₂

1.24 V

2.49 kΩ × 64.9 kΩ

= 3.8 k

R₁₁

200 μA

2.49 kΩ + 64.9 kΩ

(18)

A standard value of 3.83 kΩ can be used for R₁₂.

Figure 38 shows the temperature dependence of V_GHresulting from the above calculated values.

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100

Temperature - °C

Figure 38. Temperature Compensated V_GH

Short-Circuit Protection (Positive Charge Pump)

During start-up, the positive charge pump limits the current available from V_GHuntil V_FBP> 124 mV. If V_FBPis still

less than 124 mV after 15 ms, the boost converter, and positive and negative charge pumps are disabled and the

GD pin latched high. Either V_INor EN must be cycled to recover normal operation.

During normal operation (i.e. once the positive charge pump has reached its power good threshold) short circuits

are detected if V_FBPfalls below 0.34 V (approx. 30% of V_L). If this happens the boost converter and positive and

negative charge pumps are disabled and the GD pin latched high. Either V_INor EN must be cycled to recover

normal operation.

Undervoltage Protection (Positive Charge Pump)

During operation, if the output of the positive charge pump falls below its power good threshold for longer than

55ms, the TPS65149 will detect an undervoltage condition and turn itself off. V_INor EN must be cycled to recover

normal operation.

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Negative Charge Pump Controller

The negative charge pump controller uses an external NPN transistor to regulate an external charge pump

circuit. The controller is optimized for transistors having a DC gain (h_FE) in the range 100 to 300. Regulation of

the charge pump's output voltage is achieved by using the external transistor as a controlled current source

whose output current depends on the voltage applied to the FBN pin. The higher the transistor's output current,

the higher (i.e., more negative) the charge pump's output voltage.

UVP (Normal)

V_AVDD

93 mV

55 ms

Timer

Disable

Short-Circuit

Mode

850 mV

794 mV

SCP (Normal)

SCP (Start-Up)

Control

Logic

300 μA

Normal

Mode

2.5 mA

R₈

FBN

C₁₀

Error

Amplifier

V_GL1

C₁₁

V_REF

DRVN

R₇

V_GL2

C₁₃

R₂₂

R₁₄

R₁₃

Figure 39. Negative Charge Pump Internal Block Diagram

Setting the Output Voltage (Negative Charge Pump)

The negative charge pump's output voltage is programmed by a resistor divider according to Equation 19.

R₁₃

R₁₄

V_GL1= - V_REF

(19)

(20)

Rearranging Equation 19, the values of R₁₃and R₁₄can be easily calculated.

V_GL1

R₁₃= R₁₄

V_REF

Because of its limited output current capability, it is recommended to keep the current drawn from the VL pin

below 250 µA to achieve best accuracy. A good approach is to use a value of at least 5.1 kΩ for the lower

resistor (R₁₄) and then select the upper resistor (R₁₃) to set the desired output voltage. If a minimum charge

pump load is desired (e.g. to improve regulation at very low load currents), it is best to add an additional resistor

between V_GL1and GND, rather than reduce the values of R₁₃and R₁₄.

Note that the maximum voltage in an application is determined by the boost converter's output voltage and the

voltage drop across the diodes and NPN transistor. For a typical application in which the negative charge pump

is configured as a voltage inverter, the maximum (i.e., most negative) output voltage is given by Equation 21.

V_GL1(MAX)= - V_AVDD+ 2 ´ V + V

( )

(21)

Where V_Fis the forward voltage of each diode and V_CEis the collector-emitter voltage of the NPN transistor

(recommended to be at least 1 V, to avoid transistor saturation).

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Selecting the NPN Transistor (Negative Charge Pump)

The NPN transistor used to regulate V_GL1should have a DC gain (h_FE) of at least 100 when its collector current is

equal to the charge pump's output current. The transistor should also be able to withstand voltages up to V_AVDD

across its collector-emitter (V_CE).

The power dissipated in the transistor is given by Equation 22. The transistor must be able to dissipate this

power without its junction becoming too hot. Note that the ability to dissipate power depends heavily on adequate

PCB thermal design.

^GL1û

P_Q

V _AVDD

2 ´ V

(

)

´ I_GL1

(22)

Where I_GLis the mean (not RMS) output current drawn from the charge pump.

Selecting the Diodes (Negative Charge Pump)

Small-signal diodes can be used for most low current applications (<50 mA) and higher rated diodes for higher

power applications. The average current through the diode is equal to the output current, so that the power

dissipated in the diode is given by Equation 23.

= I_GL1´ V_F

(23)

The peak current through the diode occurs during start-up and for a few cycles may be as high as a few amps.

However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive current

rating is much lower. The diodes' reverse voltage rating should be equal to at least 2×V_AVDD

Table 4. Negative Charge Pump Diode Selection

PART NUMBER

BAV99W

I_AVG

I_PK

V_R

V_F

COMPONENT SUPPLIER

NXP

150 mA

200 mA

500 mA

1 A for 1 ms

600 mA for 1 s

5.5 A for 8 ms

75 V

30 V

40 V

1 V at 50 mA

0.8 V at 100 mA

0.51 at 500 mA

BAT54S

Fairchild Semiconductor

MBR0540

Selecting the Capacitors (Negative Charge Pump)

For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical

and 1 µF to 10 µF is suitable for most applications. Larger capacitors provide better performance in applications

where large load transient currents are present.

A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a

smaller voltage drop by the end of each switching cycle, and allow higher output voltages and/or currents to be

achieved. Smaller values tend to be physically smaller and a bit cheaper.

A collector capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values are more

suitable for high current applications but can affect stability if they are too big.

Short-Circuit Protection (Negative Charge Pump)

During start-up the negative charge pump limits the current available from V_GL1until V_FBNis less than 794 mV. If

V_FBNis still less than 794 mV after ≈20 ms⁽¹⁾, the boost converter, and positive and negative charge pumps are

disabled, and the GD pin latched high. Either V_INor EN must be cycled to recover normal operation.

During normal operation (i.e., once the negative charge pump has reached its power good threshold), short

circuits are detected if V_FBNrises above 850 mV. If this happens, the boost converter, and positive and negative

charge pumps are disabled, and the GD pin latched high. Either V_INor EN must be cycled to recover normal

operation.

Undervoltage Protection (Negative Charge Pump)

During operation, if the output of the negative charge pump falls below its power good threshold for longer than

55ms, the TPS65149 will detect an undervoltage condition and turn itself off. V_INor EN must be cycled to recover

normal operation.

(1) Actually 10ms after the boost converter's power good.

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Reset Generator (XAO)

The TPS65149 generates an open-drain reset signal that can be used to disable the T-CON during power-down.

The XAO signal is pulled low when V_DET< V_Land is high impedance when V_DET> V_L(+ hysteresis). The reset

generator is not disabled when V_INfalls below the UVLO threshold, and continues to function down to very low

values of V_IN.

Programmable VCOM

The TPS65149 contains a programmable V_COMgenerator (see Figure 40). The output voltage generated (V_DVRO

)

can be adjusted during using the integrated 7-bit DAC, which can be accessed via an I²C serial interface. The

programmable V_COMis enabled when V_IN> V_UVLOand EN = high.

V_AVDD

I²C

Interface

SCL

EEPROM

SDA

R₁₇

DVRO

V_AVDD

DAC

To VCOM Buffer

N ×I_SET

127

19R

R₁₈

I_SET

RSET

R₁₉

Figure 40. Programmable V_COMBuffer Internal Block Diagram

Once the optimum V_COMvalue has been determined, it can be stored in the on-chip EEPROM. The DAC will be

programmed with this value every time the TPS65149 is powered up.

NOTE

The factory default DAC setting is 40h, which is the midpoint of the adjustment range.

Programming V_COM

The maximum value of V_COMoccurs when the DAC setting is 0 and is determined by R₁₇and R₁₈connected

between V_AVDDand GND as follows:

R₁₈

V_COM(MAX)

´ V_AVDD

R₁₇+ R₁₈

(24)

The maximum current that can be sunk from the POS pin occurs when the DAC setting is 7Fh and is given by:

V_AVDD

I_SET

20 ´ R₁₉

(25)

The current that will be sunk from the POS pin for a given DAC setting N is given by:

I_POS

´ I_SET

127

(26)

where N is a 7-bit integer between 0 and 127 (decimal).

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The V_COMgenerated for a given DAC setting N is therefore given by:

R₁₈

N ´ R₁₇

V_COM= V_AVDD

R₁₇+ R₁₈

127 ´ 20 ´ R₁₉

(27)

DAC Register (DR)

The DAC Register (DR) contains the current 7-bit setting of the DAC. This register can be written to and read

from at any time.

During power-up the contents of the IVR are written into the DR. The contents of the DR are volatile, which

means that if they have been changed from the IVR value, they will be lost when power to the TPS65149 is

removed.

Initial Value Register (IVR)

The Initial Value Register (IVR) contains the 7-bit setting that is loaded into the DAC during power-up. This

from indirectly by reading the DR immediately after power-up, before any write operations to the DR have been

performed.

Write Protect

The TPS65149 features an active low Write Protection pin (WP) that prevents any changes to the IVR when tied

GND. The WP pin should be pulled high to allow the desired V_COMsetting to be stored in the EEPROM, and then

tied to GND (to prevent further changes) before the display is finally shipped.

The WP pin features is internally pulled down to inhibit write operations if accidentally left floating.

The internal circuitry derives the EEPROM programming voltage from V_AVDD. The AVDD pin must therefore be

connected to the boost converter output and the EN pin must be high during EEPROM write operations.

I²C Interface

The TPS65149 features an I²C serial interface that allows the contents of the IVR and DR to be read from and

written to. The TPS65149 is configured as a slave device that supports 7-bit addressing and whose 7-bit address

is 4Fh. Standard and Fast modes of operation are supported.

During normal operation the DAC contains the data last written to the IC. During power-up the contents of the

IVR are loaded into the DAC.

Two write operations are possible:

•

To the DAC – when the LSB of the data word is "1"

To the IVR – when the LSB of the data word is "0"

A read operation always reads data from the DR. This data is the same as the IVR if the read operation is

performed immediately after a write operation to the DR and the IVR. During a read operation, when the DR and

IVR contents are the same the LSB is "0", when they are different, the LSB is "1".

During an EEPROM write operation the TPS65149 ignores all further attempts to access its slave address until

the current write operation has finished.

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Example – Writing 77h to DR

1. Bus Master sends START condition.

2. Bus Master sends 9Eh (slave address plus low R/W bit).

3. TPS65149 acknowledges.

4. Bus Master sends EFh (data to be written plus LSB = "1").

5. TPS65149 acknowledges.

6. Bus Master sends STOP condition

WRITE

4Fh

77h

START

SACK

STOP

9Eh

EFh

Figure 41. Writing 77h to DAC Register (DR)

Example – Writing 77h to IVR

1. Bus Master sends START condition.

2. Bus Master sends 9Eh (slave address plus low R/W bit).

3. TPS65149 acknowledges.

4. Bus Master sends EEh (data to be written plus LSB = "0").

5. TPS65149 acknowledges.

6. Bus Master sends STOP condition

IVR

WRITE

4Fh

77h

START

SACK

STOP

9Eh

EEh

Figure 42. Writing 77h to Initial Value Register (IVR)

Example – Reading from DR when DR and IVR Contents are Identical

1. Bus Master sends START condition.

2. Bus Master sends 9Fh (slave address plus high R/W bit).

3. TPS65149 acknowledges.

4. Bus Master sends EEh from DR (LSB = "0").

5. Master does not acknowledge.

6. Bus Master sends STOP condition

Contents the Same

READ

4Fh Slave Address

77h Data

START

SACK

STOP

9Fh

EEh

Figure 43. Reading 77h from DAC Register when DR and IVR Contents are the Same

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Example – Reading from DR when DR and IVR Contents are Different

1. Bus Master sends START condition.

2. Bus Master sends 9Fh (slave address plus high R/W bit).

3. TPS65149 acknowledges.

4. Bus Master sends EFh from DR (LSB = "1").

5. Master does not acknowledge.

6. Bus Master sends STOP condition

Contents Different

READ

4Fh Slave Address

77h Data

START

SACK

STOP

9Fh

EFh

Figure 44. Reading 77h from DAC Register when DR and IVR Contents are Different

Level Shifters

The TPS65149 contains eight level shifter channels (see Figure 45). Each channel features a logic-level input

stage and a high-level output stage powered from V_GHand V_GL1. The output stages are capable of generating

high peak currents to drive the capacitive loads typically present in an LCD panel. Because the capacitive load

typically connected to the STV and RESET channels is relatively small, the peak current available from these two

channels is slightly lower than that available from the CLK channels.

During power-up, the level shifter outputs track V_GL1. During power-down, the level shifter outputs track V_GH

Power-up and power-down conditions are determined by the V_DETthreshold of the panel discharge function,

which also controls the level shifter channels during power-up and power-down.

V_GH

Level

CLKIN1 to CLKIN6

CLKOUT1 to CLKOUT6

Shifter

V_GL1

STRONG

NORMAL

V_GH

Level

STVIN, RESETIN

STVOUT, RESETOUT

Shifter

V_GL1

Figure 45. Level Shifter Block Diagram

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Panel Discharge

In addition to the eight level shifter channels described above, the TPS65149 contains two level shifter outputs

specifically intended for discharging the LCD panel during power-down (see Figure 46). The discharge channels

share the input signal connected to the VDET pin, which is compared with V_L. The discharge output stages are

identical except that DSCHG1 uses V_GL1for its negative supply rail and DSCHG2 uses V_GL2. Figure 47 to

Figure 50 show the discharge behaviour during power-up and power-down.

V_GH

V_LOGIC

Level

DSCHG1

Shifter

VDET

V_GL1

V_GH

V_L

Level

Shifter

DSCHG2

V_GL2

Figure 46. Discharge Internal Bock Diagram

Power Supply Sequencing (Boost, Charge Pumps and V_COMGenerator)

•

When V_IN< V_UVLO, all functions are disabled.⁽¹⁾

When V_IN> V_UVLO, all functions are disabled if EN is low.

When V_IN> V_UVLOand EN goes high, the boost converter, negative charge pump and V_COMgenerator are

enabled first. When the output of the boost converter reaches its power good threshold, the positive charge

pump is enabled.

•

If EN goes low, all functions are disabled.

Power Supply Sequencing (Level Shifters)

(2)

•

During power-up, when V_DETis below its input threshold, the level shifter outputs track V_GH

During normal operation, when V_DETis above its input threshold, the level shifter outputs follow their inputs.

During power-down, when V_DETfalls below its input threshold, the level shifter outputs track V_GH

Power Supply Sequencing (Panel Discharge)

•

During power-up, when V_DETis below its input threshold, DSCHG1 tracks V_GL1and DSCHG2 tracks V_GL2

During normal operation, when V_DETis above its input threshold, DSCHG1 tracks V_GL1and DSCHG2 tracks

V_GL2

During power-down, when V_DETfalls below its input threshold, DSCHG1 and DSCHG2 track V_GH

•

Power Supply Sequencing (/XAO)

•

During power-up, when V_DETis still below its input threshold, XAO is pulled low.

During normal operation, when V_DETis above its input threshold, XAO is high impedance.

During power-down, when V_DETfalls below its input threshold, XAO is pulled low.

(1) The panel discharge and level shifter discharge functions continue to function for as long as there is sufficient operating voltage on V_GH

V_GL1and V_GL2

(2) The panel discharge and level shifter discharge functions continue to function for as long as there is sufficient operating voltage on V_GH

V_GL1and V_GL2

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V_IN< V_UVLO

V_IN< V_DET

V_IN> V_UVLO

V_IN> V_DET

V_IN

V_AVDD> V_PG

V_AVDD

Minimum operating V_GL(≈-2V)

V_GL

V_GH

V_GH> V_UVLO(≈8V)

V_GH< V_UVLO(≈3V)

Level Shifter

Outputs

Tracks V_GH

DSCHG1

Tracks V_GL1

V_GL1

Tracks V_GH

DSCHG2

Tracks V_GL2

V_GL2

Figure 47. Power Supply Sequencing Using EN Pin, V_DET< V_UVLO

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V_IN> V_DET

V_IN< V_DET

V_IN

V_IN< V_UVLO

V_IN> V_UVLO

V_AVDD> V_PG

V_AVDD

Minimum operating V_GL(≈-2V)

V_GL

V_GH

V_GH> V_UVLO(≈8V)

V_GH> V_UVLO(≈3V)

Level Shifter

Outputs

Tracks V_GH

DSCHG1

Tracks V_GL1

V_GL1

Tracks V_GH

DSCHG2

Tracks V_GL2

V_GL2

Figure 48. Power Supply Sequencing Using EN Pin, V_DET> V_UVLO

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V_IN> V_UVLO

V_IN> V_DET

V_IN< V_UVLO

V_IN< V_DET

V_IN

V_AVDD> V_PG

V_AVDD

Min. Operating V_GL(≈-2V)

V_GL

V_GH

V_GH> V_UVLO(≈8V)

V_GH< V_UVLO(≈3V)

Tracks V_GH

Level Shifter

Outputs

Tracks V_GH

DSCHG1

Tracks V_GL1

V_GL1

Tracks V_GH

DSCHG2

Tracks V_GL2

V_GL2

Figure 49. Power Supply Sequencing with EN Pin Tied to V_IN, V_DET< V_UVLO

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V_IN> V_DET

V_IN< V_DET

V_IN< V_UVLO

V_IN

V_IN> V_UVLO

V_AVDD< V_PG

V_AVDD

Minimum operating V_GL(≈-2V)

V_GL

V_GH

V_GH> V_UVLO(≈8V)

V_GH< V_UVLO(≈3V)

Tracks V_GH

Level Shifter

Outputs

Tracks V_GH

DSCHG1

Tracks V_GL1

V_GL1

Tracks V_GH

DSCHG2

Tracks V_GL2

V_GL2

Figure 50. Power Supply Sequencing with EN Pin Tied to V_IN, V_DET> V_UVLO

Undervoltage Lockout

The TPS65149 features an undervoltage lockout (UVLO) function that disables the LCD bias functions if the

supply voltage (V_IN) is below the minimum needed for correct operation (V_UVLO).

Thermal Shutdown

A thermal shutdown function automatically disables all LCD bias functions if the device’s junction temperature

exceeds the safe maximum. The device automatically starts operating again once it has cooled down.

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APPLICATION INFORMATION

4u7

V_IN

V_AVDD

16.1V

10u

40u

10u

12k

AVDD

VIN

47k

22n

2R2

3n3

COMP

6k8

RHVS

470n

FREQ

AVDD

7k32

6k98

FBPH

RNTC

1k05

3.3V

DRVP

VGH

28.3 V @ T < –10°C

24 V @ T > +10°C

10k

XAO

22k

XAO

10u

FBP

AVDD

2R2

20k

1k2

470n

6V2

3k9

DVRO

RSET

HVS

10k

20k

DRVN

100n

100k

V_IN

SCL

SDA

–10V

–6V2

VGL1

VGL2

10k

10u

80k6

10k

VDET

FBN

DSCHG1

DSCHG2

100n

STVOUT

RESETOUT

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

CLKOUT5

CLKOUT6

STVIN

RESETIN

CLKIN1

CLKIN2

CLKIN3

CLKIN4

CLKIN5

CLKIN6

PGND

AGND

LGND

Figure 51. Typical Application Circuit Using Positive Charge Pump in ×2 Configuration

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4u7

13.6V

V_IN

AVDD

10u

40u

10u

10k

AVDD

VIN

47k

22n

2R2

3n3

COMP

6k8

RHVS

470n

FREQ

7k32

6k98

FBPH

RNTC

1k05

3.3V

DRVP

VGH

28.3 V @ T < –10°C

24 V @ T > +10°C

10k

22k

XAO

V_AVDD

10u

FBP

2R2

20k

1k2

470n

6V2

3k9

DVRO

RSET

HVS

10k

20k

DRVN

100n

100k

V_IN

SCL

SDA

–10V

–6V2

VGL1

VGL2

10k

10u

80k6

10k

VDET

FBN

DSCHG1

DSCHG2

100n

STVOUT

RESETOUT

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

CLKOUT5

CLKOUT6

STVIN

RESETIN

CLKIN1

CLKIN2

CLKIN3

CLKIN4

CLKIN5

CLKIN6

PGND

AGND

LGND

Figure 52. Typical Application Circuit Using Positive Charge Pump in ×2.5 Configuration

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PACKAGE OPTION ADDENDUM

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5-Feb-2014

PACKAGING INFORMATION

Orderable Device

TPS65149RSHR

TPS65149RSHT

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

VQFN

RSH

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TPS

65149

PREVIEW

RSH

250

TBD

Call TI

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Feb-2014

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS65149RSHR

ACTIVE

VQFN

RSH

2500 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 85

TPS

65149

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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