TPS65235 [TI]
具有 I2C 接口的 LNB 稳压器;
| 型号： | TPS65235 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 接口的 LNB 稳压器 稳压器 |
| 文件： | 总40页 (文件大小：2308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65235
ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
具有I2C 接口的TPS65235 LNB 电压稳压器
1 特性
3 说明
• 用于LNB 和I2C 接口的完整集成解决方案
• 兼容DiSEqC 2.x 和DiSEqC 1.x
• 支持5V、12V 和15V 电源轨
TPS65235 专为模拟和数字卫星接收器而设计，是一款
具有I2C 接口的单片稳压器。该器件专用于向碟形天线
中的 LNB 降压转换器或多开关箱提供 13V 至 18V 电
源以及 22kHz 音调信号。该器件提供了一套完整的解
决方案，具有元件数极少、功率耗散低、设计简单以及
采用I2C 标准接口等优点。
• 高达1000mA 的外部电阻器可调精确输出电流限制
• 升压开关峰值电流限制，与LDO 电流限制成正比
• 具有140mΩ低Rds(on) 内部电源开关的升压转换器
• 可选择1MHz 或500kHz 升压开关频率
• 适用于非I2C 应用的专用使能引脚
• 具有推挽式输出级的低压降(LDO) 稳压器，用于提
供VLNB 输出
• 内置精确的22kHz 音调发生器并支持外部音调输入
• 支持44kHz 和22kHz 外部音调输入
• 可调节软启动和13V 至18V 电压转换时间
• 650mV 至750mV 的22kHz 音调振幅选择
• 通过在EN 为低电平时进行访问的I2C 寄存器
• 短路动态保护
TPS65235 具有高功效。该升压转换器集成了一个在
1MHz 或500kHz 可选开关频率下运行的140mΩ功率
MOSFET。线性稳压器中的压降为 0.8V，能够更大限
度地降低功率损耗。TPS65235 提供了多种生成
22kHz 信号的方法。具有推挽式输出级的集成线性稳
压器可生成 22kHz 音调信号（在输出端叠加），即使
在零负载条件下也是如此。可由外部电阻器以 ±10%
的精度来设定线性稳压器的电流限值。通过I2C 读取的
全范围诊断可用于系统监控。
TPS65235 支持面向 22kHz 音调检测电路和输出接口
的高级DiSEqC 2.x 标准。
• 输出电压电平、DiSEqC 音调输入和输出、电流电
平以及电缆连接诊断
• 具有过热保护功能
器件信息(1)
• 20 引脚WQFN 3mm x 3mm (RUK) 封装
封装尺寸（标称值）
器件型号
TPS65235
封装
2 应用
WQFN
3.00mm x 3.00mm
• 机顶盒卫星接收器
• 电视卫星接收器
• PC 卡卫星接收器
• 卫星电视
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TPS65235
100nF
VOUT
VLNB
0.1mF
VCP
ISET
BOOST
2x22mF
110k
TCAP
AGND
22nF
PGND
10mH
VIN
LX
10mF
VCC
VIN
1mF
1mF
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSD80
TPS65235
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
Table of Contents
7.5 Programming............................................................ 18
7.6 Register Maps...........................................................20
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application for DiSEqc1.x Support................23
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 30
11 Device and Documentation Support..........................31
11.1 接收文档更新通知................................................... 31
11.2 支持资源..................................................................31
11.3 Trademarks............................................................. 31
11.4 Electrostatic Discharge Caution..............................31
11.5 Glossary..................................................................31
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................6
6.7 Typical Characteristics................................................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes..........................................17
Information.................................................................... 31
4 Revision History
Changes from Revision C (July 2019) to Revision D (May 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• Changed V(drop) min and max values..................................................................................................................5
• Changed I(rev_dis) min and max values................................................................................................................5
Changes from Revision B (July 2018) to Revision C (July 2019)
Page
• Changed V(drop) at TONEAMP = 0b From: MIN = 0.59 TYP = 0.8 MAX = 1 To: MIN = 0.49 TYP = 0.8 MAX =
1.1 in the Electrical Characteristics ....................................................................................................................5
• Changed V(drop) at TONEAMP = 1b From: MIN = 0.71 TYP = 0.9 MAX = 1.12 To: MIN = 0.65 TYP = 0.9 MAX
= 1.2 in the Electrical Characteristics .................................................................................................................5
Changes from Revision A (December 2017) to Revision B (December 2017)
Page
• Changed the GDR TONE_TRANS = 1b value From: MAX = 24.03V To: MAX = 24.33V in the Electrical
Characteristics ...................................................................................................................................................5
Changes from Revision * (January 2017) to Revision A (December 2017) Page
• Changed the VCP values From: VLNB to 7 V To: –0.3 V to 7 V in the Absolute Maximum Ratings ............... 4
• Changed the GDR values From: VLNB to VCP To: –0.3 V to 7 V in the Absolute Maximum Ratings .............4
• Changed the Operating junction temperature From: 125°C To: 150°C in the Absolute Maximum Ratings .......4
• Changed VIN MAX value From: 16 V To: 20 V in Recommended Operating Conditions ...................................4
• Changed VIN MAX value From: 16 V To: 20 V in Electrical Characteristics .......................................................5
• Changed 4.7 µF To: 4 µF in the line callouts of 图7-6 .................................................................................... 13
• Changed 4 µF To: 5 µF in the graph legends of 图7-7 ................................................................................... 13
• Changed the description of bit 1 TONE_AUTO From: "controlled by TONE_RECEIVE" To: "controlled by
TONE_TRANS" in 表7-7 .................................................................................................................................21
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
5 Pin Configuration and Functions
15 14 13
12
11
VLNB
16
10
9
VCTRL
ADDR
17
VCP
BOOST
GDR
18
19
20
8
7
FAULT
EN
ISET
6
PGND
3
2
4
5
1
图5-1. 20 Pin (WQFN-20) RUK Package (Top View)
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
LX
NO.
1
I
Switching node of the boost converter
Input of internal linear regulator
VIN
2
S
Internal 6.3-V power supply. Connect a 1-μF ceramic capacitor from this pin to ground. When VIN is 5 V,
connect VCC to VIN.
VCC
3
O
AGND
TCAP
ISET
4
5
6
S
O
O
Analog ground. Connect all ground pins and power pad together.
Connect a capacitor to this pin to set the rise time of the LNB output.
Connect a resistor to this pin to set the LNB output current limit.
Enable pin to enable the VLNB output; pull to ground to disable output, and output will be pulled to
ground, when the EN is low, the I2C can be accessed
EN
7
I
FAULT
ADDR
VCTRL
SDA
8
O
Oopen drain output pin, it goes low if any fault flag is set.
Connecting different resistor to this pin to set different I2C address, see 表7-4.
Voltage level at this pin to set the output voltage, see 表7-3.
I2C compatible bi-directional data
9
I
I
10
11
12
I/O
I
SCL
I2C compatible clock input
External modulation logic input pin which activates the 22-kHz tone output, feeding signal can be 22-kHz
tone or logic high or low.
EXTM
13
I
DOUT
DIN
14
15
16
17
18
19
20
O
I
Tone detection output
Tone detection input
VLNB
VCP
O
O
O
O
S
Output of the power supply connected to satellite receiver or switch.
Gate drive supply voltage, output of charge pump, connect a capacitor between this pin to pin VLNB.
Output of the boost regulator and Input voltage of the internal linear regulator.
Control the gate of the external MOSFET for DiSEqc 2.x support.
Power ground for Boost Converter
BOOST
GDR
PGND
Must be soldered to PCB for optimal thermal performance. Have thermal Vias on the PCB to enhance
power dissipation.
Thermal PAD
(1) I = input, O = output, I/O = input and output, S = power supply
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
1
MAX
30
UNIT
VIN, LX, BOOST, VLNB
VCP, GDR (referenced to VLNB pin)
7
–0.3
VCC, EN, ADDR, FAULT, SCL, SDA, VCTRL, EXTM, DOUT, DIN,
TCAP
7
Voltage
–0.3
V
ISET
3.6
0.3
–0.3
–0.3
–40
–55
PGND
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
20
UNIT
V
VIN
TA
Input operating voltage
Operating junction temperature
125
°C
–40
6.4 Thermal Information
TPS65235
THERMAL METRIC(1)
RUK (WQFN)
20 PINS
44.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47.3
16.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
16.4
ψJB
RθJC(bot)
3.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
VIN
4.5
90
12
120
5
20
150
7.8
V
IDD(SDN)
ILDO(Q)
UVLO
Shutdown supply current
LDO quiescent current
VIN Undervoltage Lockout
EN = 0
µA
mA
V
EN = 1, IO = 0 A, VLNB = 18.2 V
VIN Rising
2.2
4.15
280
4.3
480
4.45
550
Hysteresis
mV
OUTPUT VOLTAGE
VOUT Regulated output voltage
V(ctrl) = 1, IO = 500 mA
18
13.25
19.18
14.44
580
18.2
13.4
19.4
14.6
650
18.4
13.55
19.62
14.76
720
V
V
V(ctrl) = 0, IO = 500 mA
SCL = 1, V(ctrl) = 1, IO = 500 mA (Non I2C)
SCL = 1, V(ctrl) = 0, IO = 500 mA (Non I2C)
R(SET) = 200 kΩ, Full temperature
TJ = 25°C
V
V
I(OCP)
Output short circuit current limit
mA
mA
kHz
629
650
688
Fsw
Boost switching frequency
Switching current limit
1 MHz
977
1060
1134
I(limitsw)
VIN = 12 V, VOUT = 18.2 V,
R(SET) = 200 kΩ
2.4
3
3.6
A
Rds(on)_LS
V(drop)
On resistance of low side FET
Linear regulator voltage drop-out
VIN = 12 V
90
0.44
0.55
0.9
140
0.8
0.9
5
210
1.15
1.2
8.8
65
mΩ
V
IO = 500 mA, TONEAMP = 0
IO = 500 mA, TONEAMP = 1
VIN = 12 V, VOUT = 13.4 V or 18.2 V
EN = 1, VLNB = 21 V
V
I(cable)
I(rev)
Cable good detection current threshold
Reverse bias current
mA
mA
mA
49
58
I(rev_dis)
Disabled reverse bias current
EN = 0, VLNB = 21 V
2.9
4.6
6.3
LOGIC SIGNALS
V(EN) Enable threshold High
1.6
V
V
Enable threshold Low
0.8
7
I(EN)
Enable internal pull up current
V(EN) = 1.5 V
5
2
6
3
µA
µA
V(EN) = 1 V
4
V(VCTRL_H)
V(EXTM_H)
VCTRL, EXTM Logic threshold level
FAULT output low voltage
High level input voltage
2
V
V(VCTRL_L)
V(EXTM_L)
Low level input voltage
0.8
0.4
V
V
VOL(FAULT)
TONE
f(tone)
FAULT open drain, IOL = 1 mA
Tone frequency
Tone amplitude
22 kHz tone output
20
22
24
kHz
mV
A(tone)
IO = 0 mA to 500 mA, CO = 100 nF,
TONEAMP = 0
617
650
696
IO = 0 mA to 500 mA, CO = 100 nF,
TONEAMP = 1
703
750
803
mV
D(tone)
f(EXTM)
Tone duty cycle
45%
17.6
35.2
50%
22
55%
26.4
52.8
External tone input frequency range
22 kHz tone output
44 kHz tone output
kHz
kHz
44
TONE DETECTION
f(DIN)
Tone detector frequency capture range
0.4 VPP sine wave
17.6
0.3
22
26.4
1.5
kHz
V
V(DIN)
V(DOUT)
GDR
Tone detector input amplitude
DOUT output voltage
Sine wave, 22 kHz
Tone present, Iload = 2 mA
TONE_TRANS = 1, V(LNB) = 18.2 V
TONE_TRANS = 0, V(LNB) = 18.2 V
0.4
V
Bypass FET gate voltage/LNB
23.11
18.17
23.5
18.2
24.33
18.23
V
V
THERMAL SHUT-DOWN (JUNCTION TEMPERATURE)
T(TRIP)
Thermal protection trip Point
Thermal protection hysteresis
Temperature Rising
160
20
°C
°C
T(HYST)
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C READ BACK FAULT STATUS
V(PGOOD)
PGOOD trip levels
Feedback voltage UVP low
Feedback voltage UVP high
Feedback voltage OVP high
Feedback voltage OVP low
94%
93%
96%
94.5%
106.6%
104.6%
125
97.1%
95.5%
108%
106%
104%
102%
T(warn)
Temperature warning Threshold
°C
I2C INTERFACE
VIH
VIL
II
SDA,SCL input high voltage
2
–10
400
V
V
SDA,SCL input low voltage
Input current
0.8
10
SDA, SCL, VI = 0.4 to 4.5 V
SDA open drain, IOL = 2 mA
µA
V
VOL
f(SCL)
SDA output low voltage
Maximum SCL clock frequency
0.4
kHz
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
OUTPUT VOLTAGE
tr, tf
13 V to 18 V transition rising falling time
C(TCAP) = 22 nF
2
ms
ns
tON(min)
TONE
tr(tone)
Minimum on time for the Low side FET
75
102
130
Tone rise time
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 0
11
5.5
µs
µs
µs
µs
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 1, and EXTM has
44 kHz input
tf(tone)
Tone fall time
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 0
10.8
5.4
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 1, and EXTM has
44 kHz input
PROTECTION
tON
Overcurrent protection ON Time
Overcurrent protection OFF Time
TIMER=0
TIMER=0
2.3
3.75
118
5.52
ms
ms
tOFF
98.5
133.5
I2C INTERFACE
tBUF
Bus free time between a STOP and START
condition
1.3
µs
tHD_STA
tSU_STO
tLOW
Hold time (repeated) START condition
Setup time for STOP condition
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data setup time
0.6
µs
µs
µs
µs
µs
µs
µs
ns
0.6
1.3
tHIGH
0.6
tSU_STA
tSU_DAT
tHD_DAT
tRCL
0.6
0.1
0
Data hold time
0.9
Rise time of SCL signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
tRCL1
Rise time of SCL Signal after a Repeated START Capacitance of one bus line (pF)
condition and after an acknowledge BIT
20 + 0.1 CB
300
ns
tFCL
tRDA
tFDA
CB
Fall time of SCL signal
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
300
300
300
400
ns
ns
ns
pF
Rise time of SDA signal
Fall time of SDA signal
Capacitance of one bus line(SCL and SDA)
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6.7 Typical Characteristics
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = 2 x 22 µF/35 V (unless otherwise noted)
95%
90%
85%
80%
75%
70%
65%
60%
13.45
13.44
13.43
13.42
13.41
13.4
13.39
13.38
13.37
13.36
13.35
V(LNB) = 13.4 V
V(LNB) = 18.2 V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
D002
D001
V(LNB) = 13.4 V
L = 4.7 µH
图6-2. Load Regulation
图6-1. Power Efficiency
18.3
18.28
18.26
18.24
18.22
18.2
7
6.5
6
5.5
5
18.18
18.16
18.14
18.12
18.1
4.5
4
3.5
3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
-40
-20
0
20
40
60
80
100 120 140
D003
Junction Temperature (èC)
D004
V(LNB) = 18.2 V
图6-4. Input Supply Quiescent Current vs Junction
图6-3. Load Regulation
Temperature
135
130
125
120
115
110
105
680
670
660
650
640
630
620
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (èC)
Junction Temperature (èC)
D005
D006
ILOAD = 650 mA
图6-5. Shutdown Current vs Junction Temperature
图6-6. LNB Current Limit vs Junction Temperature
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
7 Detailed Description
7.1 Overview
TPS65235 is the Power management IC that integrates a boost converter, a LDO and a 22 kHz tone generator
to serve as a LNB power supply. This solution compiles the DiSEqC 2.x standard with or without I2C interface.
Output current limitation can be precisely programmed by an external resistor. There are two ways to generate
the 22 kHz tone signal, with or without I2C. Integrated boost features low Rds(on) MOSFET and internal
compensation. 1 MHz or 500 kHz selectable switching frequency is designed to save passive components size
and be flexible for design.
TPS65235 can support the 44-kHz tone output, when the EXTM has 44-kHz tone input, and the bit EXTM TONE
of Control Register 1 is set to “1”, the LNB tone output is 44 kHz. By default, the TPS65235 has a typical 22-
kHz tone output.
7.2 Functional Block Diagram
EN
REF_Boost
Internal Regulator
VCC
PWM Controller
PGND
REF_Boost
TCAP
BOOST
REF
VCTRL
VCP
Charge Pump
VLNB
REF_LDO
SDA
SCL
I2C Interface
I2C EN
ADDR
EN
Tone
Generator
VLNB
OCP
OTP
Tone_Auto
Tone_Trans
EXTM
Fault Diagnose
PGOOD
GDR
DIN
Logic
Tone
Det
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7.3 Feature Description
7.3.1 Boost Converter
The TPS65235 consists of an internal compensated boost converter and linear regulator. The boost converter
tracks the LNB output voltage within 800 mV even at loading 1000 mA, which minimizes power loss. When the
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input voltage VIN is greater than the expected output voltage VLNB, the linear regulator drops the voltage
difference between VIN and VLNB, which causes the lower efficiency and the higher power loss on the internal
linear regulator if the current loading is high. For this application, care must be taken to ensure that the safe
operating temperature range of the TPS65235 is not exceeded. Recommend to work at force PWM mode when
VIN > VOUT to reduce output ripple.
As default, the boost converter operates at 1 MHz. TPS65235 has internal cycle-by-cycle peak current limit in
the boost converter and DC current limit in the LNB output to protect the IC against short circuits and over
loading. When the LNB output is shorted to ground, the LNB output current is clamped at the LDO current limit.
The LDO current limit is set by the external resistor at ISET pin; meanwhile the Boost switch current limit is
proportional with LDO current limit. If overcurrent condition lasts for more than 4 ms, the Boost converter enters
hiccup mode and will re-try startup in 128 ms. This hiccup mode ON/OFF time can be selectable by I2C control
register 0x01, either 4 ms / 128 ms or 8 ms / 256 ms. At extremely light loads, the boost converter operates in a
pulse-skipping mode automatically.
Boost converter is stable with either ceramic capacitor or electrolytic capacitor.
If two or more set top box LNB outputs are connected together, one output voltage could be set higher than
others. The output with lower set voltage would be effectively turned off. Once the voltage drops to the set level,
the LNB output with lower set output voltage returns to normal conditions.
7.3.2 Linear Regulator and Current Limit
The linear regulator is used to generate the 22-kHz tone signal by changing the LDO reference voltage. The
linear regulator features low drop out voltage to minimize power loss while keeps enough head room for the 22-
kHz tone with 650-mV amplitude. It also implements a tight current limit for overcurrent protection. The current
limit is set by an external resistor connected to ISET pin. 图 7-1 shows the relationship between the current limit
threshold and the resistor value.
550
y = 117.08x-1.267
500
450
400
350
300
250
200
150
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
ISET (A)
D007
图7-1. Linear Regulator Current Limit Vs Resistor
-1.267
R
(kW) = 117.08 x I
(A)
SET
SET
(1)
A 200-kΩresistor sets the current to be 0.65 A, and 110-kΩresistor sets the current to approximately 1 A.
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7.3.3 Boost Converter Current Limit
The boost converter has the cycle-by-cycle peak current limit on the internal Power MOSFET switch to serve as
the secondary protection when LNB output is hard short. With ISW bit default setting “0” on I2C control
register 0x01, the switch current limit ISW is proportional as LDO current limit I(OCP) set by ISET pin resistor, and
the relationship can be expressed as:
I
= 3 x I
+ 0.8A
SW
(OCP)
(2)
For the 5 V VIN, if LNB current load is up to 1 A, the ISW bit should be written as “1”, the switch current limit
ISW for the internal Power MOSFET is:
I
= 5 x I
+ 0.8A
SW
(OCP)
(3)
While due to the high power loss at 5 V, VIN, it has a chance to trigger the thermal shutdown before the loading is
up to 1 A, especially the VLNB output is high.
7.3.4 Charge Pump
The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. The voltage across the
charge pump capacitor between VLNB and VCP is about 5.4 V, so the absolute value of the VCP voltage will be
VLNB + 5.4 V.
7.3.5 Slew Rate Control
When LNB output voltage transits from 13.4 V to 18.2 V or 18.2 V to 13.4 V, the cap at pin TCAP controls the
transition time. This transition time makes sure the boost converter output to follow LNB output change. Usually
boost converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage
of the linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to
generate a 0.8 V above the LNB output.
The charging and discharging current is 10 µA, thus the transition time can be estimated as:
C
I
(nF)
SS
t
(ms) = 0.8 x
TCAP
(mA)
SS
(4)
A 22-nF capacitor generates about 2 ms transition time.
In light load conditions, when LNB output voltage is set from 18.2 V to 13.4 V, the voltage drops very slow, which
causes wrong VOUT_GOOD (Bit 0 at status register 0x02) logic for LNB output voltage detection. TPS65235
has integrated a pull down circuit to pull down the output during the transition. This ensures the voltage change
can follow the voltage at TCAP. When the 22-kHz tone signal is superimposing on the LNB output voltage, the
pull down current can also provide square wave instead of a distorted waveforms.
7.3.6 Short Circuit Protection, Hiccup and Overtemperature Protection
The LNB output current limit can be set by an external resistor. When short circuit conditions occur or current
limit is triggered, the output current is clamped at the current limit for 4 ms with LDO on. If the condition retains,
the converter will shut down for 128 ms and then restart. This hiccup behavior prevents IC from being overheat.
The hiccup ON/OFF time can be set by I2C register. Refer to Control Register 1 for detail.
The low side MOSFET of the boost converter has a peak current limit threshold which serves as the secondary
protection. If boost converter’s peak current limit is triggered, the peak current will be clamped as high as 3.8 A
when setting ISW default and LNB current limit up to 1 A. If loading current continues to increase, output voltage
starts to drop and output power drops.
Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the junction
temperature exceeds 160°C, the output shuts down. When the die temperature drops below its lower threshold
typically 140°C, the output is enabled.
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When the chip is in overcurrent protection or thermal shutdown, the I2C interface and logic are still active. The
Fault pin is pulled down to signal the processor. The Fault pin signal remains low unless the following action is
taken:
1. If I2C interface is not used to control, EN pin must be recycled in order to pull Fault pin back to high.
2. If I2C interface is used, the I2C master need to read the status Control Register 2, then the Fault pin will be
back to high.
7.3.7 Tone Generation
22 kHz tone signal is implemented at the LNB output voltage as a carrier for DiSEqC command. This tone signal
can be generated by feeding an external 22-kHz clock at the EXTM pin, and it can also be generated with its
internal tone generator controlled by EXTM pin. If EXTM pin is toggled to high, the internal tone signal will be
superimposed at the LNB output, if EXTM pin is low, there will be no tone superimposed at the output stage of
the regulator facilitates a push-pull circuit, so even at zero loading; the 22-kHz tone at the output is still clean
without distortion.
There are two ways to generate the 22 kHz tone signal at the output.
For option1, if the EXTM has 44-kHz tone input, and the bit EXTM TONE of the Control Register 1 is set to "1",
the LNB tone output is 44 kHz.
EXTM
TONE
VLNB(V)
Option 1. Use external tone, gated by EXTM logic pulse
EXTM
TONE
VLNB(V)
Option 2. Use internal tone, gated by EXTM logic envelop
图7-2. Two Ways to Generate 22 kHz Tone
7.3.8 Tone Detection
A 22-kHz tone detector is implemented in the TPS65235 solution. The detector extracts the AC coupled tone
signal from the DIN input and provides it as an open-drain signal on the DOUT pin. With bit DOUTMODE default
setting of the Control Register 2, if tone is present, the DOUT output is logic low; if tone is not present, the
internal output FET is off. If a pull high resistor is connected to the DOUT pin, the output is logic high. The
maximum tone out delay with respect to the input is one and half tone cycle.
Bit DOUTMODE of Control Register 2 is reserved and should not be used.
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7.3.9 Disable and Enable
TPS65235 has a dedicated EN pin to disable and enable the LNB output. At non-I2C application, when the EN
pin is pulled to high, the LNB output is enabled, when the EN pin is pull to low, the LNB output is disabled. At I2C
application, either EN pin is low or high, the I2C registers can be accessed, which allows customer to change the
default LNB output when system power up. When the bit I2C_CON of Control Register 1 is set to “1”, the LNB
output enable or disable is controlled by bit EN of Control Register 2. By default, the bit I2C_CON of the control
register is set to “0”, which makes the LNB output is controlled by the EN pin. 图 7-3 and 图 7-4 shows the
detail control behavior.
EN pin = 0 V
Bit I2C_CON = 1
Bit I2C_CON = 0
图7-3. VLNB Output Controlled by bit EN of
图7-4. VLNB Output Controlled by EN Pin
Control Register 2
7.3.10 Component Selection
7.3.10.1 Boost Inductor
TPS65235 is recommended to operate with a boost inductor value of 4.7 µH or 10 µH. The boost inductor must
be able to support the peak current requirement to maintain the maximum LNB output current without saturation.
Below formula can be used to estimate the peak current of the boost inductor.
I
V
x D
1
2
OUT
IN
I
=
+
x
peak
1-D
L x f
S
(5)
(6)
V
IN
D = 1-
VLNB + 0.8
With the different inductance, the system will have different gain and phase margins, 图7-5 shows a Bode plot of
boost loop with 2 x 10 µF / 35 V of boost capacitor and 4.7 µH, 5.6 µH, 6.8 µH, 8.2 µH and 10 µH of boost
inductance. As the boost inductance increases, the 0 dB crossover frequency keeps relatively constant while the
phase and gain margins reduced. With 4.7 µH, the phase margin is 66.96° and with 10 µH the phase margin is
39.63°.
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4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
4.7 mH, 66.96 deg
10 mH, 39.63 deg
4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
图7-5. Gain and Phase Margin of the Boost Loop with Different Inductance (VIN = 12 V, VOUT = 18.2 V,
ILOAD = 1 A, FSW = 1 MHz, 5 µF, Typical Bode Plot)
7.3.10.2 Capacitor Selection
TPS65235 has a 1 MHz non‐synchronous boost converter integrated and the boost converter features the
internal compensation network. TPS65235 works well with both ceramic capacitor and electrolytic capacitor.
In TPS65235 application, the recommended ceramic capacitors rated are at least X7R/X5R, 35 V rating and
1206 size for the achieving lower LNB output ripple. 表 7-1 shows the recommended ceramic capacitors list for
both 4.7uH and 10uH boost inductors.
If lower cost is demanded, a 100-µF electrolytic (Low ESR) and a 10-µF/35-V ceramic capacitor also work well,
this solution provides lower system cost.
表7-1. Boost Inductor and Capacitor Selections
Boost Inductor
Capacitors
2 x 22 µF
2 x 10 µF
2 x 22 µF
2 x 10 µF
22 µF
Tolerance (%)
Rating (V)
Size
1206
1206
1206
1206
1206
±10
±10
±10
±10
±10
35
35
35
35
35
10 µH
4.7 µH
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图 7-6 and 图 7-7 show a Bode plot of boost loop with 4.7 µH / 10 µH inductance and 4 µF, 5 µF, 7.5 µF, 10 µF,
15 µF and 20 µF of boost capacitance after degrading. As the boost capacitance increases, the phase margin
decreases.
4 mF
4 mF
5 mF
7.5 mF
10 mF
20 mF
15 mF
20 mF
4 mF, 57.45 deg
20 mF, 84.49 deg
4 mF
5 mF
7.5 mF
10 mF
15 mF
20 mF
图7-6. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT
=
18.2 V, ILOAD = 1 A, FSW = 1 MHz, 4.7 µH, Typical Bode Plot)
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5 mF
7.5 mF
10 mF
15 mF
20 mF
5 mF
20 mF
5 mF, 37.23 deg
20 mF, 78.74 deg
5 mF
7.5 mF
10 mF
15 mF
20 mF
图7-7. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT
18.2 V, ILOAD = 1 A, FSW = 1 MHz, 10 µH, Typical Bode Plot)
=
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7.3.10.3 Surge Components
If surge test is needed for the application, D0 and D2 should be added as the external protection components. If
no surge test needed. The D0 and D2 can be removed.
表7-2. Surge Components
Designator
Description
Part Number
Manufacturer
Fairchild Semiconductor
Diodes Inc.
D0
D2
Diode, TVS, Uni, 28 V, 1500 W, SMC
Diode, Schottky, 40 V, 2 A, SMA
SMCJ28A
B240A-13-F
100nF 0.1mF
VOUT
16 VLNB
D3
D0
D2
17
VCP
BOOST
18
19
20
2x22mF
GDR
D1
TPS65235
PGND
1
2
10mH
VIN
10mF
1mF
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图7-8. Surge Components Selection
7.3.10.4 Consideration for Boost Filtering and LNB Noise
Smaller capacitance on boost will lead the cost down for the system, while when the inductor in system is same,
the smaller capacitance on the boost and the larger ripple on the LNB output.
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7.4 Device Functional Modes
表7-3. Logic table
EN
H
12C_CON(1) (2) (3)
SCL
VCTRL
VLNB(4)
19.4 V
14.6 V
18.2 V
13.4 V
0
0
0
0
H
H
L
H
H
H
L
H
L
H
L
Controlled by VSET[3:0]
bits at 0x01 register(5)
X
L
1
0
X
X
X
X
0 V
(1) I2C_CON is the bit7 of the I2C control register 0x01, which is used to set the VLNB output controlled by the I2C register or not.
(2) When I2C interface is used in design, all the I2C registers are accessible even if the I2C_CON bit is “0”.
(3) When I2C_CON is “1”, the VLNB output is controlled by the I2C control register even if the EN pin is low.
(4) When I2C interface is used in design, it is recommended to set the I2C_CON with “1”, if not, the LNB output will be variable because
the SCL is toggled by the I2C register access as the clock signal.
(5) Bit EN of the control register2 is used to disable or enable the LNB output, by default , the bit EN is "1" which enable the LNB output
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7.5 Programming
7.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high external. All the I2C compatible devices connect to the I2C
bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS65235 device works as a slave and supports the following data transfer modes, as defined in the
I2CBus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the
power supply solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as supply voltage remains
above 4.5 V (typical).
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The TPS65235 device supports 7-bit addressing; 10-bit addressing and general call
address are not supported.
The TPS65235 device has a 7-bit address set by ADDR pin. 表7-4 shows how to set the I2C address.
表7-4. I2C Address Selection
ADDR PIN
I2C ADDRESS
Address Format (A6 ≥A0)
Connect to VCC
Floating
0x08H
000 1000
0x09H
000 1001
Connected to GND
0x10H
001 0000
Resistor divider to make ADDR pin voltage in 3 V ~ VCC - 0.8 V
0x11H
001 0001
SDA
tSU, STA
tHD, STA
tBUF
tSU, STO
tSU, DAT
tHD, DAT
tLOW
SCL
tHD, STA
tHIGH
tSP
Start
Condition
Repeated Start
Condition
Stop Start
Condition Condition
tr
tf
图7-9. I2C Interface Timing Diagram
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7.5.2 TPS65235 I2C Update Sequence
The TPS65235 requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS65235 device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. TPS65235 performs an update on the falling edge of the LSB byte.
When the TPS65235 is disabled (EN pin tied to ground) the device cannot be updated via the I2C interface.
7-Bit Slave Address
A6….A0
S
0
A
A
A
P
Register Address
Data Byte
图7-10. I2C Write Data Format
7-Bit Slave Address
A6….A0
S
0
A
A
Sr
1
A
Register1 Address
7-Bit Slave Address
N
P
Data Byte
A: Acknowledge
N: Not Acknowledge
S: Start
System Host
Chip
P: Stop
Sr: Repeated Start
图7-11. I2C Read Data Format
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7.6 Register Maps
7.6.1 Control Register 1 (address = 0x00H) [reset = 00010000]
图7-10. Control Register 1
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-5. Control Register 1
Bit
Field
Type
Reset
Description
1: I2C control enabled
0: I2C control disabled
7
I2C_CON
R/W
0
0: PSM at light load
1: Forced PWM
6
PWM/PSM
R/W
0
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
VSET3
VSET2
VSET1
VSET0
0
1
0
0
See 表7-6 for output voltage selection
1: EXTM 44-kHz tone input support, with 44-kHz tone output at
LNB
0
EXTM TONE
R/W
0
0: EXTM 44-kHz tone input not support, with only 22-kHz tone
output at LNB
表7-6. LNB Output Voltage Selection
VSET3
VSET2
VSET1
VSET0
LNB(V)
11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11.6
12.2
12.8
13.4
14
14.6
15.2
15.8
16.4
17
17.6
18.2
18.8
19.4
20
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7.6.2 Control Register 2 (address = 0x01H) [reset = 0000101]
图7-11. Control Register 2
7
0
6
0
5
0
4
3
2
0
1
0
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-7. Control Register 2
Bit
Field
Type
Reset
Description
1: 22 kHz tone amplitude is 750 mV (typ)
0: 22 kHz tone amplitude is 650 mV (typ)
7
TONEAMP
R/W
0
1: Hiccup ON/OFF time set to 8 ms / 256 ms
0: Hiccup ON/OFF time set to 4 ms / 128 ms
6
5
TIMER
ISW
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
1: Boost switch peak current limit set to 5 x Iocp + 0.8 A
0: Boost switch peak current limit set to 3 x Iocp + 0.8 A
4
3
2
1
FSET
1: 500 kHz switching frequency
0: 1 MHz switching frequency
EN
1: LNB output voltage Enabled
0: LNB output disabled
DOUTMODE
TONE_AUTO
1: Reserved, cannot set to "1"
0: DOUT is kept to low when DIN has the tone input
1: GDR (External bypass FET control) is automatically controlled
by 22 kHz tones transmit
0: GDR (External bypass FET control) is controlled by
TONE_TRANS
R/W
R/W
0
1
1: GDR output with VCP voltage. Bypass FET is ON for tone
transmit from TPS65235
0: GDR output with VLNB voltage for tone receive. Bypass FET
is OFF for tone receiving from satellite
0
TONE_TRANS
表7-8. 22-kHz Tone Receive Mode Selection
TONE_AUTO
TONE_TRANS
Bypass FET
OFF
0
0
1
0
1
x
ON
Auto Detect
TPS65235 has full range of diagnostic flags for operation and debug. Processor can read the status register to
check the error conditions. Once the error happens, the flags are changed, once the errors are gone, the flags
are set back without I2C access.
If flags TSD and OCP are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to
processor. Once TSD and OCP are set to “1”, the FAULT pin logic is latched to low, processor need to read
this status register in order to release the fault conditions.
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7.6.3 Status Register (address = 0x02H) [reset = x0100000]
图7-12. Status Register
7
0
6
0
5
0
4
3
2
0
1
0
0
1
0
1
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-9. Status Register
Bit
Field
Type
Reset
Description
7
Reserved
R
Reserved
1: 22 kHz tone detected on DIN pin is in range
0: 22 kHz tone detected on DIN pin is out of range
6
5
TDETGOOD
LDO_ON
R
R
R
0
1
0
1: Internal LDO is turned on and boost converter is on
0: Internal LDO is turned off but boost converter is on
4
3
T125
TSD
Die temperature > 125°C
Die temperature < 125°C
1: Thermal shutdown triggered. The Fault pin logic is latched to
low, processor need to read this register in order to release the
fault conditions
R
R
0
0
0: No thermal shutdown triggered
2
OCP
1: Over current protection triggered. The Fault pin logic is
latched to low, processor need to read this register in order to
release the fault conditions
0: Overcurrent protection conditions released
1
0
CABLE_GOOD
VOUT_GOOD
1: Cable connection good
0: Cable not connected
R
R
0
0
1: LNB output voltage in range
0: LNB output voltage out of range
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application for DiSEqc1.x Support
TPS65235 can work at both I2C and non I2C interface mode, 图 8-1 shows the application with I2C interface for
supporting DiSEqC 1.x application. With nonI2C mode, the SCL, SDA and ADDR pins can be floating.
15
14
13
11
12
VOUT
D0
100nF 0.1mF
16 VLNB
VCTRL
10
9
D3
D2
17
VCP
ADDR
10k
FAULT
8
7
6
BOOST
18
TPS65235
2x22mF
EN
19
20
GDR
D1
ISET
PGND
110k
1
2
3
4
5
10mH
VIN
22nF
1mF
10mF
1mF
Copyright © 2016, Texas Instruments Incorporated
图8-1. Application for DiSEqc1.x Support
8.2.1 Design Requirements
For this design example, see the parameters in 表8-1.
表8-1. Design Parameters
PARAMETER
VALUE
Input voltage range, VIN
Output voltage range VLNB
Output current range
4.5 V to 16 V
11 V to 20 V
0 A to 1 A
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8.2.2 Detailed Design Procedure
To begin the design process, following need to be done:
• Inductor choose
– Based on the cost requirement, ripple requirement and 节7.3.10 to choose the appropriate inductor.
• Boost capacitor choose
– Based on the cost requirement, ripple requirement and 节7.3.10 to choose the appropriate capacitors.
• Diodes choose.
– D0 and D2 are for the surge protection requirement, if not requirement for surge, it can be removed. Refer
to 节7.3.10.3 for the part selection.
– D1 is for the boost loop, schottky diode is recommended. The current and voltage capability of the D1 can
be determined by the detail application which including input and output power range, and current
requirement.
– D3 is for the VLNB output protection, schottky diode is recommended. The current and voltage capability of
the D3 can be determined by the detail application for the output.
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8.2.3 Application Curves
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = 2 x 22 µF/35 V (unless otherwise noted)
VLNB = 13.4 V
VLNB = 13.4 V
图8-2. Soft Start, Delay from EN High to LNB
图8-3. Disabled, Delay From EN Low to LNB
Output High
Output Low
VLNB = 18.2 V
VLNB = 18.2 V
图8-5. Disabled, Delay From EN Low to LNB
图8-4. Soft Start,Delay from EN High to LNB
Output Low
Output High
EN = 0
VLNB = 13.4 V
EN = 0
VLNB = 13.4 V
图8-6. Soft Start, Delay From I2C Enable
图8-7. Delay From I2C Disable (I2C_CON=0) to LNB
(I2C_CON=1) to LNB Output High
Output Low
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VLNB = 13.4 V
VLNB = 13.4 V
图8-8. No Load, 22 kHz Tone Output
图8-9. 950 mA Load, 22 kHz Tone Output
VLNB = 18.2 V
VLNB = 18.2 V
图8-10. No Load, 22 kHz Tone Output
图8-11. 950 mA Load, 22 kHz Tone Output
图8-13. No load, 22 kHz Tone Delay from EXTM 22
图8-12. No load, 22 kHz Tone Delay from EXTM 22
kHz Input Turns Low To Output Tone Off
kHz Input Turns High To Output Tone On
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图8-15. No Load, 22 kHz Tone Delay From EXTM
图8-14. No Load, 22 kHz Tone Delay From EXTM
Tone Envelop Input Turns Low To Output Tone Off
Tone Envelop Input Turns High To Output Tone On
图8-16. No Load, 44 kHz Tone Delay From EXTM
图8-17. No Load, 44 kHz Tone Delay From EXTM
22 kHz Input Turns High To Output Tone On
22 kHz Input Turns Low To Output Tone Off
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ZHCSEC5D –NOVEMBER 2015 –REVISED MAY 2021
8.2.4 Typical Application for DiSEqc2.x Support
TPS65235 can support both DiSEqC 1.x application and DiSEqC 2.x application, 图 8-18 shows the application
for supporting DiSEqC 2.x application.
10k
10nF
10k
15
14
13
11
12
220mH
VOUT
0.1mF
16 VLNB
VCTRL
10
9
100nF
D0
D3
D2
22nF
17
VCP
ADDR
10k
15 Ohm
FAULT
8
7
6
BOOST
18
TPS65235
2x22mF
EN
19
20
GDR
D1
ISET
PGND
110k
1
2
3
4
5
10mH
VIN
22nF
1mF
10mF
1mF
Copyright © 2016, Texas Instruments Incorporated
图8-18. Application for DiSEqc2.x Support
8.2.4.1 Design Requirements
Refer to 节8.2 for design requirements.
8.2.4.2 Detailed Design Procedure
Refer to 节8.2 for detailed design procedures.
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8.2.4.3 Application Curves
Refer to 节8.2 for application curves. While 图8-19 is special for DiSEqC 2.x application for tone detection.
图8-19. DOUT Tone Detection Output
9 Power Supply Recommendations
The devices are designed to operate from an input supply ranging from 4.5 V to 16 V. The input supply should
be well regulated. If the input supply is located more than a few inches from the converter, an additional bulk
capacitance typically 100 µF may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
TPS65235 is designed to layout in 2‐layer PCB. To ensure reliability of the device, following common printed-
circuit board layout guidelines is recommended.
• It is critical to make sure the GND of input capacitor, output capacitor and the boost converter are connected
at one point at same layer.
• PGND and AGND are in different region, they are connected to the thermal pad. Other components are
connected AGND.
• Put the capacitors for boost as close as possible.
• The loop from VIN, inductor to LX should be as short as possible.
• The loop from VIN, inductor, D1 Schottky diode to Boost should be as short as possible.
• The loop for boost capacitors to PGND should be within the loop from LX, D1 Schottky diode to Boost.
10.2 Layout Example
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
15 14 13
11
12
D3
100nF
VOUT
VLNB
16
17
VCTRL
10
9
0.1uF
D2
VCP
ADDR
10k
FAULT
8
7
6
BOOST
18
19
20
EN
GDR
2x22uF
ISET
PGND
110k
D1
1
2
3
4
5
1uF
1uF
VIN
10uH
22nF
10uF
图10-1. Layout
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65235RUKR
TPS65235RUKT
ACTIVE
ACTIVE
WQFN
WQFN
RUK
RUK
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
65235
65235
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65235RUKR
TPS65235RUKT
WQFN
WQFN
RUK
RUK
20
20
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65235RUKR
TPS65235RUKT
WQFN
WQFN
RUK
RUK
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RUK0020B
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
0.5
0.3
PIN 1 INDEX AREA
3.1
2.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIMENSION A
OPTION 01
OPTION 02
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
(DIM A) TYP
OPT 02 SHOWN
1.7 0.05
6
10
EXPOSED
THERMAL PAD
16X 0.4
5
11
21
SYMM
4X
1.6
1
15
SEE TERMINAL
DETAIL
0.25
20X
0.15
0.1
C A
B
20
16
PIN 1 ID
SYMM
0.05
(OPTIONAL)
0.5
0.3
20X
4222676/A 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.7)
SYMM
20
16
20X (0.6)
1
15
20X (0.2)
(0.6)
TYP
21
SYMM
(2.8)
16X (0.4)
5
11
(R0.05)
TYP
(
0.2) TYP
VIA
6
10
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222676/A 02/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.47) TYP
16
(R0.05) TYP
20
20X (0.6)
1
15
21
20X (0.2)
(0.47)
TYP
SYMM
(2.8)
16X (0.4)
11
5
METAL
TYP
6
10
4X ( 0.75)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 21:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222676/A 02/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS65235-1
采用 FCCM 模式且具有 I2C 接口的 LNB 稳压器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS65235-1RUKR
采用 FCCM 模式且具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS65235-1RUKT
采用 FCCM 模式且具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS65235-3RUKR
具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS652353
具有 I2C 接口的 LNB 稳压器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS65235RUKR
具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS65235RUKT
具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65250
4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUITWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65250RHAR
4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUITWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65250RHAT
4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUITWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65250_1
4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUITWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS65251
4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK SWITCHER WITH INTEGRATED FETWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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