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TPS65266-1

ZHCSFL3 –OCTOBER 2016

TPS65266-1 2.7V 至 6V 输入电压、3A/2A/2A 输出电流三路同步

降压转换器

1 特性

其中的 DC/DC 降压转换器集成了功率 MOSFET，用

于优化功率效率并减少外部使用的元件数量。峰值电流

模式简化了补偿并提供快速瞬态响应。高时钟频率允许

采用更小的低值电感和电容。外部补偿可支持优化环路

补偿并提供快速瞬态响应。轻载条件下，PSM 模式的

降压转换器可减少提供给系统的输入功率。出现短路或

过载故障条件时，断续模式周期性限流功能可限制

MOSFET 功耗。

1

•

工作输入电压范围：2.7V 至 6V

反馈基准电压 0.6V ± 1%

最大持续输出电流 3A/2A/2A

专用使能和软启动

•

支持使能引脚放电，可精确控制启动时间

轻载条件下的脉冲跳跃模式 (PSM)

断续模式下的周期性限流过载保护

可调时钟频率范围为 250kHz 至 2.4MHz

外部时钟同步

TPS65266-1 配有电源正常监控电路，用于监视所有

转换器输出。各通道的输出电压稳压并完成排序

后，PGOOD 引脚将被置为有效。

电源正常指示器

过热保护

如果降压转换器因连续严重过载或短路导致功耗增加，

内部热保护电路将关断器件，防止器件受损。器件充分

冷却后，将自动从热关断状态中恢复。

2 应用

•

打印机和扫描仪

数字电视

器件信息⁽¹⁾

机顶盒

器件型号

TPS65266-1

封装

VQFN (32)

封装尺寸（标称值）

家庭网关和接入点网络

安全监控

5.00mm x 5.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

3 说明

TPS65266-1 整合了 3 通道的高效同步降压转换器，

适用于由输入电压低于 6V 的适配器或电池供电运行

的应用。

空白

简化应用电路原理图

效率与输出负载之间的关系

Vout1

Vin

VINx

LX1

100%

90%

80%

70%

60%

50%

40%

30%

20%

TPS65266-1

FB1

LX2

VINQ

Vout2

Vout3

PGOOD

ENx

FB2

LX3

SSx

ROSC

AGND

FB3

PGND

V_OUT= 1.5 V

V_OUT= 2.5 V

10%

0

0.5

1

1.5

2

2.5

3

Output Load (A)

D001

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSDA6

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Application ................................................. 23

Power Supply Recommendations...................... 31

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 7

6.7 Typical Characteristics.............................................. 8

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 13

7.3 Feature Description................................................. 13

10 Layout................................................................... 31

10.1 Layout Guidelines ................................................. 31

10.2 Layout Example .................................................... 32

11 器件和文档支持 ..................................................... 33

11.1 器件支持 ............................................................... 33

11.2 接收文档更新通知 ................................................. 33

11.3 社区资源................................................................ 33

11.4 商标....................................................................... 33

11.5 静电放电警告......................................................... 33

11.6 Glossary................................................................ 33

12 机械、封装和可订购信息....................................... 33

7

4 修订历史记录

日期

修订版本

注释

2016 年 10 月

*

最初发布版本。

2

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

5 Pin Configuration and Functions

RHB PACKAGE

32-Pin (VQFN)

Top View

BST1 25

LX1 26

16 BST3

15 LX3

PGND1 27

VIN1 28

EN1 29

14 PGND3

13 VIN3

12 VIN2

11 PGND2

10 LX2

Thermal

Pad

EN2 30

EN3 31

GND 32

9

BST2

A. There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for

optimal thermal performance.

Pin Functions

DESCRIPTION

NO.

1

NAME

AGND

Analog ground pin

2

3

An open-drain output; asserts low if output voltage of bucks beyond regulation range due to thermal shutdown, over-

current, under-voltage, or ENx low.

4

PGOOD

Input voltage of converter controller and reference power supply bias. TI recommends to connect a 1-µF capacitor

from the pin to analog ground and put the capacitor as near as possible to this pin.

5

6

7

VINQ

FB2

Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 feedback resistor divider.

Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate

the control loop of buck converter 2 with peak current PWM mode.

COMP2

Soft-start and tracking input for buck2 converter. An internal 5.5-µA pullup current source is connected to this pin.

The soft-start time of buck2 can be programmed by connecting a capacitor between this pin and ground.

8

9

SS2

Boot strapped supply to the high-side floating gate driver in buck2 converter. Connect a capacitor (47 nF

recommended) from BST2 pin to LX2 pin.

BST2

LX2

Switching node connection to the inductor and bootstrap capacitor for buck2 converter. The voltage swing at this pin

is from a diode voltage below the ground up to VIN2 voltage.

10

11

Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input

ceramic capacitor.

PGND2

3

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

Pin Functions (continued)

DESCRIPTION

NO.

NAME

Input power supply for buck2. Connect VIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor

(10 µF suggested).

12

VIN2

Input power supply for buck3. Connect VIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor

(10 µF suggested).

13

14

15

16

17

18

VIN3

Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input

ceramic capacitor.

PGND3

LX3

Switching node connection to the inductor and bootstrap capacitor for buck3 converter. The voltage swing at this pin

is from a diode voltage below the ground up to VIN3 voltage.

Boot strapped supply to the high-side floating gate driver in buck3 converter. Connect a capacitor (47 nF

recommended) from BST3 pin to LX3 pin.

BST3

SS3

Soft-start and tracking input for buck3 converter. An internal 5.5-µA pullup current source is connected to this pin.

The soft-start time of buck3 can be programmed by connecting a capacitor between this pin and ground.

Error amplifier output and loop compensation pin for buck3. Connect a series resistor and capacitor to compensate

the control loop of buck converter 3 with peak current PWM mode.

COMP3

19

20

FB3

Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 feedback resistor divider.

Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.

ROSC

Analog ground common to buck controllers and other analog circuits. It must be routed separately from high-current

power grounds to the (–) terminal of bypass capacitor of input voltage VINQ.

21

22

23

AGND

FB1

Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 feedback resistor divider.

Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate

the control loop of buck converter 1 with peak current PWM mode.

COMP1

Soft-start and tracking input for buck1 converter. An internal 5.5-µA pullup current source is connected to this pin.

The soft-start time of buck1 can be programmed by connecting a capacitor between this pin and ground.

24

25

26

27

28

29

30

SS1

Boot strapped supply to the high-side floating gate driver in buck1 converter. Connect a capacitor (47 nF

recommended) from BST1 pin to LX1 pin.

BST1

LX1

Switching node connection to the inductor and bootstrap capacitor for buck1 converter. The voltage swing at this pin

is from a diode voltage below the ground up to VIN1 voltage.

Power ground connection of buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input

ceramic capacitor.

PGND1

VIN1

EN1

Input power supply for buck1. Connect VIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor

(suggest 10 µF).

Enable for buck1 converter. Float to enable. Can use this pin to adjust the input undervoltage lockup of buck1 with

resistors divider.

Enable for buck2 converter. Float to enable. Can use this pin to adjust the input undervoltage lockup of buck2 with

resistors divider.

EN2

Enable for buck3 converter. Float to enable. Can use this pin to adjust the input undervoltage lockup of buck3 with

resistors divider.

31

32

—

EN3

GND

Ground pin

Thermal

PAD

No electric connection to any signal. Soldered to the ground in PCB for better thermal performance.

4

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

(1)

MIN

–0.3

–1.0

–0.3

–30

MAX

7

UNIT

VIN1, VIN2, VIN3, VINQ

LX1, LX2, LX3 (maximum withstand voltage transient <20 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

EN1, EN2, EN3, PGOOD

7

Voltage at

V

7

FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC

AGND, PGND1, PGND2, PGND3

3.6

0.3

125

150

T_J

Operating junction temperature

°C

T_stg

Storage temperature

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

VIN1, VIN2, VIN3, VINQ

2.7

–0.8

–0.1

–30

6

LX1, LX2, LX3 (maximum withstand voltage transient <20 ns)

BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively

EN1, EN2, EN3, PGOOD

Voltage at

6

V

FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC

Operating junction temperature

3

T_J

125

°C

6.4 Thermal Information

TPS65266-1

THERMAL METRIC⁽¹⁾

RHB

UNIT

32-PIN VQFN

R_θJA

Junction-to-ambient thermal resistance

34.2

27.5

8.3

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

8.3

R_θJC(bot)

2.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

6.5 Electrical Characteristics

T_J= –30°C to 125°C, V_IN= 5 V, typical values are at T_J= 25°C, (unless otherwise noted)

PARAMETER

INPUT SUPPLY VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

2.7

2.35

2.15

6

2.6

V

V_INrising

2.45

2.25

9

UVLO

VIN undervoltage lockout

Shutdown supply current

V_INfalling

2.37

V

I_DD(SDN)

EN1 = EN2 = EN3 = 0 V

µA

EN1 = EN2 = EN3 = 5 V,

FB1 = FB2 = FB3 = 0.8 V

I_{DD(Q_NSW)}

790

340

µA

EN1 = 5 V, EN2 = EN3 = 0 V,

FB1 = 0.8 V

I_{DD(Q_NSW1)}

I_{DD(Q_NSW2)}

I_{DD(Q_NSW3)}

Input quiescent current without

buck1/2/3 switching

EN2 = 5 V, EN1 = EN3 = 0 V,

FB2 = 0.8 V

EN3 = 5 V, EN1 = EN2 = 0 V,

FB3 = 0.8 V

BUCK1, BUCK2, BUCK3

V_FB

Feedback voltage

V_COMP= 1.2 V

0.594

0.6

1.2

0.606

1.26

V

V_EN(XH)

V_EN(XL)

I_EN(X1)

I_EN(X2)

I_EN(hys)

I_SSX

EN1/2/3 high-level input voltage

EN1/2/3 low-level input voltage

EN1/2/3 pullup current

1.1

1.7

1.15

2.1

V

ENx = 1 V

2.5

6.5

µA

EN1/2/3 pullup current

ENx = 1.3 V

5.3

Hysteresis current

3.2

Soft-start charging current

COMP1/2/3 voltage to inductor current

4.5

5.5

G_{(m_PS1/2/3)}

I_LX= 0.5 A

10

A/V

A

(1)

G_m

I_(LIMIT1)

Buck1 peak inductor current limit

Buck1 low-side sink current limit

Buck2/3 peak inductor current limit

Buck2/3 low-side sink current limit

Buck1 high-side switch resistance⁽²⁾

Buck1 low-side switch resistance⁽²⁾

Buck2 high-side switch resistance⁽²⁾

Buck2 low-side switch resistance⁽²⁾

Buck3 high-side switch resistance⁽²⁾

Buck3 low-side switch resistance⁽²⁾

3.55

2.35

4.6

1.4

3.1

1.2

45

50

60

5.6

3.7

I_(LIMITSINK1)

I_(LIMIT2/3)

A

I_{(LIMITSINK2/3)}

R_{ds(on)_HS1}

R_{ds(on)_LS1}

R_{ds(on)_HS2}

R_{ds(on)_LS2}

R_{ds(on)_HS3}

R_{ds(on)_LS3}

POWER GOOD

A

VINQ = 5 V

mΩ

FBx undervoltage falling

FBx undervoltage rising

92.5

95

%VREF

µA

V_{(th_PG)}

Feedback voltage threshold

I_PG

PGOOD pin leakage

1

V_{(LOW_PG)}

PGOOD pin low voltage

I_(SINK)= 1 mA

0.4

V

(1) Lab validation result

(2) Typical value without bonding wires; from design simulation

6

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

Electrical Characteristics (continued)

T_J= –30°C to 125°C, V_IN= 5 V, typical values are at T_J= 25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OSCILLATOR

F_SW

Switching frequency

R_(OSC)= 51.1 kΩ

920

250

1000

1080

2400

2

kHz

V

F_SW(range)

F_(SYNC)

F_{(SYNC_HI)}

V_{(SYNC_LO)}

Switching frequency

Clock sync frequency range

Clock sync high threshold

Clock sync low threshold

0.4

V

THERMAL PROTECTION

(1)

T_{(TRIP_OTP)}

Temperature rising

Hysteresis

160

20

°C

Thermal protection trip point

(1)

T_{(HYST_OTP)}

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

BUCK1, BUCK2, BUCK3

t_{ON_MIN}

Minimum on-time

80

115

ns

G_{m_EA}

Error amplifier transconductance

–2 µA < I_(COMPX)< 2 µA

290

µS

HICCUP TIMING

t_{Hiccup_wait}

Overcurrent wait time⁽¹⁾

Hiccup time before restart⁽¹⁾

512

cycles

t_{Hiccup_re}

16382

POWER GOOD

t_{DEGLITCH(PG)_F}

PGOOD falling edge deglitch time

128

cycles

t_{RDEGLITCH(PG)_R}PGOOD rising edge deglitch time

16350

OSCILLATOR

t_{SYNC_w}

Clock sync minimum pulse duration

80

ns

(1) Lab validation result

7

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

6.7 Typical Characteristics

T_A= 25°C, V_IN= 5 V, V_OUT1= 1.0 V, V_OUT2= 1.5 V, V_OUT3= 1.8 V F_SW= 1 MHz (unless otherwise noted)

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

V_OUT= 1 V

V_OUT= 1.5 V

V_OUT= 2.5 V

V_OUT= 1 V

V_OUT= 1.5 V

V_OUT= 2.5 V

0.01

0.1

1

3

0.01

0.1

1

2

Output Load (A)

D002

D003

Figure 1. Buck1 Efficiency

Figure 2. Buck2 Efficiency

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

1.1

1.05

1

0.95

0.9

V_OUT= 1 V

V_OUT= 1.5 V

V_OUT= 2.5 V

0.01

0.1

1

2

0

0.5

1

1.5

2

2.5

3

Output Load (A)

D004

Figure 3. Buck3 Efficiency

Figure 4. Buck1, Load Regulation

1.6

1.55

1.5

1.9

1.85

1.8

1.45

1.4

1.75

1.7

0

0.5

1

1.5

2

0

0.5

1

1.5

2

Output Load (A)

D005

D006

Figure 5. Buck2, Load Regulation

Figure 6. Buck3, Load Regulation

8

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

Typical Characteristics (continued)

T_A= 25°C, V_IN= 5 V, V_OUT1= 1.0 V, V_OUT2= 1.5 V, V_OUT3= 1.8 V F_SW= 1 MHz (unless otherwise noted)

1.08

1.04

1

1.65

IOUT 0.1 A

IOUT 1.5 A

IOUT 3 A

IOUT 0.1A

IOUT 1.0A

IOUT 2A

1.6

1.55

1.5

0.96

1.45

0.92

1.4

2.5

3

3.5

4

4.5

5

5.5

6

2.5

3

3.5

4

4.5

5

5.5

6

Input Voltage (V)

D007

D008

Figure 7. Buck1, Line Regulation

Figure 8. Buck2, Line Regulation

1.9

1.85

1.8

0.606

0.604

0.602

0.6

IOUT 0.1 A

IOUT 1.0 A

IOUT 2 A

0.598

0.596

0.594

1.75

1.7

2.5

3

3.5

4

4.5

5

5.5

6

-30

-10

10

30

50

70

90

110

130

Input Voltage (V)

Junction Temperature, T_J(°C)

D009

D010

Figure 9. Buck3, Line Regulation

Figure 10. Voltage Reference vs Temperature

1040

1020

1000

980

15

13

11

9

7

960

5

-30

-10

10

30

50

70

90

110

130

-30

-10

10

30

50

70

90

110

130

Junction Temperature, T_J(°C)

D011

D012

ROSC = 51.1 kΩ

V_IN= 5 V

Figure 11. Oscillator Frequency vs Temperature

Figure 12. Shutdown Quiescent Current vs Temperature

9

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

Typical Characteristics (continued)

T_A= 25°C, V_IN= 5 V, V_OUT1= 1.0 V, V_OUT2= 1.5 V, V_OUT3= 1.8 V F_SW= 1 MHz (unless otherwise noted)

2.3

2.2

2.1

2

5.6

5.5

5.4

5.3

5.2

5.1

1.9

-30

-10

10

30

50

70

90

110

130

-30

-10

10

30

50

70

90

110

130

Junction Temperature, T_J(°C)

D013

D014

V_IN= 5 V

EN = 1 V

V_IN= 5 V

EN = 1.3 V

Figure 13. EN Pin Pullup Current vs Temperature, EN = 1 V

Figure 14. EN Pin Pullup Current vs Temperature, EN = 1.3 V

1.28

1.23

1.24

1.2

1.19

1.15

1.11

1.07

1.16

1.12

-30

-10

10

30

50

70

90

110

130

-30

-10

10

30

50

70

90

110

130

Junction Temperature, T_J(°C)

D015

D016

V_IN= 5 V

Figure 15. EN Pin Threshold Rising vs Temperature

Figure 16. EN Pin Threshold Falling vs Temperature

6

5.8

5.6

5.4

5.2

5

4.8

4.6

4.4

4.2

4

-30

-10

10

30

50

70

90

110

130

-30

-10

10

30

50

70

90

110

130

Junction Temperature, T_J(°C)

D017

D018

V_IN= 5 V

Figure 17. SS Pin Charge Current vs Temperature

Figure 18. Buck1 High-Side Current Limit vs Temperature

10

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

Typical Characteristics (continued)

T_A= 25°C, V_IN= 5 V, V_OUT1= 1.0 V, V_OUT2= 1.5 V, V_OUT3= 1.8 V F_SW= 1 MHz (unless otherwise noted)

3.5

3.3

3.1

2.9

2.7

3.5

3.3

3.1

2.9

2.7

-30

-10

10

30

50

70

90

110

130

-30

-10

10

30

50

70

90

110

130

Junction Temperature, T_J(°C)

D019

D020

V_IN= 5 V

Figure 19. Buck2 High-Side Current Limit vs Temperature

Figure 20. Buck3 High-Side Current Limit vs Temperature

11

TPS65266-1

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7 Detailed Description

7.1 Overview

The TPS65266-1 is a triple 3-A/2-A/2-A output current, synchronous step-down (buck) converter for applications

operating off the adaptor or battery with input voltage lower than 6 V. The feedback voltage reference for each

buck is 0.6 V. Each buck is independent with dedicated enable, soft-start, and loop compensation. The

TPS65266-1 implements a constant frequency, peak current mode control that simplifies external loop

compensation. The switch clock of buck1 is 180° out-of-phase operation from the clock of buck2 and buck3

channels to reduce input current ripple, input capacitor size and power-supply-induced noise.

The TPS65266-1 has been designed for safe monotonic startup into prebiased loads. The default start-up is

when VIN is typically 2.45 V. The ENx pin has an internal pullup current source that can be used to adjust the

input voltage undervoltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for

automatically starting up the converters with the internal pullup current.

The TPS65266-1 features PGOOD pin to supervise output voltages of buck converter. The TPS65266-1 has

power-good comparators with hysteresis, which monitor the output voltages through internal feedback voltages.

When all bucks are in regulation range and power sequence is done, PGOOD is asserted high.

The SS (soft-start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during

power up. A small-value capacitor or resistor divider should be coupled to the pin for soft start or critical power-

supply sequencing requirements.

The TPS65266-1 is protected from overload and thermal fault conditions.

At light load, TPS65266-1 automatically operates in the pulse skipping mode (PSM) to save power.

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7.2 Functional Block Diagram

ROSC

OSC/SYNC

Phase Shift

VIN1

VIN2

clk

VIN

BST

VIN

I_SNS

en_buck2

enable

en_buck1

I

BST1

LX1

^SNSBST

BST2

LX2

LX

BUCK1

BUCK2

LX

PGND1

SS1

PGND2

PGND

SS

PGND

5.5 µA

Comp

SS2

FB2

SS

FB1

Vref

COMP1

VINQ

COMP2

PGOOD

vfb1

Power

Good

VIN3

clk

vfb2

vfb3

VIN

BST

VIN

I_SNS

en_buck3

enable

BST3

LX3

2.1 µA

3.2 µA

BUCK3

LX

EN1

PGND3

1.2 V

PGND

5.5 µA

Comp

SS3

FB3

SS

Discharge during power up

3.2 µA

en_buck1

2.1 µA

EN2

en_buck2

en_buck3

Vref

State

Machine

1.2 V

Discharge during power up

3.2 µA

COMP3

AGND

2.1 µA

VINQ

OT

EN3

1.2 V

Over

Temp

Discharge during power up

7.3 Feature Description

7.3.1 Adjusting the Output Voltage

The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI

recommends to use 1% tolerance or better resistors.

Vout

R1

FB

COMP

R2

0.6 V

Figure 21. Voltage Divider Circuit

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Feature Description (continued)

0.6

R₂= R₁ì

V_outœ 0.6

(1)

To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator

is more sensitive to noise. Table 1 shows the recommended resistor values.

Table 1. Output Resistor Divider Selection

Output Voltage

(V)

R1

(kΩ)

R2

(kΩ)

1

10

15

10

1.2

1.5

1.8

2.5

3.3

5

15

10

20

10

31.6

45.3

22.6

73.2

36.5

10

4.99

10

5

4.99

7.3.2 Enable and Adjusting UVLO

The EN1/2/3 pin provides electrical on and off control of the device. After the EN1/2/3 pin voltage exceeds the

threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the

regulator stops switching and enters low I_qstate.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If

an application requires controlling the EN pin, use open-drain or open-collector output logic to interface with the

pin.

The device implements internal UVLO circuitry on the VINQ pin. The device is disabled when the VINQ pin

voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 200

mV. If an application requires either a higher UVLO threshold on the VINQ pin or a secondary UVLO on the

VINx, in split-rail applications, then the ENx pin can be configured as shown in Figure 22, Figure 23, and

Figure 24. When using the external UVLO function, TI recommends to set the hysteresis to be >200 mV.

The EN pin has a small pullup current I_p, which sets the default state of the pin to enable when no external

components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO

function because it increases by I_hafter the EN pin crosses the enable threshold. Calculate the UVLO thresholds

using Equation 2 and Equation 3.

V

V_START

(

^ENFALLING) - V_STOP

V_ENRISING

R₁=

R₂=

V

I_P(1- ^ENFALLING) +I_h

V_ENRISING

(2)

R₁ì V_ENFALLING

V_STOP- V_ENFALLING+ R₁(I_h+I_p)

where

•

I_h= 3.2 µA

I_p= 2.1 µA

V_ENRISING= 1.2 V

V_ENFALLING= 1.15 V

(3)

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VINQ

i

h

R₁

p

i

EN

R₂

Figure 22. Adjustable VINQ UVLO

VIN

i

h

R₁

p

i

EN

R₂

Figure 23. Adjustable VIN UVLO, VINQ > 2.7 V

VINQ

VIN

i

h

R₁

p

i

EN

R₂

Figure 24. Adjustable VIN and VINQ UVLO

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7.3.3 Soft-Start Time

The voltage on the respective SS pin controls the start-up of buck output. When the voltage on the SS pin is less

than the internal 0.6-V reference, the TPS65266-1 regulates the internal feedback voltage to the voltage on the

SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output of

buck to track another supply during start-up. The device has an internal pullup current source of 5.5 μA (typical)

that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The TPS65266-1

regulates the internal feedback voltage to the voltage on the SS pin, allowing VOUT to rise smoothly from 0 V to

its regulated voltage without inrush current. Calculate the approximate soft-start time with Equation 4.

Css(nF)ì Vref (V)

t_ss(ms) =

Iss(µA)

(4)

Many of the common power-supply sequencing methods can be implemented using the SSx and ENx pins.

Figure 25 shows the method implementing ratiometric sequencing by connecting the SSx pins of three buck

channels together. The regulator outputs ramp up and reach regulation at the same time. When calculating the

soft-start time, the pullup current source must be tripled in Equation 4.

EN

29

EN threshold = 1.2 V

EN1

30

EN2

31

EN3

Vout3 = 1.8 V

24

SS1

Vout2 = 1.5 V

8

SS2

Vout1 = 1.0 V

17

SS3

Css

C_SS× 0.6 V

t_SS

=

16.5 µA

Figure 25. Ratiometric Power-Up Using SSx Pins

Simultaneous power-supply sequencing can be implemented by connecting capacitor to SSx pin, shown in

Figure 26. Using Equation 4 and Equation 5, calculate the capacitors.

Css1

Css2

Css3

=

Vout1 Vout2 Vout3

(5)

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EN

29

30

31

EN threshold = 1.2 V

EN1

EN2

EN3

Vout3 = 1.8 V

Vout2 = 1.5 V

24

8

SS1

SS2

SS3

Css1

Css2

Css3

Vout1 = 1.0 V

17

C_SS3× 0.6 V

5.5µA

t_SS

=

Figure 26. Simultaneous Startup Sequence Using SSx Pins

7.3.4 Power-Up Sequencing

The TPS65266-1 has a dedicated enable pin and soft-start pin for each converter. The converter enable pins are

biased by a current source that allows for easy sequencing by the addition of an external capacitor. Enable pins

have a discharge function, which ensures power-up sequencing is effective at quickly powering down and up

status. Disabling the converter with an active pulldown transistor on the ENs pin allows for a predictable power-

down timing operation. Figure 27 shows the timing diagram of a typical buck power-up sequence with connecting

a capacitor at ENx pin.

When VINQ pin voltage rises to about 1 V, the internal EN turns on and a typical 1.4-µA current is charging ENx

pin from input supply. If any of the EN pin voltages reaches 0.5 V when powered up, three EN pin discharge

functions are triggered and keep 2 ms with discharge resistor around 1.2 kΩ to GND, then a 2.1-µA pullup

current is sourcing ENx. After ENx pin voltage reaches to ENx enabling threshold, 3.2-µA hysteresis current

sources to the pin to improve noise sensitivity.

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About 1 V

ëLbv

Lnꢁernal 9b

EN Threshold

9b Çꢀresꢀold

1.2ë

0.ꢂ ë

9bx

ENx Rise Time

Dictated by C_EN

t = C_ENx× 1.2 V / 2.1 µA

Discharge time 2 ms

t = C_ENx× 0.5 V / 1.4 µA

About 1.7 V

0.6 ë

{{x

Pre-Bias Startup

ëhÜÇx

Soft Start Rise Time

Dictated by C_SS

PGOOD Deglitch Time 16350 cycles

t = C_SSx× 0.6 V / 5.5 µA

tDhh5

Figure 27. Startup Power Sequence

7.3.5 Bootstrap Voltage and BST-LX UVLO

Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 28, which is

normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side

MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less

than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47 nF. TI

recommends a ceramic capacitor with an X7R- or X5R-grade dielectric with a voltage rating of 10 V or higher

because of the stable characteristics over temperature and voltage.

To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage

is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX

drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is

turned on allowing the boot capacitor to be recharged.

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VINQ

VINx

LDO

(VBSTx-VLXx)

nBootUV

+2.1 V

BSTx

High-side

MOSFET

nBootUV

PWM

CB

UVLO

Bias

Buck Controller

Gate Driver

LXx

Low-side

MOSFET

nBootUV

PWM

BootUV

Protection

Gate Driver

Clk

Figure 28. Bootstrap Voltage and Diagram

7.3.6 Out of Phase Operation

To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.

This enables the system by having less input current ripple to reduce input capacitors’ size, cost, and EMI.

7.3.7 Output Overvoltage Protection (OVP)

The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded, the

error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower

than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum

output current. After the condition is removed, the regulator output rises and the error amplifier output transitions

to the steady-state voltage. In some applications with small output capacitance, the load can respond faster than

the error amplifier. This leads to the possibility of an output overshoot. Each buck compares the FB pin voltage to

the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off

preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower

than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.

7.3.8 Slope Compensation

To prevent the subharmonic oscillations when the device operates at duty cycles greater than 50%, the

TPS65266-1 adds built-in slope compensation, which is a compensating ramp to the switch current signal.

7.3.9 Overcurrent Protection

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side

MOSFET and low-side MOSFET.

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7.3.9.1 High-Side MOSFET Overcurrent Protection

The device implements current mode control, which uses the COMP pin voltage to control the turn off of the

high-side MOSFET and the turn-on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch

current and the current reference generated by the COMP pin voltage are compared, when the peak switch

current intersects the current reference, the high-side switch is turned off.

7.3.9.2 Low-Side MOSFET Overcurrent Protection

While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During

normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side

MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side

sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the

next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing

current limit at the start of a cycle.

The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are

off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than

the hiccup wait time, which is programmed for 512 cycles (typical) shown in Figure 29, the device shuts down

itself and restarts after the hiccup time of 16382 cycles (typical). The hiccup mode helps to reduce the device

power dissipation under a severe overcurrent condition.

OCP peak inductor current threshold

OC limiting (waiting) time

512 cycles (typical)

hiccup time

16382 cycles (typical)

Soft-start time

t = Css × 0.6 V / 5.5 µA

Output over loading

iL

Inductor Current

Soft-start is reset after OC waiting time

About 1.7 V

0.6 V

OC fault removed, soft-start and output recovery

SS

SS Pin Voltage

Output OC circuit

Vout

Output Voltage

Figure 29. Overcurrent Protection

7.3.10 Power Good

The PGOOD pin is an open-drain output. After the feedback voltage of each buck is higher than 95% (rising) of

the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin floats. TI recommends to use

a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.0 V or less.

The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) of the nominal

internal reference voltage. Also, the PGOOD is pulled low if the input voltage is undervoltage locked up, thermal

shutdown is asserted, the EN pin is pulled low, or the converter is in a soft-start period.

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7.3.11 Adjustable Switching Frequency

The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching

frequency of the device is adjustable from 250 kHz to 2.4 MHz.

To determine the ROSC resistance for a given switching frequency, use Equation 6 or the curve in Figure 30. To

reduce the solution size, the user should set the switching frequency as high as possible, but consider the

tradeoffs of the supply efficiency and minimum controllable on-time.

ƒ_osc(kHz) = 46657 ì R(kW)^œ0.976

(6)

2400

2200

2000

1800

1600

1400

1200

1000

800

600

400

200

0

20 40 60 80 100 120 140 160 180 200 220

ROSC (kO)

D021

Figure 30. ROSC vs Switching Frequency

When an external clock applies to the ROSC pin, the internal phase locked loop (PLL) has been implemented to

allow internal clock synchronizing to an external clock between 250 kHz and 2.4 MHz. To implement the clock

synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to

80%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the

switching cycle is synchronized to the falling edge of the ROSC pin.

In applications where both resistor mode and synchronization mode are needed, the device can be configured as

shown in Figure 31. Before an external clock is present, the device works in resistor mode and ROSC resistor

sets the switching frequency. When an external clock is present, the synchronization mode overrides the resistor

mode. The first time the ROSC pin is pulled above the ROSC high threshold (2.0 V), the device switches from

the resistor mode to the synchronization mode and the ROSC pin becomes high impedance as the PLL starts to

lock onto the frequency of the external clock. TI does not recommended to switch from synchronization mode

back to resistor mode because the internal switching frequency drops to 100 kHz first before returning to the

switching frequency set by ROSC resistor.

Mode

Selection

IC

ROSC

Figure 31. Works With Resistor Mode and Synchronization Mode

7.3.12 PSM

The TPS65266-1 can enter high-efficiency PSM operation at light load current.

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When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 250-mA

current typically. Because the integrated current comparator catches the peak inductor current only, the average

load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak

inductor current is clamped at 250 mA (see Figure 32).

When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current

comparator turns off the low-side MOSFET when the inductor current reaches 0, preventing it from reversing and

going negative.

Due to the delay in the circuit and current comparator tdly (typical 50 nS at V_IN= 5 V), the real peak inductor

current threshold to turn off high-side power MOSFET could shift higher depending on inductor inductance and

input/output voltages. Calculate the threshold of peak inductor current to turn off high-side power MOSFET with

Equation 7.

V

_IN- V_OUT

IL_PEAK= 250 mA +

x tdly

L

(7)

When the charge accumulated on V_OUTcapacitor is more than loading need, COMP pin voltage drops to low

voltage driven by error amplifier. There is an internal comparator at COMP pin. If comp voltage is < 0.35 V, the

power stage stops switching to save power.

250 mA

Turn off

high-side Power MOSFET

Inductor

Current Peak

Current

Sensing

x1

Current Comparator

Delay: tdly

IL_Peak

Inductor Peak Current

Figure 32. PSM Current Comparator

7.3.13 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C

typically.

7.4 Device Functional Modes

7.4.1 Operation With V_IN< 2.6 V (Minimum V_IN)

The device operates with input voltages above 2.6 V. The maximum UVLO voltage is 2.6 V and will operate at

input voltages above 2.6 V. The typical UVLO voltage is 2.45 V and the device may operate at input voltages

above that point. The device also may operate at lower input voltages, the minimum UVLO voltage is 2.35 V

(rising) and 2.15V (falling). At input voltages below the UVLO minimum voltage, the devices will not operate.

7.4.2 Operation With EN Control

The enable rising edge threshold voltage is 1.2 V typical and 1.26 V maximum. With EN held below that voltage

the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When input

voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the

device becomes active. Switching is enabled, and the soft start sequence is initiated. The device will start at the

soft start time determined by the external soft start capacitor as shown in Figure 35 to Figure 37.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is a triple-synchronous step-down DC/DC converter. It is typically used to convert a higher DC

voltage to lower DC voltages with a continuously available output current of 3 A/2 A/2 A. The following design

procedure can be used to select component values for the TPS65266-1. This section presents a simplified

discussion of the design process.

8.2 Typical Application

R1

0

C1

0.047 µF

U1

VIN1

VIN 3.3 V

VIN

L1

28

12

13

25

26

VOUT1 1.0 V 3 A

VOUT1

BST1

LX1

C5

C7

22 µF

C8

22 µF

C9

22 µF

C2

22 µF

C3

22 µF

C4

2.2 µH

VIN2

VIN3

VFB1

DNI

R5

15.0 kΩ

DNI

C6

R3

R6

22

23

FB1

VFB1

VFB2

VFB3

GND

9.1 kΩ

10.0 kΩ

1000 pF

COMP1

C10

0.047 µF

L2GND

5

GND

VOUT2 1.5 V 2 A

VOUT1

VINQ

R7

9

BST2

LX2

C11

2.2 µF

C15

0 Ω

C12

22 µF

C13

22 µF

2.2 µH

VFB2

10

DNI

R11

10.0 kΩ

C14

R12

GND

29

30

31

6

7

DNI

R10

GND

C16

15.0 kΩ

EN1

EN2

EN3

EN1

EN2

EN3

FB2

20 kΩ

COMP2

1000 pF

GND

R13

16

15

C17

BST3

LX3

0

L3

0.047 µF

VOUT3 1.8 V 2 A

VOUT1

C21

C18

22 µF

C19

22 µF

24

8

2.2 µH

SS1

SS2

SS3

VFB3

19

18

4

FB3

COMP3

PGOOD

DNI

R16

10.0 kΩ

C20

R15

R17

17

GND

20 kΩ

C25

20.0 kΩ

R9

1000 pF

VIN

C22

0.01 µF

C23

0.01 µF

C24

0.01 µF

100 kΩ

1

2

GND

AGND

DNI

20

3

21

32

GND

ROSC

SYN

GND

27

11

PGND1

PGND2

PGND3

PAD

R18

51.1 kΩ

14 GND

33

TPS65266RHB

GND

Figure 33. Typical Application Schematic

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Typical Application (continued)

8.2.1 Design Requirements

This example details the design of a triple-synchronous step-down converter. The designer must know a few

parameters to start the design process. These parameters are typically determined at the system level. For this

example, start with the following known parameters in Table 2.

Table 2. Design Parameters

Parameter

Value

Vout1

Iout1

Vout2

Iout2

Vout3

Iout3

1.0 V

3 A

1.5 V

2 A

1.8 V

2 A

Transient response 1-A load step

Input voltage

±5%

5.0 V normal, 2.7 to 6 V

Output voltage ripple

Switching frequency

±1%

1 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Inductor Selection

To calculate the value of the output inductor, use Equation 8. LIR is a coefficient that represents the amount of

inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output

capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because

the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In

general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for

the majority of applications.

V

- V_out

I_oì LIR

V _out

inmax

L =

ì

V_inmaxì ƒ_sw

(8)

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.

The RMS and peak inductor current can be found from Equation 10 and Equation 11.

V

- V_out

L

V_out

_inmaxì ƒ_sw

- V_out

inmax

I_ripple

=

ì

V

(9)

V_outì (V

)

2

inmax

(

)

V_inmaxì L ì ƒsw

I_Lrms= I_O²+

12

(10)

(11)

I_ripple

I_Lpeak= I_out

+

2

The current flowing through the inductor is the inductor ripple current plus the output current. During power-up,

faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current

level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit

of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current

rating equal to or greater than the switch current limit rather than the peak inductor current.

8.2.2.2 Output Capacitor Selection

The three primary considerations for selecting the value of the output capacitor are: the output capacitor

determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in

load current. The output capacitance must be selected based on the most stringent of these three criteria.

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The first criterion is the desired response to a large change in the load current. The output capacitor needs to

supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up

times for the regulator where the output capacitor must hold the output voltage above a certain level for a

specified amount of time after the input power is removed. The regulator is also temporarily not able to supply

sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from

no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change

in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be

sized to supply the extra current to the load until the control loop responds to the load change. The output

capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a

tolerable amount of droop in the output voltage. Equation 12 shows the minimum output capacitance necessary

to accomplish this.

2ì DI_out

ƒ_swì DV_out

C_o=

where

•

ΔIout is the change in output current.

ƒ_SWis the regulator's switching frequency.

ΔVout is the allowable change in the output voltage.

(12)

Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

1

C_o>

ì

V_oripple

8ì ƒ_sw

I_oripple

where

•

ƒ_SWis the switching frequency.

V_rippleis the maximum allowable output voltage ripple.

I_rippleis the inductor ripple current.

(13)

Equation 14 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification.

V_oripple

R_ESR

<

I_oripple

(14)

Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increase this

minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or

producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some

capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 15 can

be used to calculate the RMS ripple current the output capacitor needs to support.

V_outì (V

- V_out)

inmax

I_corms

=

12 ì V_inmaxì L ì ƒ_sw

(15)

8.2.2.3 Input Capacitor Selection

The TPS65266-1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF

of effective capacitance on the VIN input voltage pins. In some applications, additional bulk capacitance may also

be required for the VIN input. The effective capacitance includes any DC bias effects. The voltage rating of the

input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current

rating greater than the maximum input current ripple of the TPS65266-1. Calculate the input ripple current using

Equation 16.

V

- V_out

V_out

(

ì

)

inmin

I

= I_out

ì

inrms

V

inmin

(16)

25

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output

capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor

decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple

voltage of the regulator. Calculate the input voltage ripple using Equation 17.

I_outmaxì 0.25

C_inì ƒ_sw

DV =

in

(17)

8.2.2.4 Loop Compensation

The TPS65266-1 incorporates a peak current mode control scheme. The error amplifier is a transconductance

amplifier with a gain of 290 µS. A typical type II compensation circuit adequately delivers a phase margin

between 30° and 90°. C_badds a high-frequency pole to attenuate high-frequency noise when needed. To

calculate the external compensation components, follow these steps.

1. Select switching frequency, ƒ_SW, that is appropriate for application depending on L and C sizes, output ripple,

EMI, and so forth. Switching frequency between 500 kHz to 1.5 MHz gives best trade-off between

performance and cost. To optimize efficiency, lower switching frequency is desired.

2. Set up crossover frequency, ƒ_c, which is typically between 1 / 5 and 1 / 20 of ƒ_SW

.

3. R_Ccan be determined by:

2p ì ƒ_Cì V_Oì C_O

G_mœEAì Vref ì G_mœPS

R_C

=

where

•

G_{m_EA}is the error amplifier gain (290 µS).

G_{m_PS}is the power stage voltage to current conversion gain (10 A/V).

(18)

1

ƒ_p=

C_Oì R_Lì 2p

4. Calculate C_Cby placing a compensation zero at or before the dominant pole

R_Lì C_O

C_C

=

R_C

(19)

(20)

5. Optional C_bcan be used to cancel the zero from the ESR associated with C_O.

R_ESRì C_O

C_b=

R_C

6. Type III compensation can be implemented with the addition of one capacitor, C₁. This allows for slightly

higher loop bandwidths and higher phase margins. If used, C₁is calculated from Equation 21.

1

C₁=

2p ì R₁ì ƒ_c

(21)

26

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

LX

VOUT

i_L

R_ESR

R_L

Current Sense

I/V Converter

G_{m_PS}= 10 A / V

C_o

C₁

R₁

FB

Vfb

EA

COMP

V

= 0.6 V

ref

R₂

R_c

C_c

G_{m_EA}= 290 µS

C_b

Figure 34. DC/DC Loop Compensation

8.2.3 Application Curves

Figure 35. Buck1, Soft-Start, Iout = 3 A

Figure 36. Buck2, Soft-Start, Iout = 2 A

27

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

Figure 38. Buck1, Output Voltage Ripple, Iout = 3 A

Figure 37. Buck3, Soft-Start, Iout = 2 A

Figure 39. Buck2, Output Voltage Ripple, Iout = 2 A

Figure 40. Buck3, Output Voltage Ripple, Iout = 2 A

SR = 0.25 A/µs

Figure 41. Buck1, Load Transient, 0.75 to 1.5 A

Figure 42. Buck1, Load Transient, 1.5 to 2.25 A

28

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

SR = 0.25 A/µs

Figure 43. Buck2, Load Transient, 0.5 to 1.0 A

Figure 44. Buck2, Load Transient, 1.0 to 1.5 A

SR = 0.25 A/µs

Figure 45. Buck3, Load Transient, 0.5 to 1.0 A

Figure 46. Buck3, Load Transient, 1.0 to 1.5 A

Figure 47. Buck1, Hiccup and Recovery

Figure 48. Buck2, Hiccup and Recovery

29

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

Figure 50. 180° Out of Phase

Figure 49. Buck3, Hiccup and Recovery

30

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

9 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 2.7 and 6 V. This input power

supply should be well regulated. If the input supply is located more than a few inches from the TPS65266-1

converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An

electrolytic capacitor with a value of 47 μF is a typical choice.

10 Layout

10.1 Layout Guidelines

The TPS65266-1 supports a 2-layer PCB layout, shown in Figure 51.

Layout is a critical portion of good power supply design. See Figure 51 for a PCB layout example. The top

contains the main power traces for VIN, VOUT, and LX. The top layer also has connections for the remaining

pins of the TPS65266-1 and a large top-side area filled with ground. The top-layer ground area should be

connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor, and

directly under the TPS65266-1 device to provide a thermal path from the exposed thermal pad land to ground.

The bottom layer acts as ground plane connecting analog ground and power ground.

For operation at full-rated load, the top-side ground area together with the bottom-side ground plane must

provide an adequate heat dissipating area. Several signals paths conduct fast changing currents or voltages that

can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies'

performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR

ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass

capacitor connections, the VIN pins, and the ground connections. The VIN pin must also be bypassed to ground

using a low-ESR ceramic capacitor with X5R or X7R dielectric.

Because the LX connection is the switching node, the output inductor should be located close to the LX pins, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor

ground should use the same power ground trace as the VIN input bypass capacitor. Try to minimize this

conductor length while maintaining adequate width. The small signal components should be grounded to the

analog ground path.

The FB and COMP pins are sensitive to noise so the resistors and capacitors should be located as close as

possible to the IC and routed with minimal lengths of trace. Place the additional external components

approximately as shown in Figure 51.

31

TPS65266-1

ZHCSFL3 –OCTOBER 2016

www.ti.com.cn

10.2 Layout Example

VOUT1

VOUT3

BST1

LX1

BST3

LX3

PGND3

PGND1

VIN1

EN1

VIN3

VIN2

PGND2

LX2

VIN

EN2

EN3

AGND

BST2

VOUT2

TOPSIDE

GROUND

AREA

0.010-inch Diameter

Thermal VIA to Ground Plane

VIA to Ground Plane

Figure 51. PCB Layout

32

TPS65266-1

www.ti.com.cn

ZHCSFL3 –OCTOBER 2016

11 器件和文档支持

11.1 器件支持

11.1.1 相关器件

器件型号

说明

备注

TPS65261

4.5V 至 18V 三路降压，均配有输入电压电三通道降压 3A/2A/2A 输出电流，通过开漏 RESET 信号监视输入电源故

TPS65261-1

源故障指示灯

障，支持自动电源排序

三路降压 3A/1A/1A 输出电流，支持自动电源排序

双路 LDO：

TPS65262

4.5V 至 18V 三路降压，具有双路可调

TPS65262-1

LDO

TPS65262，200mA/100mA

TPS65262-1，350mA/150mA

TPS65263

4.5V 至 18V 三路降压，具有 I²C 接口

三路降压 3A/2A/2A 输出电流，I²C 控制的动态电压调节 (DVS)

11.2 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

33

重要声明

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JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售

都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

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TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

17

SEE SIDE WALL

DETAIL

2X

SYMM

33

3.5

0.3

0.2

32X

24

0.1

C A B

C

1

0.05

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.6)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.8)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.6)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.8)

17

8

METAL

TYP

16

9

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TPS65266-1RHBR
厂家：	TEXAS INSTRUMENTS
描述：	2.7V 至 6.5V 输入、3A/2A/2A 三路降压转换器 \| RHB \| 32 \| -40 to 85 转换器
文件：	总41页 (文件大小：2743K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65266-1RHBR [TI]

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