TPS65283RGET [TI]
采用 FCCM 的 4.5V 至 18V 输入、3.5A/2.5A、双路同步降压转换器 | RGE | 24 | -40 to 125;
| 型号： | TPS65283RGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 FCCM 的 4.5V 至 18V 输入、3.5A/2.5A、双路同步降压转换器 | RGE | 24 | -40 to 125 开关 输出元件 转换器 |
| 文件： | 总43页 (文件大小：3142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65283, TPS65283-1
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
具有配电开关的 TPS65283/TPS65283-1 4.5V 至 18V 输入电压、最大电流
为 3.5A 和 2.5-A 的同步双路降压转换器
1 特性
2 应用
1
•
降压转换器
•
•
•
•
•
•
USB 端口和集线器
机顶盒
–
–
4.5V 至 18V 宽输入电压范围
数字电视
集成双路降压转换器，最大持续电流为 3.5A
(Buck1)/2.5A (Buck2)
DSL/电缆调制解调器，无线路由器
家庭网关和接入点网络
汽车信息娱乐系统
–
–
反馈基准电压为 0.6V ±1%
可调节开关频率范围：200kHz 至
2MHz
3 说明
–
–
–
–
–
内置软启动时间 2.4ms
外部时钟同步
TPS65283/-1 采用耐热增强型 4mm × 4mm VQFN 封
装，是一款功能全面的
逐周期电流限制
适用于每种降压模式的电源正常状态指示器
4.5V 至 18V 输入电压 Vin、3.5A/2.5A 输出电流同步
降压直流到直流 (DC-DC) 转换器，通过高效率和集成
的高侧和低侧金属氧化物半导体场效应晶体管
(MOSFET) 对小型设计进行了优化。该器件还整合了
一个适用于配电系统的 N 通道 MOSFET 电源开关。
此器件提供一个总体配电解决方案，适用于需要精密限
流和快速保护响应的情况。
在轻负载条件下以持续电流模式 (TPS65283) 或
脉冲跳跃模式 (PSM) (TPS65283-1) 运行
•
配电开关
–
–
–
–
–
–
–
–
集成导通电阻为 60mΩ 的配电开关
工作输入电压范围为 2.4V 至 6V
可调电流限制高达 2.7A
在 1.25A（典型值）时电流限制精度为 ±10%
自动恢复过流保护
器件信息(1)
器件型号
TPS65283
TPS65283-1
封装
封装尺寸（标称值）
反向输入至输出电压保护
VQFN (24)
4.00mm x 4.00mm
过热保护
24 引脚 VQFN (RGE) 4mm × 4mm 封装
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
效率，Vin = 12V，PSM
4 典型电路原理图
100%
90%
80%
70%
60%
50%
40%
30%
TPS65283
TPS65283-1
17
14
13
FB1
FB2
18
COMP1
COMP2
BST2
19
12
11
10
9
BST1
20
LX1
LX2
Vout1
Vout2
21
PGND2
PGND1
22
VIN
VIN1
VIN2
VIN
20%
23
8
V7V
SW_IN
Buck2 at 5 V
Buck1 at 1.2 V
DVCC
PGOOD1
10%
24
1
7
Vswout
PGOOD1
SW_OUT
0%
0.002
PGOOD2
EN1
0.02
0.2
2
6
5
PGOOD2
2
3
nFAULT
SW_EN
Loading (A)
nFAULT
C001
EN2
Copyright © 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCL3
TPS65283, TPS65283-1
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 21
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ................................................ 22
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 33
13 器件和文档支持 ..................................................... 34
13.1 文档支持 ............................................................... 34
13.2 商标....................................................................... 34
13.3 静电放电警告......................................................... 34
13.4 Glossary................................................................ 34
14 机械、封装和可订购信息....................................... 34
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
典型电路原理图........................................................ 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
8.1 Absolute Maximum Ratings ...................................... 5
8.2 Handling Ratings ...................................................... 5
8.3 Recommended Operating Conditions....................... 5
8.4 Thermal Information.................................................. 5
8.5 Electrical Characteristics........................................... 6
8.6 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9
5 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (August 2017) to Revision E
Page
•
Added ROSC resistor in Figure 26 ........................................................................................................................................ 17
Changes from Revision C (August 2014) to Revision D
Page
•
•
•
•
•
已更改 将“特性”项目符号中的“...100mA 至 2.7A”更改为“....高达 2.7A” .................................................................................. 1
已删除 在“说明”的第 2 段的第 1 个句子中删除了文本“介于典型值 100mA 和 约 2.7A 之间” ................................................. 3
Changed "232 kΩ" to "80.6 kΩ" in the Description for RSET in the Pin Functions table. ..................................................... 4
Added IOS spec condition for RSET = 80.6 kΩ ........................................................................................................................ 7
Changed from "RSET is 9.1 kΩ ≤ RLIM ≤ 232 kΩ" to "RSET is 9.1 kΩ ≤ RLIM ≤ 80.6 kΩ" in the Programming the
Current-Limit Threshold section. .......................................................................................................................................... 15
•
Changed from "...adjustable 75 mA to 2.7 A" to "up to 2.7 mA..." in the Comments section of Table 2 (4 places). .......... 22
Changes from Revision B (July 2014) to Revision C
Page
•
•
Updated V7V and VSYNC_LO minimum in Electrical Characteristics.......................................................................................... 6
Updated transition voltage to lower than 0.4 V for clock signal amplitude........................................................................... 17
Changes from Revision A (June 2014) to Revision B
Page
•
将器件状态更改为生产数据..................................................................................................................................................... 1
Changes from Original (June 2014) to Revision A
Page
•
Changed Equation 3 From: ƒosc (kHz) = 41008 × R (kΩ)–0.979 To: ƒosc (kHz) = 47863 × R (kΩ)–0.988 .................................. 16
2
版权 © 2014–2019, Texas Instruments Incorporated
TPS65283, TPS65283-1
www.ti.com.cn
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
6 说明 （续）
60mΩ 独立配电开关通过使用一个外部电阻器将输出电流限制在可编程电流限制阈值。在电流典型值为 1.25A 时，
可获得达到 ±10% 的电流限制精度。nFAULT 输出在过流和反向电压条件下被置为低电平。
DC-DC 转换器中的恒定频率峰值电流模式控制简化了补偿，并且优化了瞬态响应。周期性过流保护和运行在断续
模式限制了 MOSFET 在降压输出短路或过载条件下的功率耗散。当芯片温度超过过热负载阈值时，过热保护会将
器件关断。
空白
7 Pin Configuration and Functions
24 Leads
Plastic VQFN (RGE)
(Top View)
18 17 16 15 14 13
19
20
21
22
23
24
12
BST1
LX1
BST2
LX2
11
10
9
PGND1
PGND2
Thermal Pad
VIN1
VIN2
V7V
SW_IN
SW_OUT
8
7
PGOOD1
1
2
3
4
5
6
(There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.)
Pin Functions
PIN
DESCRIPTION
NAME
NO.
Power good indicator pin. Asserts low if the output voltage of buck2 is out of range due to thermal shutdown,
dropout, over-voltage, EN, shutdown, or during slow start.
PGOOD2
1
Enable pin for buck 1. A high signal on this pin enables buck1. For a delayed start-up, add a small ceramic
capacitor from this pin to ground.
EN1
EN2
2
Enable pin for buck 2. A high signal on this pin enables buck2. For a delayed start-up, add a small ceramic
capacitor from this pin to ground.
3
Automatically select clock frequency program mode and clock synchronization mode. Program the switching
ROSC/SYNC
4
frequency of the device from 200 kHz to 2 MHz with an external resistor connecting to the pin. In clock
synchronization mode, the device automatically synchronizes to an external clock applied to the pin.
SW_EN
nFAULT
5
6
Enable power switch. Float to enable.
Active low open-drain output. Asserted during overcurrent or reverse-voltage condition of power switch.
Copyright © 2014–2019, Texas Instruments Incorporated
3
TPS65283, TPS65283-1
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
www.ti.com.cn
Pin Functions (continued)
PIN
DESCRIPTION
NAME
SW_OUT
SW_IN
NO.
7
Power switch output
Power switch input
8
Input power supply for buck2. Connect this pin as close as possible to the (+) terminal of input ceramic capacitor
(10 µF suggested).
VIN2
9
PGND2
LX2
10
11
Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck2.
Switching node connection to the inductor and bootstrap capacitor for buck2 converter. This pin voltage swings
from a diode voltage below the ground up to input voltage of buck2.
Bootstrapped supply to the high-side floating gate driver in buck converter. Connect a capacitor (47 nF
recommended) from this pin to LX2.
BST2
COMP2
FB2
12
13
14
15
16
17
18
19
Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to
compensate the control loop of buck2 with peak current PWM mode.
Feedback sensing pin for buck2 output voltage. Connect this pin to the resistor divider of buck2 output. The
feedback reference voltage is 0.6 V ±1%.
Power switch current limit control pin. An external resistor used to set current limit threshold of power switch.
Recommended 9.1 kΩ ≤ RSET ≤ 80.6 kΩ.
RSET
AGND
FB1
Analog ground common to buck controller and power switch controller. AGND must be routed separately from
high current power grounds to the (–) terminal of bypass capacitor of internal V7V LDO output.
Feedback sensing pin for buck1 output voltage. Connect this pin to the resistor divider of buck1 output. The
feedback reference voltage is 0.6 V ±1%.
Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to
compensate the control loop of buck1 converter with peak current PWM mode.
COMP1
BST1
Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend 47
nF) from this pin to LX1.
Switching node connection to the inductor and bootstrap capacitor for buck1. This pin voltage swings from a
diode voltage below the ground up to input voltage of buck1.
LX1
20
21
22
PGND1
VIN1
Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck1.
Input power supply for buck1 and internal analog bias circuitries. Connect this pin as close as possible to the (+)
terminal of an input ceramic capacitor (10 µF suggested).
Internal linear regulator (LDO) output with input from VIN1. The internal driver and control circuits are powered
from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage
level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In
PCB design, the power ground and analog ground should have one-point common connection at the (–) terminal
of V7V bypass capacitor.
V7V
23
Power good indicator pin. Asserts low if the output voltage of buck1 is out of range due to thermal shutdown,
dropout, over-voltage, EN shutdown or during slow start.
PGOOD1
24
—
Exposed pad beneath the IC. Connect to the power ground. Always solder power pad to the board, and have as
many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to
paddle inside the IC package.
PowerPAD™
4
Copyright © 2014–2019, Texas Instruments Incorporated
TPS65283, TPS65283-1
www.ti.com.cn
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
8 Specifications
8.1 Absolute Maximum Ratings
(Operating in a typical application circuit) over operating free-air temperature range and all voltages are with respect to AGND
(1)
(unless otherwise noted)
MIN
–0.3
–1
MAX UNIT
VIN1, LX1, VIN2, LX2
20
20
7
V
V
LX1, LX2 (Maximum withstand voltage transient <20 ns)
BST1, BST2 referenced to LX1, LX2 pin respectively
EN1, EN2, SW_EN, PGOOD1, PGOOD2, nFAULT, V7V, SW_IN, SW_OUT, ROSC
COMP1, COMP2, RSET, FB1, FB2
–0.3
–0.3
–0.3
–0.3
–40
V
Voltage
7
V
3.6
0.3
125
V
AGND, PGND1, PGND2
V
TJ
Operating junction temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 Handling Ratings
MIN
–55
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
–2000
–500
2000
500
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
–40
0.6
0
NOM
MAX
18
UNIT
VIN
TJ
Supply input voltage
Operating junction temperature
Output voltage
V
°C
V
125
9
VO
IO1
IO2
DC output current
3.5
2.5
A
DC output current
0
A
8.4 Thermal Information
TPS65283, TPS65283-1
THERMAL METRIC(1)
UNIT
RGE (24 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.9
41.8
14.5
0.7
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
14.4
4.1
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014–2019, Texas Instruments Incorporated
5
TPS65283, TPS65283-1
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
www.ti.com.cn
8.5 Electrical Characteristics
TJ = 25°C, VIN1 = VIN2 = 12 V, ƒSW = 500 kHz, RPG1 = RPG2 = RnFAULTx = 100 kΩ, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
4.5
18
10
V
IDDSDN
Shutdown supply current
VSW_EN = VEN1 = VEN2 = 0
5.5
0.5
µA
EN1 = EN2 = high, VFB1 = VFB2 = 1 V,
With buck1 and buck2 not switching
IDDQ_NSW
UVLO
None switching quiescent current
mA
VIN1 rising
4
4.25
3.75
500
6.3
4.5
4
V
V
Input voltage undervoltage lockout (UVLO)
VIN1 falling
3.5
Hysteresis
mV
V
V7V
Internal biasing supply
VV7V load current = 0 A, VIN1 = 12 V
6.05
6.49
IOCP_V7V
OSCILLATOR
ƒSW
Current limit of V7V LDO
180
mA
Switching frequency
ROSC = 100 kΩ
400
80
500
600
2
kHz
ns
V
TSYNC_w
VSYNC_HI
VSYNC_LO
VSYNC_D
FSYNC
Clock sync minimum pulse width
Clock sync high threshold
Clock sync low threshold
0.4
V
Clock falling edge to LX rising edge delay
Clock sync frequency range
120
ns
kHz
200
2000
BUCK1/BUCK2 CONVERTER
VCOMP1 = VCOMP2 = 1.2 V, TJ = 25°C
VCOMP1 = VCOMP2 = 1.2 V, TJ = –40°C to 125°C
–2 µA < ICOMPX < 2 µA
0.594
0.588
0.6
0.6
0.606
0.612
V
V
VFB
Feedback voltage
Gm_EA
Error amplifier transconductance
300
µS
COMP1/COMP2 voltage to inductor current
Gm(1)
Gm_SRC
ILX1 = ILX2 = 0.5 A
7.4
A/V
VENXH
VENXL
IENX
EN1, EN2 high level input voltage
EN1, EN2 low-level input voltage
EN1, EN2 pullup current
1.2
1.15
3.6
6.6
3
1.26
V
1.1
V
VEN1 = VEN2 = 1 V
µA
µA
µA
IENX
EN1, EN2 pullup current
VEN1 = VEN2 = 1.5 V
IENhys
IEN1 / IEN2 hysteresis current
TJ = 25°C
80
100
120
TON_MIN
Minimum on time
ns
TJ = –40°C to 125°C
TSS_INT
Internal soft-start time
2.4
5
ms
A
ILIMIT1
Buck1 peak inductor current limit
Buck1 low-side sink current limit
Buck2 peak inductor current limit
Buck2 low side sink current limit
High-side FET on-resistance in Buck1
Low-side FET on-resistance in buck1
High-side FET on-resistance in Buck2
Low-side FET on-resistance in buck2
Hiccup wait time
4.25
3.2
5.75
4.3
ILIMITS1
1.7
3.75
1.3
100
65
A
ILIMIT2
A
ILIMITS2
A
Rdson1_HS
Rdson1_LS
Rdson2_HS
Rdson2_LS
THICCUP_WAIT
THICCUP_RE
POWER GOOD
V7V = 6.25 V
V7V = 6.25 V
V7V = 6.25 V
V7V = 6.25 V
mΩ
mΩ
mΩ
mΩ
ms
ms
140
95
4
Hiccup time before restart
64
VFB1 / VFB2 UV falling
VFB1 / VFB2 UV rising
VFB1 / VFB2 OV rising
VFB1 / VFB2 OV falling
92.5%
95%
107.5%
105%
1
Vth_PG
Feedback voltage threshold
TDEGLITCH(PGF)
TDEGLITCH(PGR)
IPG
PG1/PG2 deglitch time (falling edge)
PG1/PG2 deglitch time (rising edge)
Power Good pin leakage
ms
ms
µA
V
2
VFB1 = VFB2 = 0.6 V
1
VLOW_PG
PG1/PG2 pin low voltage
Force FB1 = FB2 = 0.5 V, sink 1 mA to PG1/PG2 pin
0.4
(1) Specified by design.
6
Copyright © 2014–2019, Texas Instruments Incorporated
TPS65283, TPS65283-1
www.ti.com.cn
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
Electrical Characteristics (continued)
TJ = 25°C, VIN1 = VIN2 = 12 V, ƒSW = 500 kHz, RPG1 = RPG2 = RnFAULTx = 100 kΩ, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER DISTRIBUTION SWITCH
VSWIN
Power switch input voltage range
Supply current, device enabled
2.4
6
V
µA
V
IDDQH
No load on SW_OUT, RSET = 20 kΩ
VSWIN rising
140
2.25
2.15
100
2.15
2.05
2.35
2.25
VUVLO_SW
Power switch input undervoltage lockout
Power switch NMOS on-resistance
VSWIN falling
V
Hysteresis
mV
RGE package, VSWIN = 5 V, IOUT = 0.5 A,
TJ = 25°C, including bond wire resistance
60
60
mΩ
mΩ
RDSON_SW
RGE package, VSWIN = 2.5 V, IOUT = 0.5 A,
TJ = 25°C, including bond wire resistance
tD_on
tD_off
tr
Turn-on delay time
Turn-off delay time
Output rise time
Output fall time
VSWIN = 5 V, CL= 10 µF, RL= 100 Ω
1.1
1.2
ms
ms
ms
ms
(See Figure 1)
0.65
1.54
1.75
1.25
0.5
tf
RSET = 14.3 kΩ
1.575
1.125
0.4
1.925
1.375
0.6
Current limit threshold (maximum DC current
delivered to load) and short circuit current,
OUT connect to ground
RSET = 20 kΩ
IOS
A
RSET = 50 kΩ
RSET = 80.6 kΩ, TJ = 0°C to 90°C
0.15
0.325
0.5
Fault assertion or deassertion due to overcurrent
condition
TDEGLITCH(OCP)
Switch overcurrent fault deglitch
6
2
8
10
ms
VL_nFAULT
VENSWH
VENSWL
RDIS
nFAULT pin output low voltage
SW_EN high-level input voltage
SW_EN low-level input voltage
Discharge resistance(2)
InFAULT = 1 mA
150
300
mV
V
0.4
V
VSW_IN = 5 V, VSW_EN = 0 V
100
Ω
THERMAL SHUTDOWN
TTRIP_BUCK
Temperature rising
Hysteresis
160
20
Thermal protection trip point
°C
°C
THYST_BUCK
TTRIP_SW
Temperature rise
Hysteresis
145
20
Power switch thermal protection trip point
Power switch in overcurrent condition
THYST_SW
(2) The discharge function is active when the device is disabled (when enable is deasserted). The discharge function offers a resistive
discharge path for the external storage capacitor.
50%
50%
VENx
tD_on
tD_off
tf
tr
90%
90%
10%
10%
VOUTx
Figure 1. Power Switches Test Circuit and Voltage Waveforms
Copyright © 2014–2019, Texas Instruments Incorporated
7
TPS65283, TPS65283-1
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IOUT
120% x IOS
IOS
0A
tIOS
Figure 2. Response Time to Short Circuit Waveform
VIN
Decreasing
Load
Resistance
Slope = -rDS(on)
0 V
IOUT
0 A
IOS
Figure 3. Output Voltage vs Current Limit Threshold
8
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ZHCSCO8E –JUNE 2014–REVISED MAY 2019
8.6 Typical Characteristics
TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
9 V
9 V
12 V
18 V
12 V
18 V
0.002
0.02
0.2
2
0.002
0.02
0.2
2
Loading (A)
Loading (A)
C002
C003
Figure 4. Buck Efficiency (PSM) at Vout1 = 1.2 V
Figure 5. Buck Efficiency (PWM) at Vout1 = 1.2 V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
9 V
9 V
12 V
18 V
12 V
18 V
0.002
0.02
0.2
2
0.002
0.02
0.2
2
Loading (A)
Loading (A)
C003
C003
Figure 6. Buck Efficiency (PSM) at Vout2 = 5 V
Figure 7. Buck Efficiency (PWM) at Vout2 = 5 V
1.3
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
Auto PSM-PWM 0A
Forced PWM 2A
Auto PSM-PWM 0A
Forced PWM 2A
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
Loading (A)
Loading (A)
C009
C008
Figure 8. Buck Line Regulation at Vout1 = 1.2 V
Figure 9. Buck Line Regulation at Vout2 = 5 V
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Typical Characteristics (continued)
TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
5.08
5.04
5.00
4.96
4.92
4.88
1.28
1.25
1.22
1.19
1.16
1.13
1.10
Auto PSM-PWM 0A
Forced PWM 2A
Auto PSM-PWM 0A
Forced PWM 2A
5.0
7.0
9.0
11.0
13.0
15.0
17.0
19.0
5.0
7.0
9.0
11.0
13.0
15.0
17.0
19.0
VIN (V)
VIN (V)
C006
C007
Figure 10. Buck Load Regulation at Vout1 = 1.2 V
Figure 11. Buck Load Regulation at Vout2 = 5 V
0.60
0.610
0.605
0.600
0.595
0.590
0.55
0.50
0.45
0.40
Buck1
Buck2
10
40
70
100
130
10
40
70
100
130
œ50
œ20
œ50
œ20
Junction Temperature (°C)
Junction Temperature (°C)
C013
C014
Figure 12. IIN (Without Switching) vs Temperature
Figure 13. Reference Voltage vs Temperature
1.22
1.17
1.16
1.15
1.14
1.13
1.21
1.20
1.19
1.18
1.17
1.16
Buck1
Buck2
Buck1
Buck2
130
10
40
70
100
130
10
40
70
100
œ50
œ20
œ50
œ20
Junction Temperature (°C)
Junction Temperature (°C)
C023
C023
Figure 14. EN UVLO Start Up vs Temperature
Figure 15. EN UVLO Shut Down vs Temperature
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Typical Characteristics (continued)
TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
5.1
5.0
4.9
4.8
4.7
3.85
3.75
3.65
3.55
3.45
10
30
50
70
90
110 130
10
30
50
70
90
110 130
œ50 œ30 œ10
œ50 œ30 œ10
Junction Temperature (°C)
Junction Temperature (°C)
C017
C017
Figure 16. Buck1 Current Limit vs Temperature
Figure 17. Buck2 Current Limit vs Temperature
90
80
70
60
50
0.150
0.145
0.140
0.135
0.130
0.125
0.120
Buck1
Buck2
10
40
70
100
130
10
40
70
100
130
œ50
œ20
œ50
œ20
Junction Temperature (°C)
Junction Temperature (°C)
C019
C020
Figure 18. Buck Minimum On Time vs Temperature
Figure 19. Supply Current (Switch Enabled) vs Temperature
1.35
120
100
80
60
40
20
0
1.30
1.25
1.20
1.15
10
40
70
100
130
0
1
2
3
4
5
6
7
8
9
œ50
œ20
Environment Temperature (°C)
Current (A)
C021
C022
Figure 20. Switch Current Limit vs Temperature
Figure 21. Response Time vs SW_OUT Current
(Rset = 20 kΩ)
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9 Detailed Description
9.1 Overview
TPS65283, TPS65283-1 PMIC integrates dual synchronous step-down converter with regulated 0.6-V ±1%
feedback reference voltage, 4.5- to 18-V Vin, 3.5-A/2.5-A output current, which is optimized for small designs
through high efficiency and integrating the high-side and low-side MOSFETs. The device also incorporates one
N-channel MOSFET power switches for power distribution systems. This device provides a total power
distribution solution, where precision current limiting and fast protection response are required.
The TPS65283, TPS65283-1 implements a constant frequency, peak current mode control that simplifies
external loop compensation. The wide switching frequency of 250 kHz to 2 MHz allows optimizing system
efficiency and filtering size. The switching frequency can be adjusted with an external resistor connecting
between ROSC pin and ground. The switch clock of buck1 is 180° out-of-phase operation from the clock of
buck2 channel to reduce input current ripple, input capacitor size, and power supply induced noise.
The TPS65283, TPS65283-1 has been designed for safe monotonic start-up into pre-biased loads. The default
start-up is when VIN is typically 4.5 V. The ENx pin has an internal pullup current source that can be used to
adjust the input voltage UVLO with two external resistors. In addition, the ENx pin can be floating for
automatically starting up the converters with the internal pullup current.
The TPS65283, TPS65283-1 reduces the external component count by integrating the bootstrap circuit. The bias
voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO
circuit monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the
threshold, LX pin to be pulled low to recharge the boot capacitor. The TPS65283, TPS65283-1 can operate at
100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-LX UVLO threshold,
which is typically 2.1 V.
The TPS65283, TPS65283-1 features PGOOD pin to supervise output voltages of buck converter. The
TPS65283, TPS65283-1 has power good comparators with hysteresis, which monitor the output voltages through
internal feedback voltages. When the buck is in regulation range and power sequence is done, PGOOD is
asserted to high.
The TPS65283, TPS65283-1 is protected from overload and thermal fault conditions. The converter minimizes
excessive output overvoltage transients by taking advantage of the power good comparator. When the
overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the
internal feedback voltage is lower than 107.5% of the 0.6-V reference voltage. The TPS65283, TPS65283-1
implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections
to avoid inductor current runaway. If the overcurrent condition has lasted for more than the hiccup wait time (4
ms), the converter shuts down and restarts after the hiccup time (64 ms). The TPS65283, TPS65283-1 shuts
down if the junction temperature is higher than the thermal shutdown trip point. When the junction temperature
drops 20°C typically below the thermal shutdown trip point, the TPS65283, TPS65283-1 is restarted under
control of the soft-start circuit automatically. In light loading condition, TPS65283-1 automatically operates in
PSM to save power.
Power distribution switches of TPS65283, TPS65283-1 use N-channel MOSFET for applications where short
circuits or heavy capacitive loads will be encountered and provide a precision current limit protection. Additional
device features include overtemperature protection and reverse-voltage protection. The device incorporates an
internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump
supplies power to the driver circuit and provide the necessary voltage to pull the gate of the MOSFET above the
source. The charge pump operates from input voltage of power switches as low as 2.4 V and requires little
supply current. The driver controls the gate voltage of power switch. The driver incorporates circuitry that controls
the rise and fall times of output voltage to limit large current and voltage surges and provides built-in soft-start
functionality. TPS65283, TPS65283-1 device limits output current to a safe level when output load exceeds the
current limit threshold. The device asserts the nFAULT signal when overs current limit or reverse voltage faulty
condition last longer than deglitching time. When the output voltage and current return normally, the device will
auto recovery and nFAULT signal will be released.
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9.2 Functional Block Diagram
23
22
LDO
V7V
VIN1
Voltage Reference
Current Bias
Preregulator
HS current
sensing
CS
BST
Switch
19
BST1
2
EN1
Enable
Comparator
Enable
Threshold
HS driver
Current
Sensing
18
COMP1
Buck
Controller
20
PWM comparator
LX1
V7V
17
slope
comp
LS driver
FB1
0.6V
2.4-ms Internal
Soft Start
Error Amplifier
CS
LS current
sensing
5V
Oscillotor
10 µA
21
4
ROSC/
SYNC
PGND1
0.645 V
24
PGOOD1
0.555 V
16
BUCK1
AGND
EN2
9
3
13
14
1
VIN2
12
BST2
COMP2
FB2
BUCK2
11
LX2
10
PGND2
PGOOD2
SW_IN
8
UVLO
POR
7
CS
SW_OUT
Current
Sensing
Charge
Pump
Disabled + UVLO
V7V
1.25 Mꢀ
1.25 Mꢀ
15
Current
Limit
RSET
Driver
6
nFAULT
8-ms
Deglitch
Time
5
SW_EN
Enable Buffer
Thermal
Sense
POWER SWITCH
Copyright © 2017, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Power Switch Detailed Description
9.3.1.1 Overcurrent Condition
The TPS65283, TPS65283-1 responds to overcurrent conditions on power switches by limiting the output
currents to IOCP_SW level, which is set by external resistor. When the load current is less than the current-limit
threshold, the devices are not limiting current. During normal operation, the N-channel MOSFET is fully
enhanced, and VSW_OUT = VSW_IN – (ISW_OUT × Rdson_SW). The voltage drop across the MOSFET is relatively small
compared to VSW_IN, and VSW_OUT ≈ VSW_IN. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly. During current-limit operation, the N-channel
MOSFET is no longer fully enhanced and the resistance of the device increases. This allows the device to
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Feature Description (continued)
effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the
MOSFET is that the voltage drop across the device is no longer negligible (VSW_IN ≠ VSW_OUT), and VSW_OUT
decreases. The amount that VSW_OUT decreases is proportional to the magnitude of the overload condition. The
expected VSW_OUT can be calculated by IOCP_SW × RLOAD, where IOCP_SW is the current-limit threshold and RLOAD
is the magnitude of the overload condition.
Table 1 shows three possible overload conditions that can occur.
Table 1. Overload Conditions
CONDITIONS
BEHAVIORS
Short circuit or partial short
circuit present when the
device is powered up or
enabled
The output voltage is held near zero potential with respect to ground and the TPS65283, TPS65283-1
ramps output current to IOCP_SW. The device limits the current to IOS until the overload condition is
removed or the internal deglitch time (8 ms typical) is reached and the device is turned off. The device auto
recovers when the overcurrent status is removed.
The current rises until current limit. After the threshold has been reached, the device switches into its
current limiting at IOCP_SW. The device limits the current to IOS until the overload condition is removed or
the internal deglitch time (8 ms typical) is reached and the device is turned off. The device auto recovers
when the overcurrent status is removed.
Gradually increasing load
(<100 A/s) from normal
operating current to IOCP_SW
Short circuit, partial short
circuit or fast transient
overload occurs while the
device is enabled and
powered on
The device responds to the overcurrent condition within time TIOS (see Figure 3).The current sensing
amplifier is overdriven during this time, and needs time for loop response. After TIOS has passed, the
current sensing amplifier recovers and limits the current to IOCP_SW. The device limits the current to IOS
until the overload condition is removed or the internal deglitch time (8 ms typical) is reached and the device
is turned off. The device auto recovers when the overcurrent status is removed.
9.3.1.2 Reverse Current and Voltage Protection
The power switch in TPS65283, TPS65283-1 incorporates one N-channel power MOSFETs for lower resistance
and the bulk of the MOSFET is connected to ground to prevent the reverse current flowing back the input
through body diode of MOSFET when power switch is off.
When power switch is enabled, the reverse-voltage protection feature turns off the N-channel MOSFET
whenever the output voltage exceeds the input voltage by 55 mV (typical) for 4-ms (typical). This prevents
damage to devices on the input side of the TPS65283, TPS65283-1 by preventing significant current from sinking
into the input capacitance of power switch or buck output capacitance. The TPS65283, TPS65283-1 device
keeps the power switch turned off even if the reverse-voltage condition is removed and does not allow the N-
channel MOSFET to turn on until power is cycled or the device enable is toggled. The reverse-voltage
comparator also asserts the nFAULT output (active-low) after 4 ms.
9.3.1.3 nFAULT Response
The nFAULT open-drain output is asserted (active low) during an overcurrent, overtemperature, or reverse-
voltage condition. The TPS65283, TPS65283-1 asserts the nFAULT signal during a fault condition and remains
asserted while the part is latched-off. The nFAULT signal is deasserted when device power is cycled or the
enable is toggled, and the device resumes normal operation. The TPS65283, TPS65283-1 is designed to
eliminate false nFAULT reporting by using an internal delay "deglitch" circuit for over-current (8 ms typical) and
reverse-voltage (4 ms typical) conditions without the need for external circuitry. This ensures that nFAULT is not
accidentally asserted due to normal operation such as starting into a heavy capacitive load. Deglitching circuitry
delays entering and leaving fault conditions. Overtemperature conditions are not deglitched and assert the
FAULT signal immediately.
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USB_VIN
0
USB_EN
USB_OUT
USB_I
Over current is detected
Normal operation
Over current is cleared
Ios
Over current at the output
Alarm is asserted after 8 ms
Alarm is cleared
Normal operation is restored
nFAULT
tdeglitch
tdeglitch
Figure 22. USB Switches Over Current
9.3.1.4 UVLO
The UVLO circuit disables the power switch until the input voltage reaches the UVLO turn-on threshold. Built-in
hysteresis prevents unwanted on/off cycling due to input voltage drop from large current surges.
9.3.1.5 Enable and Output Discharge
The logic enable EN_SW controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current from power switch driver is reduced to less than 1 µA when a logic low is present on EN_SW. A
logic high input on EN_SW enables the driver, control circuits, and power switch. The enable input is compatible
with both TTL and CMOS logic levels.
When enable is deasserted, the discharge function is active. The output capacitor of power switch is discharged
through an internal NMOS that has a discharge resistance of 100 Ω. Hence, the output voltage drops down to 0.
The time taken for discharge depends on the RC time constant of the resistance and the output capacitor.
9.3.1.6 Power Switch Input and Output Capacitance
Input and output capacitance improves the performance of the device. The actual capacitance should be
optimized for the particular application. TI recommends to place the output capacitor in buck converter between
SW_IN and AGND as close to the device as possible for local noise decoupling. Additional capacitance may be
needed on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device
during heavy transient conditions. This is especially important during bench testing when long, inductive cables
are used to connect the input of power switches in the evaluation board to the bench power-supply. TI
recommends placing a high-value electrolytic capacitor on the output pin when large transient currents are
expected on the output.
9.3.1.7 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable through an external resistor. The TPS65283, TPS65283-1 uses
an internal regulation loop to provide a regulated voltage on the RLIM pin. The current-limit threshold is
proportional to the current sourced out of RSET. The recommended 1% resistor range for RSET is 9.1 kΩ ≤
RLIM ≤ 80.6 kΩ to adjust the current limit of the switch. Many applications require that the minimum current limit
is above a certain current level or that the maximum current limit is below a certain current level, so it is
important to consider the tolerance of the overcurrent threshold when selecting a value for RLIM. The following
equations and Figure 23 can be used to calculate the resulting overcurrent threshold for a given external resistor
value (RSET).
Current-Limit Threshold Equations (IOS):
ILIMIT = 37.793(RSET)–1.149
(1)
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3.5
3
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
REST (kW)
D010
Figure 23. Current-Limit Threshold vs RLIM
9.3.2 Buck DC-DC Converter Detailed Description
9.3.2.1 Output Voltage
The TPS65283, TPS65283-1 regulate output voltage set by a feedback resistor divider to 0.6-V reference
voltage. This pin should be directly connected to middle of resistor divider. TI recommends to use 1% tolerance
or better divider resistors. Take care to route the FB line away from noise sources, such as the inductor or the LX
switching node line. Start with 39 kΩ for the R1 resistor and use Equation 2 to calculate R2 and ensure the R2 ≤
10 kΩ.
æ
ç
è
ö
÷
ø
0.6V
R = R ´
2
1
VOUT - 0.6V
(2)
Vout = 5 V
C1
R1
82 pF
39 kΩ
23
–
+
FB
EA
R2
5.3 kΩ
0.6 V
Reference
24
COMP
Figure 24. Buck Internal Feedback Resistor Divider
9.3.2.2 Adjustable Switching Frequency
The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching
frequency of the device is adjustable from 200 kHz to 2 MHz.
To determine the ROSC resistance for a given switching frequency, use Equation 3 or the curve in Figure 25. To
reduce the solution size, set the switching frequency as high as possible, but consider tradeoffs of the supply
efficiency and minimum controllable on-time.
ƒosc (kHz) = 47863 × R (kΩ)–0.988
(3)
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3000
2500
2000
1500
1000
500
0
0
50
100
150
200
250
R (kΩ)
C011
Figure 25. ROSC vs Switching Frequency
9.3.2.3 Synchronization
The user can implement an internal phase locked loop (PLL) to allow synchronization between 200 kHz to 2
MHz, and to easily switch from resistor mode to synchronization mode. To implement the synchronization
feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% and 80%. The
clock signal amplitude must transition lower than 0.4 V and higher than 2 V. The start of the switching cycle is
synchronized to the falling edge of ROSC pin.
In applications where both resistor mode and synchronization mode are needed, configure the device as shown
in Figure 26. Before the external clock is present, the device works in resistor mode and the switching frequency
is set by ROSC resistor. When the external clock is present, the synchronization mode overrides the resistor
mode.
TPS65283
Mode
TPS65283-1
Selection
ROSC/SYNC
ROSC
Figure 26. Works With Resistor Mode and Synchronization Mode
9.3.2.4 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the FB pin voltage to the lower
of the SS pin voltage or the internal 0.6-V voltage reference. The transconductance of the error amplifier is 300
µA/V during normal operation. The frequency compensation network is connected between the COMP pin and
ground.
9.3.2.5 Slope Compensation
To prevent subharmonic oscillations when the device operates at duty cycles greater than 50%, the device adds
built-in slope compensation, which is a compensating ramp to the switch current signal.
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9.3.2.6 Enable and Adjusting UVLO
The ENx pin provides electrical on and off control of the device. When the ENx pin voltage exceeds the threshold
voltage, the device starts operation. If the ENx pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state. The ENx pin has an internal pullup current source, allowing the user to
float the ENx pin for enabling the device. If an application requires controlling the ENx pin, use open-drain or
open-collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN
pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal
VIN UVLO threshold has a hysteresis of 500 mV. If an application requires either a higher UVLO threshold on the
VIN pin, or a secondary UVLO on the PVIN, in split rail applications, then the user can configure the ENx pin as
shown in Figure 27. When using the external UVLO function, TI recommends to set the hysteresis to be greater
than 500 mV.
The ENx pin has a small pullup current Ip which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ih once the ENx pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 4 and Equation 5.
VIN
R1
EN
R2
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Adjustable VIN Undervoltage Lockout
æ
ö
÷
ø
VENFALLING
V
- V
STOP
START ç
VENRISING
è
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+ I
h
P ç
VENRISING
è
(4)
(5)
spacer
R1 ´ VENFALLING
R2 =
VSTOP - VENFALLING + R I + I
1 (h )
p
where
•
•
•
•
Ih = 3 µA
Ip = 3.6 µA
VENRISING = 1.2 V
VENFALLING = 1.15 V
9.3.2.7 Internal V7V Regulator
The TPS65283, TPS65283-1 features an internal P-channel low dropout linear regulator (LDO) that supply power
at the V7V pin from VIN supply. V7V powers the gate drivers and much of the TPS65283's, TPS65283-1’s
internal circuitry. The LDO regulates V7V to 6.3 V of overdrive voltage on power MOSFET for the best efficiency
performance. The LDO can supply a peak current of 50 mA and must be bypassed to ground with a minimum of
1-µF ceramic capacitor. TI highly recommends that the capacitor placed directly adjacent to the V7V and PGND
pins supply the high transient currents required by the MOSFET gate drivers.
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9.3.2.8 Short Circuit Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
9.3.2.8.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control, which uses the COMP pin voltage to control the turn off of the
high-side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch
current and the current reference generated by the COMP pin voltage are compared, when the peak switch
current intersects the current reference the high-side switch is turned off.
9.3.2.8.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally-set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time, which is programmed for 4 ms, the device shuts down and restarts after the hiccup time of
64 ms. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions
Vout
Current limit threshold
I
L
4 ms
V
LX
64 ms
Figure 28. DC-DC Overcurrent Protection
9.3.2.9 Bootstrap Voltage (BST) and Low Dropout Operation
The device has an integrated boot regulator and requires a small ceramic capacitor between the BST and LX
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BST
pin voltage is less than VIN and BST-LX voltage is below regulation. The value of this ceramic capacitor should
be 47 nF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V
or higher because of the stable characteristics over temperature and voltage. To improve dropout, the device is
designed to operate at 100% duty cycle as long as the BST to LX pin voltage is greater than the BST-LX UVLO
threshold, which is typically 2.1 V. When the voltage between BST and LX drops below the BST-LX UVLO
threshold, the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor
to be recharged.
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9.3.2.10 Output Overvoltage Protection (OVP)
The device incorporates an output OVP circuit to minimize output voltage overshoot. For example, when the
power supply output is overloaded, the error amplifier compares the actual output voltage to the internal
reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the
output of the error amplifier demands maximum output current. After the condition is removed, the regulator
output rises and the error amplifier output transitions to the steady state voltage. In some applications with small
output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the
possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the FB pin voltage to
the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off,
preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower
than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.
9.3.2.11 Power Good
The PGOOD pin is an open-drain output. The PGOOD pin is pulled low when buck converter is pulled below
92.5% or over 107.5% of the nominal output voltage. The PGOOD is pulled up when the buck converters’
outputs are more than 95% and lower than 105% of its nominal output voltage. The default reset time is 2 ms.
The polarity of the PGOOD is active high.
9.3.2.12 Power-Up Sequencing
The TPS65283, TPS65283-1 has a dedicated enable pin for each converter. The converter enable pins are
biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the
converter with an active pulldown transistor on the ENx pin allows for predictable power-down timing operation.
Figure 29 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx pin.
A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the
internal V7V LDO turns on. A 3.6-µA pullup current is sourcing ENx. After ENx pin voltage reaches to ENx
enabling threshold, 3-µA hysteresis current sources to the pin to improve noise sensitivity. The internal soft-start
comparator compares internal SS voltage to 0.6 V, When internal SS voltage ramps up to 0.6 V, PGOODx
monitor is enabled. After PGOODx deglitch time, and if output voltages are in the regulation, PGOODx is
asserted.
VIN
V7V
EN Threshold
Enx Rise Time
Dictated by CEN
Charge CEN
EN Threshold
with 6.6 µA
ENx
Soft Start Rise Time
Dictated by CSS
Pre-Bias Startup
PGOOD Deglitch Time
BUCKx
T = CSS × 0.6 V / 5 µA
T = CENX × (1.2 – 0.4) V / 3.6 µA
T = CENX × 0.4 V / 1.4 uA
PGOODx
Figure 29. Start-Up Power Sequence
20
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9.3.2.13 Thermal Performance
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the buck converter to stop switching when the junction temperature exceeds
thermal trip threshold. After the die temperature decreases below 140°C, the device reinitiates the power-up
sequence. The thermal shutdown hysteresis is 20°C. When USB is over-current, the internal thermal shut down
of power switch will be changed to 145°C to avoid influencing the normal operation of buck converters.
9.4 Device Functional Modes
9.4.1 Operation With VIN < 4.5 V (Minimum VIN)
The devices operate with input voltages above 4.5 V. The maximum UVLO voltage is 4.5 V and operates at input
voltages above 4.5 V. The typical UVLO voltage is 4 V, and the devices may operate at input voltages above that
point. The devices also may operate at lower input voltage; the minimum UVLO voltage is not specified. At input
voltages below the actual UVLO voltage, the devices do not operate.
9.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.2 V typical and 1.26 V maximum. With EN held below that voltage
the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When input
voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the
device becomes active. Switching is enabled, and the slow start sequence is initiated. The TPS65283,
TPS65283-1 output voltage ramps up at the internal slow-start time of 2.4 ms.
9.4.3 Operation at Light Loads
The devices are designed to operate in high-efficiency PSM under light load conditions. Pulse skipping is initiated
when the switch current falls to 0 A. During pulse skipping, the low-side FET is turned off when the switch current
falls to 0 A. The switching node (LX) waveform takes on the characteristics of DCM operation and the apparent
switching frequency decreases.
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10 Application and Implementation
10.1 Application Information
The devices are step-down DC-DC converters. They are typically used to convert a higher dc voltage to a lower
dc voltage with a maximum available output current of 3.5/2.5 A. The following design procedure can be used to
select component values for the TPS65283 and TPS65283-1. Alternately, the WEBENCH® software may be
used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses
a comprehensive database of components when generating a design. This section presents a simplified
discussion of the design process.
10.2 Typical Application
The application schematic in Figure 30 was developed to meet the previous requirements. This circuit is
available as the TPS65283, TPS65283-1 evaluation module (EVM). The sections provides the design procedure.
R14
5.49K
R12
40.2K
R19
10K
R18
10K
R15
20K
R17
20K
R13
20K
C19
47pF
C12
82pF
C13
3.3nF
C17
3.3nF
C20
22uF*2
C11
22uF*2
19
20
21
22
23
24
12
11
10
9
C19
47nF
L1
4.7uH
L2
4.7uH
BST1
BST2
C12
47nF
Vout1
1.2V/3.5A
Vout2
5V/2.5A
LX1
LX2
PGND2
VIN2
PGND1
VIN1
C10
10uF
C22
10uF
TPS65283
VIN
5.5V~18V
VIN
5.5V~18V
V7V
8
V7V
SW_IN
SW_OUT
C23
1uF
R24
100k
USB
Port
7
PGOOD1
DVCC
USB Data
C7
10uF
PGOOD1
PGOOD2
R1
100k
R2
100K
R6
100K
USB fault signal
Analog Ground
Power Ground
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Typical Application Schematic
Table 2. Related Parts
PART
NUMBER
DESCRIPTION
COMMENTS
Fixed 5V Vout, 0.3 ≤ Fsw ≤ 1.4 MHz,
Power switch: 2.5 V ≤ Vsw_in ≤ 6 V, fixed 1.2-A current limit
4.5 to 18 V Vin, 4 A, synchronous buck converter with
dual power switch
TPS65280
0.3 ≤ Fsw ≤ 1.4 MHz,
Power switch: 2.5 V ≤ Vsw_in ≤ 6 V, adjustable up to 2.7 A
current limit
TPS65281,
TPS65281-1
4.5 to 18 V Vin, 3 A, synchronous buck converter with a
power switch
0.3 ≤ Fsw ≤ 1.4 MHz, PSM at light load,
Power switch: 2.5 V ≤ Vsw_in ≤ 6 V, adjustable up to 2.7 A
current limit
4.5 to 18 V Vin, 4 A, synchronous buck converter with
dual power switches
TPS65282
TPS65286
0.3 ≤ Fsw ≤ 2.2 MHz, PSM at light load,
Power switch: 2.5 V ≤ Vsw_in ≤ 6 V, adjustable up to 2.7 A
current limit
4.5 to 28 V Vin, 6 A, synchronous buck converter with
dual power switches
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Typical Application (continued)
Table 2. Related Parts (continued)
PART
NUMBER
DESCRIPTION
COMMENTS
0.3 ≤ Fsw ≤ 2.2 MHz, PSM at light load,
Power switch: 2.5 V ≤ Vsw_in ≤ 6 V, adjustable up to 2.7 A
current limit
4.5 to 18 V Vin, 3 A / 2 A / 2 A, triple synchronous buck
converter with a power switch and pushbutton control
TPS65287
0.3 ≤ Fsw ≤ 2.2 MHz, PSM at light load,
Power switch: 2.5 V ≤ Vsw_in ≤ 6 V, Fixed 1.2 A current limit
4.5 to 18 V Vin, 3 A / 2 A / 2 A, triple synchronous buck
converter with dual power switch
TPS65288
10.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 3. Input Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 18 V
1.2 / 5 V
Output voltage
Transient response, 1.5-A load step
Input ripple voltage
ΔVout = ±5%
400 mV
Output ripple voltage
30 mV
Output current rating
3.5 / 2.5 A
500 kHz
Operating frequency
10.2.2 Detailed Design Procedure
10.2.2.1 Output Voltage Setting
To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator
is more sensitive to noise. Table 4 shows the recommended resistor values. Ensure the R2 ≤ 10 kΩ.
Table 4. Output Resistor Divider Selection
OUTPUT VOLTAGE
(V)
R1
(kΩ)
R2
(kΩ)
1
6.8
10
10
10
1.2
1.5
1.8
2.5
3.3
3.3
5
15
10
20
10
31.6
45.3
22.6
73.2
36.5
10
10
4.99
10
5
4.99
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10.2.2.2 Bootstrap Capacitor Selection
A 47-nF ceramic capacitor must be connected between the BST to LX pin for proper operation. TI recommends
to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage
rating.
10.2.2.3 Inductor Selection
The higher operating frequency allows the use of smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off,
consider the effect of inductor value on ripple current and low current operation. The ripple current depends on
the inductor value. The inductor ripple current iL decreases with higher inductance or higher frequency and
increases with higher input voltage VIN. Accepting larger values of iL allows the use of low inductances, but
results in higher output voltage ripple and greater core losses.
To calculate the value of the output inductor, use Equation 6. LIR is a coefficient that represents inductor peak-
to-peak ripple to dc load current. LIR is suggested to choose to 0.1 to about 0.3 for most applications.
Actual core loss of inductor is independent of core size for a fixed inductor value, but it is very dependent on
inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses increase. Ferrite designs have very-low core loss and
are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing
saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak
design current is exceeded. It results in an abrupt increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate. It is important that the RMS current and saturation current
ratings are not exceeding the inductor specification. Calculate the RMS and peak inductor current from
Equation 8 and Equation 9.
V - Vout
Vout
in
L =
´
IO ´LIR
V ´ ƒsw
in
(6)
spacer
DiL =
V - Vout
Vout
in
´
L
V ´ ƒsw
in
(7)
spacer
æ
ö2
Vout ´ V
- Vout
(
)
inmax
ç
ç
÷
÷
Vinmax ´L ´ ƒsw
è
ø
iLrms
=
IO2 +
12
(8)
(9)
spacer
ILpeak = IO +
DiL
2
For this design example, use LIR = 0.3, and inductor is calculated to be 2.1 µH with Vin = 12 V, Vout = 1.2 V,
Iout = 3.5 A. Choose 4.7-µH value of standard inductor, the peak-to-peak inductor ripple is about 13.1% of 3.5-A
dc load current.
10.2.2.4 Output Capacitor Selection
There are two primary considerations for selecting the value of the output capacitor. The output capacitors are
selected to meet load transient and output ripple’s requirements. Equation 10 gives the minimum output
capacitance to meet the transient specification. For this example, Lo = 4.7 µH, ΔIout = 2 A – 0.0 A = 2 A, and
ΔVout = 250 mV (5% of regulated 5 V) for Buck2. Using these numbers gives a minimum capacitance of 15 µF.
This design uses a standard 2 × 22-µF ceramic.
DIOUT2 ´L
Co >
Vout ´ DVout
(10)
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The selection of COUT is driven by the effective series resistance (ESR). Equation 11 calculates the minimum
output capacitance needed to meet the output voltage ripple specification. Where ƒsw is the switching frequency,
ΔVout is the maximum allowable output voltage ripple, and ΔiL is the inductor ripple current. In this case, the
maximum output voltage ripple is 25 mV (0.5% of regulated 5 V). From Equation 9, the output current ripple is
1.24 A. From Equation 11, the minimum output capacitance meeting the output voltage ripple requirement is
14.5 µF with 3-mΩ ESR resistance.
1
1
Co >
´
DV
8´ ƒsw
out
- esr
DiL
(11)
After considering both requirements, for this example, four 22-µF 6.3-V X7R ceramic capacitor with 3 mΩ of ESR
are used. Equation 12 calculates the maximum ESR an output capacitor can have to meet the output voltage
ripple specification. Equation 12 indicates the ESR should be less than 20.2 mΩ. In this case, the ceramic caps’
ESR is much smaller than 20.2 mΩ.
Voripple
£ Resr
Iripple
(12)
Factor in additional capacitance deratings for aging, temperature, and dc bias, which increase this minimum
value. This example uses a 22-µF 6.3-V X5R ceramic capacitor with 3 mΩ of ESR. Capacitors generally have
limits to the amount of ripple current they can handle without failing or producing excess heat. An output
capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the
root mean square (RMS) value of the maximum ripple current. Equation 13 can be used to calculate the RMS
ripple current the output capacitor needs to support. For this application, Equation 13 yields 385 mA.
Vout ´(Vin max - Vout)
Icorms =
12 ´ Vin max ´ L1 ´ ƒSW
(13)
10.2.2.5 Input Capacitor Selection
TI recommends a minimum 10-µF X7R/X5R ceramic input capacitor to be added between VIN and GND.
Connect these capacitors as close as physically possible to the input pins of the converters as they handle the
RMS ripple current shown in Equation 14. For this example, Iout = 2 A, Vout = 5 V, minimum Vin_min = 12 V,
from Equation 14, the input capacitors must support a ripple current of 998-mA RMS.
V
(
- Vout
)
Vout
inmin
I
= Iout
´
´
inrms
V
V
inmin
inmin
(14)
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 15. Using the design example values, Iout_max = 2.5 A, Cin = 10 µF, ƒSW = 500 kHz
for buck2, yields an input voltage ripple of 125 mV.
I
outmax ´ 0.25
DV =
in
Cin ´ ƒsw
(15)
To prevent large voltage transients, use a low-ESR capacitor sized for the maximum RMS current.
10.2.2.6 Minimum Output Voltage
Due to the internal design of the TPS65283, TPS65283-1, there is a minimum output voltage limit for any given
input voltage. The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V,
the output voltage may be limited by the minimum controllable on-time. The minimum output voltage in this case
is given by Equation 16.
Voutmin = Ontimemin × Fs max (Vin max + Iout min (RDS2 min – RDS1 min))_Iout min (RL + RDS2 min)
where
•
•
•
•
•
Voutmin = Minimum achievable output voltage
Ontimemin = Minimum controllable on-time (120-ns maximum)
Fsmax = Maximum switching frequency including tolerance
Vinmax = Maximum input voltage
Ioutmin = Minimum load current RDS1min = Minimum high-side MOSFET on-resistance (52-mΩ typical)
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•
•
RDS2min = Minimum low-side MOSFET on-resistance (27-mΩ typical)
RL = Series resistance of output inductor.
(16)
For the example circuit, Vin = 12 V, Fs = 500 kHz, when Iout = 0 A, the minimum output voltage is 0.72 V.
10.2.2.7 Compensation Component Selection
Integrated buck converters in TPS65283, TPS65283-1 incorporate a peak current mode. The error amplifier is a
transconductance amplifier with a gain of 300 µA/V. A typical type II compensation circuit adequately delivers a
phase margin between 60° and 90°. Cb adds a high-frequency pole to attenuate high-frequency noise when
needed. To calculate the external compensation components, follow these steps.
1. Select switching frequency ƒSW that is appropriate for application depending on L and C sizes, output ripple,
EMI, and so forth. Switching frequency between 500 kHz to 1 MHz gives the best trade-off between
performance and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒSW
.
3. RC can be determined by:
2p∂ ƒc ∂ Vo ∂Co
gM ∂ Vref ∂gmps
RC
=
where
•
•
gM is the error amplifier gain (300 µA/V),
gmps is the power stage voltage to current conversion gain (7.4 A/V).
(17)
1
ƒp =
CO ∂RL ∂ 2p
4. Calculate CC by placing a compensation zero at or before the dominant pole (
)
RL ∂Co
RC
CC
=
(18)
(19)
5. Optional Cb can be used to cancel the 0 from the ESR associated with Cb.
RESR∂Co
RC
Cb =
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C1 is calculated from Equation 20.
1
C1 =
2p∂R1 ∂ ƒC
(20)
For this design, the calculated values for the compensation components are Rc = 20 kΩ, CC = 3.3 nF, and
Cb = 22 pF.
VOUT
R1
C1
39 kΩ
Vref = 0.6 V
Vfb
VOUT
COMP
Current Sense
I/V Converter
EA
iL
R
ESR
R2
gM = 300 µS
gmps = 7.4 A/V
R
L
5.3 kΩ
C
b
R
c
C
o
C
c
Figure 31. DC-DC Loop Compensation
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10.2.3 Application Curves
TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
Figure 32. Buck1 Start Up by EN1 Pin With 2-A Loading
Figure 33. Buck2 Start Up by EN2 Pin With 2-A Loading
Figure 35. Ramp Vin to Start Up Buck2 With 2-A Loading
Figure 37. Buck2 Shut Down by EN2 Pin With 2-A Loading
Figure 34. Ramp Vin to Start Up Buck1 With 2-A Loading
Figure 36. Buck1 Shut Down by EN1 Pin With 2-A Loading
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TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
Iout1 = Iout2 = 0 A
Figure 38. Buck Output Voltage Ripple in PWM Mode
Iout1 = Iout2 = 2.5 A
Figure 39. Buck Output Voltage Ripple in PWM Mode
Iout1 = Iout2 = 0.1 A
Iout1 = Iout2 = 0 to 1 A
Figure 40. Buck Output Voltage Ripple in PSM Mode
Figure 41. Buck Output Load Transient in PSM Mode
Iout1 = Iout2 = 0 to 1 A
Iout1 = 2.5 to 3.5 A, Iout2 = 1.5 to 2.5 A
Figure 42. Buck Output Load Transient in PWM Mode
Figure 43. Buck Output Load Transient in PWM Mode
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TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
Figure 44. Buck1 Response to Hard Short
Figure 45. Buck2 Response to Hard Short
Figure 47. Buck2 Recovery from Hiccup
Figure 46. Buck1 Recovery from Hiccup
Rout = 50 Ω,
Cout = 10 μF
Figure 48. Clock Synchronization at 1 MHz
Figure 49. Power Switch Turn on Delay and Rising Time
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TJ = 25°C, Vin = 12 V, Vout1 = 1.2 V, Vout2 = 5 V, ƒSW = 500 kHz, RnFAULT1 = RnFAULT2 = 100 kΩ (unless otherwise noted)
Rout = 50 Ω,
Cout = 10 μF
Figure 50. Power Switch Turn off Delay and Fall Time
Figure 51. Power Switch Over Current With 2-A Loading
Figure 53. Power Switch Hard Short Operation
Figure 52. Power Switch Recovery from Over-Current
Figure 54. Power Switch Enable into Short Circuit
Figure 55. Power Switch Reverse Voltage Protection
Response
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11 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 to 18 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS65283 or
TPS65283-1 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
A typical choice is an electrolytic capacitor with a value of 10 μF.
12 Layout
12.1 Layout Guidelines
12.1.1 PCB Layout Recommendation
When laying out the PCB, use the following guidelines to ensure proper operation of the IC. These items are also
shown in the layout diagram of Figure 58.
•
There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supply's performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass
capacitor with X5R or X7R dielectric. This capacitor provides the ac current into the internal power MOSFETs.
Connect the (+) terminal of the input capacitor as close as possible to the VIN pin, and connect the (–)
terminal of the input capacitor as close as possible to the PGND pin. Take care to minimize the loop area
formed by the bypass capacitor connections, the VIN pins, and the power ground PGND connections.
•
Because the LX connection is the switching node, the output inductor should be located close to the LX pin,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching
node, LX, away from all sensitive small-signal nodes.
•
•
•
•
Connect V7V decoupling capacitor connected close to the IC, between the V7V and the power ground PGND
pin. This capacitor carries the MOSFET drivers’ current peaks.
Place the output filter capacitor of buck converter close to SW_IN pins. Try to minimize the ground conductor
length while maintaining adequate width.
AGND pin should be separately routed to the (–) terminal of V7V bypass capacitor to avoid switching
grounding path. TI recommends a ground plane connecting to this ground path.
The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are
sensitive to noise, so the components associated to these pins should be located as close as possible to the
IC and routed with minimal lengths of trace. Flood all unused areas on all layers with copper. Flooding with
copper reduces the temperature rise of power components. You can connect the copper areas to PGND,
AGND, VIN, or any other dc rail in the system.
•
There is no electric signal internally connected to thermal pad in the device. Nevertheless, connect exposed
pad beneath the IC to ground. Always solder thermal pad to the board and have as many vias as possible on
the PCB to enhance power dissipation.
12.1.2 Power Dissipation and Junction Temperature
The total power dissipation inside TPS65283, TPS65283-1 should not to exceed the maximum allowable junction
temperature of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the
package (RθJA) and ambient temperature.
The following analysis gives an approximation in calculating junction temperature based on the power dissipation
in the package. However, note that thermal analysis is strongly dependent on additional system-level factors.
Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices
dissipating power. Good thermal design practice must include all system-level factors in addition to individual
component analysis.
To calculate the temperature inside the device under continuous load, use the following procedure.
1. Define the total continuous current through buck converter (including the load current through power
switches). Make sure the continuous current does not exceed maximum load current requirement.
2. From the graphs in this section, determine the expected losses (y-axis) in watts for buck converter inside the
device. The loss PD_BUCK depends on the input supply and the selected switching frequency.
3. Determine the load current IOUT through the power switches. Read RDS(on) of power switch from the typical
Copyright © 2014–2019, Texas Instruments Incorporated
31
TPS65283, TPS65283-1
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
www.ti.com.cn
Layout Guidelines (continued)
characteristics graph.
4. Calculate the power loss through power switches with PD_PW = RDS(on) × IOUT
.
5. The Thermal Information table provides the thermal resistance RθJA for specific packages and board layouts.
6. To calculate the maximum temperature inside the IC, use Equation 21.
TJ = (PD_BUCK + PD_PW ) × RθJA + TA
where
•
•
•
•
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C/W)
R
PD_BUCK = Total power dissipation in buck converter (W)
PD_PW = Total power dissipation in power switches (W)
(21)
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Buck2-5 V
Buck1-1.2 V
0
1
2
3
4
Loading (A)
C012
Figure 56. Power Dissipation of TPS65283
A. VIN = 12 V, Vout1 = 1.2 V / 3 A, Vout2 = 5 V / 2 A, VSW_in = 5 V, ISW_OUT = 1.2 A
B. EVM board: 4-layer PCB, 1.6-mm thickness, 35-µm copper thickness, 68-mm × 68-mm size, 9 vias at thermal pad
Figure 57. Thermal Signature of TPS65283EVM
32
Copyright © 2014–2019, Texas Instruments Incorporated
TPS65283, TPS65283-1
www.ti.com.cn
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
12.2 Layout Example
Top Side Analog
Ground Area
BST2
LX2
BST1
LX1
Output inductor
Output inductor
VOUT2
VOUT1
Output
capacitor
Output
capacitor
PGND1
VIN1
PGND2
VIN2
Input capacitor
VIN
Top Side
Power
Ground
Area
Top Side
Power
Ground
Area
V7V
SW_IN
SW_IN
Power switch
PGOOD1
SW_OUT
input capacitor
PGOOD1
PGOOD2
Power switch
output capacitor
SW_OUT
Top Side Analog
Ground Area
Thermal VIA
Signal VIA
Figure 58. 4-Layer PCB Layout Recommendation
版权 © 2014–2019, Texas Instruments Incorporated
33
TPS65283, TPS65283-1
ZHCSCO8E –JUNE 2014–REVISED MAY 2019
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 5. 相关链接
器件
产品文件夹
单击此处
单击此处
样片与购买
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TPS65283
TPS65283-1
13.2 商标
PowerPAD is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
13.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
34
版权 © 2014–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65283-1RGER
TPS65283-1RGET
TPS65283RGER
TPS65283RGET
ACTIVE
VQFN
VQFN
VQFN
VQFN
RGE
24
24
24
24
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 125
-40 to 125
TPS
65283-1
ACTIVE
ACTIVE
ACTIVE
RGE
NIPDAU
NIPDAU
NIPDAU
TPS
65283-1
RGE
TPS
65283
RGE
TPS
65283
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65283-1RGER
TPS65283-1RGER
TPS65283-1RGET
TPS65283-1RGET
TPS65283RGER
TPS65283RGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000
3000
250
330.0
330.0
180.0
180.0
330.0
180.0
12.4
12.4
12.5
12.4
12.4
12.4
4.25
4.35
4.35
4.25
4.25
4.25
4.25
4.35
4.35
4.25
4.25
4.25
1.15
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
1.1
250
1.15
1.15
1.15
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65283-1RGER
TPS65283-1RGER
TPS65283-1RGET
TPS65283-1RGET
TPS65283RGER
TPS65283RGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000
3000
250
346.0
338.0
338.0
210.0
346.0
210.0
346.0
355.0
355.0
185.0
346.0
185.0
33.0
50.0
50.0
35.0
33.0
35.0
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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