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TPS65400-Q1

SLVSCQ2 –JULY 2015

TPS65400-Q1 4.5- to 18-V Input Flexible Power Management Unit With PMBus/I²C Interface

1 Features

–

PWM Frequency Adjustment for Each Switcher

Individual PWM Phase Alignment for Each

Switcher to Minimize Ripple and Capacitor

Size

1

•

Qualified for Automotive Applications

AEC-Q100 Qualified With the Following Results:

–

Device Temperature Grade 1: –40°C to 125°C

Ambient Operating Temperature Range

–

Adjustable Current Limit on Each Regulator

Enables Size and Cost Optimization of

Inductors

–

Device HBM ESD Classification Level H2

Device CDM ESD Classification Level C4B

Soft-Start Time

•

Efficiency up to 95% for Each Switching Regulator

Switching Regulator Specifications:

2 Applications

–

Input Voltage Range: 4.5 to 18 V

Vout Range: 0.6 V-90%Vin

SW1, SW2 Iout: 4-A Max

SW3, SW4 Iout: 2-A Max

•

Qualified for Automotive Applications

Small Cellular Base Stations (BTS) (for Example:

Picocells and Microcells); Macro BTS (Using

Multiple PMUs)

•

Power over Ethernet (PoE) Powered

Communications Infrastructure Equipment

•

Pre-Bias Startup Algorithm Minimizes Voltage Dip

During Startup

•

Powering DSP and MCUs

Internal Undervoltage Lockout (UVLO),

Overcurrent Protection (OCP), Overvoltage

Protection (OVP), and Overtemperature Protection

(OTP)

Industrial and Factory Automation

Systems Requiring Small Form Factor, High-

Efficiency, High-Ambient Operating Temperature,

and Flexible Power Management

•

Thermally-Enhanced 7-mm × 7-mm 48-Pin, 0.5-

mm Pitch VQFN Package

3 Description

Pin Accessible Features:

The TPS65400-Q1 is an integrated PMU optimized

for applications requiring small form factor and high

power conversion efficiency, enabling small space-

constrained equipment with high ambient operating

temperature without cooling. It provides high-power

efficiency at a system level by enabling a single stage

conversion from an intermediate distribution bus with

an optimized combination of regulators.

–

Adjustable VOUT With External Feedback

Resistors

Sequencing Control Through Precision Enable

Pins for Each Switcher

Resistor Adjustable PWM Switching Frequency

from 275 kHz to 2.2 MHz

–

Clock Sync Input and Clock Output

Device Information⁽¹⁾

Soft-Start Delay Through External Capacitor

Current Sharing Between SW1 and SW2 and

Between SW3 and SW4 Allows Support of

Higher Current Needs if Required

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TPS65400-Q1

VQFN (48)

7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

PMBus Runtime Control and Status

–

Runtime Voltage Positioning Through

Adjustment of V_REF

Simplified Schematic

Vin: 4.5 to 18 V

–

Enable and Disable of Each Switcher

Fault and Status Monitoring

4 A

2 A

User-Configurable PMBus / I²C Options, Saved in

EEPROM

BUCK1

BUCK2

BUCK4

BUCK3

–

Power Supply Turn-On and Turn-Off

Sequencing

Sequencing can be Based on Fixed Time

Delays or PGOOD Dependence

PMBus/I²C

Initial Voltage Positioning Through VREF

Configuration

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65400-Q1

SLVSCQ2 –JULY 2015

www.ti.com

Table of Contents

8.2 Functional Block Diagrams ..................................... 12

8.3 Feature Description................................................. 13

8.4 Device Functional Modes........................................ 27

8.5 Register Maps......................................................... 29

Application and Implementation ........................ 54

9.1 Application Information............................................ 54

9.2 Typical Applications ................................................ 55

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 System Characteristics ............................................. 9

7.7 Operational Parameters............................................ 9

7.8 Package Dissipation Ratings .................................... 9

7.9 Typical Characteristics: System Efficiency ............. 10

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

9

10 Power Supply Recommendations ..................... 66

11 Layout................................................................... 66

11.1 Layout Guidelines ................................................. 66

11.2 Layout Example .................................................... 67

12 Device and Documentation Support ................. 68

12.1 Documentation Support ........................................ 68

12.2 Community Resources.......................................... 68

12.3 Trademarks........................................................... 68

12.4 Electrostatic Discharge Caution............................ 68

12.5 Glossary................................................................ 68

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 68

4 Revision History

DATE

REVISION

NOTES

July 2015

*

Initial release.

2

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5 Description (continued)

TPS65400-Q1 implements a PMBus-I²C-compatible digital interface. It helps Core Chip optimize system

performance by runtime changing regulated voltage, power sequence, phase interleaving, operating frequency,

read back operating status, and so forth.

The TPS65400-Q1 consists of four high-current buck switching regulators (SW1, SW2, SW3, and SW4) with

integrated FETs. The switching power supplies are intended for powering high-current digital circuits such as the

processor, FPGA, ASIC, memory, and digital I/Os. SW1 and SW2 support 4 A each, and SW3 and SW4 support

2 A each. Each regulator’s switching frequency is independently adjustable up to 2.2 MHz.

Current limit programmability on each switcher enables optimization of inductor ratings for a particular application

configuration not requiring the maximum current capability.

The TPS65400-Q1 can be powered from a single-input voltage rail between 4.5 and 18 V, making it suitable for

applications running off a 5- or 12-V intermediate power distribution bus.

Sequencing requirements can be met using the individual enable terminals or by programming the sequence

through the I²C bus into the onboard EEPROM. Output voltages can be set through external resistor networks

and VREF can be programmed from 0.6 to 1.87 V in 10-mV steps. All control and status info can be accessed

through a PMBus-compatible I²C bus.

The TPS65400-Q1 provides a high level of flexibility for monitoring and control through the I²C bus while

providing the option of programmability through the use of external components and voltage levels for systems

not using I²C.

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

CB1

SW1

1

2

3

4

5

6

7

8

9

36 COMP4

35 VFB4

34 ENSW4

33 CB4

PGND(thermal pad)

SW1

PVIN1

PVIN2

PGND1

PGND2

SW2

32 SW4

31 PVIN4

30 PVIN3

29 SW3

28 CB3

SW2 10

SW2 11

CB2 12

27 ENSW3

26 VFB3

25 COMP3

A. Thermal pad must be soldered to PCB as SW3 and SW4 power ground

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SLVSCQ2 –JULY 2015

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Pin Functions

NAME

DESCRIPTION

NO.

1

CB1

Bootstrap pin for high-side MOSFET gate drive for SW1

Switch pin for SW1

2

SW1

3

4

PVIN1

PVIN2

PGND1

PGND2

5

Power input for buck switching regulator SW1

Power input for SW2

6

7

Power ground for buck converters

8

9

SW2

10 Switch pin for SW2

11

CB2

12 Bootstrap pin for SW2 high-side MOSFET gate drive

13 Enable input pin for SW2. Active high. 2-µA internal pullup current is inside.

14 Feedback input pin for SW2

ENSW2

VFB2

Compensation pin for external compensation network for SW2. Pulling this line high to VDDD configures the

SW1 controller to control both SW1 and SW2.

COMP2

SS2/PG2

PGOOD

15

16

17

Soft-start for SW2 (default). A capacitor is used to set the startup time. This pin can also be reconfigured

through I²C to display the PGOOD2 signal instead.

Default PGOOD signal is for all switchers. It can be changed according to (D2h) PIN_CONFIG_00. If all

switchers are disabled, PGOOD is low.

VDDG

VDDA

VDDD

AGND

VIN

18 Supply for gate drives. Bypass locally to PGND.

19 Output of internal regulator for analog controls.

20 3.3-V output of internal regulator digital controls

21 Ground connection for analog controls

22 Analog V_IN. Power input pin for VDDD, VDDA, and VGATE subregulator power

Chip enables. Internal pull-up current will default to high if the pin is left floating. Connect to an open-drain output

to pull low to disable. Driving with a push-pull output is not recommended. When low, internal regulators are

shutdown to minimize power, and functionsa are disabled. Configuration is reloaded from EEPROM as part of

CE

23

the power-up sequence when CE goes high.

Soft-start for SW3 (default). A capacitor is used to set the startup time. This pin can also be reconfigured

SS3/PG3

24

through I²C to display the PGOOD3 signal instead.

COMP3

VFB3

ENSW3

CB3

25 Compensation pin for external compensation network for SW3

26 Feedback input pin for SW3

27 Enable input pin for SW3. Active high. 2-µA internal pullup current is inside.

28 Bootstrap pin for SW3 high-side MOSFET gate drive

29 Switch pin for SW3. Max rated output current is 2 A.

30 Power input for buck switching regulator SW3

31 Power input for SW4

SW3

PVIN3

PVIN4

SW4

32 Switch pin for SW4. Max rated output current is 2 A.

33 Bootstrap pin for SW4 high-side MOSFET gate drive

34 Enable input pin for SW4. Active high. 2-µA internal pullup current is inside.

35 Feedback input pin for SW4

CB4

ENSW4

VFB4

Compensation pin for external compensation network for SW4. Pulling this line high to VDDD configures the

SW3 controller to control both SW3 and SW4.

COMP4

36

Soft-start for SW4 (default). A capacitor is used to set the startup time. This pin can also be reconfigured

SS4/PG4

37

through I²C to display the PGOOD4 signal instead

I2CADDR

38 Select I²C address with resistor to AGND

Reset of digital logic. When low, all switchers are disabled. Configuration is reloaded from EEPROM when

RESET_N is deasserted.

RST_N

39

RCLOCK_SYNC

40 Resistor for setting master clock frequency from 275 kHz to 2.2 MHz or for clock sync

4

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Pin Functions (continued)

NAME

DESCRIPTION

NO.

Open-drain output that is pulled low for 200 µs when a timeout condition is detected by the I²C watchdog on

either SDA or SCL.

I2CALERT

41

SDA

42 Data input/output pin for I²C bus

SCL

43 Clock input pin for I²C bus

CLK_OUT

44 Clock output signal. Open-collector output, requires pull up.

Soft-start for SW1 (default). A capacitor is used to set the startup time. This pin can also be reconfigured

SS1/PG1

45

through I²C to display the PGOOD1 signal instead.

COMP1

46 Compensation pin for external compensation network for SW1

47 Feedback input pin for SW1

VFB1

ENSW1/ENSEQ

48 Enable input pin for SW1. Active high. 2-µA internal pullup current is inside.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

(1)

MIN

–0.3

MAX

20

UNIT

PVIN1, PVIN2, PVIN3, PVIN4, VIN

CB1, CB2, CB3, CB4 referenced to SWx

7.5

ENSW1, ENSW2, ENSW3, ENSW4, SCL, SDA, CLK_OUT, VFB1, VFB2, VFB3, VFB4,

RST_N, SCL, SDA, I2CALERT, CLK_OUT, I2CADDR, RCLOCK_SYNC

–0.3

VDDD or 3.6

Input

voltage

SW1, SW2, SW3, SW4

VDDA, VDDG

–1

20

V

–0.3

7.5

PGOOD, SS1/PG1, SS2/PG2, SS3/PG3, SS4/PG4, COMP1, COMP2, COMP3, COMP4,

CE

–0.3

VDDA or 7.5

VDDD

3.6

150

260

150

T_J(max)

Junction temperature

Maximum lead temperature (soldering, 10 s)

Storage temperature

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Electrostatic

discharge

V_(ESD)

All pins

V

Charged-device model (CDM), per

AEC Q100-011

Corner pins (1, 12, 13, 24, 25, 36, 37, and 48)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

0

MAX

UNIT

VIN1, VIN2, VIN3, VIN4

I_OUT1, I_OUT2

Input voltage range

Load current

18

4

V

A

I_OUT3, I_OUT4

Load current

0

2

A

V_FB1, V_FB2, V_FB3, V_FB4

T_J

Voltage feedback

Junction temperature range

0.6

–40

1.87

125

V

°C

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7.4 Thermal Information

TPS65400-Q1

THERMAL METRIC⁽¹⁾

RGZ (VQFN)

48 PINS

29.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

14.9

6.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

6.3

R_θJC(bot)

0.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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7.5 Electrical Characteristics

V_IN= 12 V, F_SW= 500 kHz, T_J= –40°C to 125°C, typical values are at T_J= 25°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SWITCHER 1 AND SWITCHER 2

SW1, SW2 high-side current limit

adjustment range

I_limit1, I_limit2

2

6

A

I_{limit-accuracy}

Rdson HS

Rdson LS

Accuracy to nominal current limit value

SW1, SW2 HS Rds(on)

SW1, SW2 LS Rds(on)

I_limit= 4 A, 5 A, 6 A

–25%

25%

66

42

mΩ

SWITCHER 3 AND SWITCHER 4

I_limit3, I_limit4

I_{limit accuracy}

Rdson HS

Rdson LS

SW3 and SW4 current limit

0.5

3

A

Accuracy to nominal current limit value

SW3 and SW4 HS Rds(on)

SW3/4 LS Rds(on)

I_limit= 1 A, 2 A, 3 A

–25%

25%

120

90

mΩ

FEEDBACK AND ERROR AMPLIFIERS FOR SW1 – SW4

VFB

Accuracy

V_REF= 1 V

–1%

95

1%

V_REFn

V_{REF_STEP}

Gm

Error amplifier reference voltage

I²C programmable V_REFstep size

Error amplifier transconductance

Sink

Default value

800

10

mV

µS

µA

133

12

165

I_sink

I_source

Source

12

PWM SWITCHING CHARACTERISTICS

Phase_err12⁽¹⁾Phase error between SW1 and SW2

Phase_err34⁽¹⁾Phase error between SW3 and SW4

F_sw= 1.1 MHz

5⁰

Resistor-configurable PWM switching

configuration

F_sw

275

2200

10%

kHz

R_OSC= 165 kΩ

(F_sw= 1.1 MHz)

F_sw-accuracy

PWM switching frequency accuracy

–10%

V_{rclock_sync}

t_{ON_min}

Voltage reference for RCLOCK_SYNC

Lower duty cycle limit

0.8

80

V

150

ns

Minimum off-time limit (constrains the

maximum achievable duty cycle)

t_{OFF_min}

150

ns

CLOCK SYNC

V_H_SYNC

V_L_SYNC

I_CLKOUT

High signal threshold

2.6

V

Low signal threshold

1

Max current sink/source for CLK_OUT

Minimum detectable time for sync pulse

Frequency synchronization range

2

mA

ns

t_{min_SYNC}

F_SYNC

150

275

2200

kHz

Delay between input pulse to

RCLOCK_SYNC and rising edge of

CLK_OUT and PWM output

T_{SYNC_DELAY}

20

ns

TIMING CHARACTERISTICS

Delay for restart during repeated OCP

condition

INTERNAL REGULATORS AND UVLO

t_restart

ms

V_in> 6.6 V

6.1

V_in– 0.1

3.2

V_DDA

V_DDD

V_DDG

Internal subregulator output

V

4.5 V < V_in6.6 V

Output of internal subregulator

V_in> 6.6 V

6.1

Output of Internal regulator for gate

drivers

4.5 V < V_in6.6 V

V_in– 0.1

(1) Specified by design.

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Electrical Characteristics (continued)

V_IN= 12 V, F_SW= 500 kHz, T_J= –40°C to 125°C, typical values are at T_J= 25°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Quiescent non-switching, no load

current

CE high, V_FB>> V_REF, (no

switching)

I_VIN

8

mA

I_SD

Quiescent shutdown current

Input voltage UVLO

CE low

Rising

Falling

12

4.25

3.75

27

µA

V

V_{IN_UVLO}

4.48

Input voltage UVLO

3.4

V

PGOOD, ENSWx, RST_N, SSx, PG

Resistance of PGOOD outputs when

low

R_L_PGOOD

500

Ω

V_OL_PGOOD

I_SS

Logic output low voltage

Soft-start current

I_OL = 100 µA

0.1

7.3

V

4.1

5.6

µA

Enable logic high threshold (for ENSW1,

ENSW2, ENSW3, ENSW4)

V_{EN_H}

V_ENrising

V_ENfalling

1.12

1.20

1.28

V

Enable logic low threshold (for ENSW1,

ENSW2, ENSW3, ENSW4)

V_{EN_L}

0.97

1.07

130

Enable hysteresis (for ENSW1, ENSW2,

ENSW3, ENSW4)

V_{EN_HYS}

mV

I_EN

ENSWx pin pullup current

CE pin pullup current

Logic input high for CE

Logic input low CE

V_EN= 0

V_CE= 0

2

µA

V

I_CE

V_{IH_CE}

V_{IL_CE}

V_{IH_RSTN}

V_{IL_RSTN}

1.3

0.4

0.8

V

Logic input high RST_N

V

Logic input low RST_N

V

I²C MODULE (SDA, SCL, I2CALERT, I2CADDR)

V_IL_I2C

V_IH_I2C

Logic input low SCL, SDA

V

Logic input high for SCL, SDA

2.1

ON resistance of I²C pins

(SDA,SCL,I2CALERT) to GND

R_L_I2C

I2CALERT = 1

I_OL = 350 µA

85

Ω

Logic output low voltage for

SCL,SDA,I2CALERT pins

V_OL_I2C

0.1

1

V

I_LEAK

Input leakage current

SDA, SCL = 3.3 V

µA

uA

ms

µs

I_I2CADDR

t_TIMEOUT

Source current of I2CADDR pin

Timeout detection on SDA or SCL low

VDDD = 3.3 V, VIN > 4.5 V

20

30

t_{TIMEOUT_PULSE}Duration of timeout pulse on I2CALERT

200

FAULTS

(2)

T_TSD

Thermal shutdown threshold

Thermal shutdown hysteresis

160

20

⁰C

(2)

T_{TSD_restart}

OVP threshold rising (fault latched,

PGOOD asserted)

% of

V_REF

0.6V < V_REF< 1.87 V

0.6 V < V_REF< 1.87 V

111

104

55

V_{FB_OVP}

OVP threshold falling (fault cleared,

PGOOD deasserted)

% of

V_REF

Time after OVP before protection

activation and PGOOD fall

t_OVPSDOWN

95

µs

Undervoltage threshold (PGOOD

deasserted)

% of

V_REF

0.6 V < V_REF< 1.87 V

92

V_{FB UVP}

Undervoltage Threshold (PGOOD

asserted)

% of

V_REF

83

55

t_UVPSDOWN

Time after UVP before PGOOD fall

µs

(2) Specified by lab validation.

8

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7.6 System Characteristics

The following specification table entries are specified by the design (component values provided in the typical application

circuit are used). These parameters are not specified by production testing. Minimum and Max values apply over the full

operating ambient temperature range (–40°C ≤ T_J≤ 125°C), over the V_INrange = 5 to 12 V, and I_OUTrange unless otherwise

specified. L = 3.3 µH, DCR = 10.4 mΩ, V_OUT= 1.2 V, 1% FB resistor.

PARAMETER

TEST CONDITIONS

MIN

TYP

0.1

30

MAX

UNIT

%/V

%/A

µs

V_LINEREG

Line regulation

V_LOADREG

Load regulation

t_r

VOUT step duration (t_r)

VOUT step settling time (t_s)

VOUT step overshoot/undershoot

For 50-mV step

t_s

For 50-mV step

30

µs

V_OVUV

6

mV

Vin = 5 V, Vo = 1.2 V, Iout = 4 A,

ƒ_sw= 500 kHz

77%

76%

77%

74%

Efficiency (SW1 and SW2)

Vin = 12 V, Vo = 1.2 V Iout = 4 A,

ƒ_sw= 500 kHz

Vin = 5 V, Vo = 1.2 V, Iout = 2 A,

ƒ_sw= 500 kHz

Efficiency (SW3 and SW4)

Average (⁽¹⁾) current sharing

Vin = 12 V, Vo = 1.2 V Iout = 2 A,

ƒ_sw= 500 kHz

IOUT_match

accuracy (SW1 and SW2, SW3 and I_load= I_OUTmax

SW4)

20%

Peak current (⁽²⁾) sharing accuracy

(SW1 and SW2, SW3 and SW4)

IPK_match

t_acc

I_load= I_OUTmax

20%

10%

Timing accuracy for delays and

restarts

–10%

Time after RSTn or CE is released

Default value

t_{reset_delay}

1

ms

for power sequence to begin

Minimum delay after reset is

t_{reset_delay_max}

0

released for power sequence to

begin

t_{reset_delay}set to 0 ms

1.1

(1) Average current sharing accuracy is highly dependent on the matching of the inductor and capacitor.

(2) Peak current sharing accuracy refers to the max inductor current in each phase.

7.7 Operational Parameters

Values recommended that ensure proper system behavior

PARAMETER

MIN

TYP

4.7

3.3

10

MAX

UNIT

C_A

Stabilization capacitor to be connected to VDDA

Stabilization capacitor to be connected to VDDD

Stabilization capacitor to be connected to VDDG

SW1 to SW4 input voltage

µF

V

C_D

C_G

Vin1, Vin2, Vin3, Vin4

4.5

0.6

18

90% of Vin

Vout1, Vout2, Vout3, Vout4 SW1 to SW4 output voltage

V

7.8 Package Dissipation Ratings⁽¹⁾

PACKAGE

R

_θJA(°C/W)

T_A= 25°C

T_A= 55°C

3.14 W

T_A= 85°C

1.77 W

RGZ

29.8

4.5 W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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7.9 Typical Characteristics: System Efficiency

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0

30%

V_IN= 12 V; V_OUT= 1V8

V_IN= 12 V; V_OUT= 1V5

V_IN= 12 V; V_OUT= 1V2

V_IN= 12 V; V_OUT= 1V

V_IN= 5 V; V_OUT= 1V8

20%

V_IN= 5 V; V_OUT= 1V5

V_IN= 5 V; V_OUT= 1V2

V_IN= 5 V; V_OUT= 1V

10%

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

I_OUT

D001

D002

With 500 kHz and XAL6060-472 4.7-µH, 13.2-mΩ inductor

Figure 1. Buck1 and Buck2 Power Efficiency, V_IN= 12 V

Figure 2. Buck1 and Buck2 Power Efficiency, V_IN= 5 V

100%

90%

80%

70%

60%

50%

40%

90%

80%

70%

60%

50%

40%

30%

V_IN= 12 V; V_OUT= 1V8

V_IN= 12 V; V_OUT= 1V5

V_IN= 5 V; V_OUT= 1V8

V_IN= 5 V; V_OUT= 1V5

20%

V_IN= 12 V; V_OUT= 1V2

V_IN= 12 V; V_OUT= 1V

V_IN= 5 V; V_OUT= 1V2

V_IN= 5 V; V_OUT= 1V

10%

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

I_OUT

D004

D001

With 500 kHz F_SWand 4.7-µH, 34-mΩ inductor

Figure 3. Buck3 and Buck4 Power Efficiency, V_IN= 12 V

Figure 4. Buck3 and Buck4 Power Efficiency, V_IN= 5 V

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8 Detailed Description

8.1 Overview

The TPS65400-Q1 is an integrated PMU optimized for applications that require small form factor and high-power

conversion efficiency enabling small space-constrained equipment with high-ambient operating temperature

without cooling. It provides high-power efficiency at a system level by enabling a single-stage conversion from an

intermediate distribution bus with an optimized combination of regulators.

The TPS65400-Q1 consists of four high-current buck-switching regulators (SW1, SW2, SW3, and SW4) with

integrated FETs. The switching power supplies are intended for powering high-current digital circuits such as the

processor, FPGA, ASIC, memory, and digital I/Os. SW1 and SW2 support 4 A each, and SW3 and SW4 support

2 A each. Each regulator’s switching frequency is independently adjustable up to 2.2 MHz.

Current limit programmability on each switcher enables optimization of inductor ratings for a particular application

configuration not requiring the maximum current capability.

The TPS65400-Q1 can be powered from a single-input voltage rail between 4.5 and 18 V, making it suitable for

applications running off a 5- or 12-V intermediate power distribution bus.

Sequencing requirements can be met using the individual enable pins or by programming the sequence through

the I²C bus into the onboard EEPROM. Output voltages can be set through external resistor networks and VREF

can be programmed from 0.6 to 1.87 V in 10-mV steps. All control and status info can be accessed through a

PMBus-compatible I²C bus.

The TPS65400-Q1 provides a high level of flexibility for monitoring and control through the I²C bus while

providing the option of programmability through the use of external components and voltage levels for systems

not using I²C.

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8.2 Functional Block Diagrams

COMP2

COMP1

PVIN1

VREF DAC

SS DAC

CB1

SDA

EEPROM

and

SCL

I2C

PWM Controller

Gate Driver

SW1

Charge Pump

I2CADDR

I2CALERT

OCP

PGND1

VFB1

RCLOCK_SYNC

CLK_OUT

CLOCK

(Adj Fsw and ꢀ)

OVP

UVP

ISENSE

PVIN2

CB2

ENSW1

ENSW2

ENSW3

Sequencing

Controller

VREF DAC

SS DAC

Enable

and

PWM Controller

Gate Driver

PGOOD

SW2

ENSW4

PGOOD

OCP

PGND2

VFB2

OVP

UVP

ISENSE

SS1/PG1

SS2/PG2

SS3/PG3

SS4/PG4

Soft-Start

or

PGOOD#

TPS65400-Q1

PVIN3

CB3

VREF DAC

SS DAC

RST_N

CE

Gate Driver

PWM Controller

SW3

OCP

VIN

PGND (Thermal Pad)

VFB3

ISENSE

OVP

UVP

VDDD

VDDA

VDDG

Internal

Sub-Reg

and

PVIN4

CB4

Bias

VREF DAC

SS DAC

VREF

UVLO

OTP

AGND

PWM Controller

SW4

Gate Driver

OCP

PGND (Thermal Pad)

VFB4

OVP

UVP

ISENSE

COMP3

COMP4

Figure 5. TPS65400-Q1 Functional Block Diagram

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Functional Block Diagrams (continued)

INPUT+

0

VDDG

RCLOCK_SYNC

PVIN1

VIN

VDDA

Regulator

VDDG

Regulator

Oscillator

CB1

VDDD

Regulator

UVLO

VREF1

Generator

UVLO

OVP1

OUTPUT+

COMP

Precharge

SW1

VREF1

Logic

GM1

SS1

FB1

0.5V

OCP1

High Side

PGND1

Zero Cross

Detect

Current

Sense

COMP1

High Side

Current

Limit

Low Side

Current

Limit

Slope

Comp.1

Soft-Start

Control 1

OVP1/UVP1

Detector

SS1/PG1

Function

OCP1

Control

UVP1

OVP1

AGND

A. All other switchers follow the same pattern

Figure 6. Simplified Control Block Diagram for Switcher1

8.3 Feature Description

8.3.1 Startup Timing and Power Sequencing

8.3.1.1 Startup Timing

Figure 7 shows the startup timing of the TPS65400-Q1. Upon power-up or the rising edge of CE, the internal

power rails VDDA, VDDG, and VDDD startup during the time labeled t_start. Following t_start, a delay of t₁follows

(which is defined by the user through the timing of RST_N). During time t_startand t₁, the COMP terminal is

internally discharged through a 1-kΩ resistor. At the rising edge of RST_N, the TPS65400-Q1 begins two actions:

1. The TPS65400-Q1 begins its precharge of the COMP terminal (indicated by t_precharge). The length of t_precharge

needed to precharge the COMP terminal depends on the time constant of the R and C components. The

internal precharge voltage source remains on even during normal operation, preventing the COMP terminal

from falling below 0.6 V except during faults (OVP, OCP, and so forth).

2. The TPS65400-Q1 begins its configuration sequence (indicated by t_config), and loads parameters from the

EEPROM. Parameters to be set include Vout, switching frequency, soft-start timing, and current limit.

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Feature Description (continued)

After t_configis complete, t_{reset_delay}begins. The length of t_{reset_delay}is user-configurable through PMBus register

DCh. After t_{reset_delay}is complete, the TPS65400-Q1 begins its startup sequence. The startup sequence is

EEPROM-configurable, so any of the four switchers could be the first to startup with a configurable delay. In this

particular example, SW1 is configured to startup first after a delay of t_{SW1_TON_DELAY}, which is configurable

through PMBus register (DDh) TON_TOFF_DELAY.

VIN

CE

VDDA

VDDG

VDDD

t_start

t₁

RST_N

t_config

t_{reset_delay}

COMP

t_precharge

ENSW1

t₂

VOUT1

t_{SW1_TON_DELAY}

t

A. PGOOD1 and ENSW2 are tied together externally, and t_{ON_DELAY1}and t_{ON_DELAY2}are configured through PMBus.

Figure 7. Timing Showing Startup from CE

To summarize, the length of time from rising edge of CE to soft-start of the first switcher in the sequence is:

t_{CE_to_SS}= t_start+ t₁+ t_config+ t_{reset_delay}+ t₂+ t_{SW1_ON_DELAY}

(1)

The delays, t_{reset_delay}and t_{SW1_ON_DELAY}, are both configurable through PMBus. The delay, t_config, is typically 1.1

ms. The delays, t₁and t₂, are determined by the user-defined timing of RST_N and ENSW1. They can both be

set to 0 by pulling RST_N high before the end of t_startand ENSW1 high before the end of t_{reset_delay}. One simple

way to do this would be to tie both signals to VDDD.

8.3.1.2 External Sequencing

To use external sequencing, either connect all the enable pins (ENSW1, ENSW2, ENSW3, and ENSW4) to an

external sequencing controller, or connect them to PGOOD outputs as shown in Figure 8. By default, t_{ON_DELAY}

and t_{OFF_DELAY}are both set to 5 ms. This allows the user complete flexibility of sequencing order and timing with

the ENSWx pins without modifying any of the default settings in the TPS65400-Q1.

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Feature Description (continued)

ENSW1

ENSW2

ENSW3

ENSW4

VOUT1

VOUT2

1

2

3

VOUT3

4

VOUT4

PGOOD1

PGOOD2

PGOOD3

PGOOD4

PGOOD

t

1. t_SS1

2. t_SS2

3. t_SS3

4. t_SS4

A. Default behavior (external sequencing)

Figure 8. Example of Sequencing Where Timing is Controlled by an External Sequencer With ENSWx

Pins

8.3.1.3 Internal Sequencing

The default settings for SEQUENCE_ORDER (see (D5h) SEQUENCE_ORDER) effectively disable sequencing

by setting all switchers to start at the same time. Therefore, to use internal sequencing, the default values for

SEQUENCE_ORDER must be changed to the desired sequence. In addition, the user can configure the start or

stop sequence to have a dependence on the PGOOD output of the previous switcher, or to wait for a set delay. If

configured to have a dependence on PGOOD, the soft-start for the next switcher begins after PGOOD of the

previous goes high and the wait time determined by t_{ON_DELAY}is complete. If configured to wait for a set delay,

the wait time determined by t_{ON_DELAY}begins immediately upon the enabling of the previous switcher.

In addition, each supply can be disabled such that it is bypassed in the power-up sequence. For example, if the

sequence is SW1-SW2-SW3-SW4, and SW2 is disabled, then SW3 will be powered up after SW1. The initial

configuration of the TPS65400-Q1 (for first-time power-up) needs to be done using one of the methods described

in Initial Configuration.

8.3.2 UVLO and Precision Enables

The TPS65400-Q1 implements a UVLO function that prevents startup when the voltage at VIN (terminal 22) is

below 4 V. In most applications, VIN and all of the power rails (PVIN1, PVIN2, PVIN3, and PVIN4) are tied to the

same source and this single UVLO function is sufficient. However, in some applications, the power rails may be

tied to different input voltages, and there is the possibility that the TPS65400-Q1 may attempt to startup a

switcher even when its associated PVINx rail has not reached a high-enough voltage. In these cases, the

precision enable threshold on each ENSWx can be used to precisely set the startup threshold for each individual

switcher with a simple resistor divider to PVINx.

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Feature Description (continued)

In cases where a single UVLO threshold is needed for all four switchers, but at a different level than 4 V, the

TPS65400-Q1 can be configured for single-terminal enable (PMBus register D2h, bits 0:1 = 10) where the

ENSW1/ENSEQ terminal is used as a sequence enable terminal. Then, a resistor divider to the appropriate

PVINx rail can be used to set a precise UVLO threshold that applies to all four switchers.

8.3.3 Soft-Start and Prebiased Startup

The TPS65400-Q1 implements a soft-start function that minimizes discharge of the output when starting up in a

prebiased condition. Soft-start time, t_SS, is set by t_{ON_TRANSITION_RATE}(digital soft-start) or by a capacitor

connected to the corresponding SSx pin (analog soft-start). In this setup, the SSx pin sources a 5-µA current

charging the capacitor, and the voltage at the SSx pin limits the reference voltage at the input of the error

amplifier.

At the beginning of the soft-start, the soft-start input to the error amplifier is set to 0. The SSx input is raised

gradually and reaches its target value during the time t_ss. If V_FB> V_SS, then no switching occurs. After the Soft-

Start signal crosses VFB, the switching begins. The first switching pulse is on the low-side FET, which charges

the high-side bootstrap capacitor. The unit runs in discontinuous conduction mode (DCM) with the zero-cross

detector enabled on the low side (diode emulation). The high-side FET is pulsed according to the error amplifier

output on the COMP pin. If the IC is configured for continuous conduction mode (CCM) operation (default), the

low-side FET pulses gradually transition to normal CCM operation; at each successive switching cycle, the low-

side gate pulse is gradually ramped until full synchronous switching occurs. At this point, the switcher enters

normal CCM operation.

VREF

FB

SS

t_ss

HS_GATE

LS_GATE

Pulse extension into regular CCM operation

Initial bootstrap capacitor

charge pulse

Figure 9. Soft-Start Under Prebiased Condition and CCM Mode Programmed

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Feature Description (continued)

VREF

FB

SS

HS_GATE

LS_GATE

Initial Bootstrap capacitor

charge pulse

t_ss

Figure 10. Soft-Start Under Prebiased Condition and DCM Mode Programmed

8.3.3.1 Analog Soft-Start (Default) and Digital Soft-Start

The TPS65400-Q1 has the ability to use an analog-based soft-start ramp based on external capacitors (one input

for each switcher) or to use internal signals based on digital logics and DACs to perform the soft-start function.

When using external soft-start configuration (default configuration), the SSx pins are connected to the soft-start

input of the error amplifier.

When using the internal digital soft-start signal, the soft-start input to the error amplifier increases step-by-step at

a rate set according to the value set in TON_RAMP_RATE (see (DEh) TON_TRANSITION_RATE).

VREF

t_{ss_}

step

¨9_{ss_}

step

Soft-Start

Done

Figure 11. Internal Soft-Start Input to Error Amplifier When Digital Soft-Start is Selected

ΔVSS_step is 10 mV. Tss_step depends on the soft-start time option selected. See (DEh)

TON_TRANSITION_RATE for more details.

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Feature Description (continued)

8.3.3.2 Soft-Start Capacitor Selection

When using external soft-start capacitor to set the soft-start time, use Equation 2.

Css

t_ss

u Vref

Iss

(2)

Css is the value of the capacitor connected between the SSx pin and AGND. VREF is the value of the reference

voltage (default is 0.8 V). I_SSis the current sourced by the SS1/PG1 pin during soft-start.

8.3.4 PWM Switching Frequency Selection

The master clock frequency, F_OSC, can be set by external resistor on the RCLOCK_SYNC terminal, or by

synchronizing with an external clock. To set using an external resistor, use this formula.

F_SW(kHz) = 138664 R_OSC(kΩ)^–0.948

(3)

2500

2000

1500

1000

500

0

100

200

300

400

500

600

700

800

R _OSC(k:)

D003

Figure 12. Frequency vs R_osc

To sync to an external source, an AC-coupled signal should be applied to the terminal. A fixed resistor should

still be connected to set a minimum frequency. The frequency of the input signal to synchronize with should

always be higher than the minimum frequency. If the internal PLL cannot synchronize, the switchers will fall back

to the minimum frequency set by the resistor. The CLK_OUT terminal outputs the master clock F_OSC

.

The PWM frequency of each switcher is determined by this master clock frequency and an I²C-programmable

choice of 4 divider ratios (1, 2, 4, or 8) by setting CLK_DIV (see (D7h) FREQUENCY_PHASE).

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Feature Description (continued)

CLK_OUT

SW1

CLK_DIV

SW1

DELAY_SELECT

To clock input

V_{Freq_ref}

ROSC

4 × Master CLK

4

OSCILLATOR

/4

/1, 2, 4, 8

Delay

SW1 FREQ

RCLOCK_SYNC

Frequency

Modulator

SW2

DELAY_SELECT

CLK_DIV

Delay

SW2 FREQ

SW3

CLK_DIV

DELAY_SELECT

Delay

SW3 FREQ

SW4

DELAY_SELECT

CLK_DIV

Delay

SW4 FREQ

A. The frequency modulator is used for external clock synchronization.

Figure 13. Diagram of PWM Clock Generation

The intent of the individual divider ratios is to allow users to set the frequency of each switcher independently.

For example, with a master clock F_OSCof 1.1 MHz, SW1 and SW2 have a divider ratio of 4 for a 275-kHz PWM,

and SW3 and SW4 have a divider ratio of 1 for a PWM frequency of 1.1 MHz. Select the divider ratio so that the

PWM frequency stays within the range of 275 kHz to 2.2 MHz for whichever master clock frequency is set.

In addition to selecting the frequency, each switcher can have its PWM frequency delayed. This enables the

designer to minimize ripple current by properly selecting the delays so that the switching frequencies are out of

phase. The default switching frequency is at CLK_DIV = F_OSC/ 1 with PHASE_DELAY for SW1 at 0˚, SW2 at

180˚, SW3 at 90˚, and SW4 at 270˚. More information on frequency selection and delay is given in (D7h)

FREQUENCY_PHASE.

8.3.5 Clock Synchronization

The RCLOCK_SYNC terminal can be used to synchronize the master clock switching frequency, F_OSC, with an

external clock source or another TPS65400-Q1. The external clock signal (which can come from another

TPS65400-Q1 CLK_OUT terminal) should be AC coupled to the RCLOCK_SYNC terminal as shown in

Figure 14. Choose the ROSC value so that the fixed frequency is nominally 30% lower than the external

synchronizing clock frequency. An internal protection diode clamps the low level of the synchronizing signal to

approximately –0.5 V. The internal clock synchronizes to the rising edge of the external clock.

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Feature Description (continued)

C_CLK

To RCLOCK_SYNC

R_OSC

AGND

Figure 14. AC-Coupled Clock Synchronization

TI recommends to choose an AC-coupling capacitance in the range of 50 to 100 pF. Exceeding the

recommended capacitance may inject excessive energy through the internal clamping diode structure present on

the RCLOCK_SYNC terminal. The typical trip level of the synchronization terminal is 1.5 V. To ensure proper

synchronization and to avoid damaging the IC, the peak-to-peak value (amplitude) should be between 2.5 V and

V_DDA. The minimum duration of this pulse must be greater than 200 ns, and its maximum duration must be 200

ns less than the period of the switching cycle.

The external clock synchronization process begins after the TPS65400-Q1 is enabled and an external clock

signal is detected. The frequency modulator adjusts the oscillator frequency to match the frequency of the pulses

into the RCLOCK_SYNC terminal. It generally takes 50 cycles before the PWM frequency locks. If the external

clock signal is removed after frequency synchronization, the master clock F_OSCdrifts to the frequency selected by

ROSC.

8.3.6 Phase Interleaving

The TPS65400-Q1 offers the ability to output rails of higher currents by connecting SW1 and SW2 in parallel, or

by connecting SW3 and SW4 in parallel. To configure this option, the COMP2 or COMP4 terminal must be tied to

VDDA through a 4-kΩ resistor.

Upon the initialization sequence after a reset, the TPS65400-Q1 attempts to discharge the COMP terminal

through a 2-kΩ internal resistor. When it detects that the COMP terminal is pulled high, it configures itself to

operate in current sharing mode. If SW2 is set to current sharing mode, its PWM output is controlled by the error

amplifier and COMP1 terminal of SW1 and set to the same frequency as SW1. Likewise, if SW4 is set to current

sharing mode, its PWM output is controlled by the error amplifier and COMP3 terminal of SW3 and set to the

same frequency as SW3. This means that the frequency settings for SW2 and SW4 in the EEPROM are ignored

in that mode of operation.

When current sharing mode is detected on a particular pair, the output slave’s I²C access is invalid and the

output slave’s default settings follow that of its master (see (00h) PAGE). The only exception is that the slave

switcher PWM is a fixed 180° phase-shift from its master.

Table 1. Programmable Options When Current Sharing Enabled

Pair

Output

SW1

Current Sharing Relationship

Switching Frequency

Programmable

Switching Phase

Programmable

Master + 180°

Programmable

Master + 180°

Master

Slave

SW1-SW2

SW2

Follows master

Programmable

SW3

Master

Slave

SW3-SW4

SW4

Follows master

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8.3.7 Fault Handling

OVP, OCP, and undervoltage protection (UVP) are handled for each switcher independently. OVP or OCP faults

that occur on one switcher do not affect the other outputs. There are two exceptions:

•

If current-sharing mode (ISHARE) is detected for a switcher that faults, both switchers in parallel have the

same response to OVP or OCP.

•

When using internal sequencing, in the case of faults occurring during the initial power-up sequence, all

switchers are disabled for 500 ms, after which, the startup sequence is restarted.

During the soft-start time for a switcher, all fault signals (OVP, OCP, and UVP) are disabled and reset to the

unfaulted condition. The first moment when faults can be triggered is after the end of the soft-start sequence.

OVP thresholds are set as a percentage of VREF. A deglitching time of 50 μs is used for the overvoltage. When

an overvoltage occurs at the OVP upper threshold limit, the high-side FET and the low-side FET are disabled for

that switcher until the OVP falling threshold is reached. When the OVP falling threshold is reached, the low-side

FET turns on for 200 ns to ensure that the bootstrap capacitor is recharged before resuming normal operation of

the converter.

Output voltage falling below the UVP thresholds causes the corresponding PGOOD output to fall, but the

switcher continues to operate as it tries to increase the output voltage. However, if the PGOOD terminal is tied to

the enable ENSWx signal of another switcher on the PCB (for external sequencing), the output for that ENSWx-

PGOOD-tied switcher is disabled until output voltage is nominal and PGOOD is good.

OTP shuts down all switchers. When the temperature drops below the hysteresis level, a soft reset is triggered

and the chip restarts from the startup sequence.

Fault Monitoring describes fault reporting and clearing of fault status registers.

The OVP and UVP sensing is deglitched to prevent unwanted tripping. The faults need to be sustained for more

than 55 μs typically (60 μs max) to be registered and trigger protection circuits and PGOOD output to fall. Fault

detection is disabled on a given switcher when its VREF is being ramped (as result of an I²C command to

change VREF). An additional 100-μs fault blanking time results after VREF has been adjusted to its target level.

8.3.8 OCP for SW1 to SW4

The OCP is I²C-programmable and set by the IOUT_MAX command. By default, the peak current IOUT_MAX for

SW1 and SW2 is 6 A, and for SW3 and SW4 it is 3 A. When the current reaches this threshold, the unit

immediately turns off the high-side FET and keeps the low-side FET off for the remainder of the switching cycle.

The following cycle are skipped (high-side FET off, low-side FET off) regardless of the inductor current. If the

current in the inductor is still higher than the IOUT_MAX after the skipped cycle, the following cycles are also

skipped until the current reach below the IOUT_MAX.

If the IOUT_MAX is reached more than 256 active cycles continuously, the switcher shut downs for 20 ms and

restarts. If the switcher is running in interleaved operation, both the switcher that tripped the IOUT_MAX

threshold and its interleaved counterpart shut down for 20 ms. After that period of time, the unit restarts and goes

through soft-start operation. For very-low duty cycle operation and faulty operation with very-fast current increase

during the high-side FET on-time (due to inductor saturation and so forth), OCP is also enforced on the low side

to ensure no runaway condition exists.

Table 2. Current Limit

Options

SWITCHER

IOUT_MAX

2 A

3 A

SW1, SW2

4 A

5 A

6 A (default)

0.5 A

1 A

SW3, SW4

2 A

3 A (default)

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While the converter is shut down following an OCP event spanning more than 256 cycles, the COMP terminal is

pulled low for 1.1 ms prior to precharge and re-enabling of the converter. At the same time, the SSx pin is

discharged to AGND for 1.1 ms. If the soft-start is digital (SSx pins used as PGOODx outputs), the soft-start

value is reset.

First OCP detect

256^thconsecutive OCP detect

A

OCP Limit

t

Figure 15. Inductor Current During Overcurrent Event

At high switching frequency (>1 MHz) and particularly when there is a fault in the converter such as saturation of

the inductor, the current sensor might not sense the overcurrent event. To ensure that current protection is

provided in all operating scenarios, low-side current sensing is also present to provide overcurrent detection and

protection when the low-side FET is on. If over-current is detected when the low-side FET is on, the low-side

FET stays on (and the high-side FET off) until the current drops below the threshold. A new cycle will then begin

(high side on, low side off) when the next switching cycle occurs as driven by the internal clock derived from the

oscillator (internal or external synchronization). A dedicated counter records the low-side OCP events and

initiates a shutdown of the converter after 256 OCP event counts. Six consecutive cycles without a low-side OCP

event resets the counter.

A

Triggered Low Side OC

Low Side OCP Limit

t

Figure 16. Inductor Current During Overcurrent Event With Low-Side Detection

8.3.9 Overcurrent Protection for SW1 to SW4 in Current Sharing Operation

When the converter is running in interleaved operation, an OCP event will not trigger the COMP terminal to be

pulled low to 0.6 V. Instead, the error amplifier is switched off (tri-stated). This ensures that the COMP terminal

voltage remains constant so that the other phase continues to operate during the OCP event. An OCP event on

one switcher lasting more than 256 cycles triggers the shutdown of both switchers running in interleaved mode.

8.3.10 Recovery on Power Loss

All contents of the registers are saved and stored in the data store (non-volatile memory) with the exceptions

listed in Table 4 (Supported PMBus Commands) when STORE_DEFAULT_ALL is issued. Contents of the

registers are copied from the data store when power is restored. This allows the system processor to turn on the

power supplies as needed with the same default settings before power was lost.

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8.3.11 Feedback Compensation

Current Sense

and Peak

Current Control

Gmps = 10 A/V (default)

VOUT

IL

RFB1

RLoad

C1

R_ESR

FB

COMP

EA

VREF

+

RFB2

Rc

Gm = 120 µA/V

C_Roll

Co

Cc

Figure 17. Simplified Equivalent Feedback Compensation Network

A typical compensation circuit could be type II (R_Cand C_C) to have a phase margin between 60° and 90°, or type

III (R_C, C_C, and C_ff) to improve the converter transient response. C_Rolladds a high-frequency pole to attenuate

high-frequency noise when needed. C_Rollshould be set to at least twice the crossover frequency to avoid

interacting with the feedback compensation. It may also prevent noise coupling from other rails if there is

possibility of cross coupling in between rails when layout is very compact.

Table 3 shows the recommended values for the compensation network components as an initial start. These

result in the compensating zero of the Type II to match the dominant pole of the converter.

Table 3. Compensation Calculation Table

TYPE II

TYPE III

F_SW

Select cross over frequency to be less than 1/5 of

switching frequency (typical is 1/10)

F_C

10

2SuF_Cu V_OUTuC_O

GmuGm_PSu VREF

2SuF_CuC_O

GmuGm_PS

R_C

Set R_C

Set C_C

R_LOADuC_O

C_C

R_C

R_esruC_o

Add C_Rollif needed to remove large signal coupling to

high impedance COMP node.

C_Roll

R_C

1

C_ffcompensating capacitor for type III compensation

network. Choose ƒz_ffsame as F_C.

C_ff

N/A

2Su fz_ffuR_FB1

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8.3.12 Adjusting Output Voltage

The output voltage of each buck is set with a resistor divider from BUCK output to FB pin and ground. TI

recommends to use a 1% tolerance resistor or better one to get higher output voltage accuracy.

Vout

Vref

RFB1

EA

±

FB Pin

RFB2

TPS65400

Figure 18.

With RFB1 and RFB2, output voltage is determined by:

RFB1

RFB2

§

·

Vout Vref u 1 ꢀ

¨

¸

¹

©

(4)

Default Vref in TPS65400-Q1 is 0.8 V. It can be programed from 0.6 to 1.87 V by digital interface PMBus. See

(D8h) VREF_COMMAND for more detailed information.

8.3.13 Digital Interface – PMBus

TPS65400-Q1 implements a PMBus-compatible I²C digital interface. The PMBus specification referenced by this

section is PMBus Power System Management Protocol Specification Part I – General Requirements, Transport

and Electrical Interface, Revision 1.2, dated 6 September 2010. The specification is published by the Power

Management Bus Implementers Forum and is available from http://pmbus.org/Specifications. See details in

PMBus and Register Maps.

8.3.14 Initial Configuration

The recommended method of configuring the TPS65400-Q1 the first time is through an external programmer

through a separate I²C programming header (as shown in Figure 19). The programming header needs to

connect to the SCL, SDA, CE, VDDD, and DGND lines, and can be done using a USB-to-I²C tool. This enables

the user to tailor the settings of the TPS65400-Q1 for each PCB specifically after PCB assembly, before the first

power-up of the board.

An alternative method is to use the firmware in an on-board microcontroller to do the initial configuration. To do

this, the user has two options:

•

Power the microcontroller and the TPS65400-Q1 (VDDD, CE, and DGND connections needed) from an

external source not controlled by the TPS65400-Q1.

•

Design the PCB so that the default settings of the TPS65400-Q1 allow the microcontroller to be powered

when power is applied to the TPS65400-Q1 the first time. The designer also needs to ensure that the default

power-up sequence, ramp-rates, and other default parameters do not damage any components when power

is applied the first time. After configuration, the microcontroller should pull CE low, and then all future power-

ups result in the newly configured power-up scheme to occur.

Using either method for the microcontroller requires the firmware to check if the TPS65400-Q1 has been

previously configured, or if a modification needs to be made to an already programmed configuration. Users may

use USER_DATA_BYTE_00 and/or USER_DATA_BYTE_01 to store a version number to identify which version

of the configuration is stored in the TPS65400-Q1.

A hybrid option may also be done where the initial configuration is done using an external programmer, and the

subsequent revisions are done through the microcontroller firmware. This eliminates the risk from damage

caused by the default configuration during the first power-up, but still allows the microcontroller firmware to

modify settings such as the VREF settings for subsequent power-ups.

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User-Issued ON

OPERATION

User-Issued Soft-OFF

PAGE = 0xFF

VOUT1

VOUT2

VOUT3

VOUT4

1

2

5

3

4

PGOOD1

PGOOD2

PGOOD3

PGOOD4

8

7

6

t

1. SW1 TON_DELAY

2. SW2 TON_DELAY

3. SW3 TON_DELAY

4. SW4 TON_DELAY

5. SW4 TOFF_DELAY

6. SW3 TOFF_DELAY

7. SW2 TOFF_DELAY

8. SW1 TOFF_DELAY

A. Configuration:

1. Enable pins ENSWx set to inactive in PIN_CONFIG_00

2. Start sequence order SW1-SW2-SW3-SW4 in SEQUENCE_ORDER

3. Stop sequence order SW4-SW3-SW2-SW1 in SEQUENCE_ORDER

Figure 19. Example of Internal On Sequencing and Off Sequencing With the Default START_PGOOD

Dependence

OPERATION (SWx) refers to OPERATION register in the corresponding PMBus PAGE. See (01h) OPERATION

for more information on the OPERATION register.

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ENSW1

ENSW2

ENSW3

ENSW4

PVIN1

CB1

12 V

VOUT1

SW1

VDDD

PGOOD1

PGOOD2

PGOOD3

PGOOD4

SS1/PG1

SS2/PG2

SS3/PG3

SS4/PG4

PGND1

VFB1

VDDD

PVIN2

CB2

12 V

VDDD

VOUT2

VDDD

SW2

PGOOD(Global)

PGOOD

Host

(Optional)

VDDD

PGND2

VFB2

SDA

SCL

TPS65400-Q1

VDDD

PVIN3

CB3

12 V

I2CALERT

I2CADDR

VOUT3

RCLOCK_SYNC

SW3

CLK_OUT

RST_N

CE

PGND (Thermal Pad)

VFB3

VDDD

12 V

PVIN4

CB4

12 V

VIN

VDDD

VDDA

VDDG

AGND

SW4

PGND (Thermal Pad)

VFB4

COMP3

COMP4

COMP1

COMP2

Figure 20. Internal Sequencing Schematic With Host

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ENSW1

ENSW2

ENSW3

ENSW4

PVIN1

CB1

VIN1

VOUT1

SW1

SS1/PG1

SS2/PG2

SS3/PG3

SS4/PG4

PGND1

VFB1

PVIN2

CB2

VIN2

VOUT2

SW2

PGOOD

VDDD

PGND2

VFB2

SDA

SCL

Programmer

TPS65400-Q1

PVIN3

CB3

VIN3

I2CALERT

I2CADDR

VOUT3

RCLOCK_SYNC

SW3

CLK_OUT

RST_N

CE

PGND (Thermal Pad)

VFB3

VDDD

VIN

PVIN4

CB4

VIN

VDDD

VDDA

VDDG

AGND

SW4

PGND (Thermal Pad)

VFB4

COMP3

COMP4

COMP1

COMP2

Figure 21. Internal Sequencing Schematic Without Host

8.4 Device Functional Modes

8.4.1 CCM Operation Mode

When the VIN/PVINx are above UVLO threshold and ENSWx are above the threshold, all four switchers operate

in continuous current mode(CCM) with IOUT_MODE(see (D6h) IOUT_MODE) setting default. In CCM, the

converters work in peak current mode for easy loop compensation and cycle-by-cycle high side MOSFET current

limit.

8.4.2 CCM/DCM Operation Mode

When DCM mode is enabled by setting IOUT_MODE (see (D6h) IOUT_MODE), the switchers transition to DCM

operation at light loads. During DCM mode, the low-side FET is turned off to prevent negative inductor current.

This increases light-load efficiency, but output ripple and transient response during DCM or during transitions

between DCM and CCM mode can be degraded.

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Device Functional Modes (continued)

At light load, the COMP terminal is driven by the error amplifier to the minimum clamp voltage. When the COMP

voltage reaches below 0.6 V and the error amplifier is sinking more than 5 μA, both the high-side and low-side

FET will be tri-stated to prevent the output voltage from rising above the set value. The FET function is re-

enabled when the GM amplifier sinks less than 3 μA. This results in a burst mode operation at light load. The

low-side FET has a 200-ns one-shot ON-time to ensure that the bootstrap capacitor is charged before the normal

function of the converter is resumed.

8.4.3 Current Sharing Mode

When SW1/SW2 pair output and/or SW3/SW4 pair output are shared, the responding pairs current sharing mode

is enabled and the ENABLE_PIN_CONFIG is set to single ENABLE. For the detail configuration, see Current

Sharing Typical Application .

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8.5.1 PMBus

8.5.1.1 Overview

The TPS65400-Q1 implements a lightweight PMBus-compliant layer supporting packet error checking, high-

speed bus, and group commands.

8.5.1.2 PMBus Protocol

The PMBus specification follows SMBus version 2.0. Figure 22 through Figure 29 show all supported command

transactions.

8.5.1.2.1 PMBus Protocol

Figure 22. Send Byte Protocol With PEC

1

7

1

8

1

8

1

Start

Slave

address

Wr

Ack

Command

code

Ack

PEC

Ack

Stop

Figure 23. Write Byte Protocol With PEC

1

7

1

8

1

8

1

8

1

Start

Slave

address

Wr

Ack

Command

code

Ack

Data byte

Ack

PEC

Ack

Stop

Figure 24. Read Byte Protocol With PEC

1

7

1

8

1

Start

Slave address

Wr

Ack

Command code

Ack

Restart

7

1

8

1

8

1

Slave address

Rd

Ack

Data byte

Ack

PEC

Nack

Stop

Figure 25. Read Word Protocol With PEC

1

7

1

8

1

7

1

Rd

1

Start

Slave

address

Wr

Ack

Command

code

Ack

Restart

Slave

address

Ack

8

1

8

1

8

1

Data word (low)

Ack

Data word (high)

Ack

PEC

Nack

Stop

8.5.1.2.2 Transactions (No PEC)

Figure 26. Send Byte Protocol

1

7

1

8

1

Start

Slave address

Wr

Ack

Command code

Ack

Stop

Figure 27. Write Byte Protocol

1

7

1

8

1

8

1

Start

Slave

address

Wr

Ack

Command

code

Ack

Data byte

Ack

Stop

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Figure 28. Read Byte Protocol

1

7

1

8

1

Start

Slave address

Wr

Ack

Command code

Ack

Restart

7

1

8

1

Slave address

Rd

Ack

Data byte

Nack

Stop

Figure 29. Read Word Protocol

1

7

1

8

1

8

7

1

Start

Slave

address

Wr

Ack

Command

code

Ack

Restart

Slave

address

Rd

Ack

8

1

8

1

Data word (low)

Ack

Data word (high)

Nack

Stop

8.5.1.2.3 Addressing

The 7-bit I²C address is set through the I2CADDR terminal with a resistor RADDR connected to AGND. Table 6

shows the connection between the voltage at the I2CADDR terminal and the set I²C address at V_DDD= 3 V. The

I²C address is determined only upon startup during t_{RESET_DELAY}after rising edge of CE or RST_N. This makes it

immune to noise that may occur during normal operation. TI recommends resistors with 5% or lower tolerance. If

I²C is not necessary in the application, TI recommends to tie the I2CADDR terminal directly to VDDD.

Table 6. I²C Address Selection

R_ADDR

180 kΩ

120 kΩ

82 kΩ

56 kΩ

39 kΩ

22 kΩ

10 kΩ

2 kΩ

7-bit Address

1101 111

1101 110

1101 101

1101 100

1101 011

1101 010

1101 001

Test mode (factory-use only)

8.5.1.2.4 Startup

After CE is asserted and V_DDDhas reached 3.3 V, there is approximately a 320 μs delay before the PMBus

interface is active. During this time the TPS65400-Q1 is restoring its configuration from the EEPROM.

8.5.1.2.5 Bus Speed

100- and 400-kHz bus speeds are supported.

8.5.1.2.6 I2CALERT Terminal

When a timeout condition occurs, the I2CALERT terminal is pulsed low for 200 μs. A timeout condition is defined

as per SMBUS 2.0, t_TIMEOUT. In addition to SCL, a timeout condition also occurs when the SDA line is asserted

low. If the timeout condition persists, I2CALERT continues to pulse every t_TIMEOUT. The TPS65400-Q1 never

intentionally pulls the SCL low beyond t_LOW:SEXT⁽¹⁾, as that violates timing specifications. Therefore, the

I2CALERT terminal acts as a watchdog for other devices sharing the same bus that violate the cumulative clock

low extend time. On a system level, it can be seen as a non-maskable interrupt (NMI) signal for the I²C bus.

(1) t_LOW:SEXT: Cumulative clock low extend time (slave device). See more details on SMBus specification http://smbus.org/specs/.

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Table 7. Timeout Specifications

PARAMETER

Detect clock low timeout

Detect data low timeout

MIN

25

MAX

35

UNIT

ms

t_TIMEOUT:SCL

t_TIMEOUT:SDA

25

35

ms

8.5.1.2.7 CONTROL Terminal

The TPS65400-Q1 enable terminals ENSWx are equivalent to the CONTROL terminals in the fault handling. The

enable terminals behave as follows:

•

Unit does not power up until commanded by the enable terminal and OPERATION command. By default, the

OPERATION command is ON, so the powering up of the unit depends on the enable terminal state.

•

To start, the unit requires that the on/off portion of the OPERATION command is instructing the unit to run.

Depending on PIN_CONFIG_00, the unit may also require the enable terminal to be asserted for the unit to

start and energize the output.

•

Polarity of the enable terminal is active high. If unconnected, the terminal goes high.

When commanding the unit to turn on or off through the enable terminals, the programmed turn on delays,

turn off delays are always observed.

There are differences in enable terminal functionality depending on terminal configuration PIN_CONFIG_00. For

more information, refer to OPERATION and PIN_CONFIG_00.

8.5.1.2.8 Packet Error Checking

The TPS65400-Q1 supports an optional PEC code to be validated at the end of every write and to be appended

to the end of every read. TI highly recommends it, but it is not required.

8.5.1.2.9 Group Commands

Fully-compliant group commands are supported.

8.5.1.2.10 Unsupported Features

All undocumented, optional features are not supported. Extended commands are not supported.

8.5.2 PMBus Register Descriptions

The PMBus specification referenced by this section is PMBus Power System Management Protocol Specification

Part II – Command Language, Revision 1.2, dated 6 September 2010. The specification is published by the

Power Management Bus Implementers Forum and is available from http://pmbus.org/specifications.

8.5.2.1 Overview

The following parameters can be programmed and read. These are individually available for each power supply

output (SW1-SW4):

•

Voltage reference

Start sequencing

Stop sequencing

Switching frequency

Switching phase

Soft-start time

Current limit

Current sharing operation with SW1-SW2 and/or SW3-SW4 pairs

Power Good

Fault status

Each power supply has its own set of PMBus commands. Paging is supported to allow device selection for a

PMBus session ((00h) PAGE). Table 4 lists supported PMBus commands and paging values.

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8.5.2.2 Memory Model

Supported PMBus Commands describes the memory model for PMBus devices. Values used by the PMBus

device are loaded into volatile operating memory from the following places:

•

Values hard-coded into an IC design

Values programmed from hardware terminals

A non-volatile memory called the default store

Communications from the PMBus

On-board data flash memory is used to implement the hard-coded values and the default store values. Values in

the default store may be changed using the STORE_DEFAULT_ALL command described in (11h)

STORE_DEFAULT_ALL. The user store is not supported. Table 4 describes the ordering of memory loading and

precedence. In general, the hard-coded parameters are loaded into operating memory first. Second, any

terminal-programmable settings take effect. Third, values from the default store are loaded. Later, commands

issued from the PMBus take effect. In all cases, an operation on a parameter overwrites any prior value that was

already in the operating memory.

Power

Up

Idle

Reset

Communications

from PMBUS

Real-Time Changes

Hard-Coded Values

Read-Only Register

Bits

Store Supported

Registers to Default

Store

User Issues

STORE_DEFAULT_ALL?

Yes

Hardware Pins

Pin Configuration and

Electrical States

No

Non-Volatile Memory

Default Store

User Issues

SOFT_RESET?

Yes

(EEPROM)

No

Figure 30. Memory Model

8.5.2.3 Data Formats

Data is sent as a byte, an 8-bit binary value, a word, a 16-bit binary value, or a block of bytes whose length is

specified by a length byte.

8.5.2.4 Fault Monitoring

Registers (78h) STATUS_BYTE, (79h) STATUS_WORD, (7Ah) STATUS_VOUT of the PMBus specification

describe fault monitoring for PMBus devices. The TPS65400-Q1 only supports reporting faults. Fault conditions

are set in the corresponding status register and the host or power system manager can poll it. Any bits set in the

status register remain set even if the fault condition is removed or corrected. The fault bits in the status register

remain set until one of the following occur:

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•

The device receives a CLEAR_FAULTS command.

A RESET signal is asserted by either issuing a SOFT_RESET or by asserting/deasserting the CE terminal.

Bias power is removed from the PMBus device.

Fault Handling describes fault thresholds and specific response behaviors.

8.5.3 PMBus Core Commands

These PMBus core commands are defined in the PMBus Specification. This section describes details that are

unique to the TPS65400-Q1 implementation.

8.5.3.1 (00h) PAGE

The PAGE command provides the ability to configure, control, and monitor multiple outputs on a single

TPS65400-Q1 using a single PMBus physical address. All subsequent commands that depend on PAGE are

applied to the rail selected by the PAGE command.

Rails are numbered starting with one, while pages are numbered starting at 0. Table 8 shows the relationship

between the PMBus PAGE value and the rail number.

Table 8. PAGE Data Byte Contents

CURRENT

SHARING

RELATIONSHIP

DEFAULT

VALUE

BITS

NAME

READ / WRITE

VALUE

OUTPUT RAIL

PAIRING

0x00

0x01

SW1

SW2

SW3

SW4

Invalid

All

Master

Slave

Master

Slave

—

SW1-SW2

SW3-SW4

0x02

7:0

PAGE

R/W

0xFF

0x03

0x04 to 0xFE

0xFF

—

On the TPS65400-Q1, current share is organized in pairs (PAGE = 0x00, 0x01 and PAGE = 0x02, 0x03). When

current sharing mode is detected on a particular pair, the slave PAGE is invalid and the slave’s default settings

follow that of its master PAGE. The only exception is that the slave switcher PWM will be a fixed 180° phase-shift

from its master (see (D7h) FREQUENCY_PHASE). Additionally, the ISHARE bit will be asserted (see (D6h)

IOUT_MODE).

(00h) PAGE of the register map describes the PAGE command in more detail.

NOTE

The PAGE parameter is not stored in the default store in data flash.

8.5.3.2 (01h) OPERATION

The OPERATION command in conjunction with input from the enable pins ENSWx is used to turn on or off

(enable or disable) the currently selected switching regulator as determined by the current PAGE. Margins are

not supported. Data byte contents are given in Table 9.

Table 9. Operation Data Byte Contents

PAGE SUPPORT

BITS [7:6]

BITS [5:4]

BITS [3:2]

BITS [1:0]

SEQUENCIN OUTPUT ON OR OFF

G

DELAY

0x00 to 0x03,

0xFF

00

XX

No

Immediate off

None

0x00 to 0x03

0xFF

01

10

XX

00

XX

No

Yes

No

Soft off

t_{OFF_DELAY}

t_{ON_DELAY}

0x00 to 0x03

On with soft-start

(default)

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Table 9. Operation Data Byte Contents (continued)

PAGE SUPPORT

BITS [7:6]

BITS [5:4]

BITS [3:2]

BITS [1:0]

SEQUENCIN OUTPUT ON OR OFF

G

DELAY

0xFF

10

00

XX

Yes

On with soft-start

(default⁽¹⁾

t_{ON_DELAY}

)

(1) This is also the default behavior upon reset with active ENABLE selected (see (D2h) PIN_CONFIG_00)

Input from the enable pin overrides the off state of the corresponding output. The pin function configuration

command PIN_CONFIG_00 can accept or ignore enable pins as well as disable OPERATION sequencing

command support (see (01h) OPERATION). If the OPERATION state is on, and PIN_CONFIG_00 is set to

accept enable pins, action from enable pins would result in a delay specified by TON_TOFF_DELAY. Figure 31

shows how the on/off states are triggered.

Immediate OFF

OPERATION [7:4]

Soft OFF or ON

PIN_CONFIG_00

and

ON/OFF

Delay

Block

OPERATION

Logic

PIN_CONFIG_00 [1:0]

Fault

Logic

ENABLE Pin

Figure 31. On/Off Configuration (Per Output)

When a fault occurs, the output state will turn OFF and possibly attempt to turn ON repeatedly for persistent

faults. Specific fault response behaviors are described in Fault Handling.

NOTE

TI recommends that if OPERATION is to be used exclusively, all outputs should be set to

the same order and enable pins should be ignored (see (D5h) SEQUENCE_ORDER, and

(D2h) PIN_CONFIG_00).

The OPERATION parameter is not stored in the default store in data flash.

8.5.3.3 (03h) CLEAR_FAULTS

The CLEAR_FAULTS command clears all faults for the selected output. If PAGE 0xFF is selected, all faults for

all PAGE outputs are cleared.

NOTE

POWER_GOOD_N and OFF indicate the current state of the outputs and cannot be

cleared.

8.5.3.4 (10h) WRITE_PROTECT

The WRITE_PROTECT command disables writes on the PMBus. It has one data byte, described in Table 10.

Table 10. WRITE_PROTECT Command Data Byte Contents

DATA BYTE VALUE

MEANING

1000 0000

Disable all writes except to the WRITE_PROTECT command

0100 0000

(default)

Disable all writes except to the WRITE_PROTECT, OPERATION, and PAGE commands

0010 0000

Disable all writes except to the WRITE_PROTECT, OPERATION, PAGE, and VREF_COMMAND commands

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Table 10. WRITE_PROTECT Command Data Byte Contents (continued)

DATA BYTE VALUE

0000 0000

MEANING

Enable writes to all commands

If an invalid command is received, a communications fault is set. WRITE_PROTECT does not protect against

CLEAR_FAULTS. The user is able to CLEAR_FAULTS anytime regardless of the WRITE_PROTECT state.

This command has no PAGE support.

NOTE

The WRITE_PROTECT parameter is not stored in the default store in data flash.

8.5.3.5 (11h) STORE_DEFAULT_ALL

The STORE_DEFAULT_ALL command saves the PMBus parameters from operating memory into the default

store in data flash (EEPROM). The TPS65400-Q1 uses the most recently written set of default store values at

startup. The maximum time it takes for the data flash to be written is 70 ms.

This command has no PAGE support.

NOTE

The OPERATION, PAGE, and WRITE_PROTECT parameters are not stored in the default

store in data flash.

CAUTION

When STORE_DEFAULT_ALL is issued, operating memory should not be written to

during the save.

8.5.3.6 (19h) CAPABILITY

The CAPABILITY command is a read-only command.

This command has no PAGE support.

Table 11. CAPABILITY COMMAND Data Byte Contents

BIT

7

READ / WRITE

DEFAULT VALUE

MEANING

R

1

Packet error checking is supported

6:5

01

Maximum supported bus speed is 400 kHz

Device does not have a SMBALERT pin and does not support the SMBus alert

response protocol

4

R

0

3:0

0000

Reserved

8.5.3.7 (78h) STATUS_BYTE

The STATUS_BYTE command is a read-only command. Write mask is not supported. The bits are listed in

Table 12.

Table 12. STATUS_BYTE Data Byte Contents

PAGE SUPPORT

DEFAULT

VALUE

BIT

NAME

READ / WRITE

MEANING

—

7

6

5

4

Not supported

OFF

R

0

—

Yes

—

Output is off

VOUT_OV

IOUT_OC

Output overvoltage fault

Output overcurrent fault

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Table 12. STATUS_BYTE Data Byte Contents (continued)

PAGE SUPPORT

DEFAULT

VALUE

BIT

NAME

READ / WRITE

MEANING

No

—

2

3

1

TEMPERATURE

Not supported

CML

R

—

0

Overtemperature fault

—

No

—

Invalid command code, data, or packet

NONE OF THE

ABOVE

A fault or warning not listed in bits [7:1] has

occurred

Yes

0

R

—

Overtemperature fault and CML is independent of PAGE. When there is PAGE support, the meaning of the bits

applies only for the selected output PAGE. For PAGE = 0xFF, STATUS_BYTE is a logical OR of all PAGE =

0x00 to 0x03 STATUS_BYTE values.

An exception to NONE OF THE ABOVE is that the MFR bit in STATUS_WORD is ignored due to no PAGE

support.

PAGE support is for outputs 0x00 to 0x03, 0x0FF.

8.5.3.8 (79h) STATUS_WORD

The STATUS_WORD command is a read-only command. Write mask is not supported. Only the parameters in

Table 13 are supported.

Table 13. STATUS_WORD Data Word Contents (Upper Byte)

PAGE SUPPORT

BIT

NAME

READ / WRITE

DEFAULT

VALUE

MEANING

Output voltage fault set if any bit in

STATUS_VOUT is asserted (for the same page)

Yes

7

VOUT

R

—

6

5

Not supported

R

0

—

Set if any bit in STATUS_MFR_SPECIFIC is

asserted

No

4

MFR

R

—

Yes

—

3

2

1

0

POWER_GOOD_N

Not supported

R

—

0

Output voltage is within PGOOD range, negated

—

0

—

0

The lower byte of STATUS_WORD is STATUS_BYTE.

The MFR bit is independent of PAGE. When there is PAGE support, the meaning of the bits applies only for the

selected output PAGE. For PAGE = 0xFF, STATUS_WORD is a logical OR of all PAGE = 0x00 to 0x03

STATUS_WORD values.

PAGE support is for outputs 0x00 to 0x03, 0x0FF.

8.5.3.9 (7Ah) STATUS_VOUT

The STATUS_VOUT command is a read-only command. Write mask is not supported. Only the parameters in

Table 14 are supported.

Table 14. STATUS_VOUT Data Byte Contents

BIT

7

NAME

READ / WRITE

DEFAULT VALUE

MEANING

VOUT_OV

R

—

0

VOUT overvoltage fault

6

Not supported

VOUT_UV

—

5

0

—

4

—

0

VOUT undervoltage fault

3

Not supported

—

2

0

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Table 14. STATUS_VOUT Data Byte Contents (continued)

BIT

1

NAME

Not supported

READ / WRITE

DEFAULT VALUE

MEANING

R

0

—

0

STATUS_VOUT shows the voltage output status for the PAGE selected output. For PAGE = 0xFF,

STATUS_VOUT is a logical OR of all PAGE = 0x00-0x03 STATUS_ VOUT values. VOUT_OV in

STATUS_VOUT is identical to VOUT_OV in STATUS_BYTE for the same PAGE.

PAGE support is for outputs 0x00 to 0x03, 0x0FF.

8.5.3.10 (80h) STATUS_MFR_SPECIFIC

The STATUS_MFR_SPECIFIC command is a read-only command. Write mask is not supported. Only the

parameters in Table 15 are supported.

Table 15. STATUS_MFR_SPECIFIC Data Byte Contents

BIT

NAME

Not supported

READ /

WRITE

DEFAULT

VALUE

MEANING

7

6

5

4

3

2

1

0

R

0

—

Not supported

0

Not supported

0

POWER_GOOD4_N

POWER_GOOD3_N

POWER_GOOD2_N

POWER_GOOD1_N

—

SW4 output voltage is within PGOOD range, negated

SW3 output voltage is within PGOOD range, negated

SW2 output voltage is within PGOOD range, negated

SW1 output voltage is within PGOOD range, negated

STATUS_MFR_SPECIFIC reports the individual output negated PGOODs. These bit values also can be

retrieved from POWER_GOOD_N if an individual output is selected through PAGE.

This command has no PAGE support.

8.5.3.11 (98h) PMBUS_REVISION

The PMBUS_REVISION command is a read-only command.

Table 16. PMBUS_REVISION Data Byte Contents

BITS

7:4

NAME

READ / WRITE

DEFAULT VALUE

MEANING

Part I revision

Part II revision

R

0010

Supports version 1.2

3:0

This command has no PAGE support.

8.5.3.12 (ADh) IC_DEVICE_ID

The IC_DEVICE_ID command is a read-only block command and returns the ASCII characters of the part

number TPS65400-Q1.

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Table 17. IC_DEVICE_ID Data Block Contents

BYTE

NAME

READ / WRITE

DEFAULT VALUE

ASCII VALUE

7

6

5

4

3

2

1

0

0x30

0x33

0x34

0x36

0x32

0x4D

0x4C

0x07

0

3

4

IC_DEVICE_ID

Length byte

R

6

2

M

L

—

This command has no PAGE support.

8.5.3.13 (AEh) IC_DEVICE_REV

The IC_DEVICE_REV command is a read-only block command and returns the 2-byte device code of the part.

The device code is identical to the 2-byte DEVICE_CODE. Refer to DEVICE_CODE for details (see (FCh)

DEVICE_CODE).

Table 18. IC_DEVICE_REV Data Block Contents

BYTE

2:1

NAME

READ / WRITE

DEFAULT VALUE

See DEVICE_CODE

0x02

DEVICE_CODE

Length byte

R

0

This command has no PAGE support.

8.5.4 Manufacturer-Specific Commands

8.5.4.1 (D0h) USER_DATA_BYTE_00

The USER_DATA_BYTE_00 command contains 8 bits for reading and writing user-defined data. Upon issuing

STORE_DEFAULT_ALL, contents of this command are saved to the default store in data flash.

Table 19. USER_DATA_BYTE_00 Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT VALUE

7:0

USER_DATA_BYTE_00

R/W

0x00

This command has no PAGE support.

8.5.4.2 (D1h) USER_DATA_BYTE_01

The USER_DATA_BYTE_01 command contains 7 bits, USER_DATA_BITS_01, for reading and writing user-

defined data. Upon issuing STORE_DEFAULT_ALL, contents of this command are saved to the default store in

data flash.

The most significant bit, STORED, is a read-only bit that indicates whether the user has written to the default

store through STORE_DEFAULT_ALL. This indicator bit cannot be cleared.

Table 20. USER_DATA_BYTE_01 Data Byte Contents

BITS

7

NAME

STORED

READ / WRITE

DEFAULT VALUE

R

0

6:0

USER_DATA_BYTE_01

R/W

0000000

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This command has no PAGE support.

8.5.4.3 (D2h) PIN_CONFIG_00

The PIN_CONFIG_00 command selects pin function and behavior for enable pins ENSWx and the global

PGOOD pin.

ENABLE_PIN_CONFIG selects between active ENABLE, inactive ENABLE, or single ENABLE behavior for

ENSWx pins.

•

When active ENABLE is selected, each pin in conjunction with OPERATION controls its respective switcher

on/off. For details, see (01h) OPERATION and (DDh) TON_TOFF_DELAY.

•

When inactive ENABLE is selected, the state of all ENSWx pins is ignored.

When single ENABLE is selected, ENSW1 pin acts as a sequence start and sequence stop pin, with all other

ENSWx pins ignored. This allows the device to emulate classic sequencing behavior. A start sequence

begins when ENSW1 is asserted, and a stop sequence begins when ENSW1 is deasserted. If ENSW1 were

to de-assert before a start sequence were complete, a stop-sequence would begin immediately.

PGOOD_PIN_CONFIG sets the function of the global PGOOD pin.

•

By default, the global PGOOD pin is configured to output a logical AND of each individual power supply’s

PGOOD. If all supplies were to turn off, the global PGOOD pin would be de-asserted.

•

The global PGOOD pin can be selected to output the status of any individual power supply’s PGOOD, or any

OR/AND combination thereof. If an individual supply’s PGOOD#_MASK bit is masked, its PGOOD status

would be masked from the global PGOOD pin. If all PGOOD#_MASK pins were masked, the output of the

global PGOOD pin would be at logic zero regardless of the PGOOD_LOGIC selected.

•

PGOOD#_MASK only applies to the output pin logic and does not affect STATUS_WORD or sequencing.

Table 21. PIN_CONFIG_00 Data Byte Contents

READ /

WRITE

DEFAULT

VALUE

BINARY

VALUE

BITS

NAME

MEANING

PINS AFFECTED

7

—

R

0

—

0

—

AND of all unmasked PGOODs

OR of all unmasked PGOODs

PGOOD4 is masked

PGOOD_PIN_CONFIG

: PGOOD_LOGIC

6

5

R/W

0

1

0

PGOOD_PIN_CONFIG

: PGOOD4_MASK

R/W

1

PGOOD4 is unmasked

PGOOD_PIN_CONFIG

: PGOOD3_MASK

0

PGOOD3 is masked

4

Global PGOOD pin

1

0

1

0

1

PGOOD3 is unmasked

PGOOD2 is masked

PGOOD2 is unmasked

PGOOD1 is masked

PGOOD1 is unmasked

PGOOD_PIN_CONFIG

: PGOOD2_MASK

3

2

R/W

1

PGOOD_PIN_CONFIG

: PGOOD1_MASK

Active ENABLE

00

01

Enable pins ENSWx control each

switcher independently

Inactive ENABLE

All enable pins ENSWx are

ignored

ENABLE_PIN_CONFI

G

1:0

R/W

00

ENSW# pins

Single ENABLE

ENSW1 starts and stops

sequencing. All other enable pins

are ignored.

1X

Table 22 shows example configurations for PGOOD_PIN_CONFIG.

Table 22. PGOOD_PIN_CONFIG Example Configurations

PGOOD_PIN_CONFIG BINARY VALUE

GLOBAL PGOOD PIN

01111 (default)

PGOOD1 and PGOOD2 and PGOOD3 and PGOOD4

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Table 22. PGOOD_PIN_CONFIG Example Configurations (continued)

PGOOD_PIN_CONFIG BINARY VALUE

GLOBAL PGOOD PIN

11111

00101

X0001

X0010

X0100

X1000

PGOOD1 or PGOOD2 or PGOOD3 or PGOOD4

PGOOD1 and PGOOD3

PGOOD1

PGOOD2

PGOOD3

PGOOD4

This command has no PAGE support.

CAUTION

Changing PIN_CONFIG_00 during normal operation has no effect. The configuration

can only be modified by storing into EEPROM and then reloading the configuration

upon reset.

8.5.4.4 (D3h) PIN_CONFIG_01

PIN_CONFIG_01 command selects pin function and behavior for the selected output’s SSx/PG pin.

SSPG_PIN_CONFIG sets the selected power supply’s SSx/PG pin to a soft-start time input pin or a power good

output pin.

•

When selected as soft-start time input pin SSx, the internal soft-start ramp rate TON_TRANSITION_RATE is

ignored. A 5-µA current source will be connected internally and an external capacitor can be used to set the

soft-start delay.

•

When selected as a power good output pin PG (PGOOD), the pin outputs the status of the selected power

supply’s power good.

Table 23. PIN_CONFIG_01 Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

MEANING

PINS AFFECTED

7:1

0

—

R

0000000

0

—

0

—

SSPG_PIN_CON

FIG

R/W

SSx pin

PG pin

SSx/PG pin

1

PAGE support is for outputs 0x00 through 0x03.

CAUTION

Changing PIN_CONFIG_01 during normal operation will have no effect. The

configuration can only be modified by storing into EEPROM and then reloading the

configuration upon reset.

8.5.4.5 (D4h) SEQUENCE_CONFIG

The SEQUENCE_CONFIG command determines sequencing behavior.

START_PGOOD determines whether the next output in sequence looks at the previous output’s PGOOD before

turning on. For turning on, the previous output’s PGOOD must be good. For the first in sequence, there is no

PGOOD reference so START_PGOOD for those particular switchers are ignored. START_PGOOD applies to all

switchers.

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Table 24. SEQUENCE_CONFIG Data Byte Contents

BITS

NAME

—

READ / WRITE

DEFAULT VALUE

BINARY VALUE

MEANING

—

7:1

0

R

0000000

0

—

0

START_PGOOD

R/W

PGOOD is checked

PGOOD is ignored

1

This command has no PAGE support.

CAUTION

TI does not recommend changing SEQUENCE_CONFIG during start sequencing or

stop sequencing.

8.5.4.6 (D5h) SEQUENCE_ORDER

The SEQUENCE_ORDER command determines the order in which each output starts and stops. If two or more

supplies are assigned the same sequence number, they start/stop at the same time. If sequencing is not used,

all sequence bits should be set to the same value. For PGOOD sequencing options, see (D4h)

SEQUENCE_CONFIG.

Table 25. SEQUENCE_ORDER Data Byte Contents

BITS

7:4

NAME

—

READ / WRITE

DEFAULT VALUE

BINARY VALUE

VALUE

MEANING

R

0000

00

—

00

01

10

11

00

01

10

11

—

3:2

STOP_ORDER

R/W

1 (first to stop)

Stop sequence

order number

2

3

4 (last to stop)

1:0

START_ORDER

R/W

00

1 (first to start)

Start sequence

order number

2

3

4 (last to start)

CAUTION

TI does not recommend changing SEQUENCE_ORDER during start sequencing or

stop sequencing.

PAGE support is for outputs 0x00 to 0x03.

8.5.4.7 (D6h) IOUT_MODE

The IOUT_MODE command configures the selected output to be:

•

Operating in CCM

Operating in Mixed CCM/DCM

There is a read-only bit, IOUT_SHARE, that indicates that the current selected output:

•

Shares its current

Does not share its current

On the TPS65400-Q1, current share is organized in pairs (PAGE = 0x00, 0x01 and PAGE = 0x02, 0x03). When

current sharing mode is detected on a particular pair, the slave PAGE is invalid and the slave’s default settings

follow that of its master PAGE. The only exception is that the slave switcher PWM is a fixed 180° phase-shift

from its master (see (D7h) FREQUENCY_PHASE).

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Table 26. IOUT_MODE Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT VALUE

BINARY VALUE

MEANING

7:2

—

R

000000

—

0

1⁽¹⁾

—

Current is not shared

Current is shared⁽¹⁾

Mixed CCM/DCM

CCM

1

0

IOUT_SHARE

CCM

R

—

1

0

R/W

1

(1) This bit is only observable from the master PAGEs (see (00h) PAGE).

PAGE support is for outputs 0x00 through 0x03.

CAUTION

Changing IOUT_MODE during normal operation has no effect. The configuration can

only be modified by storing into EEPROM and then reloading the configuration upon

reset.

8.5.4.8 (D7h) FREQUENCY_PHASE

The FREQUENCY_PHASE command sets the output switching frequency and phase of the selected output. The

switching frequency is a quotient from the division of the master clock, F_OSC, by the selected divisor CLK_DIV.

PHASE_DELAY determines the phase shift as a multiple of the internal PLL period, which is scaled at 4× less

than the master clock period 1 / F_OSC

.

Table 27. FREQUENCY_PHASE Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT VALUE BINARY VALUE

VALUE

—

MEANING

7

—

R

0

—

00000

00001

..

—

0

1 / (4 × FOSC)

..

Switching delay time

(phase)

6:2

1:0

PHASE_DELAY

CLK_DIV

R/W

See Table 28

11110

11111

00

30 / (4 × FOSC)

31 / (4 × FOSC)

FOSC / 1

FOSC / 2

FOSC / 4

FOSC / 8

01

00

Switching frequency

10

11

Table 28. PHASE_DELAY Default Data Bit Values

PAGE

0x00

0x01

0x02

0x03

PHASE_DELAY BINARY VALUE

PHASE SHIFT (°)

00000

00010

00001

00011

0

180

90

270

The phase shift in degrees is calculated by Equation 5.

PHASE_DELAY

Phase shift

(degrees)

2^{CLK _DIV}

(5)

When current sharing mode is detected on a particular pair, the slave PAGE is invalid and the slave’s default

settings follow that of its master PAGE. The only exception is that the slave switcher PWM is a fixed 180° phase-

shift from its master. Additionally, the ISHARE bit is asserted (see (D6h) IOUT_MODE).

PAGE support is for outputs 0x00 through 0x03.

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CAUTION

Changing the FREQUENCY_PHASE during normal operation has no effect. The

configuration can only be modified by storing into EEPROM and then reloading the

configuration upon reset.

8.5.4.9 (D8h) VREF_COMMAND

The VREF_COMMAND command sets the voltage reference (VREF) for the selected output. Values range from

0.6 to 1.87 V with a bit resolution of 10 mV per LSB.

Table 29. VREF_COMMAND Data Byte Contents

BITS

NAME

READ / WRITE DEFAULT VALUE

BINARY VALUE

—

VALUE

—

MEANING

7

—

R

0

—

0000000

0000001

…

0.60 V

0.61 V

…

6:0

VREF_COMMAND

R/W

0010100

…

0.8 V

…

Reference voltage

1111110

1111111

1.86 V

1.87 V

The voltage reference can be changed while one or more voltage outputs are enabled. To reduce the effect of

large transient steps, digital slew rate limiting is implemented. The larger the change in the voltage reference, the

greater the delay that is incurred as the voltage steps toward the new reference. For details, see (DFh)

VREF_TRANSITION_RATE.

Faults are blanked during transition. A 100-s fault blanking time results after a transition completes.

PAGE support is for outputs 0x00 through 0x03.

8.5.4.10 (D9h) IOUT_MAX

The IOUT_MAX command sets the current limit for the selected output.

Table 30. IOUT_MAX Data Byte Contents, PAGE = 0x00, 0x01

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7:3

—

R

00000

—

000

001

010

011

1XX

2 A

3 A

4 A

5 A

6 A

2:0

IOUT_MAX

R/W

100

Current limit

Table 31. IOUT_MAX Data Byte Contents, PAGE = 0x02, 0x03

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7:2

—

R

000000

11

—

00

01

10

11

—

0.5 A

1 A

—

1:0

IOUT_MAX

R/W

Current limit

2 A

3 A

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The limit set by the IOUT_MAX byte sets both the high-side and low-side current limit.

PAGE support is for outputs 0x00 through 0x03.

8.5.4.11 (DAh) USER_RAM_00

The USER_RAM_00 command is a reset notification status. Upon any RESET condition, the device clears this

value to 0x00. This value can only be set to 0x01 by the PMBus master.

Table 32. USER_RAM_00 Data Byte Contents

BITS

7:1

0

NAME

—

READ / WRITE

DEFAULT VALUE

R

0000000

0

USER_RAM_00

R/W

This command has no PAGE support.

8.5.4.12 (DBh) SOFT_RESET

The SOFT_RESET command triggers a software reset of the device. It is equivalent to sending an assert-

deasserting pulse to the CE pin. Consequently, all switchers turn off and all faults are cleared.

This command has no PAGE support.

8.5.4.13 (DCh) RESET_DELAY

The RESET_DELAY command sets the delay time before any switcher can begin its soft-start after CE is

asserted. Thus, if the turn-on sequence or an individual switcher is enabled before this delay is over, no action

occurs until the delay is completed. After this delay period is passed, enabling the turn-on sequence of an

individual switcher would have an immediate effect subject to the t_{ON_DELAY}and soft-start time.

Table 33. RESET_DELAY Data Byte Contents⁽¹⁾

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7:3

—

R

00000

—

000

001

010

011

100

101

110

111

1 ms⁽²⁾

50 ms

100 ms

250 ms

500 ms

1000 ms

1500 ms

2000 ms

2:0

RESET_DELAY

R/W

000

Reset delay time

(1) All the delay times are subject to the delay between the rising edge of CE and the stabilizing delay time of the VDDD supply, which can

be up to 1.1 ms, depending on the bypass capacitor sizing for these rails. The RESET_DELAY in the table is in addition to this power-up

delay and has an accuracy of ±62.5 μs.

(2) When setting the RESET_DELAY to 1 ms, TI recommends that the t_{ON_DELAY}for the outputs starting up first be greater than 5 ms.

Because, the COMP pin precharge starts at the same time as the RESET_DELAY. If RESET_DELAY is 1 ms, and t_{ON_DELAY}is 0 ms,

then the COMP pin precharge may not stabilize before the switcher soft-start begins. The time needed to stabilize the COMP pin

precharge depends on the RC compensation values connected to the COMP pin.

This command has no PAGE support.

8.5.4.14 (DDh) TON_TOFF_DELAY

The TON_TOFF_DELAY command sets the delay times after receiving an on or off command for the selected

output to begin turning on or off.

TON_DELAY of this command are lexically equivalent to TON_DELAY. If TON_DELAY is set to 0 ms, the device

would begin turning on immediately. If TOFF_DELAY is set to 0 ms, the device would begin turning off

immediately.

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Table 34. TON_TOFF_DELAY Data Byte Contents

NAME

READ /

WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7:6

5:3

—

R

00

—

TON_DELAY

R/W

010

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

0 ms

Delay time before starting

1 ms

5 ms

25 ms

100 ms

500 ms

1000 ms

2000 ms

0 ms

2:0

TOFF_DELAY

R/W

000

Delay time before stopping

1 ms

5 ms

25 ms

100 ms

500 ms

1000 ms

2000 ms

These delays are always in effect including when the outputs are internally or externally sequenced, or arbitrarily

turned on or off. The only exceptions are:

•

The device receives an immediate OFF from the OPERATION command.

The device turns its output off internally (such as in a fault condition).

PAGE support is for outputs 0x00 through 0x03.

8.5.4.15 (DEh) TON_TRANSITION_RATE

The TON_TRANSITION_RATE command sets the soft-start ramp rate for the selected output. This command is

ignored by default because soft-start is set externally through the SSx/PG pin. Only when the SSx/PG pin is

configured as PG through PIN_CONFIG_01 will TON_TRANSITION_RATE determine the soft-start rate.

The soft-start ramp rate refers to the rate at which the reference voltage is increased. The time to complete the

soft-start can be calculated from the target reference voltage as Equation 6.

Vref

t_ss

Soft start ramp rate

(6)

For example, if VREF is set to 0.6 V and the default soft-start ramp rate of 0.5 V/ms is selected, then the soft-

start time would be 1.2 ms. If VREF is set to 1 V and the soft-start ramp rate of 0.25 V/ms is selected, then the

soft-start time would be 4 ms.

Table 35. TON_TRANSITION_RATE Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7:2

—

R

000000

10

—

00

01

10

11

—

2 V/ms

1 V/ms

1:0

TON_RAMP_RATE

R/W

Soft-start ramping rate

0.5 V/ms

0.25 V/ms

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PAGE support is for outputs 0x00 through 0x03.

8.5.4.16 (DFh) VREF_TRANSITION_RATE

The VREF_TRANSITION_RATE command determines the stepping rate and stepping size when dynamically

switching the reference voltage VREF of the selected output.

Table 36. VREF_TRANSITION_RATE Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7

VREF_RAMP_ENABLE

R/W

1

0

—

Ramping disabled

Ramping enabled

—

1

—

6

—

R

0

—

5:3

VREF_RAMP_TIMESTEP

R/W

011

000

1 µs

Delay time per ramping

step

001

2 µs

010

3 µs

011

4 µs

100

6 µs

101

8 µs

110

12 µs

16 µs

See Table 37

111

2:0

VREF_RAMP_BITSTEP

R/W

000

See Table 37

Ramp up and ramp

down LSB increments /

decrements

Table 37. VREF_RAMP_BITSTEP Data Bit Values

VREF_RAMP_BITSTEP BINARY VALUE

RAMP UP (LSB increments)

RAMP DOWN (LSB decrements)

000 (default)

001

1

2

1

2

3

4

5

6

8

010

4

011

6

100

8

101

10

12

16

110

111

VREF_RAMP_BITSTEP sets the amount of voltage reference bits to ramp up and ramp down per

VREF_RAMP_TIMESTEP time. During ramping, if the target step is less than or equal to the

VREF_RAMP_BITSTEP setting, ramping reduces to a fine voltage step of 1 LSB per VREF_RAMP_TIMESTEP

time until the target voltage has been reached. For the actual voltage change per LSB, refer to (D8h)

VREF_COMMAND.

PAGE support is for outputs 0x00 through 0x03.

8.5.4.17 (F0h) SLOPE_COMPENSATION

The SLOPE_COMPENSATION command modifies control loop compensation parameters to compensate for

inductor ripple current harmonics from switching.

Table 38. SLOPE_COMPENSATION Data Byte Contents

BITS

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

7:2

—

R

000000

—

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Table 38. SLOPE_COMPENSATION Data Byte Contents (continued)

NAME

READ / WRITE

DEFAULT

VALUE

BINARY VALUE

VALUE

MEANING

00

01

10

11

45 mV/µs

70 mV/µs

100 mV/µs

145 mV/µs

Slope

compensation

1:0

SLOPE_COMPENSATION

R/W

01

The default slope compensation will be adequate for most applications. The equivalent current slope

compensation ramp on the inductor can be found by the following formula:

ΔI_L= –G_mps× SL_comp(A/S)

(7)

Where Gmps is the current sense gain of the peak current control to COMP voltage in Amps per Volt and

SLcomp is the slope compensation voltage expressed in the table above.

Ideal slope compensation is achieved when:

V_out

'I_L

!

L

(8)

PAGE support is for outputs 0x00 through 0x03.

8.5.4.18 (F1h) ISENSE_GAIN

The ISENSE_GAIN command modifies the current sense G_mpsof the feedback loop for the selected output.

(F0h) SLOPE_COMPENSATION describes the equivalent current slope compensation ramp on the inductor.

Table 39. ISENSE_GAIN Data Byte Contents, PAGE = 0x00, 0x01

BITS

7:2

NAME

—

READ / WRITE

DEFAULT VALUE

BINARY VALUE

VALUE

—

MEANING

—

R

000000

01

—

00

01

10

11

1:0

ISENSE_GAIN

R/W

20 A/V

10 A/V

5 A/V

2.5 A/V

Current sense gain

Table 40. ISENSE_GAIN Data Byte Contents, PAGE = 0x02, 0x03

BITS

7:2

NAME

—

READ / WRITE

DEFAULT VALUE

BINARY VALUE

VALUE

—

MEANING

—

R

000000

01

—

00

01

10

11

1:0

ISENSE_GAIN

R/W

10 A/V

5 A/V

Current sense gain

2.5 A/V

1.25 A/V

PAGE support is for outputs 0x00 through 0x03.

8.5.4.19 (FCh) DEVICE_CODE

The DEVICE_CODE command returns a 2-byte read-only device code. For the TPS65400-Q1, this is 0x00FX,

where 'X' is the revision/version number. This command has no PAGE support.

Table 41. DEVICE_CODE Data Word Contents

BITS

15:4

3:0

NAME

READ / WRITE

DEFAULT VALUE

DEVICE_CODE_ID

DEVICE_CODE_REV

R

0x00F

X

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS65400-Q1 PMU is designed to support the trend towards smaller space-constrained systems, which

require high-efficiency to limit power dissipation in a closed environment. The TPS65400-Q1 is intended to

provide a complete highly-efficiency power management solution in a small form factor while providing maximum

control through the I²C bus and ease of use.

The TPS65400-Q1 can support input voltages from 4.5 to 18 V, allowing it to be used in systems powered from a

single 5- or 12-V intermediate power bus. High system power conversion efficiency is achieved by providing a

single-stage conversion from, for example, the 12-V input voltage to the high-current voltage rails required by the

digital circuits.

The two buck regulators SW1 and SW2 can provide an output voltage in the range of 0.6 V to 90%Vin and up to

4-A peak continuous current.

The two buck regulators SW3 and SW4 can provide an output voltage in the range of 0.6 V to 90%Vin and up to

(1) (2)

2-A peak continuous current.

(1) ESD using the human body model, which is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal.

(2) Maximum sustainable DC current depends on ambient temperature and IC power dissipation (see Thermal Information)

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9.2 Typical Applications

9.2.1 Internal Operation Typical Application

ENSW1

ENSW2

ENSW3

ENSW4

PVIN1

CB1

12 V

SW1

CORE

SS1/PG1

SS2/PG2

SS3/PG3

SS4/PG4

PGND1

VFB1

PVIN2

CB2

12 V

PGOOD (Global)

PGOOD

VDDD

SW2

CORE

VDDD

PGND2

VFB2

SDA

I²C Master

VDDD

TPS65400-Q1

SCL

VDDD

ASIC/FPGA

Memory

I2CALERT

PVIN3

CB3

12 V

I2CADDR

RCLOCK_SYNC

Host

(Optional)

SW3

CLK_OUT

RST_N

CE

PGND (Thermal Pad)

VFB3

VDDD

12 V

PVIN4

CB4

12 V

VIN

PLL

I/O

VDDD

VDDA

VDDG

AGND

SW4

PGND (Thermal Pad)

VFB4

COMP3

COMP4

COMP1

COMP2

Figure 32. Typical Application Schematic

9.2.1.1 Design Requirements

Table 42 lists PMBus commands to configure this device.

Table 42. PMBus Commands Used for Internal Operation

COMMAND NAME

PAGE

CODE

00h

NAME

—

BITS

7:0

—

COMMENT

Selects output rail

STORE_DEFAULT_ALL

11h

—

Save settings as default

PGOOD_PIN_CONFIG

ENABLE_PIN_CONFIG⁽¹⁾

SSPG_PIN_CONFIG

START_PGOOD

START_ORDER

STOP_ORDER

RESET_DELAY⁽¹⁾

6:2

1:0

0

Configure PGOOD pin to mask PGOOD4

Active ENABLE (manufacturer default)

Set to PG for internal soft-start

Disable PGOOD dependence

Start sequence order

PIN_CONFIG_00

D2h

PIN_CONFIG_01

D3h

D4h

SEQUENCE_CONFIG

0

3:2

1:0

2:0

SEQUENCE_ORDER

RESET_DELAY

D5h

DCh

Stop sequence order

Reset delay time

(1) Only necessary if the defaults have been overwritten since device manufacture

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Typical Applications (continued)

Table 42. PMBus Commands Used for Internal Operation (continued)

COMMAND NAME

CODE

NAME

BITS

5:3

COMMENT

Delay time before starting

Delay time before stopping

Internal soft-start ramping rate

TON_DELAY

TON_TOFF_DELAY

DDh

TOFF_DELAY

TON_RAMP_RATE

2:0

TON_TRANSITION_RATE

DEh

1:0

To achieve the timing requirements shown in Table 42, an example configuration script is shown in Table 43.

Table 43. Example Configuration Script for Internal Operation

COMMAND NAME

CODE

WRITE BYTE

COMMENT

PAGE

00h

0xFF

Selects all

PGOOD pin is a function of PGOOD1 and PGOOD2 and

PGOOD3

PIN_CONFIG_00

D2h

0x1C

SEQUENCE_CONFIG

RESET_DELAY⁽¹⁾

PAGE

D4h

DCh

00h

0x01

0x02

0x00

0x01

0x08

Disable PGOOD dependence

100-ms reset delay

Selects SW1

PIN_CONFIG_01

SEQUENCE_ORDER

D3h

D5h

Configure SS1/PG1 pin to PG1 for internal soft-start

First to Start, third to Stop

0-ms turn-on delay

100-ms turn-off delay

TON_TOFF_DELAY

DDh

0x04

TON_TRANSITION_RATE

PAGE

DEh

00h

D3h

D5h

TON_RAMP_RATE

Internal soft-start ramping rate

Selects SW3

0x02

0x01

0x05

PIN_CONFIG_01

SEQUENCE_ORDER

Configure SS3/PG3 pin to PG3 for internal soft-start

Second to start, second to stop

100-ms turn-on delay

25-ms turn-off delay

TON_TOFF_DELAY

DDh

0x23

TON_TRANSITION_RATE

PAGE

DEh

00h

D3h

D5h

TON_RAMP_RATE

Internal soft-start ramping rate

Selects SW2

0x01

0x02

PIN_CONFIG_01

SEQUENCE_ORDER

Configure SS2/PG2 pin to PG2 for internal soft-start

Third to start, first to stop

100-ms turn-on delay

25-ms turn-off delay

TON_TOFF_DELAY

DDh

0x23

TON_TRANSITION_RATE

STORE_DEFAULT_ALL

DEh

11h

TON_RAMP_RATE

—

Internal soft-start ramping rate

Save settings as default

(1) Only necessary if the defaults have been overwritten after device manufacture.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Component Selection

9.2.1.2.1.1 Output Inductor Selection

Equation 9 gives the current ripple flowing in the inductor in CCM.

§

·

¸

V_out

V

V_outu 1ꢀ

¨

©

in ¹

'I_L

L u f_sw

where

•

ΔI_Lis the current ripple in the inductor.

V_outis the output voltage.

V_inis the input voltage of the converter.

L is the value of the inductor in henry.

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•

ƒ_SWis the switching frequency of the converter.

(9)

Typically, the value of L is chosen to have the ripple current be 0.1× to 0.3× the full-load current. Choose the

inductor so that the saturation current is higher than the maximum expected current plus half the current ripple at

maximum operating temperature.

9.2.1.2.1.2 Output Capacitor Selection

The output capacitor needs to be properly sized to reduce voltage ripple due to the switching action (ripple

voltage) and to reduce output voltage swings during transient load currents. Equation 10 gives the output voltage

ripple.

V ꢂ V

ꢀ _outꢁ

u V

out

in

'V_{out _ripple}

ꢀ¦_sw²u&u/u 9

in

(10)

(11)

Equation 11 gives the voltage variation during output current transients.

2

uL

'I_{out _ transient}

'V_{out _ transient}

C_ou V_out

9.2.1.2.2 Internal Operation With Some Switchers Disabled

For applications where the internal settings for sequencing and soft-start are sufficient, all used output rails

should have their enable terminals ENSWx tied high or floating and all unused output rails should have their

enable pins ENSWx tied low for the default active ENABLE setting of ENABLE_PIN_CONFIG. This prevents the

device from turning on an unused output by software default from an OPERATION ON request. This requirement

extends to unpowered switchers; if a pair of switchers is unused, then both ENSWx pins must be tied low.

9.2.1.2.3 Internal Operation With All Switchers Enabled

For applications where all outputs rails will be used, it is sufficient to leave all enable terminals ENSWx

disconnected and to set ENABLE_PIN_CONFIG to inactive.

9.2.1.2.4 Example Configuration

Figure 33 shows an internal sequencing schematic example where only switchers 1 to 3 are used for a set of

timing requirements. If the internal configuration and fault handling is sufficient, and provided that the user

configures the chip through SDA/SCL before placing it on a target board, then it is not necessary for a

supervisory and housekeeping host controller chip like a MCU or DSP to be connected to the TPS65400-Q1. In

such a case, digital terminals PGOOD, SSx/PG, SDA/SCL, I2CALERT, and CLK_OUT can be left unconnected

with no pull-ups required, during normal operation. RST_N can be tied directly to VDDD (no pull-up required).

I2CADDR can be tied directly to VDDD after programming. Control line CE can be left unconnected if the chip is

constantly powered after VIN is provided.

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CE

0+1a

100 ms

VOUT1

1b

3b

VOUT3

VOUT2

2b

25 ms

3c

3a

2a

1c

^{25 ms}2c

100 ms

PGOOD1

PGOOD3

PGOOD2

PGOOD

ON (default)

OPERATION

PAGE = 0xFF

User-Issued Soft-OFF

t

0. RESET_DELAY

1. SW1

2. SW2

3. SW3

a. TON_DELAY

b. V_REF/ TON_RAMP_RATE

c. TOFF_DELAY

PGOOD dependence disabled, switcher 4 disabled

Figure 33. Example Timing Diagram for Internal Sequencing

9.2.1.2.5 Unused Switchers

If the default setting active ENABLE of ENABLE_PIN_CONFIG is selected, ENSWx for unused switchers must

always be tied low.

9.2.1.3 Application Curves

Figure 34. Configurable Power-Up Sequence

Figure 35. Phase Shift Between Channels

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1%

11

10.8

10.6

10.4

10.2

10

Vref3 Accuracy

Vref1 Accuracy

Vref2 Accuracy

Vref4 Accuracy

Vref1 Step

Vref2 Step

Vref3 Step

Vref4 Step

0.8%

0.6%

0.4%

0.2%

0

9.8

9.6

9.4

9.2

-0.2%

9

0

25

50

75

100

125

0

25

50

75

100

125

150

Code

D006

D007

Figure 36. V_REFAccuracy vs Code

Figure 37. V_REFStep Accuracy vs Code

1.816

1.815

1.814

1.813

1.812

1.811

1.81

3.315

3.31

3.305

3.3

3.295

3.29

1.809

1.808

3.285

0

1

2

3

4

0

1

2

3

4

I_OUT1(A)

I_OUT2(A)

D008

D009

Figure 38. V_OUT1Load Regulation

Figure 39. V_OUT2Load Regulation

1.2095

1.209

1.211

1.21

1.2085

1.208

1.2075

1.207

1.209

1.208

1.2065

1.206

0

0.5

1

1.5

2

0

0.5

1

1.5

2

I_OUT3(A)

I_OUT4(A)

D010

D011

Figure 40. V_OUT3Load Regulation

Figure 41. V_OUT4Load Regulation

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9.2.2 Current Sharing Typical Application

An example configuration is shown where both pairs of outputs are current shared. Soft-start time is configured

externally with capacitors (this is the default setting) and ENABLE_PIN_CONFIG is set to single ENABLE.

ENSW1

ENSW2

ENSW3

ENSW4

PVIN1

CB1

VIN1

VOUT1

SW1

SS1/PG1

SS2/PG2

SS3/PG3

SS4/PG4

PGND1

VFB1

PVIN2

CB2

VIN!

PGOOD(Global)

PGOOD

VDDD

SW2

PGND2

VFB2

SDA

SCL

VDDD

TPS65400-Q1

I2CALERT

I2CADDR

PVIN3

CB3

VIN3

Host

(Optional)

VOUT3

RCLOCK_SYNC

SW3

CLK_OUT

RST_N

CE

VDDD

VIN

PGND (Thermal Pad)

VFB3

PVIN4

CB4

VIN3

VIN

VDDD

VDDA

VDDG

AGND

SW4

PGND (Thermal Pad)

VFB4

COMP3

COMP4

COMP1

COMP2

VDDA

Figure 42. Current Sharing Schematic

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9.2.2.1 Design Requirements

Table 44 lists PMBus commands to configure this device.

Table 44. PMBus Commands Used for Current Sharing With Single-Pin Enable⁽¹⁾

COMMAND NAME

PAGE

CODE

00h

NAME

BITS

7:0

—

COMMENT

—

Selects output rail

Save settings as default

STORE_DEFAULT_ALL

11h

PGOOD_PIN_CONFIG⁽¹⁾

ENABLE_PIN_CONFIG

SSPG_PIN_CONFIG⁽¹⁾

START_PGOOD⁽¹⁾

START_ORDER

6:2

1:0

0

PGOOD pin and of all PGOOD (manufacturer default)

Single ENABLE

PIN_CONFIG_00

D2h

PIN_CONFIG_01

D3h

D4h

Set to SSx for external soft-start (manufacturer default)

Enable PGOOD dependence (manufacturer default)

Start sequence order

SEQUENCE_CONFIG

0

3:2

1:0

5:3

2:0

SEQUENCE_ORDER

TON_TOFF_DELAY

D5h

DDh

STOP_ORDER

Stop sequence order

TON_DELAY

Delay time before starting

TOFF_DELAY

Delay time before stopping

(1) Only necessary if the defaults have been overwritten since device manufacture.

To achieve the timing requirements shown in Table 44, see the example configuration script in Table 45.

Table 45. Example Configuration Script for Current Sharing With Single-Pin Enable

COMMAND NAME

CODE

00h

WRITE BYTE

COMMENT

PAGE

Selects all

PIN_CONFIG_00

SEQUENCE_CONFIG⁽¹⁾

PAGE

D2h

D4h

00h

Single ENABLE

Enable PGOOD dependence (manufacturer default)

Selects SW1 to SW2 pair

Configure SS1/PG1 pin to SS1 for external soft-start

(manufacturer default)

PIN_CONFIG_01⁽¹⁾

SEQUENCE_ORDER

TON_TOFF_DELAY

PAGE

D3h

D5h

DDh

00h

0x04

0x24

0x02

0x00

0x01

0x23

—

First to start, second to stop

100-ms turn-on delay

100-ms turn-off delay

Selects SW3 to SW4 pair

Configure SS2/PG2 pin to SS2 for external soft-start

(manufacturer default)

PIN_CONFIG_01⁽¹⁾

SEQUENCE_ORDER

TON_TOFF_DELAY

STORE_DEFAULT_ALL

D3h

D5h

DDh

11h

Second to start, first to stop

100-ms turn-on delay

25-ms turn-off delay

Save settings as default

(1) Only necessary if the defaults have been overwritten since device manufacture.

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Current Sharing Timing Example

Figure 43 shows an example configuration in which both the SW1-SW2 pair and SW3-SW4 pair are current

shared. The enable pin of the slave converter can either follow the master converter or be floating. For the

PGOOD pin, the slave PGOOD follows the master PGOOD. Due to internal pull-ups to VDDD on ENSWx lines,

the user has an option to control ENSWx if an always on condition is desired.

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ENSW1

1a

100 ms

1b

VOUT1

VOUT3

3b

25 ms

3c

3a

1c

100 ms

PGOOD1

PGOOD3

PGOOD

t

C_ss

I_ss

a. t_{ON_DELAY}

b.

c. t_{OFF_DELAY}

1. SW1-SW2

3. SW3-SW4

V_REF

A. External soft-start, single ENABLE

Figure 43. Example Timing Diagram for Current Sharing With Single-Pin Enable

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9.2.3 External Sequencing Application

Figure 44 shows an example configuration where the VOUT outputs are linked to enable terminal ENSWx inputs

in a daisy-chain configuration for start sequence SW1-SW2-SW3-SW4.

ENSW1

ENSW2

ENSW3

ENSW4

PVIN1

CB1

VIN1

VOUT1

VOUT2

VOUT3

VOUT1

SW1

SS1/PG1

SS2/PG2

SS3/PG3

SS4/PG4

PGND1

VFB1

PVIN2

CB2

VIN2

PGOOD(Global)

PGOOD

VOUT2

VDDD

SW2

PGND2

VFB2

SDA

SCL

VDDD

TPS65400-Q1

I2CALERT

I2CADDR

PVIN3

CB3

VIN3

Host

(Optional)

VOUT3

RCLOCK_SYNC

SW3

CLK_OUT

RST_N

CE

VDDD

VIN

PGND (Thermal Pad)

VFB3

PVIN4

CB4

VIN4

VIN

VDDD

VDDA

VDDG

AGND

VOUT4

SW4

PGND (Thermal Pad)

VFB4

COMP3

COMP4

COMP1

COMP2

VDDA

A. Sequencing through VOUT

Figure 44. External Sequencing Schematic, Vout > VEN

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9.2.3.1 Design Requirements

Table 46 and Table 47 list PMBus commands to configure this device.

Table 46. PMBus Commands Used for External Sequencing through VOUT

COMMAND NAME

PAGE

CODE

00h

NAME

BITS

7:0

—

COMMENT

—

Selects output rail

Save settings as default

STORE_DEFAULT_ALL

PIN_CONFIG_00

PIN_CONFIG_01

TON_TOFF_DELAY

RESET_DELAY

11h

PGOOD_PIN_CONFIG⁽¹⁾

ENABLE_PIN_CONFIG⁽¹⁾

SSPG_PIN_CONFIG⁽¹⁾

TON_DELAY

TOFF_DELAY⁽¹⁾

RESET_DELAY⁽¹⁾

6:2

1:0

0

PGOOD pin and of all PGOOD (manufacturer default)

Active ENABLE (manufacturer default)

Set to SSx for external soft-start (manufacturer default)

Delay time before starting

D2h

D3h

DDh

DCh

5:3

2:0

Delay time before stopping

Reset delay time

(1) Only necessary if the defaults have been overwritten since device manufacture.

To achieve the timing requirements shown in Table 46, see Table 47 for an example configuration script.

Table 47. Example Configuration Script for External Sequencing through VOUT

COMMAND NAME

CODE

00h

WRITE BYTE

0xFF

COMMENT

PAGE

Selects all

PIN_CONFIG_00⁽¹⁾

RESET_DELAY⁽¹⁾

PAGE

D2h

DCh

00h

0x3C

Active ENABLE (manufacturer default)

100-ms reset delay

0x02

0x00

Selects SW1

PIN_CONFIG_01⁽¹⁾

D3h

0x00

Configure SS1/PG1 pin to SS1 for external soft-start

100-ms turn-on delay

0-ms turn-off delay

TON_TOFF_DELAY

DDh

0x20

PAGE

PIN_CONFIG_01⁽¹⁾

00h

D3h

0x01

0x00

Selects SW2

Configure SS2/PG2 pin to SS2 for external soft-start

100-ms turn-on delay

0-ms turn-off delay

TON_TOFF_DELAY

DDh

0x20

PAGE

PIN_CONFIG_01⁽¹⁾

00h

D3h

0x02

0x00

Selects SW3

Configure SS3/PG3 pin to SS3 for external soft-start

100-ms turn-on delay

0-ms turn-off delay

TON_TOFF_DELAY

DDh

0x20

PAGE

PIN_CONFIG_01⁽¹⁾

00h

D3h

0x03

0x00

Selects SW4

Configure SS4/PG4 pin to SS4 for external soft-start

100-ms turn-on delay

0-ms turn-off delay

TON_TOFF_DELAY

DDh

11h

0x20

—

STORE_DEFAULT_ALL

Save settings as default

(1) Only necessary if the defaults have been overwritten since device manufacture.

9.2.3.2 Detailed Design Procedure

9.2.3.2.1 External Sequencing Through PG Pins

In an application where the programmable soft-start ramping rate is sufficient and where stop sequencing is not

required, it is possible to wire Power Good pins (global PGOOD, PG) to enable pins (ENSWx) according to the

desired start sequence. This is useful in cases where multiple PMUs are configured and the PG or global

PGOOD output of one PMU is required to turn on an output of another PMU.

9.2.3.2.2 External Sequencing Through SW

In an application where output voltages exceed the threshold voltage of the enable pins ENSWx, it is possible to

wire a properly divided VOUT directly to the enable pins according to the desired start sequence.

64

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9.2.3.2.3 Example Configuration

CE

0+1a

100 ms

1b

VOUT1

VOUT2

VOUT3

VOUT4

2b

3b

4b

2a

3a

4a

100 ms

PGOOD1

PGOOD2

PGOOD3

PGOOD4

PGOOD

t

4. SW4

0. RESET_DELAY

a. t_{ON_DELAY}

1. SW1

2. SW2

3. SW3

C_ss

I_ss

b.

V_REF

Figure 45. Example Timing Diagram for External Sequencing Through VOUT

NOTE

Only necessary if the defaults have been overwritten since device manufacture.

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10 Power Supply Recommendations

This device is designed to operate from an input voltage supply range between 4.5 and 18 V. This input power

supply should be well regulated. If the input supply is located more than a few inches from the TPS65400-Q1

converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An

electrolytic capacitor with a value of 47 μF is a typical choice.

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of high-current multi-channel DC-DC. Follow these guidelines for layout. See Layout

Example for a PCB layout example.

•

Place VOUT and SW on the top layer and an inner power plane for VIN.

Also on the top layer, fit connections for the remaining pins of TPS65400-Q1 and a large top-side area filled

with ground.

•

Connect the top layer ground area to the internal ground layer or layers using vias at the input bypass

capacitor, the output filter capacitor, and directly under the TPS65400-Q1 device to provide a thermal path

from the power pad to ground.

•

Tie the AGND pin directly to the power pad under the IC.

For operation at full-rated load, the top-side ground area together with the internal ground plane must provide

adequate heat dissipating area.

•

Several signals paths conduct fast-changing currents or voltages that can interact with stray inductance or

parasitic capacitance to generate noise or degrade the power supplies' performance. To help eliminate these

problems, bypass the VIN pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric.

Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the

ground connections. Because the SW connection is the switching node, the output inductor should be located

close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.

•

The output filter capacitor ground should use the same power ground trace as the VIND input bypass

capacitor. Try to minimize this conductor length while maintaining adequate width.

The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are

sensitive to noise so the components associated to these pins should be located as close as possible to the

IC and routed with minimal lengths of trace.

•

The VFB node is a high-impedance analog node which is easier to pick noise on board. Keep FB node trace

as short as possible.

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11.2 Layout Example

Figure 46. Layout Schematic

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

•

PMBus Power System Management Protocol Specification Part I – General Requirements, Transport and

Electrical Interface, Revision 1.2, dated 6 September 2010, published by the Power Management Bus

Implementers Forum (http://pmbus.org/Specifications).

12.1.2 Related Parts

PART NUMBER

DESCRIPTION

COMMENTS

Triple buck 3-A/1-A/1-A output current, dual LDOs 100-

mA/200-mA output current, automatic power sequencing

Triple buck 3-A/2-A/2-A output current, I²C-controlled

dynamic voltage scaling (DVS)

TPS65262

TPS65263

4.5- to 18-V, triple buck with dual adjustable LDOs

4.5- to 18-V, triple buck with I²C interface

Triple buck 3-A/2-A/2-A output current, support 1-s, 32-ms,

and 256-ms PGOOD deglitch time, adjustable current limit

setting by external resistor

4.5- to 18-V, triple buck with different PGOOD

deglitch time

TPS65651-1/2/3

TPS65287

Triple buck 3-A/2-A/2-A output current, up to 2.1-A USB

4.5- to 18-V, triple buck with power switch and push- power with overcurrent setting by external resistor, push-

button control

button control for intelligent system power-on/power-off

operation

Triple buck 3-A/2-A/2-A output current, 2 USB power switches

current limiting at typical 1.2 A (0.8/1/1.4/1.6/1.8/2/2.2 A

available with manufacture trim options)

TPS65288

4.5- to 18-V, triple buck with dual power switches

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

68

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PACKAGE MATERIALS INFORMATION

www.ti.com

8-Oct-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65400QRGZRQ1

TPS65400QRGZTQ1

VQFN

RGZ

48

2500

250

330.0

180.0

16.4

7.3

1.1

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Oct-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS65400QRGZRQ1

TPS65400QRGZTQ1

VQFN

RGZ

48

2500

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

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complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65288RHAT
厂家：	TEXAS INSTRUMENTS
描述：	具有双负载开关的 4.5V 至 18V 输入、3A/2A/2A 同步降压转换器 \| RHA \| 40 \| -40 to 125 开关转换器
文件：	总75页 (文件大小：1420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65288RHAT [TI]

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