TPS65301QPWPRQ1 [TI]
具有 3 个 LDO 和受保护传感器电源的汽车类 5.6V 至 40V、1.2A 降压转换器 | PWP | 24 | -40 to 125;
| 型号： | TPS65301QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 3 个 LDO 和受保护传感器电源的汽车类 5.6V 至 40V、1.2A 降压转换器 | PWP | 24 | -40 to 125 开关 光电二极管 传感器 转换器 |
| 文件： | 总38页 (文件大小：2229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
3MHz 降压稳压器和三重线性稳压器以及受保护传感器电源
查询样片: TPS65301-Q1
1
特性
描述
•
输入 VIN 电压范围介于 5.75V 至 40V 之间，瞬态
TPS65301-Q1 电源是一个单开关模式降压电源和三个
电压高达 45V
线性稳压器的组合。 这是一款单片高压开关稳压器，
此稳压器具有一个集成型 1.2A 峰值电流开关，45V 功
率金属氧化物半导体场效应晶体管 (MOSFET)，一个
低压线性稳压器，两个电压稳压器控制器以及一个受保
护传感器电源。
•
•
为了实现稳定性，所有输出支持陶瓷输出电容器
带有集成高侧开关的 5.45V 开关模式稳压器
–
建议使用的开关模式频率范围为 2MHz 至
3MHz
•
•
•
过流保护和 1.2A 峰值开关电流
一个线性稳压器 5V ± 2%
此器件具有一个电压监视器，此监视器监控开关模式电
源的输出，3.3V 线性稳压器和 1.2V 线性稳压器。 一
个外部定时电容器用于设定加电延迟时间和复位输出
nRST 的释放时间。 这个复位输出还被用于表示开关
模式电源，3.3V 线性稳压器电源或者 1.2V 线性稳压
器电源是否在设定的限值之外。 受保护传感器电源
5VS 在额定限值内跟踪 3.3V 线性稳压器。
两个电压为 3.3V 的线性稳压器控制器，分别
为1.2V ± 2%
•
•
•
•
•
受保护 5V 传感器电源输出，此输出跟踪 3.3V 电源
IGN_EN 输入的状态指示器输出
点火 (IGN_EN) / 使能输入 (EN) 周期上的软启动
用于同步的外部时钟输入
TPS65301-Q1 器件开关频率范围介于 2MHz 至 3MHz
之间，从而实现半高电感器和低值输入以及输出陶瓷电
容器的使用。 外部环路补偿为用户提供了针对适当的
运行条件而进行转换器优化的灵活性。
针对快速负瞬态的可编程加电复位延迟、复位功能
滤波器定时器
•
针对下列电源的电压监视器
–
VREG，3.3V，1.2V
•
•
•
针对过多功率耗散的热关断保护
此器件具有内置保护特性，诸如 IGN_EN ON 或者使
能周期上的软启动、逐脉冲电流限制、热感测、和过多
功率耗散而引起的关断。
运行结温范围高达 150°C
耐热增强型 24 引脚超薄型小外形尺寸 (HTSSOP)
或者 24 引脚四方扁平无引线 (QFN) 封装
VIN_D
2
4
BOOT
PH
VI = 5.6 V to 40 V
3
1
VIN
Supply
应用范围
5.45 V
•
•
•
用于 TMS570 微控制器的电源
EN
9
22
14
VREG
COMP
IGN_EN
RT/CLK
5
8
用于 C28XXX 数字信号处理器 (DSP) 的电源
15
针对车载应用的通用电源
VSENSE
SS
20
TPS65301PWPR-Q1
BOOT_LDO
3.3VDRIVE
3.3VSENSE
6
19
18
3.3 V
5 V
GND
10
12
21
DELAY
nRST
23
5VS
7
1.2VDRIVE
1.2VSENSE
17
16
1.2 V
PGND
24
图 1. 典型应用电路原理图
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC10
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
FUNCTION
Buck Regulator
TERMINAL
VALUE
–0.3 to 45
–0.3 to 50
UNIT
VIN, VIN_D
BOOT
V
V
V
PH
–1 to 45
–2 V for 30 nS
VSENSE
IGN_EN
EN
–0.3 to 5.5
–0.3 to 45
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 8
–0.3 to 8
–0.3 to 8
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 7
–0.3 to 7
–0.3 to 7
–0.3 to 9
–0.3 to 7
–1 to 45
V
V
Control
V
3.3VSENSE
1.2VSENSE
RT/CLK
VREG
V
V
V
V
Output
3.3VDRIVE
1.2VDRIVE
nRST
V
V
V
IGN_ST
SS
V
V
DELAY
COMP
V
V
BOOT_LDO
5V
V
V
5VS
V
Temperature
Operating junction temperature range, TJ
Storage Temperature Range, TS
ESD(2)
–40 to 150
–55 to 165
±2
°C
°C
kV
Electrostatic Discharge HBM
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
5.6
5.6
–1
0
NOM
MAX
40
UNIT
V
VIN, VIN_D
BOOT
48
V
PH
40
V
IGN_EN
40
V
EN, VSENSE, 3.3VSENSE, 1.2VSENSE, RT/CLK, nRST, IGN_ST
VREG, 3.3VDRIVE, 1.2VDRIVE
SS, DELAY, COMP
0
5.25
7.5
6.5
8.1
125
V
0
V
0
V
BOOT_LDO
0
V
Operating ambient temperature range, TA
–40
°C
2
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
THERMAL INFORMATION
TPS65301-Q1
THERMAL METRIC(1)
PWP
24 PINS
33.6
RHF
24 PINS
30.3
30.5
8.7
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
16.6
14.5
ψJT
0.4
0.3
ψJB
14.3
8.8
θJCbot
1.3
1.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
DC CHARACTERISTICS
VIN = 6 V to 27 V, IGN_EN = VIN, TJ-Max = 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN, VIN_D (Input Power Supply)
VIN,
Supply voltage on VIN, line
VIN_D
Normal mode, after initial startup
5.6
14
40
V
Iq-Normal
ISD VIN
Current normal mode
Open-loop test
5.57
2.2
mA
IGN = 0 V, VIN = 12 V, TA = –40°C to 125°C
IGN = 0 V, VIN = 12 V, TA = –40°C to 125°C
15
15
Shut down
µA
ISD VIND
2.2
IGN_EN (Ignition Input)
VIGN_EN Input voltage range
VIH
Input into IGN_EN pin
14
3.16
3.03
23.7
4
40
V
V
V
Input high
Input low
Enable device to be ON (rising signal)
Enable device to be OFF (falling signal)
Enable device to be ON, VIGN_EN = 18 V
Enable device to be ON, VIGN_EN = 3.7 V
3.6
VIL
2.2
0.7
50
7
IIH
Input high
µA
EN (Logic Level Enable)
VIH
VIL
Input high
Input low
Enable device to be ON (rising signal)
Enable device to be OFF (falling signal)
1.7
2.3
V
V
1.53
Switch-Mode Output 5.45 V
Regulator output internal
resistor network
VREG
CO
Fixed output based on internal resistor network
5.30
10
5.45
5.70
V
ESR = 0.001 Ω to 100 mΩ; large output capacitance
may be required for load transients
Output capacitor for 5.45 V
µF
rds(on)
IO-CL
tON-min
Dmax
Internal switch resistance
Switch current limit
Minimum ON time
Measured across VIN_D and PH pins, IVREG = 1 A
VIN = 12 V
0.3
2
Ω
A
1.2
3
40
ns
Maximum duty cycle
97%
VSENSE (Internal Reference Voltage)
VREG ref Internal reference voltage
1.954
2
2.046
V
Copyright © 2013, Texas Instruments Incorporated
3
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
DC CHARACTERISTICS (continued)
VIN = 6 V to 27 V, IGN_EN = VIN, TJ-Max = 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SS (Soft-Start Timer for Switch-Mode Converter)
ISS
Soft-start source current
Css = 0.001 µF to 0.01 µF
40
50
60
µA
IGN_ST (Ignition Input Status)
Output asserted low when IGN_EN < 2.2 V, IOL = 1
mA
VOL
IIH
Output low
0.056
0.05
0.4
2
V
Leakage test
IGN_ST = 5 V
µA
5V (5-V Linear Regulator)
5VO
Output voltage
Line regulation
IO = 1 mA, VREG = 5.45 V
4.9
5
10
10
5.1
20
30
V
∆VO-Line
5.15 V < VREG < 5.45 V, IO = 1 mA, VIN = 12 V
1 mA < IO < 200 mA, VREG = 5.45 V, VIN = 12 V
mV
mV
∆VO-Load Load regulation
IO = 150 mA, measure VREG when VO(nom) – 0.1
V, then VDO = VREG – (5VO – 0.1) V, VREG > 5 V
VDO
I5V-CL
CO
Dropout voltage
Current limit
0.15
1080
2.2
0.26
V
5VO = 0.8 x 5VO (nom)
350
1
mA
µF
ESR = 0.001 Ω to 2 Ω. Larger output capacitance
may be required for load transients.
Output capacitor
10
75
f = 100 Hz, VREG = 5.45 V, IO = 100 mA, VIN = 12
V
PSRR
Power-supply rejection ratio
Soft start on enable cycle
45
60
13
dB
ms
Vsoft-start
5VO = 0 V (initially) with fsw = 2.5 MHz
3.3-V Linear Regulator Controller (3.3VSENSE)
3.3VO
Output voltage
IO = 5 mA, Vnpn_power input = 5.3 V
3.234
3.3
1
3.366
10
V
∆3.3VO-
Line
3.8 V < Vnpn_power input < 7 V (with nRST not
triggered)
Line regulation
mV
∆3.3VO-
Load
Load regulation
5 mA < IO < 550 mA
7.5
4.7
30
10
75
mV
µF
ESR = 0.001 Ω to 2 Ω. Large output capacitance
may be required for load transients.
CO
Output capacitor for 3.3 V
1
f = 100 Hz, VREG = 5.45 V, IO = 200 mA, VIN = 12
V
PSRR
tss
Power-supply rejection ratio
Soft-start time
45
60
dB
ms
3.3VO = 0 V (initially) with fsw = 2.5 MHz
12.3
3.3VDRIVE (Ex. Switch Control Output)
Base drive current. NPN turn
ON
IOH
3.3VDRIVE – 3.3VSENSE = 1 V
3.3VDRIVE – 3.3VSENSE at 0.2 V
10
28
50
mA
mA
IOL
NPN turn off
0.1
0.412
1.2-V Linear Regulator Controller (1.2VSENSE)
1.2VO
Output voltage
IO = 5 mA, Vnpn_power input = 5.3 V
1.176
1.2
1
1.224
10
V
∆1.2VO-
Line
3.25 V < Vnpn_power input < 7 V (with nRST not
triggered)
Line regulation
mV
∆1.2VO-
Load
Load regulation
5 mA < IO < 350 mA
5
15
mV
µF
ESR = 0.001 Ω to 100 mΩ. Large output
capacitance may be required for load transients.
CO
Output capacitor for 1.2 V
8
10
12
75
PSRR
tss
Power-supply rejection ratio
Soft-start time
f = 100 Hz, VREG = 6 V, IO = 200 mA, VIN = 12 V
1.2VO = 0 V (initially) with fsw = 2.5 MHz
45
60
dB
ms
8.5
1.2VDRIVE (Ex. Switch Control Output)
Base drive current. NPN turn
ON
IOH
IOL
1.2VDRIVE – 1.2VSENSE = 1 V
1.2VDRIVE – 1.2VSENSE at 0.2 V
10
27
50
mA
mA
NPN turn off
0.1
0.47
5VS (Protected Sensor Supply Linear Regulator)
VSENSOR Output tolerant range
VSENSOR output shorted fault conditions
–1
VIN
5.1
V
V
VSENSO
Output voltage
R
IO = 1 mA to 100 mA, VREG = 5.45 V
4.9
5
4
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
DC CHARACTERISTICS (continued)
VIN = 6 V to 27 V, IGN_EN = VIN, TJ-Max = 150°C, unless otherwise noted
PARAMETER
Short circuit current
Output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
I5VS_SC
I5VS
5VS = 45 V
2.25
VREG = 5.45 V
150
mA
∆5VSLOA
D
Load regulation
1 mA < I5VS < 75 mA, VREG = 5.45 V, VIN = 12 V
15
mV
IO = 150 mA, Measure VREG when 5VS (nom) –
0.1 V
Then VDO = VREG – (5VS – 0.1) V, VREG > 5.1 V
VDO
Drop out voltage
0.4
10
V
Output capacitor for protected ESR = 0.001 Ω to 2 Ω, Larger output capacitance
CO
1
µF
5-V supply
may be required for load transients
I5VS-CL
ILkg
Current limit
5VS = 0.8 x 5VS (nom)
180
320
60
650
5
mA
µA
dB
Leakage current
Power-supply rejection ratio
EN_LIN_REG = 0 V with VIN = 14 V
f = 100 Hz, VREG = 6 V, I5VS = 75 mA, VIN = 12 V
PSRR
DELAY (Power-On-Reset Delay)
VThreshold Threshold voltage
Threshold to release nRST high
1.3
1.4
2.05
2
2.6
2.6
V
ICharge
Capacitor charging current
µA
nRST (Reset Indicator)
Reset asserted due to falling VREG or 3.3 VO or 1.2
VO output voltages, IOL = 1 mA
VOL
Output low
0
0.16
0.4
V
tnRSTdly
Filter time
Delay before nRST is asserted low
11
0.875
0.93
µs
Trigger nRST for VREG output
0.845
0.9
0.905
0.96
0.96
2
VREG
3.3 VO
1.2 VO
µA
VTH_VREG Trigger nRST for 3.3 VO
Trigger nRST for 1.2 VO
VREG ramp down
0.9
0.93
IIH
Leakage test
Reset = 5 V
0.07
RT/CLK (Oscillator Setting of External Clock Input)
Switching freq using RT mode
2
2
3
3
MHz
ns
Switching freq using CLK
mode
fsw
Minimum clock input pulse
duration
40
Internal oscillator frequency
External clock input
Input high
–14%
–20%
14%
10%
2.3
Switching frequency tolerance for clock
VIH
VIL
V
V
Input low
0.6
Copyright © 2013, Texas Instruments Incorporated
5
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
DEVICE INFORMATION
17
14 13
12
19 18
20
16 15
VREG
nRST
COMP
NC
21
11
10
GND
PGND
PH
22
23
IGN_ST
5V
9
8
24
VIN_D
2
3
4
5
1
6
7
PIN DESCRIPTIONS
PIN
NUMBER
I/O
DESCRIPTION
NAME
PWP RHF
PH
VIN_D
BOOT
1
2
3
4
5
6
7
23
24
1
O
I
Source of internal switching FET
Drain input for internal high side MOSFET. Pin 2 and pin 4 must be connected together externally.
External bootstrap capacitor connected to PH (pin 1) to drive gate of internal switching FET
Unregulated input voltage supply. Pin 2 and pin 4 must be connected together externally.
Ignition input (high-voltage tolerant) internally pulls to ground. Must be externally pulled up to enable
External capacitor connected to ground for stability of internal regulator
O
I
VIN
2
IGN_EN
BOOT_LDO
5VS
3
I
4
O
O
5
External capacitor to ground for stability of regulated output
External resistor connected ground to program the internal oscillator. Alternative option is to feed an
external clock to provide reference for switching frequency.
RT/CLK
8
6
I/O
A high logic-level input signal to enable and low signal to disable device. Internally pulled down to
ground
EN
5V
9
7
8
9
I
10
11
O
O
External capacitor to ground for stability of regulated output
Active-low, open-drain ignition input indicator, output connected to external bias voltage through a
resistor. Asserted high after ignition input is high
IGN_ST
GND
NC
12
13
10
11
12
13
14
15
16
17
18
19
O
–
O
I
Ground pin, must be electrically connected to exposed pad on PCB for proper thermal performance
Connect to ground
COMP
VSENSE
14
Error amplifier output to connect external compensation components
Inverting node of error amplifier for voltage-mode control of preregulated supply
Voltage node of 1.2-V supply
115
1.2VSENSE 16
1.2VDRIVE 17
3.3VSENSE 18
I
O
I
Output current source to drive the base of an external bipolar transistor to regulate the 1.2-V supply
Voltage node of 3.3-V supply
3.3VDRIVE
SS
19
20
21
O
O
O
Output current source to drive the base of an external bipolar transistor to regulate the 3.3-V supply
External capacitor to ground to program soft-start time
DELAY
External capacitor to ground to program the power-on-reset delay
Buck converter output. Integrated internal low-side FET to load output during start-up or limit voltage
overshoot
VREG
22
20
I
6
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
PIN DESCRIPTIONS (continued)
PIN
NUMBER
I/O
DESCRIPTION
NAME
PWP RHF
Active-low, open-drain reset output connected to external bias voltage through a resistor. This output is
asserted high after the preregulator, 3.3-V, and 1.2-V regulator outputs are regulating and the delay
timer has expired. Also, output is asserted low if any one of these three supplies is out of the set
regulation, this threshold is internally set.
nRST
23
21
O
Power ground pin, must be electrically connected to exposed pad on PCB for proper thermal
performance
PGND
24
–
22
–
O
–
Thermal
pad
Electrically connect to ground and solder to ground plane of PCB for thermal efficiency
Copyright © 2013, Texas Instruments Incorporated
7
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
EFFICIENCY
vs
OUTPUT CURRENT ON VREG
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1
5.50
5.45
5.40
5.35
5.30
T
= 25C
A
Vin = 12 V
0.8
Vin = 6 V
0.6
0.4
0.2
0
Vin = 12 V
Vin = 7 V
Vin = 5.9 V
Vreg=5
Vin = 5.8 V
0.8
Vin = 5.6 V
0.2
Fsw=2245 kHz
L=10 uH
Co=10 uF
0
200
400
600
Output Current (mA)
800
1000
1200
0.0
0.4
0.6
1.0
1.2
1.4
G001
I_VREG (A)
C002
Figure 2.
Figure 3.
BUCK CURRENT LIMIT
vs
VSENSE REFERENCE VOLTAGE
vs
TEMPERATURE
TEMPERATURE
2.10
1.90
1.70
1.50
1.994
1.993
1.992
1.991
1.99
1.989
1.988
1.987
1.986
1.985
0
1
2
3
4
5
6
Temperature (°C)
7
8
9
10
-50
0
50
100
150
Temperature (°C)
G002
G003
Figure 4.
Figure 5.
CURRENT CONSUMPTION IIN
QUIESCENT CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
7
6
5
Isd_total
4.98
4
3
Isd_vind
4.92
4.86
4.8
2
1
Isd_vin
0
-40
-10
0
25
50
Temperature (°C)
85
100 125 150
G005
-50
-25
0
25
50
Temperature (°C)
75
100 125 150
G004
Figure 6.
Figure 7.
8
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TYPICAL CHARACTERISTICS (continued)
A001
Figure 8. Load Transient Response, 10 mA to 1 A
5-V Linear Regulator (5 VO)
DROPOUT VOLTAGE
OUTPUT VOLTAGE 5VO
vs
vs
TEMPERATURE
TEMPERATURE
5.015
5.01
5.005
5
250
230
210
190
170
150
130
110
4.995
4.99
−60 −40 −20
0
20 40 60 80 100 120 140 160
Temperature (°C)
-50
0
50 100
Temperature (°C)
150
G006
G007
Figure 9.
Figure 10.
A002
Figure 11. Load Transient Response, 10 mA to 200 mA
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TYPICAL CHARACTERISTICS (continued)
3.3-V Linear Regulator Controller (3.3 VO)
OUTPUT BASE DRIVE
vs
3.3VSENSE
vs
TEMPERATURE
TEMPERATURE
32
30
3.314
3.310
3.306
3.302
3.298
28
26
24
22
-40
-10
0
25
Temperature (°C)
50
85
100 125 150
-40
-10
0
25
Temperature (°C)
50
85
100 125 150
G008
G009
Figure 12.
Figure 13.
A003
Figure 14. Load Transient Response, 10 mA to 550 mA
10
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TYPICAL CHARACTERISTICS (continued)
1.2-V Linear Regulator Controller (1.2 VO)
OUTPUT BASE DRIVE
1.2VSENSE
vs
TEMPERATURE
vs
TEMPERATURE
30
1.203
1.202
1.201
1.2
28
26
24
22
20
1.199
1.198
1.197
1.196
-40
-10
0
25
Temperature (°C)
50
85
100 125 150
-40
-10
0
25
Temperature (°C)
50
85
100 125 150
G010
G011
Figure 15.
Figure 16.
A004
Figure 17. Load Transient Response, 10 mA to 350 mA
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INTERNAL FUNCTIONAL BLOCKS
24 PGND
VIN_D
VIN
2
4
Buck Reg
Control
3
BOOT
1
PH
Wake
Up
COMP
EN
IGN_EN
RT/CLK
9
Network
14
22
COMP
VREG
OR
5
8
Error Amp
Ref
+
-
VSENSE
15
BG Ref
SS 20
-
+
3.3-V
19
18
3.3VDRIVE
3.3VSENSE
Linear
Regulator
Control
Internal
Reg
-
BOOT_LDO
6
0.8 V
+
10 5V
Regulator
Control
-
0.8 V
GND 12
+
1.2-V
Linear
Regulator
Control
1.2VDRIVE
17
16
1.2VSENSE
-
0.8 V
+
5-V Protected
Sensor Supply
Control
-
0.8 V
+
Reverse Protected
5VS
7
nRST
23
21
DELAY
1.2 V
VREG
3.3 V
Voltage Supervisor
with Reset Delay
Figure 18. Internal Functional Blocks
(pin numbers apply to TPS65301PWPRQ1)
PIN FUNCTIONS
Buck Supply, VIN_D
This is an input power source for the internal high-side MOSFET of the switch-mode power supply.
Phase Node for Buck Regulator, PH
This terminal provides the floating voltage reference for the internal drive circuitry.
Bootstrap, BOOT
The ceramic capacitor on this pin acts a as a voltage supply for the internal high-side MOSFET gate-drive
circuitry. The capacitor connects between the BOOT and PH terminals. Operating with a duty cycle of 100%
automatically reduces the duty cycle to approximately 95% on every fifth cycle to allow this capacitor to recharge.
Voltage-Sense Node, VSENSE
An internal resistor between VREG and this pin and another internal resistor between this pin and ground form
the voltage-sense network. This terminal is the inverting input for the error amplifier of the control loop. This input
is compared to an internal reference of 2 V for the control circuitry.
Error Amplifier Output, COMP
The error amplifier output forms a compensation network for the voltage mode control topology. The amplifier
changes state with increase in voltage output on this pin.
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Internal Regulated Boot Supply, BOOT_LDO
The internally regulated supply acts as a refresh power source for the bootstrap capacitor every switching cycle.
An external capacitor to ground is needed to stabilize the voltage source.
Clock Pulse, RT/CLK
A resistor to ground on this terminal sets the buck converter switching frequency. Alternatively, an external clock
input on this pin overrides the internal free-running clock (default value) by detecting positive edges of
consecutive pulses and synchronizing to the external input signal. If the external clock input is removed, the
system synchronizes to the internal clock signal of 2.2 MHz.
Output Voltage, VREG
This terminal represents the buck (step-down) output voltage VREG of the converter. The output voltage of the
buck-mode regulator is fixed at 5.45 V. This output requires a ceramic capacitor (4.7-µF to 10-µF range).
Ignition Enable Input, IGN_EN
The IGN_EN pin acts as an enable and disable input to activate the step-down power-supply output. The input is
high-voltage tolerant up to 45 V. An internal resistor limits current into this terminal for such high input voltage.
Logic Level Enable Input, EN
The EN pin is a logic-level disable input to all outputs when IGN_EN is low and all outputs are active.
Regulated Output, 5V
This terminal is the regulated output and requires a low-ESR ceramic capacitor to ground for loop stabilization.
This capacitor must be placed close to the pin of the IC. The output requires larger capacitance to compensate
for wide load transient steps.
Power-On Delay, DELAY
A capacitor on this pin sets the desired delay time. The output of this pin provides a source current to charge the
external capacitor once the VREG, 3.3-V and 1.2-V supplies have all exceeded the internally set threshold (0.9 ×
their respective regulated supply values).
3.3-V Drive Output, 3.3VDRIVE
This pin provides an output to drive an external bipolar transistor (BJT) for the 3.3-V supply. The output is
protected by current limiting of both the source and sink capabilities.
3.3-V Voltage Sense, 3.3VSENSE
This pin is the voltage node of 3.3-V supply. Voltage of approximately 1.65 V on this terminal initiates a current
foldback during shorts on the regulated output.
1.2-V Drive Output, 1.2VDRIVE
This pin provides an output to drive an external bipolar transistor (BJT) for the 1.2-V supply. The output is
protected by current limiting of both the source and sink capabilities.
1.2-V Voltage Sense, 1.2VSENSE
This pin is the voltage node of 1.2-V supply. Voltage of approximately 0.6 V on this terminal initiates a current
foldback during shorts on the regulated output.
Soft Start, SS
A ceramic capacitor is connected from this terminal to ground to set a soft-start timer for the buck regulator
supply. There is an internal pullup current source of 50 µA typical, which is activated on IGN_EN to charge the
external capacitor on the SS pin.
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Input Voltage, VIN
The VIN pin is the input power source for the device. This pin must be externally protected against voltage levels
greater than 45 V and against a reversed battery. This input line requires a filter capacitor to minimize noise.
Additionally, for EMI considerations, an input filter inductor may also be required.
Protected 5-V supply, 5VS
This terminal is the regulated protected sensor supply which requires a low ESR ceramic capacitor to ground for
loop stabilization. This capacitor must be placed close to the pin of the IC. The output is protected for shorts to
–1 V and VIN supply.
Reset Indicator, nRST
The nRST pin is an open-drain output. The power-on reset output is asserted low until the output voltages on the
VREG, 3.3-V, and 1.2-V supplies exceed their set thresholds and the power-on delay timer has expired.
Additionally, whenever the IGN_EN and EN_LIN_REG pins are low or open, nRST is immediately asserted low
regardless of the output voltage. If a thermal shutdown occurs due to excessive thermal, conditions this pin is
asserted low.
Ignition Input Status, IGN_ST
The IGN_ST pin is an open-drain output. This output indicates whether input signal IGN_EN is present.
Additionally, whenever the IGN pin is low or open, IGN_ST is immediately asserted low.
Power Ground, PGND
Power ground terminal, which is internally connected to the exposed thermal pad.
Ground, GND
Signal ground terminal, which is internally connected to the exposed thermal pad.
14
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DEVICE INFORMATION
Buck Converter
PWM Operation
The switch-mode power supply (SMPS) operates in a fixed-frequency pulse-width modulation (PWM) mode. The
switching frequency is set by an external resistor or synchronized with an external clock input. The internal N-
channel MOSFET is turned on (SET) at the beginning of each cycle. This MOSFET is turned off (RESET) when
the PWM comparator resets the latch. Once the high external FET is turned OFF, the external Schottky diode
recirculates the energy stored in the inductor for the remainder of the switching period.
The external bootstrap capacitor acts as a voltage supply for the internal high side MOSFET. This capacitor is
recharged on every recirculation cycle (when the internal high-side MOSFET is turned OFF). In the case of
commanding 100% duty cycle for the internal high side MOSFET, the device automatically revert to 87% to allow
the bootstrap capacitor to recharge.
Voltage-Mode Control Loop
The voltage-mode control monitors the set output voltage and processes the signal to control the internal
MOSFET. A voltage feedback signal is compared to a constant ramp waveform, resulting in a PWM modulation
pulse. An input line-voltage feedforward technique is incorporated to compensate for changes in the input voltage
and ensures the output voltage is stable by adjusting the ramp waveform for the correct duty cycle. The internal
MOSFET is protected from excess power dissipation with a current limit and frequency foldback circuitry during
an output-to-ground short-circuit event.
A combination of internal and external components forms a compensation network to ensure error-amplifier gain
does not cause instability due to input voltage changes or load perturbations.
Modes of Operation
The converter operates in different modes based on load current, input voltage, and component selection.
Continuous-Conduction Mode (CCM)
This mode of operation is typically when the inductor current is non-zero and the load current is greater than
IL CCM
.
(1- D)´ VREG
2´ fSW ´ L
IIND _ CCM
³
where
•
•
•
•
•
IIND_CCM = Inductor current in continuous-conduction mode
D = duty cycle
VREG = output voltage
L = Inductor
fSW = switching frequency
In this mode, the duty cycle should always be greater than the minimum tON or the converter may go into burst
mode.
Discontinuous Mode (DCM)
(1- D)´ VREG
IIND _DCM
³
2´ fSW ´ L
This mode of operation is typically when the inductor current goes to zero and the load current is less than
IIND DCM
.
Tracking Mode
When the input voltage is low and the converter approaches approximately 100% duty cycle, the following
equation determines the output voltage.
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t
æ
ç
è
OFF _MIN ö
VREG = 1-
´(VIN -ILoad ´ RDS)
ç
÷
÷
T
ø
where
•
•
•
t = Period
RDS = Internal FET resistance
ILOAD = output load current
Output Voltage 5.45 V (VREG)
Output voltage VREG is generated by the converter supplied from the battery voltage VIN and the external
components (L, C). The output is sensed through an internal resistor divider and compared with an internal
reference voltage.
This output requires larger output capacitors (4.7-µF to 10-µF range) to ensure that during load transients the
output does not drop below the reset threshold for a period longer than the reset deglitch filter time.
An internal load is enabled for a short period whenever
•
•
a start-up condition occurs, that is, during power up or when IGN_EN or EN is toggled.
an overvoltage condition exists on this output.
Switching Frequency (RT/CLK)
The oscillator frequency of the buck regulator is selectable by means of a resistor placed at the RT/CLK pin to
ground. The switching frequency (fSW) can be set in the range 2 MHz to 3 MHz in this resistor mode.
Alternatively, if there is an external clock input signal, the internal oscillator synchronizes to this signal within 10
µs.
The following equation determines the value of resistor (RT) for the required switching frequency fSW
.
98.4´109
RT =
(Ohms)
fSW
Boost Capacitor (BOOT)
This capacitor provides the gate-drive voltage for the internal MOSFET switch. X7R and X5R grade dielectrics
are recommended due to their stable values over temperature. It may be necessary to select a lower value of
boost capacitor for low-VREG and/or high-frequency applications, or to select a higher value for high-VREG
and/or low-frequency applications (for example, 100 nF for 500 kHz / 5 V and 220 nF for 500 kHz / 8 V.) Usually,
a 0.1-µF capacitor is used for the boot capacitor.
Soft Start (SS)
To limit the start-up inrush current for the switch-mode supply, an internal soft-start circuit is used to ramp up the
reference voltage from 0 V to its final value of 0.8 V. The regulator uses the internal reference or the SS-pin
voltage as the power-supply reference voltage to regulate the output accordingly. The following equation
determines the soft-start timing.
C´ 0.8 V
50´10-6
Time (tSS ) =
where
•
C = Capacitor on SS pin, usually 0.1 µF or lower
Power-On Delay (DELAY)
The power-on delay function delays the release of the nRST line. The method of operation is to detect when all
VREG (5.45 V), 3.3-V and 1.2-V power-supply outputs are above 90% (typical) of the set value. This then
triggers a current source to charge the external capacitor on the DELAY terminal. Once this capacitor is charged
to approximately 2 V, the nRST line is asserted high. The delay time is calculated using the following equation:
2 V ´ C
tDELAY
=
2 mA
16
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where
•
C = capacitor on DELAY pin
Example: For a 20-ms delay, C = 20 nf.
Reset (nRST)
The nRST pin is an open-drain output. The power-on reset signal is a voltage supervisor output to indicate the
output voltages on VREG (5.45 V), 3.3 V, and 1.2 V are within the specified tolerance of their set regulated
voltages. Additionally, whenever both the IGN_EN and EN pins are low or open, nRST is immediately asserted
low regardless of the output voltage. If a thermal shutdown occurs due to excessive thermal conditions, this pin is
asserted low.
Conversely on power down, once the VREG or 3.3V or 1.2V output voltage falls below 90% of its respective set
threshold, nRST is pulled low after a de-glitch filter delay of approximately 15 µs (max). This is implemented to
prevent nRST from being invoked due to noise on the output supplies.
Thermal Shutdown
This device has independent two thermal sensing circuits for the VREG (5.45 V), 5-V regulators; if either one of
these circuits detects the power FET junction temperature to be greater than the set threshold, that particular
output-power switch is turned OFF. The appropriate FET turns back ON once it is allowed to cool sufficiently.
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Reset Function
Vin
SS
Vin
SS
Approx 0.9 x 1.2 Vout
1.2Vout
Approx 0.9 x 1.2 Vout
1.2Vout
Approx 0.9 x 3.3 Vout
3.3Vout
VREG
Approx 0.9 x 3.3 Vout
3.3Vout
5.45 V (typ)
5.45 V (typ)
Approx 4.91 V
VREG
2 V
DELAY
DELAY
nRST
tdelay
nRST
15µs(max- deglitch time)
On power up, ALL three regulated supplies,
VREG, 3.3 V and 1.2 V have to be more than
90% of their respective value before the delay
timer capacitor on delay pin can start charging
On power down, if any one of the three regulated
supplies, VREG, 3.3 V and 1.2 V drops below the
90% RIꢀLW¶VꢀYDOXHꢀQ567ꢀLVꢀDVVHUWHGꢀORZꢀDIWHUꢀDꢀVPDOOꢀ
deglitch filter time. Once nRST is asserted low, it can
only go high again after ALL three supplies are above
the 90% value and delay pin voltage higher than 2 V.
Figure 19. Reset Function
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Linear Regulators
Fixed Linear Regulator Output (5 V)
This is a fixed, regulated output of 5 V ±2% over temperature and input supply using a precision voltage-sense
resistor network. A low-ESR ceramic capacitor is required for loop stabilization; this capacitor must be placed
close to the pin of the IC. This output is protected against shorts to ground by a foldback current limit for safe
operating conditions, and a current limit for limiting inrush current due to depleted charge on the output capacitor.
Initial IGN_EN or EN initiates power cycle of the soft-start circuit on this regulator. The soft-start takes typically
13 ms. This output may require a larger output capacitor to ensure that during load transients the output does not
drop below the required regulated specifications.
Fixed Linear Regulator Controller (3.3 V)
The linear regulator controller requires an external NPN bipolar pass transistor of sufficient gain stage to support
the maximum load current required. The base-drive output current is protected by current limiting both the source
and sink drive circuitry. The 3.3VSENSE pin is the remote sense input of the output of the REG3 supply and
controls the 3.3VDRIVE output accordingly. This regulator is fixed 3.3 V with ±2% tolerance using a precision
voltage-sense resistor network. A low-ESR ceramic output capacitor is used for loop compensation of the
regulator. A voltage on this pin of less than approximately 50% of the regulated value initiates a current limit on
the 3.3VDRIVE output.
This output may require larger output capacitors to support load transients, so the output does not drop below
90% of 3.3 V.
Fixed Linear Regulator Controller (1.2 V)
The linear regulator controller requires an external NPN bipolar pass transistor of sufficient gain stage to support
the maximum load current required. The 1.2VSENSE pin is the remote sense input of the output of 1.2-V supply
and controls the 1.2VDRIVE output accordingly. This regulator output is 1.2 V with ±2% tolerance using a
precision voltage-sense resistor network. A low-ESR ceramic output capacitor is used for loop compensation of
the regulator. A voltage on this pin of less than approximately 50% of the regulated value initiates a current limit
on the 1.2VDRIVE output.
This output may require larger output capacitors to support load transients, so the output does not drop below
90% of 1.2 V.
Protected Sensor Supply Output, (5VS)
This is a fixed regulated output from of 5 V ±2% over temperature and input supply using precision voltage sense
resistor network. A low ESR ceramic capacitor is required for loop stabilization; this capacitor must be placed
close to the pin of the IC. This output is protected against shorts to ground by a fold back current limit for safe
operation conditions, and a current limit for limiting in-rush current due to depleted charge on the output
capacitance. This output is also protected against shorts to battery voltage by limiting the reverse current. This
supply can thus be used to power a sensor outside the electrical control unit ECU. On initial IGN_EN or EN
power cycle the soft start circuit on this regulator is initiated. The soft-start takes typically 10 ms. This output may
require larger output capacitor to ensure that during load transients the output does NOT drop below the required
regulated specifications.
Modes of Operation
Operational Mode
The purpose of the EN input is to keep the regulated supplies ON for a period for the microprocessor to log
information into the memory locations once the ignition input is disabled. The microprocessor disables the power
supplies by pulling EN low after this activity is complete.
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APPLICATION INFORMATION
This is a starting point and theoretical representation of the values to be used for the application, further
optimization of the components derived may be required to improve the performance of the device.
Buck Converter
Duty Cycle
VO
D =
V
I
where
•
•
VO = Output voltage
VI = Input voltage
Output Inductor Selection (L)
The minimum inductor value is calculated using the coefficient KIND that represents the amount of inductor ripple
current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor, and
so the typical range of this ripple current is in the range of KIND = 0.2 to 0.3, depending on the ESR and the
ripple-current rating of the output capacitor.
Inductor ripple current
IRipple = KIND ´ IO
where
•
IO = Output current
Benefits of Low Inductor Value
•
•
•
•
Low inductor value gives high di/dt, which allows for fewer output capacitors for good load transient response.
Gives higher saturation current for the core due to fewer turns
Fewer turns yields low DCR and therefore less dc inductor losses in the windings.
High di/dt provides faster response to load steps.
Benefits of High Inductor Value
•
•
•
•
Low ripple current leads to lower conduction losses in MOSFETs
Low ripple; means lower RMS ripple current for capacitors
Low ripple; yields low ac inductor losses in the core (flux) and windings (skin effect)
Low ripple; gives continuous inductor current flow over a wide load range
(VI-Max - V O )´ VO
LMin
=
fSW ´ IRipple ´ VI-Max
where
•
•
fSW = the regulator switching frequency
IRipple = Allowable ripple current in the inductor, typically ±20% of maximum output load IO
Inductor Peak Current
IRipple
IL-Peak = IO +
2
Output Capacitor Selection (CO)
The selection of the output capacitor determines several parameters in the operation of the converter, the
modulator pole, the voltage droop on the out capacitor, and the output ripple.
20
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During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the
output voltage above a certain level for a specified time and not issue a reset until the main regulator control loop
responds to the change. The capacitance value determines the modulator pole and the rolloff frequency due to
the LC output-filter double pole—the output ripple voltage is a product of the output capacitor ESR and ripple
current.
The minimum capacitance needed to maintain desired output voltage during a high-to-low load transition and
prevent overshoot is
2
L (IO-max )2 - (IO-min
)
(
)
CO
=
2
(VO-max )2 - (VO-min
)
where
•
•
Io-max is maximum output current
Io-min is minimum output current
The difference between the output current, maximum to minimum, is the worst-case load step in the
system.
•
•
Vo-max is maximum tolerance of regulated output voltage
Vo-min is the minimum tolerance of regulated output voltage
Output capacitor root-mean-square (RMS) ripple current IO_RMS. This is to prevent excess heating or failure due
to high ripple currents.
This parameter is sometimes specified by the manufacturer.
VO ´(VI-max - VO )
IO _RMS =
12 ´ VI-max ´L ´ fSW
External Schottky Diode (D)
The TPS65301-Q1 requires an external ultrafast Schottky diode with fast reverse-recovery time connected
between the PH and power ground terminals. The diode conducts the output current during the off-state of the
internal power switch. This diode must have a reverse breakdown higher than the maximum input voltage of the
application. A Schottky diode is selected for its lower forward voltage. The Schottky diode is selected based on
the appropriate power rating, which factors in the dc conduction losses and the ac losses due to the high
switching frequencies. The power dissipation PD is determined by
(VI - VFD )2 ´ fSW ´CJ
PD = IO ´ VFD ´(1- D) +
where
•
•
VFD = forward conducting voltage of Schottky diode
CJ = junction capacitance of the Schottky diode
Input Capacitor (CI)
The TPS65301-Q1 requires an input ceramic decoupling capacitor type X5R or X7R and bulk capacitance to
minimize input ripple voltage. The dc voltage rating of this input capacitance must be greater than the maximum
input voltage. The capacitor must have an input ripple-current rating higher than the maximum input ripple
current of the converter for the application. The input capacitors for power regulators are chosen to have
reasonable capacitance-to-volume ratio and to be fairly stable over temperature. The value of the input
capacitance is based on the input voltage desired (∆VI).
I
O-max ´ 0.25
CI =
DVI ´ fSW
Input capacitor root-mean-square (RMS) ripple current II_RMS is calculated using the following equation.
æ
ç
ç
è
ö
÷
÷
ø
VI_min - VO
VO
II_RMS = IO
´
´
VI_min
VI_min
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Loop Compensation
The double pole is due to the output-filter components inductor and capacitor. The calculations for the following
equations use values taken from Figure 20.
Loop-Control Frequency Compensation
Internal
compensation
L
C2 = 20 pf
C4 = 140 pf
R3 = 8k
VO = VREG
C
C
ESR
R4 = 163.36k
R2
C3
C
O
VSENSE
R5 = 94.7K
COMP
Vref = 2 V
Internal Resistor
Divider
Type 3 Compensation
Figure 20. Loop-Control Frequency Compensation
Type III Compensation
fCO = fSW × 0.1 (the cutoff frequency when the gain is 1 is called the unity-gain frequency).
fCO is typically 1/5 to 1/10 of the switching frequency double-pole frequency response due to the LC output filter.
The LC output filter gives a double pole, which has a –180° phase shift.
½
Make the two zeroes close to the double pole (LC), for example, fZ1 ≈ fZ2 ≈ ½π(LCOUT) .
1. Make the first zero below the filter double pole (approximately 50% to 75% of fLC
2. Make the second zero at the filter double pole (fLC
Make the two poles above the crossover frequency fCO
3. Make the first pole at the ESR frequency (fESR
4. Make the second pole at 0.5 the switching frequency
)
)
.
)
The following compensation components are integrated in the device with the following typical values. Guidelines
for compensation components:
R3 = 8 kΩ, C4 = 140 pF, C2 = 20 pF
The double pole to due to the output filter components LC,
1
fLC
=
2p LCO
22
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
The ESR of the output capacitor C gives a zero that has a 90° phase shift. The ESR of the output capacitor
should be in the range of 1 mΩ to 100 mΩ.
1
fESR
=
2p´ CO ´ESR
PWM Modulator Gain K
V
I
K =
V
ramp
where
•
Vramp = VI / 10, VI = Input operating voltage
Resistor Values
Select R5 = 94.7 kΩ
R5´(VO - V
R4 =
)
ref
,
where V = 2 V
ref
V
ref
f
CO ´ Vramp ´ R4
LC ´ VI
R2 =
f
Calculate C3 based on placing a zero at 50% to 75% of the output-filter double-pole frequency (below set at
50%).
1
C3 =
p´R2´ fLC
Gain of Amplifier
R2´(R4 + R3)
=
(R4´R3)
AV
Poles and Zero Frequencies
1
fP1
=
2p´R2´ C2
1
fP2
=
2p´R3´ C4
1
fZ1
=
2p´R2´ C3
1
fZ2
=
2p´R4´ C4
Copyright © 2013, Texas Instruments Incorporated
23
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
Open Loop Error
Amp Gain
fZ1 fZ2
fP1 fP2
Modulator Gain
Compensation
Gain
Closed Loop Gain
fLCo
fESR
Frequency
Figure 21. Typical Gain vs Frequency
Power Dissipation
Switch-Mode Power-Supply Losses
The power dissipation losses are applicable for continuous-conduction mode operation (CCM).
A
P5.45V_CON = IO2 × Rds(on) × (VO/VI) (Conduction losses)
A
P5.45V_SW = ½ × VI × IO × (tr + tf) × fSW (Switching losses)
A
P5.45V_Gate = Vdrive × Qg × fsw (Gate drive losses)
where typically Qg = 1 × 10–9 (nC)
A
PIC = VI × Iq-normal (Supply losses)
A
PTotal = PCON + PSW + PGate + P5V_Lin Reg + PIC
where
VO = VREG = Output voltage
VI = Input voltage
IO = Output current
tr = FET switching rise time (tr max. = 20 ns)
tf = FET switching fall time (tf max. = 20 ns)
Vdrive = FET gate-drive voltage (typically Vdrive = 6 V and Vdrive max. = 8 V)
fSW = Switching frequency
Linear Regulator (5V) and Sensor Supply (5VS):
P5V_Lin Reg = (VREG – 5 V) × IO_5V
24
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
P5VS_Lin Reg = (VREG – 5 V) × IO_5VS
Total Power Dissipation
PIC = VI × Iq-normal (Supply losses)
PTotal = PCON + PSW + PGate + P5V_Lin Reg + P5VS_Lin Reg + PIC
For given operating ambient temperature TA
TJ = TA + Rth × PTotal
For a given max junction temperature TJ-Max = 150°C
TA-Max = TJ-Max – Rth × PTotal
where
PTotal = Total power dissipation (watts)
TA = Ambient temperature in °C
TJ = Junction temperature in °C
TA-Max = Maximum ambient temperature in °C
TJ-Max = Maximum junction temperature in °C
Rth = Thermal resistance of package in (°C/W)
Other factors not included in the foregoing information which affect the overall efficiency and power losses are
•
•
•
Inductor AC and DC losses
Trace resistance and losses associated with the copper trace routing connection
Schottky diode
PCB Layout
The following guidelines are recommended for PCB layout of the TPS65301-Q1 device.
Inductor L
Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors may be used; however, they
must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.
Input Filter Capacitors CI
Input ceramic filter capacitors should be located in close proximity to the VIN terminal. Surface-mount capacitors
are recommended to minimize lead length and reduce noise coupling.
Feedback
Route the feedback trace such that there is minimum interaction with any noise sources associated with the
switching components. Recommended practice is to ensure placing the inductor away from the feedback trace to
prevent a source of EMI noise.
Traces and Ground Plane
All power (high-current) traces should be thick and as short as possible. The inductor and output capacitors
should be as close to each other as possible. This reduces EMI radiated by the power traces due to high
switching currents.
In a two-sided PCB it is recommended to have ground planes on both sides of the PCB to help reduce noise and
ground-loop errors. The ground connection for the input and output capacitors and IC ground should be
connected to this ground plane.
In a multi-layer PCB, the ground plane is used to separate the power plane (where high switching currents and
components are placed) from the signal plane (where the feedback trace and components are) for improved
performance.
Copyright © 2013, Texas Instruments Incorporated
25
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
Also arrange the components such that the switching-current loops curl in the same direction. Place the high-
current components such that during conduction the current path is in the same direction. This prevents magnetic
field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI.
Application Notes
Design Guide – Step-by-Step Design Procedure
Following are the details of a switching regulator design using the requirements of Table 1.
Table 1. Switching Regulator Requirements
Parameter
Requirement
Input voltage, VI
6.5 V to 27 V, typical 14 V
5.45 VO ±2% at 6.3 W
1 A
Output voltage, 5.45 V
Maximum output current I5.45V_max
Minimum output current I5.45V_min
Transient response 0.01 A to 0.8 A
Reset threshold
0.01 A
5%
90% of output voltage
5 VO at 1 W
5 V
3.3 V
3.3 VO at 1 W
1.2 VO at 0.5 W
5 VO at 0.5 W
2.5 MHz
1.2 V
5VS
Switching frequency fSW
Overvoltage threshold
Undervoltage threshold
106% of output voltage
95% of output voltage
VIN_D
2
4
BOOT
S1
3
1
0.1 µF
L
6.3W
Supply
PH
VIN
EN
5.45 V
10 µF
10 µH
R2
10 µf
S2
9
14
22
30k
COMP
VREG
IGN_EN
RT/CLK
5
8
Vign
6k
1 nF
C3
15
R1
C1
VSENSE
SS
20
TPS65301PWPR-Q1
3k
PSS302NZ
2.2 µF
11
6
3.3VDRIVE
IGN_ST
1W
19
18
BOOT_LDO
3.3 V
3.3VSENSE
5 V
1 µF
1W
GND
5VS
10
23
5V
12
7
2.2 µF
3k
0.5W
5VS
nRST
2.2 µF
C2
1.2VDRIVE
1.2VSENSE
PSS302NZ
2.2 µF
0.48W
DELAY
17
16
21
1.2 V
L: B82462G4103MOOO (EPCOS) or XFL4020 472MEB (Coilcraft)
S1: MBRS310T3 (ON Semiconductors) or SS3H10 (Vishay)
S2: B240A, SS16 (Vishay)
External BJT: PBSS302NZ (NXP)
Figure 22. Application Schematic
26
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
Duty Cycle
VO
D =
5.45
14
=
= 0.389
V
I
Output Inductor Selection (L)
IRipple = KIND ´IO = 0.25 ´ 1 = 0.25 A
(V
- VO )´ VO
(27 - 5.45)´5.45
I-Max
LMin
=
=
= 7mH
fSW ´IRipple ´ V
2.5 MHz ´ 0.25´ 27
I-Max
Use 10 µH due to variations in temperature and manufacture.
Inductor peak current:
IRipple
0.25
2
IL-Peak = IO
+
= 1+
= 1.125 A
2
Output Capacitor Selection (CO)
2
2
é
ë
ù
û
L
I
- I
(
)
(
)
O-max
O-min
ê
ú
CO
=
2
2
V
-
V
(
)
(
)
O-max
O-min
10´10-6((1)2 - (0.01)2 )
(5.60)2 - (5.30)2
CO
=
= 3.06mF
Due to variations in temperature and manufacture, use a 10-µF capacitor with a voltage rating greater than the
maximum 10-V output.
VO ´(VI-max - VO )
IO _RMS
=
12 ´ VI-max ´L ´ fSW
5.45´(27 - 5.45)
12 ´ 27´10´10-6 ´ 2.5´106
IO _RMS
=
= 0.050A
External Schottky Diode (D) Power Dissipation
(VI - VFD )2 ´ fSW ´CJ
PD = IO ´ VFD ´(1- D) +
(14 - 0.55)2 ´ 2.5´106 ´30´10-12
PD = 1´ 0.55´(1- 0.389) +
= 0.34W
Input Capacitor (CI)
O _max ´ 0.25
CI =
I
1´ 0.25
0.3´ 2.5´106
=
= 0.33mF
DV ´ fSW
I
Due to variations in temperature and manufacture, use a 10-µF capacitor with a voltage rating greater than the
maximum 45-V transient.
Input-capacitor root-mean-square (RMS) ripple current II_RMS
:
æ
ç
ç
è
ö
÷
÷
ø
V
- VO
VO
5.45
6
6 - 5.45
æ
ö
I_min
I
= IO ´
´
= 1´
´
= 0.29A
I_RMS
ç
÷
V
V
6
è
ø
I_min
I_min
Copyright © 2013, Texas Instruments Incorporated
27
TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
Loop Compensation
The double pole is due to the output filter components LC, and the calculations in the formulas refer to Figure 20.
1
1
fLC
=
=
2p LCO 2p 10 mH´10mF
= 15.9 kHz
1
1
fESR
R4 =
R2 =
=
=
2p´ CO ´ESR 2p´10 mF´ 0.005
= 3.2 MHz
R5´(VO - Vref)
94.7 kΩ ´(5.45 - 2)
=
= 163.36 kΩ
Vref
2
f
CO ´ Vramp ´R4
250 kHz ´1.4´163.36 kΩ
15.9 kHz ´14
=
= 256.9 kΩ
f
LC ´ V
I
Calculate C3 based on placing a zero at 50% to 75% of the output-filter double-pole frequency.
1
1
C3 =
=
= 786 pF
p´R2´ fLC p´ 256.9 kΩ ´15.9 kHz
Poles and Zero Frequencies
1
1
fP1
fP2
fZ1
fZ2
=
=
= 30.98 kHz
2p´R2´ C2 2p´ 256.9 kΩ ´20 pF
1
1
=
=
= 142.1 kHz
2p´R3´ C4 2p´ 8 kΩ ´140 pF
1
1
=
=
= 7.93 kHz
= 6.77 kHz
2p´R2´ C3 2p´ 264.2 kΩ ´76 pF
1
1
=
=
2p´R4´ C4 2p´168 kΩ ´140 pF
Power Dissipation
P5.45V _ CON = IO ´RdsON ´(VO / V ) = 12 ´0.5´(5.45 / 14) = 0.195 W
2
I
P5.45_SW = 1/ 2´ V ´IO ´(tr + tf)´ fSW
I
= 1/ 2´14´1´(20 ns + 20 ns)´ 2.5 MHz = 0.7 W
P5.45V_Gate = Vdrive ´Qg ´ fSW = 8´1 nC´ 2.5 MHz = 0.02 W
P5V _Lin _Reg = (VREG - 5 V)´IO = (5.45 - 5)´0.2 = 0.09 W
P5VS _Lin _Reg = (VREG - 5 V)´IO = (5.45 - 5)´0.1= 0.045 W
P
= V ´I = 14´ 5.47 mA = 0.08 W
I IC
IC
PTotal = P5.45V _ CON + P
+ P
+ P
+ P
+ P
5.45V _ SW
5.45V _ Gate
5V _LinReg
5VS _LinReg IC
= 0.195 + 0.7 + 0.02 + 0.09 + 0.045 + 0.08 = 1.13 W
28
Copyright © 2013, Texas Instruments Incorporated
TPS65301-Q1
www.ti.com.cn
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
JESD51-5
3.0
2.0
1.0
45
80
115
150
Ambient Temperature (°C)
Figure 23. Power Dissipation Derating Profile, 24-Pin PWP Package With Thermal Pad
S2
10 µf
L
nRST
TPS65301PWPRQ1
PH
PGND 24
nRST 23
5.45 V
1
2
3
4
5
6
3k
VIN_D
0.1 µF
BOOT
VIN
VREG 22
S1
C2
DELAY 21
SS 20
Supply
10 µF
IGN_EN
C1
6k
BOOT_LDO
3.3VDRIVE 19
3.3VSENSE 18
30k
1 nF
1 µF
2.2 µF
3.3 V
1.2 V
T2
Vign
5VS
7
8
9
5VS
2.2 µF
RT/CLK
17
1.2VDRIVE
R1
T1
Enable
EN
1.2VSENSE 16
2.2 µF
C3
2.2 µF
15
10
11
12
5V
VSENSE
5V
3k
IGN_ST
COMP 14
IGN_ST
R2
Exposed PAD
Connected to
Ground Plane
NC
13
GND
Connection to backside of PCB through vias
Connection to topside of PCB through vias
Connection to ground plane of PCB through vias
Power bus
Voltage Output rails
T1, T2 are PSS302NZ, sufficent heat sink may be required for
power dissipation
Figure 24. PCB Layout
Copyright © 2013, Texas Instruments Incorporated
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TPS65301-Q1
ZHCSBV9B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
修订历史记录
Changes from Revision A (November 2013) to Revision B
Page
•
•
•
•
•
Changed 在 特性 列表中，将运行结温范围从 -40°C 至 150°C 改为最高 150°C .................................................................. 1
Changed DC CHARACTERISTICS condition statement from TJ = –40°C to 150°C to TJ-Max = 150°C ................................ 3
Changed DC CHARACTERISTICS condition statement from TJ = –40°C to 150°C to TJ-Max = 150°C ................................ 4
Changed DC CHARACTERISTICS condition statement from TJ = –40°C to 150°C to TJ-Max = 150°C ................................ 5
Changed Y-axis name from Current (mA) to Efficiency in the EFFICIENCY vs OUTPUT CURRENT ON VREG
graph in the TYPICAL CHARACTERISTICS section ........................................................................................................... 8
•
Added OUTPUT VOLTAGE vs OUTPUT CURRENT graph to TYPICAL CHARACTERISTICS section ............................. 8
Changes from Original (October 2013) to Revision A
Page
•
•
•
•
Changed 文档状态从 产品预览 改为生成数据 ...................................................................................................................... 1
Changed min value for VIL in the DC CHARACTERISTICS table from 2 to 2.2 .................................................................. 3
Deleted the 5VS oft-start time, TSS, parameter from the DC CHARACTERISTICS table .................................................... 5
Changed the min, typ, and max values for the nRST parameter for VREG output from 0.87, 0.9, and 0.93 to 0.845,
0.875, and 0.905 respectively ............................................................................................................................................... 5
30
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65301QPWPRQ1
ACTIVE
HTSSOP
PWP
24
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS65301
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65301QPWPRQ1 HTSSOP PWP
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 24
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPS65301QPWPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 24
4.4 x 7.6, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
PACKAGE OUTLINE
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC SMALL OUTLINE
6.6
6.2
SEATING PLANE
C
TYP
PIN 1 ID
A
0.1 C
AREA
22X 0.65
24
1
2X
7.9
7.7
NOTE 3
7.15
12
13
0.30
24X
4.5
4.3
0.19
B
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
2.40
1.65
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
(
0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
SYMM
BASED ON
0.125 THICK
STENCIL
22X (0.65)
13
12
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
0.125
0.15
0.175
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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