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TPS65653-Q1

ZHCSJI6 –MARCH 2019

TPS65653-Q1 双路 3A 降压转换器

1 特性

2 应用

1

•

下列性能符合 AEC-Q100 标准：

•

雷达系统 ECU

汽车音响主机和仪表组

汽车摄像头模块

环视系统 ECU

汽车显示屏

–

器件温度 1 级：-40°C 至 +125°C 的环境工作温

度范围

•

输入电压：2.8V 至 5.5V

两个高效降压直流/直流转换器：

–

输出电压：1V 至 3.36V

最大输出电流为每相 3A

3 说明

TPS65653-Q1 设计用于为雷达等噪声敏感型应用提供

严格的电源规范。该器件包含两个降压直流/直流转换

器以及通用数字输出信号。该器件由 I²C 兼容串行接口

和使能信号进行控制。

可编程输出电压压摆率范围：0.5mV/µs 至

10mV/µs

–

4MHz 开关频率

用于降低 EMI 的扩频模式和相位交错

•

可配置通用输出信号（GPO、GPO2）

自动 PWM/PFM（AUTO 模式）操作可在较宽输出电

流范围内最大限度地提高效率。TPS65653-Q1 支持远

程电压检测，可补偿稳压器输出与负载点 (POL) 之间

的 IR 压降，从而提高输出电压的精度。此外，可以强

制开关时钟进入 PWM 模式以及将其与外部时钟同

步，从而最大限度地降低干扰。

I²C 兼容接口，支持标准 (100kHz)、快速

(400kHz)、快速+ (1MHz) 和高速 (3.4MHz) 模式

•

具有可编程屏蔽的中断功能

可编程电源正常信号 (PGOOD)

外部时钟输入以同步开关

输出短路和过载保护

TPS65653-Q1 器件支持可编程启动和关断延迟与排序

（包括与使能信号同步的 GPO 信号）。在启动和电压

变化期间，器件会对输出转换率进行控制，从而最大限

度地减小输出电压过冲和浪涌电流。

过热警告和保护

过压保护 (OVP) 和欠压锁定 (UVLO)

具有可湿性侧面的 28 引脚、5mm × 5mm VQFN

封装

简化原理图

器件信息

器件型号

封装

VQFN (28)

封装尺寸（标称值）

VIN

VOUT_B0

TPS65653-Q1

5.00mm × 5.00mm

VIN_B0

VIN_B1

SW_B0

FB_B0

LOAD

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

VIN

VANA

VOUT_B1

直流/直流效率与输出电流

SW_B1

FB_B1

SDA

SCL

nINT

EN

DC/DC Efficiency vs Output Current

100

CLKIN (GPO2)

GPO

90

80

70

PGOOD

GNDs

60

Vin = 3.3V, Vout = 1V, AUTO

Vin = 3.3V, Vout = 1.8V, AUTO

Vin = 3.3V, Vout = 2.5V, AUTO

50

0.001

0.01

0.1

Load (A)

1

3

Fron

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSF06

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 29

7.5 Programming........................................................... 30

7.6 Register Maps......................................................... 33

Application and Implementation ........................ 47

8.1 Application Information............................................ 47

8.2 Typical Application .................................................. 47

Power Supply Recommendations...................... 53

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 I²C Serial Bus Timing Parameters.......................... 10

6.7 Typical Characteristics............................................ 12

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description ................................................ 14

8

9

10 Layout................................................................... 53

10.1 Layout Guidelines ................................................. 53

10.2 Layout Example .................................................... 54

11 器件和文档支持 ..................................................... 55

11.1 器件支持................................................................ 55

11.2 接收文档更新通知 ................................................. 55

11.3 社区资源................................................................ 55

11.4 商标....................................................................... 55

11.5 静电放电警告......................................................... 55

11.6 术语表 ................................................................... 55

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 3 月

*

初始发行版

2

TPS65653-Q1

www.ti.com.cn

ZHCSJI6 –MARCH 2019

5 Pin Configuration and Functions

RHD Package

28-Pin VQFN With Thermal Pad

Top View

21

20

19

18

17

16

15

SW_B0

VIN_B0

GPO

SW_B1

VIN_B1

CLKIN

nINT

22

23

24

25

26

27

28

14

13

12

11

10

9

THERMAL PAD

PGOOD

VIN

8

1

2

3

4

5

6

7

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NUMBER

NAME

NC

1

2

3

4

5

O

A

Unused. Leave this pin floating.

FB_B0

FB_B1

AGND

VANA

Output voltage feedback (positive) for Buck 0

Output voltage feedback (positive) for Buck 1

Ground

A

G

P/I

Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.

Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin

floating.

6

EN

D/I

7

8

9

NC

VIN

O

I

Unused. Leave this pin floating.

Unused. Connect this pin to VANA.

nINT

D/O

Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground.

External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is not

used, leave the pin floating.

10

CLKIN

D/I/O

P/I

Input for Buck 1. The separate power pins VIN_Bx are not connected together internally -

VIN_Bx pins must be connected together in the application and be locally bypassed.

11, 12

VIN_B1

SW_B1

13, 14

15, 16

P/O

P/G

Buck 1 switch node. If the Buck 1 is not used, leave the pin floating.

Power ground for Buck 1

PGND_B1

Serial interface clock input for I²C access. Connect a pullup resistor. If the I²C interface is not

used, connect the pin to Ground.

17

SCL

D/I

Serial interface data input and output for I²C access. Connect a pullup resistor. If the I²C

interface is not used, connect the pin to Ground.

18

19

SDA

D/I/O

G

SGND

Ground

(1) A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

3

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NUMBER

20, 21

NAME

PGND_B0

SW_B0

P/G

P/O

Power ground for Buck 0

Buck 0 switch node. If the Buck 0 is not used, leave the pin floating.

22, 23

Input for Buck 0. The separate power pins VIN_Bx are not connected together internally -

VIN_Bx pins must be connected together in the application and be locally bypassed.

24, 25

VIN_B0

P/I

26

27

28

GPO

PGOOD

VIN

D/O

I

General-purpose digital output. If the pin is not used, leave the pin floating.

Power-good indication signal. If the pin is not used, leave the pin floating.

Unused. Connect this pin to VANA.

Thermal

Pad

—

Connect to PCB ground plane using multiple vias for good thermal performance.

4

TPS65653-Q1

www.ti.com.cn

ZHCSJI6 –MARCH 2019

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

MAX

UNIT

Voltage on power connections (must use the same

VIN, VIN_Bx, VANA

input supply)

–0.3

6

V

(VIN_Bx + 0.3 V) with 6-V

maximum

SW_Bx

Voltage on buck switch nodes

–0.3

V

(VANA + 0.3 V) with 6-V

maximum

FB_Bx

Voltage on buck voltage sense nodes

Voltage on logic pins (input or output pins)

(VANA + 0.3 V) with 6-V

maximum

SDA, SCL, nINT, EN

PGOOD, GPO, CLKIN

(GPO2)

(VANA + 0.3 V) with 6-V

maximum

T_J-MAX

T_stg

Junction temperature

Storage temperature

−40

150

260

–65

°C

Maximum lead temperature (soldering, 10 seconds)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

All pins

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per AEC

Q100-011

Corner pins (1, 7, 8, 14,

15, 21, 22, 28)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

INPUT VOLTAGE

Voltage on power connections (must use the same input

supply)

VIN, VIN_Bx, VANA

2.8

5.5

V

EN, nINT

Voltage on logic pins (input or output pins)

Voltage on logic pins (input pin)

Voltage on logic pins (output pins)

0

5.5

VANA

V

CLKIN

PGOOD, GPO, GPO2

Voltage on I2C interface, Standard (100 kHz), Fast (400

kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes

0

1.95

V

SCL, SDA

Voltage on I2C interface, Standard (100 kHz), Fast (400

kHz), and Fast+ (1 MHz) Modes

VANA with 3.6-V

maximum

TEMPERATURE

T_J

Junction temperature

Ambient temperature

−40

140

125

°C

T_A

5

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

6.4 Thermal Information

TPS65653-Q1

THERMAL METRIC⁽¹⁾

RHD (VQFN)

28 PINS

36.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJCtop

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.6

8.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

8.8

R_θJCbot

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

note.

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx},V_{VOUT_Bx}, and I_OUTrange,

unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1 V, unless otherwise noted.⁽¹⁾⁽²⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL COMPONENTS

Input filtering

C_{IN_VANA}

Effective capacitance, connected from VANA

to AGND

100

10

nF

µF

capacitance for VANA

Input filtering

Effective capacitance, connected from VIN_Bx

to PGND_Bx

C_{IN_BUCK}

capacitance for buck

regulators

1.9

10

Output filtering

C_{OUT_BUCK}

capacitance for buck

regulators, local

Effective capacitance

POL capacitance

22

µF

Point-of-load (POL)

capacitance for buck

regulators

C_{POL_BUCK}

Total output capacitance, VIN_Bx ≤ 4 V and

Slew rate ≤ 3.8 mV/µs

150

100

µF

C_OUT-

TOTAL_BUCK

Buck output capacitance,

total (local and POL)

Total output capacitance, VIN_Bx > 4 V

Total output capacitance, Slew rate > 3.8

mV/µs

Input and output

capacitor ESR

ESR_C

[1-10] MHz

2

10

mΩ

0.47

L

Inductor

Inductance of the inductor

µH

–30%

30%

DCR_L

Inductor DCR

25

mΩ

BUCK REGULATORS

V_{(VIN_Bx)}

V_(VANA)

,

VIN_Bx and VANA pins must be connected to

the same supply line

Input voltage range

2.8

1

3.3

5.5

V

Programmable voltage range

Step size, 1 V ≤ V_OUT< 1.4 V

Step size, 1.4 V ≤ V_OUT≤ 3.36 V

Output current

1

5

3.36

V_{OUT_Bx}

Output voltage

Output current

mV

20

I_{OUT_Bx}

3⁽³⁾

A

V

Input and Output voltage Minimum voltage between V_{(VIN_Bx)}and

difference V_OUTto fulfill the electrical characteristics

0.8

(1) All voltage values are with respect to network ground.

(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,

but do represent the most likely norm.

(3) The maximum output current can be limited by the forward current limit I_{LIM FWD}. The power dissipation inside the die increases the

junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient

temperature.

6

TPS65653-Q1

www.ti.com.cn

ZHCSJI6 –MARCH 2019

Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx},V_{VOUT_Bx}, and I_OUTrange,

unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1 V, unless otherwise noted.⁽¹⁾⁽²⁾

.

PARAMETER

TEST CONDITIONS

Force PWM mode

MIN

TYP

MAX

UNIT

DC output voltage

–2%

2%

accuracy, includes

V_{OUT_Bx_DC}

voltage reference, DC

load and line regulations,

process and temperature

PFM mode. Average output voltage level is

increased by max. 20 mV

2% + 20

mV

–2%

PWM mode, L = 0.47 µH, I_OUT= 500 mA,

COUT = 22uF + 22uF

4

(GCM31CR71A226KE02)

Ripple voltage

mV_p-p

PFM mode, L = 0.47 µH, I_OUT= 10 mA,

COUT = 22uF + 22uF

25

(GCM31CR71A226KE02)

DC_LNR

DC_LDR

T_LDSR

DC line regulation

I_OUT= 1 A

±0.05

0.3%

±60

%/V

mV

DC load regulation in

PWM mode

V_{OUT_Bx}= 1 V, I_OUTfrom 0 to I_OUT(max)

Transient load step

response

I_OUT= 0 A to 3 A, T_R= T_F= 1 µs, PWM

mode, V_{VIN_Bx}= 3.3 V, V_{OUT_Bx}= 1 V, C_OUT

44 µF, L = 0.47 µH, f_SW= 4 MHz

=

V_{(VIN_Bx)}stepping 3 V ↔ 3.5 V, T_R= T_F= 10

µs, I_OUT= I_OUT(max)

T_LNSR

Transient line response

±10

mV

A

Programmable range

1.5

4

Forward current limit per

phase (peak for every

switching cycle)

Step size

0.5

7.5%

2.0

I_{LIM FWD}

Accuracy, V_{(VIN_Bx)}≥ 3 V, I_LIM= 4 A

Accuracy, 2.8 V ≤ V_{(VIN_Bx)}< 3 V, I_LIM= 4 A

–5%

–20%

1.6

20%

3.0

I_{LIM NEG}

Negative current limit

A

On-resistance, high-side

FET

R_{DS(ON) HS FET}

Between VIN_Bx and SW_Bx pins (I = 1 A)

50

110

mΩ

On-resistance, low-side

FET

R_{DS(ON) LS FET}

ƒ_SW

Between SW_Bx and PGND_Bx pins (I = 1 A)

PWM mode

45

4

90

mΩ

MHz

µs

Switching frequency

3.6

4.4

From ENx to V_{OUT_Bx}= 0.35 V (slew-rate

control begins)

Start-up time (soft start)

120

SLEW_RATEx[2:0] = 010

SLEW_RATEx[2:0] = 011

SLEW_RATEx[2:0] = 100

SLEW_RATEx[2:0] = 101

SLEW_RATEx[2:0] = 110

SLEW_RATEx[2:0] = 111

10

7.5

3.8

Output voltage slew-

rate⁽⁴⁾

–15%

15% mV/µs

1.9

0.94

0.47

PFM-to-PWM - current

threshold⁽⁵⁾

I_PFM-PWM

I_PWM-PFM

R_{DIS_Bx}

550

290

250

mA

PWM-to-PFM - current

threshold⁽⁵⁾

Output pulldown

resistance

Regulator disabled

150

350

Ω

(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.

(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and

the inductor current level.

7

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx},V_{VOUT_Bx}, and I_OUTrange,

unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1 V, unless otherwise noted.⁽¹⁾⁽²⁾

.

PARAMETER

TEST CONDITIONS

V_{(VIN_Bx)}and V_(VANA)fixed 3.7 V

Overvoltage threshold (compared to DC

MIN

TYP

MAX

UNIT

39

–53

4

50

64

–29

15

Output voltage

output voltage level, V_{VOUT_Bx_DC}

Undervoltage threshold (compared to DC

output voltage level, V_{VOUT_Bx_DC}

)

monitoring for PGOOD

pin and for power-good

Interrupt

mV

–40

)

Deglitch time during operation and after

voltage change

µs

Gating time for PGOOD

signal after regulator

enable or voltage

change

PGOOD_MODE = 0

800

EXTERNAL CLOCK AND PLL

Nominal frequency

1

24

MHz

µs

f_{EXT_CLK}

External input clock⁽⁶⁾

Nominal frequency step size

1

Required accuracy from nominal frequency

Delay for missing clock detection

Delay and debounce for clock detection

–10%

10%

1.8

20

External clock detection

Clock change delay

(internal to external)

Delay from valid clock detection to use of

external clock

600

300

µs

PLL output clock jitter

Cycle to cycle

ps, p-p

PROTECTION FUNCTIONS

Temperature rising, TDIE_WARN_LEVEL = 0

115

127

125

137

20

135

147

Thermal warning⁽⁷⁾

Temperature rising, TDIE_WARN_LEVEL = 1

Hysteresis

°C

Temperature rising

Hysteresis

140

150

20

160

Thermal shutdown⁽⁷⁾

VANA overvoltage

Voltage rising

5.6

5.45

40

5.8

6.1

V

mV

V

VANA_OVP

Voltage falling

5.73

5.96

Hysteresis

Voltage rising

2.51

2.5

2.63

2.6

2.75

2.7

VANA undervoltage

lockout

VANA_UVLO

Voltage falling

Buck short-circuit

detection

Threshold

280

360

440

mV

LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS

Current measurement

Maximum code

range

10.22

A

Resolution

LSB

20

mA

Measurement accuracy

I_OUT> 1 A

<10%

PFM mode (automatically changing to PWM

mode for the measurement)

45

4

Measurement time

µs

PWM mode

CURRENT CONSUMPTION

Standby current

consumption, regulators

disabled

9

µA

(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.

(7) For a given device thermal warning will always happen at a lower temperature than thermal shutdown.

8

TPS65653-Q1

www.ti.com.cn

ZHCSJI6 –MARCH 2019

Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C ≤ T_J≤ +140°C, specified V_VANA, V_{VIN_Bx},V_{VOUT_Bx}, and I_OUTrange,

unless otherwise noted. Typical values are at T_J= 25°C, V_VANA= V_{VIN_Bx}= 3.7 V, and V_OUT= 1 V, unless otherwise noted.⁽¹⁾⁽²⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Active current

consumption, one buck

regulator enabled in auto

mode, internal RC

oscillator, PGOOD

monitoring enabled

I_{OUT_Bx}= 0 mA, not switching

58

µA

Active current

consumption, two buck

regulators enabled in

auto mode, internal RC

oscillator, PGOOD

monitoring enabled

I_{OUT_Bx}= 0 mA, not switching

100

15

µA

Active current

consumption during

PWM operation, one

buck regulator enabled

I_{OUT_Bx}= 0 mA

mA

Active current

consumption during

PWM operation, two

buck regulators enabled

I_{OUT_Bx}= 0 mA

30

2

mA

PLL and clock detector

current consumption

f_{EXT_CLK}= 1 MHz, Additional current

consumption when enabled

DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN

V_IL

V_IH

Input low level

Input high level

0.4

V

1.2

10

Hysteresis of Schmitt

Trigger inputs

V_HYS

80

200

mV

EN/CLKIN pulldown

resistance

EN_PD/CLKIN_PD = 1

500

kΩ

DIGITAL OUTPUT SIGNALS nINT, SDA

nINT: I_SOURCE= 2 mA

SDA: I_SOURCE= 20 mA

0.4

V

V_OL

R_P

Output low level

External pullup resistor

for nINT

To VIO Supply

10

kΩ

DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2

V_OL

Output low level

I_SOURCE= 2 mA

0.4

V

Output high level,

configured to push-pull

V_VANA

–

V_OH

I_SINK= 2 mA

V_VANA

0.4

Supply voltage for

V_PU

external pullup resistor,

configured to open-drain

V_VANA

V

External pullup resistor,

configured to open-drain

R_PU

10

kΩ

ALL DIGITAL INPUTS

I_LEAK

Input current

All logic inputs over pin voltage range

−1

1

µA

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6.6 I²C Serial Bus Timing Parameters

These specifications are ensured by design. Unless otherwise noted, V_{IN_Bx}= 3.7 V. See ⁽¹⁾and Figure 1.

MIN

MAX

UNIT

Standard mode

Fast mode

100

400

1

kHz

f_SCL

Serial clock frequency

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

3.4

1.7

MHz

µs

4.7

1.3

0.5

0.16

0.32

4

Fast mode

t_LOW

SCL low time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

Fast mode

0.6

0.26

0.06

0.12

250

100

50

t_HIGH

SCL high time

Data setup time

Data hold time

Fast mode+

µs

ns

µs

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

Fast mode

t_SU;DAT

t_HD;DAT

t_SU;STA

Fast mode+

High-speed mode

Standard mode

10

3450

900

Fast mode

10

Fast mode+

10

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

70

10

150

4.7

0.6

0.26

0.16

4

Setup time for a start or

a repeated start

condition

Fast mode

Fast mode+

High-speed mode

Standard mode

Fast mode

0.6

0.26

0.16

4.7

1.3

0.5

4

Hold time for a start or a

repeated start condition

t_HD;STA

µs

Fast mode+

High-speed mode

Standard mode

Bus free time between a

stop and start condition

t_BUF

Fast mode

Fast mode +

Standard mode

Fast mode

0.6

0.26

0.16

Setup time for a stop

condition

t_SU;STO

Fast mode+

High-speed mode

Standard mode

1000

300

120

80

Fast mode

20

t_rDA

Rise time of SDA signal Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

ns

10

20

160

(1) C_brefers to the capacitance of one bus line.

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I²C Serial Bus Timing Parameters (continued)

These specifications are ensured by design. Unless otherwise noted, V_{IN_Bx}= 3.7 V. See ⁽¹⁾and Figure 1.

MIN

MAX

UNIT

Standard mode

300

20 × (V_DD/ 5.5

Fast mode

300

120

V)

t_fDA

Fall time of SDA signal

20 × (V_DD/ 5.5

V)

ns

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

30

80

160

1000

300

120

40

Fast mode

20

t_rCL

Rise time of SCL signal Fast mode+

High-speed mode, C_b= 100 pF

ns

10

20

10

High-speed mode, C_b= 400 pF

80

Rise time of SCL signal High-speed mode, C_b= 100 pF

after a repeated start

80

t_rCL1

condition and after an

acknowledge bit

High-speed mode, C_b= 400 pF

20

160

Standard mode

Fast mode

300

20 × (V_DD/ 5.5

V)

t_fCL

Fall time of a SCL signal

20 × (V_DD/ 5.5

V)

ns

Fast mode+

120

High-speed mode, C_b= 10 – 100 pF

High-speed mode, C_b= 400 pF

10

20

40

80

Capacitive load for each

bus line (SCL and SDA)

C_b

400

50

pF

ns

Pulse width of spike

suppressed (SCL and

SDA spikes that are less

then the indicated width

are suppressed)

Standard mode, fast mode, and fast mode+

High-speed mode

t_SP

10

t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

Figure 1. I²C Timing

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6.7 Typical Characteristics

Unless otherwise specified: V_{(VIN_Bx)}= V_(VANA)= 3.7 V, V_{OUT_Bx}= 1 V, T_A= 25°C, L = 0.47 µH (Murata DFE252012PD-R47M),

C_{OUT_BUCK}= 22 µF, and C_{POL_BUCK}= 22 µF

15

14

13

12

11

10

9

70

68

66

64

62

60

58

56

54

52

50

8

7

6

5

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

D101

D102

Regulators disabled

V_{OUT_Bx}= 1 V

Load = 0 mA

Figure 2. Standby Current Consumption vs Input Voltage

Figure 3. Active State Current Consumption vs Input

Voltage, One Buck Regulator Enabled in PFM Mode

24

22

20

18

16

14

12

10

8

6

4

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

D103

V_{OUT_Bx}= 1 V

Load = 0 mA

Figure 4. Active State Current Consumption vs Input Voltage, One Buck Regulator Enabled in Forced PWM Mode

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7 Detailed Description

7.1 Overview

The TPS65653-Q1 is a high-efficiency, high-performance flexible power supply device with two step-down

DC/DC converter cores (Buck0 and Buck1) for automotive applications. Table 1 lists the output characteristics of

the regulators.

Table 1. Supply Specification

OUTPUT

SUPPLY

V_OUTRANGE (V)

RESOLUTION (mV)

I_MAXMAXIMUM OUTPUT CURRENT (mA)

5 (1 V to 1.4 V)

20 (1.4 V to 3.36 V)

Buck0

Buck1

1 to 3.36

3000

5 (1 V to 1.4 V)

20 (1.4 V to 3.36 V)

1 to 3.36

3000

The TPS65653-Q1 also supports switching clock synchronization to an external clock (CLKIN pin). The nominal

frequency of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.

Additional features include:

•

Soft-start

Input voltage protection:

–

Undervoltage lockout

Overvoltage protection

•

Output voltage monitoring and protection:

–

Overvoltage monitoring

Undervoltage monitoring

Overload protection

•

Thermal warning

Thermal shutdown

The TPS65653-Q1 has one dedicated general purpose digital output (GPO) signal. CLKIN pin can be

programmed as a second GPO signal (GPO2) if external clock is not needed. The output type (open-drain or

push-pull) is programmable for the GPOs.

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7.2 Functional Block Diagram

VANA

nINT

Interrupts

Buck0

ILIM Det

Pwrgood Det

Enable/

Disable,

Delay

Control

Slew-Rate

Control

Overload and

SC Det

EN

Iload ADC

GPO

Buck1

ILIM Det

Pwrgood Det

SDA

SCL

I2C

Overload and

SC Det

Iload ADC

OTP

EPROM

Registers

PGOOD

Digital

Logic

Thermal

Monitor

UVLO

SW

Reset

Ref &

Bias

Oscillator

CLKIN (GPO2)

7.3 Feature Description

7.3.1 DC/DC Converters

7.3.1.1 Overview

The TPS65653-Q1 includes two step-down DC/DC converter cores. The cores are designed for flexibility; most

of the functions are programmable, thus giving a possibility to optimize the regulator operation for each

application. The buck regulators deliver 1-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply

voltage.

The TPS65653-Q1 has the following features:

•

DVS support with programmable slew rate

Automatic mode control based on the loading (PFM or PWM mode)

Forced PWM mode option

Optional external clock input to minimize crosstalk

Optional spread-spectrum technique to reduce EMI

Phase control for optimized EMI

Synchronous rectification

Current mode loop with PI compensator

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Feature Description (continued)

•

Soft start

Power Good flag with maskable interrupt

Power Good signal (PGOOD) with selectable sources

Average output current sensing (for PFM entry and load current measurement)

The following parameters can be programmed via registers, the default values are set by OTP bits:

•

Output voltage

Forced PWM operation

Switch current limit

Output voltage slew rate

Enable and disable delays

There are two modes of operation for the buck converter, depending on the output current required: pulse-width

modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load

currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically

switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM

mode can be selected to maintain fixed switching frequency at all load current levels.

A block diagram of a single core is shown in Figure 5.

HS FET

CURRENT

SENSE

VIN

FB

POS

CURRENT

LIMIT

RAMP

GENERATOR

V

OUT

-

GATE

CONTROL

ERROR

AMP

SW

+

LOOP

COMP

VOLTAGE

SETTING

SLEW RATE

CONTROL

NEG

CURRENT

LIMIT

POWER

+

VDAC

-

GOOD

ZERO

CROSS

DETECT

LS FET

CURRENT

SENSE

MASTER

INTERFACE

PROGRAMMABLE

PARAMETERS

CONTROL

BLOCK

SLAVE

INTERFACE

IADC

GND

Figure 5. Detailed Block Diagram Showing One Core

7.3.1.2 Transition Between PWM and PFM Modes

PWM mode operation optimizes efficiency at mid to full load at the expense of light-load efficiency. The

TPS65653-Q1 converter operates in PWM mode at load current of about 600 mA or higher. At lighter load

current levels the device automatically switches into PFM mode for reduced current consumption when forced

PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a high efficiency is

achieved over a wide output-load current range.

7.3.1.3 Buck Converter Load Current Measurement

Buck load current can be monitored via I²C registers. The monitored buck converter is selected with the

LOAD_CURRENT_BUCK_SELECT bit in SEL_I_LOAD register. A write to this selection register starts a current

measurement sequence. The regulator is automatically forced to PWM mode for the measurement period. The

measurement sequence is 50 µs long, maximum.

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Feature Description (continued)

TPS65653-Q1 can be configured to give out an interrupt (I_MEAS_INT bit in INT_TOP_1 register) after the load

current measurement sequence is finished. Load current measurement interrupt can be masked with

I_MEAS_MASK bit (TOP_MASK_1 register). The measurement result can be read from registers I_LOAD_1 and

I_LOAD_2. Register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2

bit BUCK_LOAD_CURRENT[8] the MSB bit. The measurement result BUCK_LOAD_CURRENT[8:0] LSB is 20

mA, and maximum code value of the measurement corresponds to 10.22 A.

7.3.1.4 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband

frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add

EMI-filters and shields to the boards. The TPS65653-Q1 has register selectable spread-spectrum mode which

minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency

varies around the center frequency, reducing the EMI emissions radiated by the converter and associated

passive components and PCB traces (see Figure 6). This feature is available only when internal RC oscillator is

used (EN_PLL bit is 0 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC bit in CONFIG

register, and it affects both buck cores.

Frequency

Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread

spectrum architecture of the TPS65653-Q1 spreads that energy over a large bandwidth.

Figure 6. Spread-Spectrum Modulation

7.3.2 Sync Clock Functionality

The TPS65653-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulators with

the external clock. The block diagram of the clocking and PLL module is shown in Figure 7. Depending on the

EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt

is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1

register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL

register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy

limits (–10%/+10%) of the selected frequency for valid clock detection.

The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is

expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1

and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.

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Feature Description (continued)

24MHz

RC

Oscillator

Internal

24MHz

clock

CLKIN

Detector

Divider

“EXT_CLK_

FREQ“

Clock Select

Logic

CLKIN

1MHz

24MHz

PLL

“EN_PLL“

1MHz

Divider

24

Figure 7. Clock and PLL Module

Table 2. PLL Operation

DEVICE

OPERATION MODE

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

EN_PLL

CLOCK

STANDBY

ACTIVE

0

Disabled

No

Internal RC

When external clock

appears or disappears

Automatic change to external

clock when available

STANDBY

ACTIVE

1

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

7.3.3 Power-Up

The power-up sequence for the TPS65653-Q1 is as follows:

•

VANA (and VIN_Bx) reach minimum recommended levels (V_VANA> VANA_UVLO). This initiates power-on-reset

(POR), OTP reading, and enables the system I/O interface. The I²C host should allow at least 1.2 ms before

writing or reading data to the TPS65653-Q1.

•

Device enters standby mode.

The host can change the default register setting by I²C if needed.

The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I²C

interface.

Transitions between the operating modes are shown in Modes of Operation.

7.3.4 Regulator Control

7.3.4.1 Enabling and Disabling Regulators

The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable

and disable the buck regulators:

•

Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 0 in BUCKx_CTRL_1

register)

•

Using EN control pin (BUCKx_EN bit is 1 AND BUCKx_EN_PIN_CTRL bit is 1)

If the EN control pin is used for enable and disable then the delay from the control signal rising edge to start-up

is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and the delay from control signal falling

edge to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register. The delays are

valid only for EN signal transitions and not for control with I²C writings to the BUCKx_EN bit.

The control of the regulator (with 0-ms delays) is shown in Table 3.

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Table 3. Regulator Control

BUCKx_EN

BUCKx_EN_PIN_CTRL

EN PIN

Don't Care

Low

BUCKx OUTPUT VOLTAGE

Disabled

Enable/disable control with

BUCKx_EN bit

0

1

Don't Care

0

1

BUCKx_VSET[7:0]

Disabled

Enable/disable control with

EN pin

High

BUCKx_VSET[7:0]

The buck regulator is enabled by the EN pin or by I²C writing as shown in Figure 8. The soft-start circuit limits the

in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes slew-

rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the 0.35-V

level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), the regulator

is disabled, and BUCKx_SC_INT interrupt in INT_BUCK register is set. When the output voltage reaches the

Power-Good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set. The Power-Good

interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in BUCK_MASK

register. The Power-Good interrupt flag can be also generated when the output voltage becomes invalid. The

interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. A

BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage: 1 means valid and

0 means invalid output voltage. A PGOOD_WINDOW_BUCK bit in PGOOD_CTRL_1 register sets the detection

method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage

detection.

Voltage decrease because of load

Voltage

BUCKx_VSET[7:0]

Powergood

Ramp

BUCKx_CTRL_2(BUCKx_SLEW_RATE[2:0])

0.6V

0.35V

Time

Resistive pull-down

(if enabled)

Soft start

Enable

BUCK_STAT(BUCKx_STAT)

BUCK_STAT(BUCKx_PG_STAT)

INT_BUCK(BUCKx_PG_INT)

nINT

0

1

0

1

0

1

0

0 1

0

Powergood

interrupts

Host clears

interrupts

BUCK_MASK(BUCKx_PGF_MASK) = 0

BUCK_MASK(BUCKx_PGR_MASK) = 0

Figure 8. Buck Regulator Enable and Disable

The EN input pin has an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in

CONFIG register.

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7.3.4.2 Changing Output Voltage

The output voltage of the regulator can be changed by writing to the BUCKx_VOUT register. The voltage change

for buck regulator is always slew-rate controlled, and the slew-rate is defined by the BUCKx_SLEW_RATE[2:0]

bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is used automatically. When the

programmed output voltage is achieved, the mode becomes the one defined by load current, and the

BUCKx_FPWM bit in BUCKx_CTRL_1 register.

The voltage change and Power-Good interrupts are shown in Figure 9.

Ramp for Buck

BUCKx_CTRL2(SLEW_RATEx[2:0])

Voltage

BUCKx_VSET

Powergood

Time

BUCK_STAT(BUCKx_STAT)

BUCK_STAT(BUCKx_PG_STAT)

INT_BUCK(BUCKx_PG_INT)

1

0

1

0

1

0

nINT

Powergood

interrupt

Host clears

interrupt

Powergood

interrupt

Host clears

interrupt

BUCK_MASK(BUCKx_PGF_MASK)=0

BUCK_MASK(BUCKx_PGR_MASK)=0

Figure 9. Regulator Output Voltage Change

7.3.5 Enable and Disable Sequences

The TPS65653-Q1 device supports start-up and shutdown sequencing with programmable delays for different

regulator outputs using single EN control signal. The Buck regulator is selected for delayed control with:

•

BUCKx_EN = 1 in BUCKx_CTRL_1 register

BUCKx_EN_PIN_CTRL = 1 in BUCKx_CTRL_1 register

BUCKx_VSET[7:0] bits in BUCKx_VOUT register defines the voltage when EN pin is high

The delay from rising edge of EN pin to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits in

BUCKx_DELAY register and

•

The delay from falling edge of EN pin to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits

in BUCKx_DELAY register.

The GPO (and GPO2) digital output signals can be also controlled as a part of start-up and shutdown

sequencing with the following settings:

•

GPOx_EN = 1 in GPO_CTRL register

GPOx_EN_PIN_CTRL = 1 in GPO_CTRL register

The delay from rising edge of EN pin to the rising edge of GPO/GPO2 signal is set by

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GPOx_STARTUP_DELAY[3:0] bits in GPOx_DELAY register and

•

The delay from falling edge of EN pin to the falling edge of GPO/GPO2 signal is set by

GPOx_SHUTDOWN_DELAY[3:0] bits in GPOx_DELAY register.

An example of the start-up and shutdown sequences for the buck regulators are shown in Figure 10. The start-up

and shutdown delays for the Buck0 regulator are 1 ms and 4 ms; for the Buck1 regulator start-up and shutdown

delays are 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.

Typical sequence

EN

EN_BUCK0

EN_BUCK1

1ms

4ms

3ms

1ms

Sequence with short EN low and high periods

EN

Startup cntr

0

1

0

1

2

3

4

5

6

0

Shutdown cntr

EN_BUCK0

EN_BUCK1

0

1

0

1

2 0

1

2

3

4

5

1ms

4ms

3ms

1ms

Figure 10. Start-Up and Shutdown Sequencing

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7.3.6 Device Reset Scenarios

There are two reset methods implemented on the TPS65653-Q1:

•

Software reset with SW_RESET bit in RESET register

Undervoltage lockout (UVLO) reset from VANA supply

An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event

disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the

default values and OTP bits are loaded (see Figure 15). I²C interface is not reset during software reset.

If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately,

GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA

supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the

registers and a startup is initiated according to the register settings.

7.3.7 Diagnosis and Protection Features

The TPS65653-Q1 is capable of providing four levels of protection features:

•

Information of valid regulator output voltage which sets interrupt or PGOOD signal;

Warnings for diagnosis which sets interrupt;

Protection events which are disabling the regulators; and

Faults which are causing the device to shutdown.

The TPS65653-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the

nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all

the pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in

INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is

not generated. The mask bit change with I²C does not affect, because the RESET_REG_MASK bit is loaded

from OTP during reset sequence.

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Table 4. Summary of Interrupt Signals

RECOVERY/INTERRUPT

CLEAR

EVENT

OUTCOME

INTERRUPT BIT

INTERRUPT MASK BIT

STATUS BIT

Write 1 to BUCKx_ILIM_INT bit

Interrupt is not cleared if current

limit is active

BUCK_INT

BUCKx_ILIM_INT

Buck current limit triggered

No effect

BUCKx_ILIM_MASK

BUCKx_ILIM_STAT

Buck short circuit (V_OUT< 0.35

V at 1 ms after enable) or

overload (V_OUTdecreasing

below 0.35 V during operation,

1-ms debounce)

BUCK_INT

BUCKx_SC_INT

Regulator disable

No effect

N/A

Write 1 to BUCKx_SC_INT bit

Write 1 to TDIE_WARN_INT bit

Interrupt is not cleared if

temperature is above thermal

warning level

Thermal warning

TDIE_WARN_INT

TDIE_WARN_MASK

TDIE_WARN_STAT

Write 1 to TDIE_SD_INT bit

Interrupt is not cleared if

temperature is above thermal

shutdown level

All regulators disabled

immediately and GPO

and GPO2 are set to low

Thermal shutdown

TDIE_SD_INT

OVP_INT

N/A

TDIE_SD_STAT

OVP_STAT

All regulators disabled

immediately and GPO

and GPO2 are set to low

Write 1 to OVP_INT bit

Interrupt is not cleared if VANA

voltage is above VANA_OVPlevel

VANA overvoltage (VANA_OVP

)

Buck power good, output

voltage becomes valid

BUCK_INT

BUCKx_PG_INT

No effect

BUCKx_PGR_MASK

BUCKx_PGF_MASK

PGOOD_MASK

BUCKx_PG_STAT

PGOOD_STAT

SYNC_CLK_STAT

N/A

Write 1 to BUCKx_PG_INT bit

Write 1 to PGOOD_INT bit

Write 1 to SYNC_CLK_INT bit

Write 1 to I_MEAS_INT bit

Buck power good, output

voltage becomes invalid

BUCK_INT

BUCKx_PG_INT

No effect

PGOOD pin changing from

active to inactive state⁽¹⁾

No effect

PGOOD_INT

External clock appears or

disappears

No effect to regulators

No effect

SYNC_CLK_INT⁽²⁾

I_MEAS_INT

SYNC_CLK_MASK

I_MEAS_MASK

Load current measurement

ready

Immediate shutdown,

registers reset to default

values

Supply voltage VANA_UVLO

triggered (VANA falling)

N/A

Startup, registers reset to

default values and OTP

bits loaded

Supply voltage VANA_UVLO

triggered (VANA rising)

RESET_REG_INT

RESET_REG_MASK

Write 1 to RESET_REG_INT bit

Immediate shutdown

followed by power up,

registers reset to default

values

Software requested reset

RESET_REG_INT

RESET_REG_MASK

N/A

Write 1 to RESET_REG_INT bit

(1) PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. PGOOD_POL bit in PGOOD_CTRL_1 register affects only PGOOD

pin polarity, not Power Good and PGOOD_INT interrupt polarity.

(2) Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled.

7.3.7.1 Power-Good Information (PGOOD pin)

In addition to the interrupt-based indication of the current limit and the Power-Good level the TPS65653-Q1

device supports monitoring with PGOOD signal:

•

Regulator output voltage,

Input supply overvoltage,

Thermal warning and

Thermal shutdown.

Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This

selection is individual for both buck regulators and is set by EN_PGOOD_BUCKx bits in PGOOD_CTRL_1

register. When a regulator is disabled, the monitoring is automatically masked to prevent it forcing PGOOD

inactive. A thermal warning can be also selected for PGOOD indication with EN_PGOOD_TWARN bit in

PGOOD_CTRL_2 register. The monitoring from all the output rails, thermal warning (TDIE_WARN_STAT), input

overvoltage interrupt (OVP_INT), and thermal shutdown interrupt (TDIE_SD_INT) are combined, and PGOOD

pin is active only if all the selected sources shows a valid status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in

PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and

overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD

bits in the PGOOD_CTRL_1 register.

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PGOOD is only active or asserted when all enabled power resource output voltages are within specified

tolerance for each requested/programmed output voltage.

PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance

for each requested/programmed output voltage.

The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.

7.3.7.1.1 PGOOD Pin Gated mode

The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2

register.

For the gated mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.

PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status

indication.

•

During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an

800-µs gated time period. It typically remains active or asserted for normal conditions.

During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to

inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.

Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown

sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit

configuration provides a smart PORz function for processor that eliminates the need for additional

components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the

PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and

TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the

corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by

toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 11.

V_(VANA)

VANA_UVLO

Shut

down

Read

OTP

Standby

Active

State

PGOOD pin

Clear fault

EN pin

4ms

Buck internal enable

VOUT (Buck1)

800us Timer

Buck1 internal powergood

Figure 11. PGOOD Pin Operation in Gated Mode

7.3.7.1.2 PGOOD Pin Continuous Mode

The continuous (or unvalid) mode of operation is selected by setting PGOOD_MODE bit to 1 in

PGOOD_CTRL_2 register.

For the continuous mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration.

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•

PGOOD is set to inactive or de-asserted as soon as regulator is enabled.

PGOOD status begins indicating output voltage regulation status immediately and continuously.

During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or de-

asserted while output voltages are outside of regulation ranges and active or asserted when inside of

regulation ranges.

The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing

1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are

cleared by clearing the interrupt bits.

When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive.

When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the

invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows

all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 12

and an example of operation is shown in Figure 13.

The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs

are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is

selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.

EN_PGOOD

_BUCK0

Power Good

Buck0

EN_PGOOD

_BUCK1

Power Good

Buck1

PGOOD

Active high

EN_PGOOD

_TWARN

TDIE_WARN_STAT

TDIE_SD_INT

OVP_INT

Figure 12. PGOOD Block Diagram (Continuous Mode)

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V_(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

Active

PGOOD pin

EN pin

4ms

Buck1 internal enable

VOUT (Buck1)

Buck1 internal powergood

Figure 13. PGOOD Pin Operation in Continuous Mode

7.3.7.2 Warnings for Diagnosis (Interrupt)

7.3.7.2.1 Output Power Limit

The Buck regulators have programmable output peak current limits. The limits are individually programmed for

both regulators with BUCKx_ILIM[2:0] bits in BUCKx_CTRL_2 register. If the load current is increased so that the

current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation).

The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20

µs, the TPS65653-Q1 device sets the BUCKx_ILIM_INT bit in INT_BUCK register and pulls the nINT pin low.

The host processor can read BUCKx_ILIM_STAT bits in BUCK_STAT register to see if the regulator is still in

peak current regulation mode and the interrupt is cleared by writing 1 to BUCKx_ILIM_INT bit. The current limit

interrupt can be masked by setting BUCKx_ILIM_MASK bit in BUCK_MASK register to 1. The Buck overload

situation is shown in Figure 14.

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Regulator disabled

by digital

New startup if

enable is valid

Voltage

VOUTx

350mV

Resistive

pull-down

1ms

Time

Current

ILIMx

20ms

0

1

0

INT_BUCK(BUCKx_ILIM_INT)

INT_BUCK(BUCKx_SC_INT)

BUCK_STAT(BUCKx_STAT)

nINT

1

0

1

Host clearing the interrupt by writing to flags

Figure 14. Buck Regulator Overload Situation

7.3.7.2.2 Thermal Warning

The TPS65653-Q1 device includes a protection feature against overtemperature by setting an interrupt for host

processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit in CONFIG

register.

If the TPS65653-Q1 device temperature increases above thermal warning level the device sets

TDIE_WARN_INT bit in INT_TOP_1 register and pulls the nINT pin low. The status of the thermal warning can

be read from TDIE_WARN_STAT bit in TOP_STAT register, and the interrupt is cleared by writing 1 to

TDIE_WARN_INT bit. The thermal warning interrupt can be masked by setting TDIE_WARN_MASK bit in

TOP_MASK_1 register to 1.

7.3.7.3 Protection (Regulator Disable)

If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal

shutdown, input overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and

the output pulldown resistor is enabled (if enabled with BUCKx_RDIS_EN bit in BUCKx_CTRL_1 register). The

turnoff time of the output voltage is defined by the output capacitance, load current, and the resistance of the

integrated pull-down resistor. The pulldown resistors are active as long as VANA voltage is above approximately

a 1.2-V level.

7.3.7.3.1 Short-Circuit and Overload Protection

A short-circuit protection feature allows the TPS65653-Q1 to protect itself and external components against short

circuit at the output or against overload during start-up. For buck regulators the fault thresholds are about 350

mV, and the protection is triggered and the regulator is disabled if the output voltage is below the threshold level

1 ms after the regulator is enabled.

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In a similar way the overload situation is protected during normal operation. If the output voltage falls below 0.35

V and 0.3 V and remains below the threshold level for 1 ms the regulator is disabled.

In buck regulator short-circuit and overload situations the BUCKx_SC_INT bit in INT_BUCK register and the

INT_BUCKx bit in INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0, and

the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT bit.

Upon clearing the interrupt the regulator makes a new start-up attempt if the regulator is in an enabled state.

7.3.7.3.2 Overvoltage Protection

The TPS65653-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes.

If the input voltage rises above VANA_OVPvoltage level, all the regulators are disabled immediately (without

switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled

(BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register), GPOs are set to logic low level, nINT signal is pulled low,

OVP_INT bit in INT_TOP_1 register is set to 1, and BUCKx_STAT bit in BUCK_STAT register is set to 0. The

host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage

detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT

bit in TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage

detection level or the overvoltage interrupt is pending.

7.3.7.3.3 Thermal Shutdown

The TPS65653-Q1 has an overtemperature protection function that operates to protect itself from short-term

misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are

disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit in INT_TOP_1 register

is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the

TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can

read the status of the thermal shutdown from the TDIE_SD_STAT bit in TOP_STAT register. Regulators cannot

be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown

interrupt is pending.

7.3.7.4 Fault (Power Down)

7.3.7.4.1 Undervoltage Lockout

When the input voltage falls below VANA_UVLOat the VANA pin, the buck regulators are disabled immediately

(without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor,

and the TPS65653-Q1 device enters SHUTDOWN. When V_(VANA)voltage is above VANA_UVLOthreshold level, the

device powers up to STANDBY state.

If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the

RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The

host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the

RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been

below VANA_UVLOlevel (or the host has requested reset with SW_RESET bit in RESET register), and the

registers are reset to default values.

7.3.8 Operation of the GPO Signals

The TPS65653-Q1 device supports up to 2 general purpose output signals, GPO and GPO2. The GPO2 signal is

multiplexed with CLKIN signal. The selection between CLKIN and GPO2 pin function is set with CLKIN_PIN_SEL

bit in CONFIG register.

The GPO pins are configured with the following bits:

•

GPOx_OD bit in GPO_CTRL register defines the type of the output, either push-pull with V_(VANA)level or open

drain

The logic level of the GPOx pin is set by EN_GPOx bit in GPO_CTRL register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown

sequence control see Enable and Disable Sequences.

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7.3.9 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

Table 5. Digital Signal Filtering

RISING EDGE

LENGTH

FALLING EDGE

LENGTH

EVENT

SIGNAL/SUPPLY

Enable/disable for BUCKx or

GPOx

EN

3 µs⁽¹⁾

VANA UVLO

VANA

3 µs⁽¹⁾(VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

Thermal warning

Thermal shutdown

Current limit

1 µs (VANA voltage rising)

20 µs (VANA voltage falling)

TDIE_WARN_INT

TDIE_SD_INT

VOUTx_ILIM

FB_B0, FB_B1

20 µs

1 ms

20 µs

N/V

Overload

PGOOD pin and power-good

interrupt

PGOOD / FB_B0, FB_B1

6 µs

(1) No glitch filtering, only synchronization.

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7.4 Device Functional Modes

7.4.1 Modes of Operation

SHUTDOWN: The V_(VANA)voltage is below VANA_UVLOthreshold level. All switch, reference, control, and bias

circuitry of the TPS65653-Q1 device are turned off.

READ OTP: The main supply voltage V_(VANA)is above VANA_UVLOlevel. The regulators are disabled, and the

reference and bias circuitry of the TPS65653-Q1 are enabled. The OTP bits are loaded to registers.

STANDBY: The main supply voltage V_(VANA)is above VANA_UVLOlevel. The regulators are disabled, and the

reference, control and bias circuitry of the TPS65653-Q1 are enabled. All registers can be read or

written by the host processor via the system serial interface. The regulators can be enabled if

needed.

ACTIVE:

The main supply voltage V_(VANA)is above VANA_UVLOlevel. At least one regulator is enabled. All

registers can be read or written by the host processor via the system serial interface.

The operating modes and transitions between the modes are shown in Figure 15.

SHUTDOWN

V(

< VANA_UVLO

VANA)

V(

> VANA_UVLO

FROM ANY STATE

VANA)

EXCEPT SHUTDOWN

READ

OTP

REG

RESET

STANDBY

2

I C RESET

REGULATOR

ENABLED

REGULATOR(S)

DISABLED

ACTIVE

Figure 15. Device Operation Modes

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7.5 Programming

7.5.1 I²C-Compatible Interface

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on

the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates

or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed on the line and

remain HIGH even when the bus is idle. The TPS65653-Q1 supports standard mode (100 kHz), fast mode (400

kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 16. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

The TPS65653-Q1 is controlled via an I²C-compatible interface. START and STOP conditions classify the

beginning and end of the I²C session. A START condition is defined as SDA transitions from HIGH to LOW while

SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I²C

master always generates the START and STOP conditions.

SDA

SCL

S

P

START

STOP

Condition

Figure 17. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. During data

transmission the I²C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 18 shows the

SDA and SCL signal timing for the I²C-compatible bus. See the Figure 1 for timing values.

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Programming (continued)

t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

Figure 18. I²C-Compatible Timing

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The TPS65653-Q1

pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The TPS65653-Q1 generates an

acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

NOTE

If the V_(VANA)voltage is below VANA_UVLOthreshold level during I²C communication the

TPS65653-Q1 device does not drive SDA line. The ACK signal and data transfer to the

master is disabled at that time.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1

indicates a READ. The second byte selects the register to which the data will be written. The third byte contains

data to write to the selected register.

ACK from slave

START MSB Chip Address LSB

W

ACK MSB Register Address LSB ACK

MSB Data LSB

ACK STOP

SCL

SDA

START

id = 0x60

W

ACK

address = 0x40

ACK

address 0x40 data

ACK STOP

Figure 19. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60

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Programming (continued)

ACK from slave

ACK from slave REPEATED START

ACK from slave Data from slave NACK from master

START MSB Chip Address LSB

W

MSB Register Address LSB

RS

MSB Chip Address LSB

R

MSB Data LSB

STOP

SCL

SDA

START

ACK

NACK

STOP

id = 0x60

W

address = 0x3F

RS

id = 0x60

R

address 0x3F data

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 20. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60

7.5.1.4 I²C-Compatible Chip Address

NOTE

The device address for the TPS65653-Q1 is 0x61.

After the START condition, the I²C master sends the 7-bit address followed by an eighth bit, read or write (R/W).

R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address

selects the register address to which the data is written. The third byte contains the data for the selected register.

MSB

LSB

1

Bit 7

1

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

R/W

Bit 0

I²C Slave Address (chip address)

Here in an example with device address of 1100000Bin = 60Hex.

Figure 21. Device Address Example

7.5.1.5 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-

bit word is sent to the TPS65653-Q1, the internal address index counter is incremented by one and the next

register is written. Table 6 shows writing sequence to two consecutive registers. Note that auto-increment feature

does not work for read.

Table 6. Auto-Increment Example

DEVICE

ADDRES WRITE

S = 0x61

MASTER

ACTION

REGISTER

ADDRESS

START

DATA

STOP

TPS6565

3-Q1

ACK

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7.6 Register Maps

7.6.1 Register Descriptions

The TPS65653-Q1 is controlled by a set of registers through the I²C-compatible interface. The device registers,

their addresses and their abbreviations are listed in Table 7. A more detailed description is given in the

DEV_REV to I_LOAD_1 sections.

An "X" indicates register bits which are updated from OTP memory during READ OTP state.

Table 7. Summary of TPS65653-Q1 Control Registers

Read /

Write

Addr

Register

D7

D6

D5

D4

D3

D2

D1

D0

0x00

0x01

DEV_REV

OTP_REV

R

DEVICE_ID[1:0]

Reserved

R

OTP_ID[7:0]

BUCK0_

EN_PIN_CT BUCK0_EN

RL

BUCK0_

CTRL_1

BUCK0_FP BUCK0_RDI

0x02

0x03

0x04

R/W

Reserved

WM

S_EN

BUCK0_

CTRL_2

Reserved

BUCK0_ILIM[2:0]

BUCK1_ILIM[2:0]

BUCK0_SLEW_RATE[2:0]

BUCK1_

EN_PIN_CT BUCK1_EN

RL

BUCK1_

CTRL_1

BUCK1_FP BUCK1_RDI

WM

S_EN

BUCK1_

CTRL_2

0x05

0x06

0x07

0x0C

0x0D

0x10

0x11

R/W

BUCK1_SLEW_RATE[2:0]

BUCK0_

VOUT

BUCK0_VSET[7:0]

BUCK1_VSET[7:0]

BUCK1_

VOUT

BUCK0_

DELAY

BUCK0_SHUTDOWN_DELAY[3:0]

BUCK1_SHUTDOWN_DELAY[3:0]

GPO_SHUTDOWN_DELAY[3:0]

BUCK0_STARTUP_DELAY[3:0]

BUCK1_STARTUP_DELAY[3:0]

GPO_STARTUP_DELAY[3:0]

BUCK1_

DELAY

GPO_

DELAY

GPO2_

DELAY

GPO2_SHUTDOWN_DELAY[3:0]

GPO2_

GPO2_STARTUP_DELAY[3:0]

GPO_

CTRL

0x12

R/W

Reserved

GPO2_OD EN_PIN_CT GPO2_EN

RL

Reserved

GPO_OD

EN_PIN_CT

RL

GPO_EN

STARTUP_ SHUTDOW

CLKIN_PIN

TDIE

_WARN

_LEVEL

EN_

SPREAD

_SPEC

0x13

0x14

0x15

CONFIG

R/W

Reserved

DELAY_SE N_DELAY_

_SEL

CLKIN_PD

EN_PD

L

SEL

PLL_CTRL

EN_PLL

Reserved

EXT_CLK_FREQ[4:0]

PGOOD_WI

NDOW_BU

CK

PGOOD_CT

RL_1

PGOOD_P

OL

PGOOD_O

D

EN_PGOOD EN_PGOOD

_BUCK1

Reserved

_BUCK0

PG_FAULT

_GATES_P

GOOD

PGOOD_CT

RL_2

EN_PGOOD

_TWARN

PGOOD_M

ODE

0x16

R/W

PG_FAULT PG_FAULT

0x17

0x18

0x19

0x1A

0x1B

PG_FAULT

RESET

R

Reserved

_BUCK1

_BUCK0

SW_

RESET

R/W

Reserved

PGOOD_

INT

INT_

SYNC_

TDIE_SD_I

NT

TDIE_

WARN_INT

I_MEAS_

INT

INT_TOP_1

INT_TOP_2

INT_BUCK

Reserved

OVP_INT

BUCK

CLK_INT

RESET_

REG_INT

Reserved

BUCK1_

PG_INT

BUCK1_

SC_INT

BUCK1_

ILIM_INT

BUCK0_

PG_INT

BUCK0_

SC_INT

BUCK0_

ILIM_INT

Reserved

TDIE_

WARN_

STAT

TOP_

STAT

PGOOD_ST

AT

SYNC_CLK

_STAT

TDIE_SD

_STAT

OVP_

STAT

0x1D

0x1E

R

Reserved

BUCK_STA

T

BUCK1_

STAT

BUCK1_

ILIM_STAT

BUCK0_

STAT

BUCK0_

PG_STAT

BUCK0_

ILIM_STAT

Reserved

PG_STAT

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Register Maps (continued)

Table 7. Summary of TPS65653-Q1 Control Registers (continued)

Read /

Write

Addr

0x20

0x21

Register

D7

D6

D5

D4

D3

D2

D1

D0

TOP_

MASK_1

PGOOD_

INT_MASK

SYNC_CLK

_MASK

TDIE_WAR

N_MASK

I_MEAS_

MASK

R/W

Reserved

TOP_

MASK_2

RESET_

REG_MASK

Reserved

BUCK1_

ILIM_

MASK

BUCK0_

ILIM_

MASK

BUCK_MAS

K

BUCK1_PG BUCK1_PG

F_MASK R_MASK

BUCK0_PG BUCK0_PG

F_MASK R_MASK

0x22

0x24

R/W

Reserved

LOAD_CUR

RENT_

BUCK_SEL

ECT

SEL_I_

LOAD

Reserved

BUCK_LOA

D_CURREN

T[8]

0x25

0x26

I_LOAD_2

I_LOAD_1

R

BUCK_LOAD_CURRENT[7:0]

34

TPS65653-Q1

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ZHCSJI6 –MARCH 2019

7.6.1.1 DEV_REV

Address: 0x00

D7

D6

D5

D4

D3

D2

D1

D0

DEVICE_ID[1:0]

Reserved

Bits

7:6

Field

Type

R

Default

X

Description

DEVICE_ID[1:0]

Reserved

Device specific ID code.

5:0

R

00 0010

7.6.1.2 OTP_REV

Address: 0x01

D7

D6

D5

D4

D3

D2

D1

D0

OTP_ID[7:0]

Bits

Field

Type

Default

Description

7:0

OTP_ID[7:0]

R

X

Identification Code of the OTP EPROM Version.

7.6.1.3 BUCK0_CTRL_1

Address: 0x02

D7

D6

D5

D4

D3

D2

D1

D0

BUCK0_EN

Reserved

BUCK0_FPWM BUCK0_RDIS_ BUCK0_EN_PI

EN

N_CTRL

Bits

7:4

3

Field

Type

R/W

Default

0000

X

Description

Reserved

BUCK0_FPWM

Buck0 mode selection:

0 - Automatic transitions between PFM and PWM modes (AUTO mode)

1 - Forced to PWM operation.

2

1

0

BUCK0_RDIS_EN

R/W

1

X

Enable output discharge resistor (R_{DIS_Bx}) when Buck0 is disabled:

0 - Discharge resistor disabled

1 - Discharge resistor enabled.

BUCK0_EN_PIN

_CTRL

Enable control for Buck0:

0 - only BUCK0_EN bit controls Buck0

1 - BUCK0_EN bit AND EN pin control Buck0.

BUCK0_EN

Enable Buck0 regulator:

0 - Buck0 regulator is disabled

1 - Buck0 regulator is enabled.

7.6.1.4 BUCK0_CTRL_2

Address: 0x03

D7

D6

D5

D4

D3

D2

D1

BUCK0_SLEW_RATE[2:0]

D0

Reserved

BUCK0_ILIM[2:0]

35

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

Bits

7:6

Field

Type

R/W

Default

Description

Reserved

00

X

5:3

BUCK0_ILIM[2:0]

Sets the switch current limit of Buck0. Can be programmed at any time during

operation:

0x0 - 1.5 A

0x1 - 2.0 A

0x2 - 2.5 A

0x3 - 3.0 A

0x4 - 3.5 A

0x5 - 4.0 A

0x6 - Reserved

0x7 - Reserved

2:0 BUCK0_SLEW_RA

TE[2:0]

R/W

X

Sets the output voltage slew rate for Buck0 regulator (rising and falling edges):

0x0 - Reserved

0x1 - Reserved

0x2 - 10 mV/µs

0x3 - 7.5 mV/µs

0x4 - 3.8 mV/µs

0x5 - 1.9 mV/µs

0x6 - 0.94 mV/µs

0x7 - 0.47 mV/µs

7.6.1.5 BUCK1_CTRL_1

Address: 0x04

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

BUCK1_FPWM BUCK1_RDIS_ BUCK1_EN_PI

BUCK1_EN

EN

N_CTRL

Bits

7:4

3

Field

Type

R/W

Default

0000

X

Description

Reserved

BUCK1_FPWM

Buck1 mode selection:

0 - Automatic transitions between PFM and PWM modes (AUTO mode)

1 - Forced to PWM operation.

2

1

0

BUCK1_RDIS_EN

R/W

1

X

Enable output discharge resistor (R_{DIS_Bx}) when Buck1 is disabled:

0 - Discharge resistor disabled

1 - Discharge resistor enabled.

BUCK1_EN_PIN

_CTRL

Enable control for Buck1:

0 - only BUCK1_EN bit controls Buck1

1 - BUCK1_EN bit AND EN pin control Buck1.

BUCK1_EN

Enable Buck1 regulator:

0 - Buck1 regulator is disabled

1 - Buck1 regulator is enabled.

7.6.1.6 BUCK1_CTRL_2

Address: 0x05

D7

D6

D5

D4

D3

D2

D1

BUCK1_SLEW_RATE[2:0]

D0

Reserved

BUCK1_ILIM[2:0]

36

TPS65653-Q1

www.ti.com.cn

Bits

ZHCSJI6 –MARCH 2019

Field

Type

R/W

Default

Description

7:6

5:3

Reserved

00

X

BUCK1_ILIM[2:0]

Sets the switch current limit of Buck1. Can be programmed at any time during

operation:

0x0 - 1.5 A

0x1 - 2.0 A

0x2 - 2.5 A

0x3 - 3.0 A

0x4 - 3.5 A

0x5 - 4.0 A

0x6 - Reserved

0x7 - Reserved

2:0 BUCK1_SLEW_RA

TE[2:0]

R/W

X

Sets the output voltage slew rate for Buck1 regulator (rising and falling edges):

0x0 - Reserved

0x1 - Reserved

0x2 - 10 mV/µs

0x3 - 7.5 mV/µs

0x4 - 3.8 mV/µs

0x5 - 1.9 mV/µs

0x6 - 0.94 mV/µs

0x7 - 0.47 mV/µs

7.6.1.7 BUCK0_VOUT

Address: 0x06

D7

D6

D5

D4

D3

D2

D1

D0

BUCK0_VSET[7:0]

Bits

Field

Type

Default

Description

7:0 BUCK0_VSET[7:0]

R/W

X

Sets the output voltage of Buck0 regulator

Reserved, DO NOT USE

0x00 ... 0x4C

1 V - 1.4 V, 5 mV steps

0x4C - 1 V

...

0x9D - 1.4 V

1.4 V - 3.36 V, 20 mV steps

0x9E - 1.42 V

...

0xFF - 3.36 V

7.6.1.8 BUCK1_VOUT

Address: 0x07

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_VSET[7:0]

Bits

Field

Type

Default

Description

7:0 BUCK1_VSET[7:0]

R/W

X

Sets the output voltage of Buck1 regulator

Reserved, DO NOT USE

0x00 ... 0x4C

1 V - 1.4 V, 5 mV steps

0x4C - 1 V

...

0x9D - 1.4 V

1.4 V - 3.36 V, 20 mV steps

0x9E - 1.42 V

...

0xFF - 3.36 V

37

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

7.6.1.9 BUCK0_DELAY

Address: 0x0C

D7

D6

D5

D4

D3

D2

D1

D0

BUCK0_SHUTDOWN_DELAY[3:0]

BUCK0_STARTUP_DELAY[3:0]

Bits

Field

Type

Default

Description

7:4

BUCK0_

SHUTDOWN_

DELAY[3:0]

R/W

X

Shutdown delay of Buck0 from falling edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

3:0

BUCK0_

STARTUP_

DELAY[3:0]

R/W

X

Startup delay of Buck0 from rising edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.10 BUCK1_DELAY

Address: 0x0D

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_SHUTDOWN_DELAY[3:0]

BUCK1_STARTUP_DELAY[3:0]

Bits

Field

Type

Default

Description

7:4

BUCK1_

SHUTDOWN_

DELAY[3:0]

R/W

X

Shutdown delay of Buck1 from falling edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

3:0

BUCK1_

STARTUP_

DELAY[3:0]

R/W

X

Startup delay of Buck1 from rising edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.11 GPO_DELAY

Address: 0x10

D7

D6

D5

D4

D3

D2

D1

GPO_SHUTDOWN_DELAY[3:0]

GPO_STARTUP_DELAY[3:0]

Bits

Field

Type

Default

Description

7:4

GPO_

R/W

X

Delay for GPO falling edge from falling edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

SHUTDOWN_

DELAY[3:0]

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

3:0

GPO_

STARTUP_

DELAY[3:0]

R/W

X

Delay for GPO rising edge from rising edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.12 GPO2_DELAY

Address: 0x11

D7

D6

D5

D4

D3

D2

D1

GPO2_SHUTDOWN_DELAY[3:0]

GPO2_STARTUP_DELAY[3:0]

38

TPS65653-Q1

www.ti.com.cn

Bits

ZHCSJI6 –MARCH 2019

Field

Type

Default

Description

7:4

GPO2_

SHUTDOWN_

DELAY[3:0]

R/W

X

Delay for GPO2 falling edge from falling edge of EN signal:

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)

3:0

GPO2_

R/W

X

Delay for GPO2 rising edge from rising edge of EN signal:

STARTUP_

DELAY[3:0]

0x0 - 0 ms

0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

...

0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)

7.6.1.13 GPO_CTRL

Address: 0x12

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

GPO2_OD

GPO2_EN_PIN

_CTRL

GPO2_EN

Reserved

GPO_OD

GPO_EN_PIN_

CTRL

GPO_EN

Bits

Field

Type

Default

Description

7

6

Reserved

GP02_OD

R

0

R/W

X

GPO2 signal type when configured as General Purpose Output (CLKIN pin):

0 - Push-pull output (VANA level)

1 - Open-drain output

5

4

GPO2_EN_PIN_C

TRL

R/W

X

Control for GPO2:

0 - Only GPO2_EN bit controls GPO2

1 - GPO2_EN bit AND EN pin control GPO2.

GPO2_EN

Output level of GPO2 signal (when configured as General Purpose Output):

0 - Logic low level

1 - Logic high level

3

2

Reserved

GPO_OD

R

0

R/W

X

GPO signal type:

0 - Push-pull output (VANA level)

1 - Open-drain output

1

0

GPO_EN_PIN_CT

RL

R/W

X

Control for GPO:

0 - Only GPO_EN bit controls GPO

1 - GPO_EN bit AND EN pin control GPO.

GPO_EN

Output level of GPO signal:

0 - Logic low level

1 - Logic high level

7.6.1.14 CONFIG

Address: 0x13

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

STARTUP_DE SHUTDOWN_ CLKIN_PIN_SE

CLKIN_PD

EN2_PD

TDIE_WARN_

LEVEL

EN_SPREAD

_SPEC

LAY_SEL

DELAY_SEL

L

Bits

Field

Type

R/W

Default

Description

7

6

Reserved

0

STARTUP_DELAY

_SEL

X

Startup delay range from EN signals.

0 - 0 ms - 7.5 ms with 0.5 ms steps

1 - 0 ms - 15 ms with 1 ms steps

5

4

SHUTDOWN_DEL

AY_SEL

R/W

X

Shutdown delay range from EN signals.

0 - 0 ms - 7.5 ms with 0.5 ms steps

1 - 0 ms - 15 ms with 1 ms steps

CLKIN_PIN_SEL

CLKIN pin function:

0 - GPO2

1 - CLKIN

39

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

Bits

Field

Type

Default

Description

3

CLKIN_PD

R/W

X

Selects the pull down resistor on the CLKIN input pin. (valid also when selected as

GPO2)

0 - Pull-down resistor is disabled.

1 - Pull-down resistor is enabled.

2

1

0

EN_PD

R/W

X

Selects the pull down resistor on the EN input pin.

0 - Pull-down resistor is disabled.

1 - Pull-down resistor is enabled.

TDIE_WARN_

LEVEL

Thermal warning threshold level.

0 - 125°C

1 - 137°C.

EN_SPREAD

_SPEC

Enable spread spectrum feature:

0 - Disabled

1 - Enabled

7.6.1.15 PLL_CTRL

Address: 0x14

D7

D6

EN_PLL

D5

D4

D3

D2

D1

D0

Reserved

EXT_CLK_FREQ[4:0]

Bits

Field

Type

R/W

Default

Description

7

6

Reserved

EN_PLL

0

X

Selection of external clock and PLL operation:

0 - Forced to internal RC oscillator. PLL disabled.

1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use

when available, interrupt generated if external clock appears or disappears.

5

Reserved

R/W

0

This bit must be set to '0'.

4:0 EXT_CLK_FREQ[4

:0]

X

Frequency of the external clock (CLKIN):

0x00 - 1 MHz

0x01 - 2 MHz

0x02 - 3 MHz

...

0x16 - 23 MHz

0x17 - 24 MHz

0x18...0x1F - Reserved

See electrical specification for input clock frequency tolerance.

7.6.1.16 PGOOD_CTRL_1

Address: 0x15

D7

D6

D5

D4

D3

D2

D1

EN_PGOOD_B EN_PGOOD_B

UCK1 UCK0

D0

PGOOD_POL

PGOOD_OD

Reserved

PGOOD_

WINDOW_BUC

K

Reserved

Bits

Field

Type

Default

Description

7

PGOOD_POL

PGOOD_OD

Reserved

R/W

X

PGOOD signal polarity.

0 - PGOOD signal high when monitored outputs are valid

1 - PGOOD signal low when monitored outputs are valid

6

R/W

X

PGOOD signal type:

0 - Push-pull output (VANA level)

1 - Open-drain output

5

4

R/W

0

PGOOD_

WINDOW_BUCK

X

Buck Output voltage monitoring method for PGOOD signal:

0 - Only undervoltage monitoring

1 - Overvoltage and undervoltage monitoring.

3:2

Reserved

R/W

00

40

TPS65653-Q1

www.ti.com.cn

Bits

ZHCSJI6 –MARCH 2019

Field

Type

Default

Description

PGOOD signal source control from Buck1

0 - Buck1 is not monitored

1

EN_PGOOD_BUC

K1

R/W

X

1 - Buck1 Power-Good threshold voltage monitored

0

EN_PGOOD_BUC

K0

R/W

X

PGOOD signal source control from Buck0

0 - Buck0 is not monitored

1 - Buck0 Power-Good threshold voltage monitored

7.6.1.17 PGOOD_CTRL_2

Address: 0x16

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

EN_PGOOD_T PG_FAULT_G PGOOD_MOD

WARN

ATES_PGOOD

E

Bits

7:3

2

Field

Type

R/W

Default

0 0000

X

Description

Reserved

EN_PGOOD_TWA

RN

Thermal warning control for PGOOD signal:

0 - Thermal warning not monitored

1 - PGOOD inactive if thermal warning flag is active.

1

0

PG_FAULT_GATE

S_PGOOD

R/W

X

Type of operation for PGOOD signal:

0 - Indicates live status of monitored voltage outputs.

1 - Indicates status of PG_FAULT register, inactive when at least one PG_FAULT_x

bit is inactive.

PGOOD_MODE

Operating mode for PGOOD signal:

0 - Gated mode

1 - Continuous mode

7.6.1.18 PG_FAULT

Address: 0x17

D7

D6

D5

D4

D3

D2

D1

PG_FAULT_BU PG_FAULT_BU

CK1 CK0

D0

Reserved

Bits

7:2

1

Field

Type

R/W

Default

00 0000

0

Description

Reserved

PG_FAULT_BUCK

1

Source for PGOOD inactive signal:

0 - Buck1 has not set PGOOD signal inactive.

1 - Buck1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit

can be cleared by writing '1' to this bit when Buck1 output is valid.

0

PG_FAULT_BUCK

0

R/W

0

Source for PGOOD inactive signal:

0 - Buck0 has not set PGOOD signal inactive.

1 - Buck0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit

can be cleared by writing '1' to this bit when Buck0 output is valid.

7.6.1.19 RESET

Address: 0x18

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

SW_RESET

Bits

7:1

0

Field

Type

R/W

Default

000 0000

0

Description

Reserved

SW_RESET

Software commanded reset. When written to 1, the registers will be reset to default

values, OTP memory is read, and the I²C interface is reset.

The bit is automatically cleared.

41

TPS65653-Q1

ZHCSJI6 –MARCH 2019

www.ti.com.cn

7.6.1.20 INT_TOP_1

Address: 0x19

D7

D6

D5

D4

D3

D2

D1

D0

PGOOD_INT

Reserved

BUCK_INT

SYNC_CLK_IN TDIE_SD_INT TDIE_WARN_I

OVP_INT

I_MEAS_INT

T

NT

Bits

Field

Type

Default

Description

7

PGOOD_INT

R/W

0

Latched status bit indicating that the PGOOD pin has changed from active to inactive.

Write 1 to clear interrupt.

6

5

Reserved

R

0

BUCK_INT

Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for

the interrupt is indicated in INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared to 0x00.

4

3

SYNC_CLK_INT

TDIE_SD_INT

R/W

0

Latched status bit indicating that the external clock has appeared or disappeared.

Write 1 to clear interrupt.

Latched status bit indicating that the die junction temperature has exceeded the

thermal shutdown level. The regulators have been disabled if they were enabled and

GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is

active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in

TOP_STAT register.

Write 1 to clear interrupt.

2

1

TDIE_WARN_INT

OVP_INT

R/W

0

Latched status bit indicating that the die junction temperature has exceeded the

thermal warning level. The actual status of the thermal warning is indicated by

TDIE_WARN_STAT bit in TOP_STAT register.

Write 1 to clear interrupt.

Latched status bit indicating that the input voltage has exceeded the over-voltage

detection level. The regulators have been disabled if they were enabled and GPO and

GPO2 signals are driven low. The actual status of the over-voltage is indicated by

OVP_STAT bit in TOP_STAT register.

Write 1 to clear interrupt.

0

I_MEAS_INT

R/W

0

Latched status bit indicating that the load current measurement result is available in

I_LOAD_1 and I_LOAD_2 registers.

Write 1 to clear interrupt.

7.6.1.21 INT_TOP_2

Address: 0x1A

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

RESET_REG_I

NT

Bits

7:1

0

Field

Type

R/W

Default

000 0000

0

Description

Reserved

RESET_REG_INT

Latched status bit indicating that either VANA supply voltage has been below

undervoltage threshold level or the host has requested a reset using SW_RESET bit in

RESET register. The regulators have been disabled, and registers are reset to default

values and the normal startup procedure is done.

Write 1 to clear interrupt.

7.6.1.22 INT_BUCK

Address: 0x1B

D7

D6

BUCK1_PG

_INT

D5

D4

D3

D2

D1

D0

Reserved

BUCK1_SC

_INT

BUCK1_ILIM

_INT

Reserved

BUCK0_PG

_INT

BUCK0_SC

_INT

BUCK0_ILIM

_INT

42

TPS65653-Q1

www.ti.com.cn

Bits

ZHCSJI6 –MARCH 2019

Field

Type

R/W

Default

Description

7

6

Reserved

0

BUCK1_PG_INT

Latched status bit indicating that Buck1 Power-Good event has been detected.

Write 1 to clear.

5

4

BUCK1_SC_INT

BUCK1_ILIM_INT

R/W

0

Latched status bit indicating that the Buck1 output voltage has been over 1 ms below

short-circuit threshold level.

Write 1 to clear.

Latched status bit indicating that the Buck1 output current limit has been active.

Write 1 to clear.

3

2

Reserved

R/W

0

BUCK0_PG_INT

Latched status bit indicating that Buck0 Power-Good event has been detected.

Write 1 to clear.

1

0

BUCK0_SC_INT

BUCK0_ILIM_INT

R/W

0

Latched status bit indicating that the Buck0 output voltage has been over 1 ms below

short-circuit threshold level.

Write 1 to clear.

Latched status bit indicating that the Buck0 output current limit has been active.

Write 1 to clear.

7.6.1.23 TOP_STAT

Address: 0x1D

D7

D6

D5

D4

D3

D2

D1

D0

PGOOD_STAT

Reserved

SYNC_CLK

_STAT

TDIE_SD

_STAT

TDIE_WARN

_STAT

OVP_STAT

Reserved

Bits

Field

PGOOD_STAT

Type

Default

Description

7

R

0

Status bit indicating the status of PGOOD pin:

0 - PGOOD pin is inactive

1 - PGOOD pin is active

6:5

4

Reserved

R

00

0

SYNC_CLK_STAT

Status bit indicating the status of external clock (CLKIN):

0 - External clock frequency is valid

1 - External clock frequency is not valid.

3

2

1

0

TDIE_SD_STAT

R

0

Status bit indicating the status of thermal shutdown:

0 - Die temperature below thermal shutdown level

1 - Die temperature above thermal shutdown level.

TDIE_WARN

_STAT

Status bit indicating the status of thermal warning:

0 - Die temperature below thermal warning level

1 - Die temperature above thermal warning level.

OVP_STAT

Reserved

Status bit indicating the status of input overvoltage monitoring:

0 - Input voltage below overvoltage threshold level

1 - Input voltage above overvoltage threshold level.

7.6.1.24 BUCK_STAT

Address: 0x1E

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_STAT

BUCK1_PG

_STAT

Reserved

BUCK1_ILIM

_STAT

BUCK0_STAT

BUCK0_PG

_STAT

Reserved

BUCK0_ILIM

_STAT

Bits

Field

Type

Default

Description

7

BUCK1_STAT

R

0

Status bit indicating the enable/disable status of Buck1:

0 - Buck1 regulator is disabled

1 - Buck1 regulator is enabled.

6

BUCK1_PG_STAT

R

0

Status bit indicating Buck1 output voltage validity (raw status)

0 - Buck1 output voltage is valid.

1 - Buck1 output voltage is invalid.

43

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Bits

5

Field

Type

R

Default

Description

Reserved

0

4

BUCK1_ILIM

_STAT

R

Status bit indicating Buck1 current limit status (raw status)

0 - Buck1 output current is below current limit level

1 - Buck1 output current limit is active.

3

2

BUCK0_STAT

BUCK0_PG_STAT

Reserved

R

0

Status bit indicating the enable/disable status of Buck0:

0 - Buck0 regulator is disabled

1 - Buck0 regulator is enabled.

Status bit indicating Buck0 output voltage validity (raw status)

0 - Buck0 output voltage is valid.

1 - Buck0 output voltage is invalid.

1

0

R

0

BUCK0_ILIM

_STAT

Status bit indicating Buck0 current limit status (raw status)

0 - Buck0 output current is below current limit level

1 - Buck0 output current limit is active.

7.6.1.25 TOP_MASK_1

Address: 0x20

D7

D6

D5

D4

D3

D2

D1

D0

PGOOD_INT_

MASK

Reserved

SYNC_CLK

_MASK

Reserved

TDIE_WARN

_MASK

Reserved

I_LOAD_

READY_MASK

Bits

Field

Type

Default

Description

7

PGOOD_INT

_MASK

R/W

X

Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect PGOOD_STAT status bit in TOP_STAT register.

6:5

4

Reserved

R/W

00

X

SYNC_CLK

_MASK

Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1

register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register.

3

2

Reserved

R/W

0

TDIE_WARN

_MASK

X

Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.

1

0

Reserved

R/W

0

I_MEAS

_MASK

X

Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1

register).

0 - Interrupt generated

1 - Interrupt not generated.

7.6.1.26 TOP_MASK_2

Address: 0x21

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

RESET_REG

_MASK

Bits

7:1

0

Field

Type

R/W

Default

000 0000

X

Description

Reserved

RESET_REG

_MASK

Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):

0 - Interrupt generated

1 - Interrupt not generated.

This change of this bit by I²C writing has no effect because it will be read from OTP

memory during reset.

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7.6.1.27 BUCK_MASK

Address: 0x22

D7

D6

D5

D4

D3

D2

D1

D0

BUCK1_PGF

_MASK

BUCK1_PGR

_MASK

Reserved

BUCK1_ILIM

_MASK

BUCK0_PGF

_MASK

BUCK0_PGR

_MASK

Reserved

BUCK0_ILIM

_MASK

Bits

Field

Type

Default

Description

7

BUCK1_PGF_MAS

K

R/W

X

Masking of Power Good invalid detection for Buck1 power good interrupt

(BUCK1_PG_INT in INT_BUCK register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.

6

BUCK1_PGR_MAS

K

R/W

X

Masking of Power Good valid detection for Buck1 Power Good interrupt

(BUCK1_PG_INT in INT_BUCK register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.

5

4

Reserved

R

0

BUCK1_ILIM

_MASK

R/W

X

Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK

register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register.

3

2

BUCK0_PGF_MAS

K

R/W

X

Masking of Power Good invalid detection for Buck0 power good interrupt

(BUCK0_PG_INT in INT_BUCK register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.

BUCK0_PGR_MAS

K

Masking of Power Good valid detection for Buck0 power good interrupt

(BUCK0_PG_INT in INT_BUCK register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.

1

0

Reserved

R

0

BUCK0_ILIM

_MASK

R/W

X

Masking for Buck0 current limit detection interrupt (BUCK0_ILIM_INT in INT_BUCK

register):

0 - Interrupt generated

1 - Interrupt not generated.

This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STAT register.

7.6.1.28 SEL_I_LOAD

Address: 0x24

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

LOAD_CURRE

NT_BUCK

_SELECT

Bits

7:1

0

Field

Type

R/W

Default

000 0000

0

Description

Reserved

LOAD_CURRENT_

BUCK_SELECT

Start the current measurement on the selected regulator:

0 - Buck0

1 - Buck1

The measurement is started when register is written.

7.6.1.29 I_LOAD_2

Address: 0x25

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

BUCK_LOAD_

CURRENT[8]

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Bits

7:1

0

Field

Type

R

Default

000 0000

0

Description

Reserved

BUCK_LOAD_

CURRENT[8]

R

This register describes the MSB bit of the average load current on selected regulator

with a resolution of 20 mA per LSB and maximum 10.22-A current.

7.6.1.30 I_LOAD_1

Address: 0x26

D7

D6

D5

D4

D3

D2

D1

D0

BUCK_LOAD_CURRENT[7:0]

Bits

Field

Type

Default

Description

7:0

BUCK_LOAD_

CURRENT[7:0]

R

0000 0000 This register describes 8 LSB bits of the average load current on selected regulator

with a resolution of 20 mA per LSB and maximum 10.22-A current.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65653-Q1 is a power management unit including two step-down regulators and two general-purpose

digital output signals.

8.2 Typical Application

L₀

V_{OUT_B0}

V_IN

LOAD

VIN_B0

VIN_B1

SW_B0

FB_B0

C_{IN_BUCK0}

C_{IN_BUCK1}

C_{OUT_BUCK0}

C_{OUT_POL0}

VIN

L₁

V_{OUT_B1}

LOAD

SW_B1

FB_B1

VANA

C_ANA

SDA

SCL

nINT

EN

C_{OUT_BUCK1}

C_{OUT_POL1}

CLKIN (GPO2)

GPO

PGOOD

GNDs

Figure 22. TPS65653-Q1 Typical Application

8.2.1 Design Requirements

8.2.1.1 Inductor Selection

The inductors L₀and L₁are shown in the Typical Application. The inductance and DCR of the inductor affects the

control loop of the buck regulator. TI recommends using inductors similar to those listed in Table 8. Pay attention

to the saturation current and temperature rise current of the inductor. Check that the saturation current is higher

than the peak current limit and the temperature rise current is higher than the maximum expected rms output

current. For the minimum effective inductance to ensure good performance at maximum peak output current over

the operating temperature range refer to Electrical Characteristics. DC resistance of the inductor must be less

than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss also affects conversion efficiency.

Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Shielded

inductors are preferred as they radiate less noise.

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Typical Application (continued)

Table 8. Recommended Inductors

RATED DC CURRENT

I_SATmaximum (typical) /

I_TEMPmaximum (typical) (A)

DCR

MANUFACTURER

Murata

PART NUMBER

VALUE

DIMENSIONS L × W × H (mm)

2.5 × 2 × 1.2

typical / maximum (mΩ)

DFE252012PD-

R47M

0.47 µH (20%)

5.2 (–) / 4 (–)⁽¹⁾

— / 27

40 / 46

Tayo Yuden

MDMK2020TR47M 0.47 µH (20%)

MV

2 × 2 ×1.2

4.2 (4.8) / 2.3 (2.45)

(1) Operating temperature range is up to 125°C including self temperature rise.

8.2.1.2 Buck Input Capacitor Selection

The input capacitors C_{IN_BUCK0}and C_{IN_BUCK1}are shown in the Typical Application. A ceramic input bypass

capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to

the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input

voltage filtering. Use X7R type of capacitors, not Y5V or F. Also the DC bias characteristics capacitors must be

considered. Minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at

maximum input voltage including tolerances, ambient temperature range and aging. This is assuming that there

are at least 22 μF of additional capacitance common for all the power input pins on the system power rail. See

Table 9.

The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces

voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering

of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient

ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.

Table 9. Recommended Buck Input Capacitor (X7R Dielectric)

DIMENSIONS L × W × H

(mm)

VOLTAGE

RATING

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

Murata

GCM21BR71A106KE22

10 µF (10%)

0805

2 × 1.25 × 1.25

10 V

8.2.1.3 Buck Output Capacitor Selection

The output capacitor C_{OUT_BUCK0}and C_{OUT_BUCK1}are shown in Typical Application. A ceramic local output

capacitor of 22 μF is required per buck. Use ceramic capacitors, X7R type; do not use Y5V or F. DC bias voltage

characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow

from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces

output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and

ESL to perform these functions. Minimum effective output capacitance to ensure good performance is 10 μF per

buck including the DC voltage rolloff, tolerances, aging, and temperature effects.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

R_ESR. The R_ESRis frequency dependent (as well as temperature dependent); make sure the value used for

selection process is at the switching frequency of the part. See Table 10.

POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher

output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreases

the PFM switching frequency. However, output capacitance higher than 100 μF per buck is not necessarily of any

benefit. Note that the output capacitor may be the limiting factor in the output voltage ramp, see Specifications for

maximum output capacitance for different slew-rate settings. For large output capacitors, the output voltage might

be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the

output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be

longer. At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can

increase the input voltage if the load current is small and the output capacitor is large compared to input

capacitor. Below 0.6 V level the output capacitor is discharged by the internal discharge resistor and with large

capacitor more time is required to settle V_OUTdown as a consequence of the increased time constant.

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Table 10. Recommended Buck Output Capacitors (X7R Dielectric)

MANUFACTURER

PART NUMBER

VALUE

CASE SIZE

DIMENSIONS L × W × H

(mm)

VOLTAGE RATING

Murata

GCM31CR71A226KE02

22 µF (10%)

1206

3.2 × 1.6 × 1.6

10 V

8.2.2 Detailed Design Procedure

The performance of the TPS65653-Q1 device depends greatly on the care taken in designing the printed circuit

board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,

while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling

capacitors must be connected close to the device and between the power and ground pins to support high peak

currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output

traces as short as possible, because trace inductance, resistance, and capacitance can easily become the

performance limiting items. The separate buck regulator power pins VIN_Bx are not connected together

internally. Connect the VIN_Bx power connections together outside the package using power plane construction.

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8.2.3 Application Curves

Measurements are done using typical application set up with connections shown in Figure 22. Graphs may not

reflect the OTP default settings. Unless otherwise specified: V_{(VIN_Bx)}= V_(VANA)= 3.7 V, V_{OUT_Bx}= 1 V, T_A= 25°C,

L = 0.47 µH (Murata DFE252012PD-R47M), C_{OUT_BUCK}= 22 µF, and C_{POL_BUCK}= 22 µF.

100

90

80

70

60

50

40

100

90

80

70

60

50

40

Vin = 5V, AUTO

Vin = 3.3V, AUTO

Vin = 5V, FPWM

Vin = 3.3V, FPWM

Vout=1V

Vout=1.8V

Vout=2.5V

0.001

0.01

0.1

1

3

0.001

0.01

0.1

1

3

Output Current (A)

BUCK

V_OUT= 1.8 V

V_IN= 3.3 V

Figure 24. Buck Efficiency in Forced PWM Mode

Figure 23. Buck Efficiency in PFM/PWM and Forced PWM

Mode

100

90

80

70

60

1.02

1.015

1.01

1.005

1

0.995

0.99

0.985

0.98

Vout=1V

Vout=1.8V

Vout=2.5V

50

Vin = 3.3V, FPWM

Vin = 5.5V, FPWM

40

0.001

0.01

0.1

1

3

0

0.5

1

1.5

2

2.5

3

Output Current (A)

BUCK

V_IN= 5 V

Figure 25. Buck Efficiency in Forced PWM Mode

V_OUT= 1 V

Figure 26. Buck Output Voltage vs Load Current in Forced

PWM Mode

1.02

1.015

1.01

1.005

1

1.02

1.016

1.012

1.008

1.004

1

0.996

0.992

0.988

0.984

0.98

0.995

0.99

0.985

0.98

Vin = 3.3V, AUTO

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

BUCK

V_OUT= 1 V

Load = 1 A

Figure 27. Buck Output Voltage vs Load Current in

PFM/PWM Mode

Figure 28. Buck Output Voltage vs Input Voltage in PWM

Mode

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1.014

1.008

1.002

0.996

0.99

0.984

PWM

PFM

0.978

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

4mhz

Load = 1 A (PWM) and 0.1 A (PFM)

Figure 29. Buck Output Voltage vs Temperature

Slew-rate = 10 mV/µs

I_LOAD= 0 A

V_OUT= 1 V

Figure 30. Buck Start-Up With EN1, Forced PWM Mode

Slew-rate = 10 mV/µs

R_LOAD= 1 Ω

V_OUT= 1 V

Slew-rate = 10 mV/µs

R_LOAD= 1 Ω

V_OUT= 1 V

Figure 31. Buck Start-Up with EN1, Forced PWM Mode

Figure 32. Buck Shutdown With EN1, Forced PWM Mode

I_OUT= 500 mA

I_OUT= 10 mA

Figure 34. Buck Output Voltage Ripple,

Forced PWM Mode

Figure 33. Buck Output Voltage Ripple, PFM Mode

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Figure 36. Buck Transient From PWM-to-PFM Mode

Figure 35. Buck Transient From PFM-to-PWM Mode

I_OUT= 0.1 A → 2 A → 0.1 A

T_R= T_F= 400 ns

I_OUT= 0.1 A → 2 A → 0.1 A

T_R= T_F= 400 ns

Figure 38. Buck Transient Load Step Response, Forced

PWM Mode

Figure 37. Buck Transient Load Step Response, AUTO

Mode

V_OUT(200mV/div)

Time (400 µs/div)

Figure 39. Buck V_OUTTransition from 0.6 V to 1.4 V With

Different Slew Rate Settings

Figure 40. Buck V_OUTTransition from 1.4 V to 0.6 V With

Different Slew Rate Settings

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Figure 41. Buck Start-up With Short on Output

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. The VANA input

and VIN_Bx buck inputs must be connected together, and they must use the same input supply. This input

supply must be well regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the

input current transient does not cause too high a drop in the TPS65653-Q1 supply voltage that can cause false

UVLO fault triggering. If the input supply is located more than a few inches from the TPS65653-Q1 additional

bulk capacitance may be required in addition to the ceramic bypass capacitors.

10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the TPS65653-Q1 make the choice of layout important. Good

power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and

generation and can cause a good design to perform with less-than-expected results. With a range of output

currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB

design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and

current regulation across its intended operating voltage and current range.

1. Place C_INas close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the V_INtrace wide and thick

to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of

TPS65653-Q1, as well as the trace between the negative node of the input capacitor and power PGND_Bx

pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source

for the switching converter. The inductance of the connection is the most important parameter of a local

decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper

device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to

top layer by using thin dielectric layer between top layer and ground plane.

2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output

voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI

behavior. Route the traces between the output capacitors of the TPS65653-Q1 and the input capacitors of

the load direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a

quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling

capacitor as close as possible to the VANA pin.

4. If remote voltage sensing can be used for the load, connect the TPS65653-Q1 feedback pins FB_Bx to the

respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept

away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as

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Layout Guidelines (continued)

the I²C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close

to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if

possible. If series resistors are used for load current measurement, place them after connection of the

voltage feedback.

5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers

which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.

Due to the small package of this converter and the overall small solution size, the thermal performance of the

PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and

convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of

a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.

Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB

designs with vias to different planes. This results in reduced junction-to-ambient (R_θJA) and junction-to-board

(R_θJB) thermal resistances, thereby reducing the device junction temperature, T_J. TI strongly recommends

performance of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design

process by using a thermal modeling analysis software.

10.2 Layout Example

VOUT0

VOUT1

C_OUT0

C_OUT1

GND

L1

L0

21 20 19

17

16

18

15

14

SW_B0

SW_B1

VIN_B1

22

23

13

12

SW_B0

VIN_B0

C_IN0

C_IN1

29

AGND

24

VIN

25

VIN

GND

11

VIN_B1

CLKIN

nINT

10

9

GPO

26

27

PGOOD

8

VIN

28

VIN

1

2

3

4

5

6

7

VIN

C_ANA

AGND

Figure 42. TPS65653-Q1 Board Layout

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11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

55

PACKAGE OUTLINE

RHD0028W

VQFN - 1 mm max height

S

C

A

L

E

2

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.05)

A

-

A

2

5

.

0

SECTION A-A

TYPICAL

C

1 MAX

SEATING PLANE

0.08

0.05

0.00

3.4 0.1

(0.2) TYP

8

14

EXPOSED

THERMAL PAD

24X 0.5

7

15

A

SYMM

A

4X

3

1

21

0.3

28X

0.2

0.1

C A B

28

22

PIN 1 ID

(OPTIONAL)

SYMM

0.05

0.65

0.45

28X

4222120/B 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHD0028W

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.4)

SYMM

22

28

28X (0.75)

1

21

28X (0.25)

(1.45)

SYMM

(4.65)

(0.5) TYP

15

7

(R0.05) TYP

(

0.2) TYP

VIA

8

14

(1.45)

(4.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222120/B 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RHD0028W

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.84) TYP

28

22

METAL

TYP

28X (0.75)

1

21

28X (0.25)

(0.84)

TYP

SYMM

(4.65)

24X (0.5)

7

15

(R0.05) TYP

8

14

4X ( 1.47)

(4.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4222120/B 02/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TPS6565342RHDTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有集成开关的汽车类 4MHz、双路 3A 降压转换器 \| RHD \| 28 \| -40 to 125 开关转换器
文件：	总62页 (文件大小：4210K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS6565342RHDTQ1 [TI]

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