TPS65721RSNT_技术文档

TPS65720

TPS65721

www.ti.com

SLVS979 –OCTOBER 2009

PMU for Bluetooth Headsets

Check for Samples: TPS65720 TPS65721

1

FEATURES

DESCRIPTION

2

•

Battery Charger With Power Path Management

•

28 V Rated Power Path With:

The TPS65720 is a small power management unit

targeted for Bluetooth headsets or other portable low

power consumer end equipments. It contains an USB

friendly Lithium-Ion battery charger, a high efficient

step down converter, a low dropout linear regulator

and additional supporting functions. The device is

controlled by an I2C interface. Several settings can

be customized by the use of non volatile memory

which is factory programmed. The 2.25MHz

step-down converter enters a low power mode at light

load for maximum efficiency across the widest

possible range of load currents. For low noise

applications the devices can be forced into fixed

frequency PWM mode using the I2C compatible

interface. The device allows the use of small

inductors and capacitors to achieve a small solution

size. TPS65720 provides an output current of up to

200mA on the DCDC converter. The TPS65720 also

integrates one 200mA LDO. The LDO operates with

an input voltage range between 1.8V and 5.6V

allowing it to be supplied from the output of the

step-down converter or directly from the system

voltage.

–

100 mA Input Current Limit

500 mA input Current Limit

•

300 mA Charge Current

200 mA Step-Down Converter for TPS65720

400 mA Step-Down Converter for TPS65721

Up to 92% Efficiency

V_INRange for DCDC Converter From 2.3V to

5.6V

•

2.25 MHz Fixed Frequency Operation

Power Save Mode at Light Load Current

Output Voltage Accuracy in PWM Mode ±2%

100% Duty Cycle for Lowest Dropout

1 General Purpose 200mA LDO

V_INRange for LDO From 1.8V to 5.6V

I2C Compatible Interface

4GPIOs

Available in a 25 Ball WCSP With 0,4mm Pitch

and in 4mm × 4mm 32-Pin QFN Package

The TPS65720 comes in a small 25-ball wafer chip

scale package (WCSP) with 0,4mm ball pitch or a

4mm × 4mm QFN package with a 0,4mm pitch

(TPS65721).

APPLICATIONS

•

Bluetooth Headsets

•

Handheld Equipment

TPS65720

BAT

AC

BAT

1uF

10k

LiIon

TS

charger / power path

NTC

ISET

R5

SYS

3k

a charge

current of150mA

4.7uF / 6.3V

for

2.2uH

VDCDC1=2.05

V

L1

R1

360k

FB_DCDC1

DCDC1

200mA

4.7uF

22pF

R2

150k

bluetooth chip

VINLDO1

2.2uF

VLDO1 = 1.85V

LDO1

200mA

VLDO1

Vin

4.7uF / 4V

2 x 100k

2 x 3.3k

RESET

INT

reset

generator

Reset

INT

/

startup logic

SYS

R6

HOLD_LDO1

GPIO

PB_IN

HOLD_DCDC1

ON /

OFF

SCLK

SDAT

SCLK

SDAT

I2C interface

PGND

AGND

GPIO0

GPIO1

GPIO or

5mA current

sink

GPIO2

GPIO3

to SYS or VDCDC1

depending on LED

forward voltage

indication LEDs

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65720

TPS65721

SLVS979 –OCTOBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

PACKAGE

MARKING

(1)

T_A

PART NUMBER

SIZE FOR WCSP VERSION PACKAGE CODE

PACKAGE

-40°C TO 85°C

TPS65720

D = 2105 μm ±25 μm

E = 2105 μm ±25 μm

YFF

WCSP

TPS65720

-40°C TO 85°C

TPS65721

RSN

QFN⁽¹⁾

65720

(1) The RSN and YFF package is available in tape and reel. Add R suffix (TPS65720YFFR; TPS65721RSNR) to order quantities of 3000

parts per reel. Add T suffix (TPS65720YFFT; TPS65721RSNT) to order quantities of 250 parts per reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VALUE / UNIT

Input voltage range on all pins except A/PGND, AC, GPIOx pins with respect to AGND

Input voltage range on GPIOx pins with respect to AGND

Input voltage range on AC pin with respect to AGND

Voltage range on pin VLDO1, FB_LDO1, TS_OUT, TS with respect to AGND

Current at AC, BAT, SYS, L1, VLDO1, VINLDO1, PGND

Current at GPIOx, AGND

–0.3 to 7 V

–0.3 to VSYS

–0.3 to 28 V

–0.3 to 3.6 V

600 mA

20 mA

Current at all other pins

3 mA

Continuous total power dissipation

See dissipation rating table

–40°C to 85°C

125°C

Operating free-air temperature, T_A

Maximum junction temperature, T_J

Storage temperature, T_ST

–65°C to 150°C

DISSIPATION RATINGS⁽¹⁾

PACKAGE

R_θJA

T

_A≤ 25°C

DERATING FACTOR

ABOVE T_A= 25°C

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

YFF

55 K/W

38 K/W

1.8 W

18 mW/K

26 mW/K

1 W

0.7 W

1 W

RSN

2.6 W

1.4 W

(1) The thermal resistance was measured on a high K board.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

V_AC

Input voltage range at AC pin

Voltage range at SYS pin

Input current at AC

4.35

2.2

28

5.6

V

V_SYS

I_INUSB

I_OUTSYS

I_BAT

500

mA

V

Output current at SYS

400

Average current into / out of BAT pin

300

V_INDCDC1

V_DCDC1

I_OUTDCDC1

L

Input voltage range for step-down converter DCDC1

Output voltage range for DCDC1 step-down converter; externally adjustable

Output current at L

2.3

0.6

5.6

V_INDCDC1

400

V

mA

μH

V

(1)

Inductor at L

2.2

1.8

0.8

3.3

4.7

V_INLDO1

V_LDO1

I_LDO1

Input voltage range for LDO1

Output voltage range for LDO1

Output current at LDO1

VSYS

3.3

V

200

mA

(1) See application section for more details

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Product Folder Link(s): TPS65720 TPS65721

TPS65720

TPS65721

www.ti.com

SLVS979 –OCTOBER 2009

RECOMMENDED OPERATING CONDITIONS (continued)

MIN NOM

MAX UNIT

C_INAC

C_BAT

Input capacitor at AC⁽¹⁾

Capacitor at BAT⁽¹⁾

Capacitor at SYS⁽¹⁾

0.1

4.7

1

4.7

10

μF

C_SYS

C_INDCDC1

Input capacitor at V_INDCDC1⁽¹⁾; if connected to SYS, only one 4.7μF cap required for

SYS and CINDCDC1

(1)

C_OUTDCDC1Output capacitor at V_DCDC1

4.7

2.2

700

10

22

μF

Ω

C_INLDO1

C_OUTLDO1

R_ISET

Input capacitor at VINLDO1⁽¹⁾

Output capacitor at LDO1⁽¹⁾

Minimum R_ISETvalue for proper operation; lower values may trigger the short circuit

protection on ISET

T_A

T_J

Operating ambient temperature

Operating junction temperature

–40

85

°C

125

ELECTRICAL CHARACTERISTICS

V_SYS= 3.6V, V_DCDC1= 2.05V, PFM mode, L = 3.3μH, C_OUTDCDC1= 4.7μF, V_INLDO1=2.05V, V_LDO1=1.85V, T_A= –40°C to 85°C

typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY CURRENT

DCDC1 enabled, IOUT = 0mA. PFM mode enabled; device not

switching

36

45

μA

Operating quiescent current when only DCDC1

converter is enabled

I_Q

DCDC1 enabled, IOUT = 0mA. PWM mode

Current into BAT pin (PFM mode)

Current into VINLDO1

2.8

33

13

mA

μA

50

18

Operating quiescent current when LDO1 and

DCDC1 are enabled

I_Q

Shutdown current after voltage was applied to BAT For VINLDO1=0V (LDO1 supplied by DCDC1); powered by

4

12

13

17

18

μA

but device never enabled before (shipping mode)

VBAT=3.6V

For VINLDO1=0V (LDO1 supplied by DCDC1); powered by

VBAT=3.6V

I_SD

Shutdown current after first power-up

For VINLDO1≠0V (LDO1 supplied by SYS); powered by

VBAT=3.6V

Shutdown current after first power-up

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Product Folder Link(s): TPS65720 TPS65721

TPS65720

TPS65721

SLVS979 –OCTOBER 2009

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

V_SYS= 3.6V, V_DCDC1= 2.05V, PFM mode, L = 3.3μH, C_OUTDCDC1= 4.7μF, V_INLDO1=2.05V, V_LDO1=1.85V, T_A= –40°C to 85°C

typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD

High level input voltage for SCLK, SDAT, GPIOx,

V_IH

GPIOs configured as input

1.2

0

VSYS

0.4

V

HOLD_DCDC1, HOLD_LDO1, PB_IN

Low level input voltage for SCLK, SDAT, GPIOx,

HOLD_DCDC1, HOLD_LDO1, PB_IN

V_IL

GPIOs configured as input

Low level output voltage for SDAT, GPIOx, INT,

RESET

V_OL

GPIOs configured as output; Io=1mA; no internal pull-up

0

0.4

GPIO2, GPIO3 configured as current sink; VOL=0.4V ; for

Tj=0°C to 85°C

Sink current for GPIO2, GPIO3

Sink current for GPIOx

–20%

5

20%

3

mA

I_OL

GPIOx configured as open drain output ; output = LOW

Minimum voltage for proper current regulation from

GPIO2 or GPIO3 to GND if programmed as a

current sink

V_OL

Io=5mA; current sink turned on

0.4

V

VLDO1,

nom-13%

VLDO1,

nom-7%

V_{RESET-falling}

V_RESET-rising

Falling edge; Reset is asserted LOW for TPS65720

V

LDO1 out of regulation reset voltage

Reset delay time on pin RESET

Rising edge; Reset is released HIGH for TPS65720 after

T_RESET

VLDO1,

nom-4%

Low to high transition of RESET pin, depending on setting of

Bit RESET_DELAY

9

70

11

90

13

110

ms

T_RESET

HIGH to LOW transition of RESET pin RESET will go low by

HOLD pin going LOW AND HOLD Bit set to 0 OR voltage at

V_resetfalling below the threshold

10

μs

V_{THRESHOLD_down}Threshold voltage for reset input

V_{THRESHOLD_hys}Hysteresis on THRESHOLD

Falling voltage; QFN package only

Rising voltage; QFN package only

Rising and falling voltage

–3%

39

570

30

3%

mV

ms

T_debounce

I_LKG

Debounce time at PB_IN

Input leakage current

50

60

PB_IN, SDAT, SCLK, GPIOx configured as output, INT,

RESET, output high impedance

0.2

μA

STEP-DOWN CONVERTER

V_SYS

Input voltage for DCDC1

2.3

5.6

V

V_SYSfalling

V_SYSrising

2.15

2.2

2.25

UVLO

Internal undervoltage lockout threshold hysteresis

120

mV

POWER SWITCH

R_DS(ON)

I_{LK_HS}

V_SYS= V_INDCDC1= 3.6V, YFF package

V_SYS= V_INDCDC1= 3.6V, RSN package

V_DS= 5.6V

350

400

600

650

1

High side MOSFET on-resistance

High side MOSFET leakage current

Low side MOSFET on-resistance

Low side MOSFET leakage current

mΩ

μA

mΩ

μA

V_INDCDC1/2= 3.6 V, YFF package

V_INDCDC1/2= 3.6 V, RSN package

VDS = 5.6 V

300

350

500

550

1

R_DS(ON)

I_{LK_LS}

2.3 V ≤ V_IN≤ 5.6 V, TPS65720

2.3 V ≤ V_IN≤ 5.6 V, TPS65721

V_SYS> 2.7 V; TPS65720

425

625

600

850

775

1150

200

400

mA

Forward current limit high-side and low side

MOSFET

I_LIMF

I_o

DC output current

mA

V_SYS> 2.7 V ; TPS65721

OSCILLATOR

f_SW

Oscillator Frequency

2.03

0.6

2.25

2.48

Vin

MHz

OUTPUT

V_OUT

V_FB

Output Voltage Range

Feedback voltage

V

0.6

1%

0.5

I_FB

FB pin input current

0.1

3%

2%

μA

V_IN= 2.3 V to 5.6 V; PFM operation, 0 mA < I_OUT< I_OUTMAX

V_IN= 2.3 V to 5.6 V, PWM operation, 0 mA < I_OUT< I_OUTMAX

PWM operation

DC Output voltage accuracy⁽¹⁾

V_OUT

–2%

DC output voltage load regulation

%/A

V

VDCDC1,

nom-14%

VDCDC1,

nom-7%

V_{PGOOD-falling}

V_PGOOD-rising

PGOOD threshold at falling output voltage

<PGOODZ_DCDC1> is set to 1

<PGOODZ_DCDC1> is set to 0

VDCDC1,

nom-5%

PGOOD threshold at rising output voltage

V

t_Start

Start-up time

Time from active EN to Start switching

Time to ramp from 5% to 95% of V_OUT

170

250

μs

t_Ramp

V_OUTramp time

(1) Output voltage specification does not include tolerance of external voltage programming resistors

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Product Folder Link(s): TPS65720 TPS65721

TPS65720

TPS65721

www.ti.com

SLVS979 –OCTOBER 2009

ELECTRICAL CHARACTERISTICS (continued)

V_SYS= 3.6V, V_DCDC1= 2.05V, PFM mode, L = 3.3μH, C_OUTDCDC1= 4.7μF, V_INLDO1=2.05V, V_LDO1=1.85V, T_A= –40°C to 85°C

typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DCDC1 disabled; the discharge function can be disabled as an

EEPROM option

R_DIS

Internal discharge resistor at L

300

400

Ω

THERMAL PROTECTION FOR DCDC1 AND LDO1

T_SD

Thermal shutdown

Increasing junction temperature

Decreasing junction temperature

150

30

°C

Thermal shutdown hysteresis

VLDO1 LOW DROPOUT REGULATOR

V_INLDO

V_LDO1

V_{FB_LDO1}

I_{FB_LDO1}

I_O

Input voltage range for LDO1

1.8

0.8

5.6

3.3

V

LDO1 output voltage range

LDO1 output voltage

Default output voltage for TPS65720 only

Externally adjustable version only: TPS65721

1.85

0.8

V

Feedback voltage

V

FB pin input current

0.1

200

500

180

μA

mA

mV

Output current for LDO1

I_SC

LDO1 short circuit current limit

Dropout voltage at LDO1, YFF package

Dropout voltage at LDO1, RSN package

Output voltage accuracy for LDO1

Line regulation for LDO1

VLDO1 = GND; VinLDO1=2.05V

350

120

I_O= 200 mA, V_INLDO= 2.05 V

I_O= 200 mA

–1.5%

–1%

2.5%

1%

V_INLDO1= V_LDO1+ 0.5V (min. 1.8V) to 5.6 V (VSYS), I_O= 50 mA

I_O= 0 mA to 200 mA for LDO1

Load regulation for LDO1

PGOOD debounce time

–1%

2%

Internal PGOOD comparator at VOUTLDO1 is debounced by

80

μs

Internal soft-start when LDO is enabled;

Time to ramp from 5% to 95% of V_OUT

t_Ramp

R_DIS

V_OUTRamp time

250

LDO disabled, discharge function per default disabled in

register

Internal discharge resistor at VLDO1

250

400

Ω

BATTERY VOLTAGE COMPARATOR

Battery voltage comparator threshold voltage

Depending on Bits <VBAT0>, <VBAT1>; falling voltage

Rising voltage

–3%

3%

V

Battery voltage comparator threshold voltage

hysteresis

200

3.3

80

mV

POWER PATH

V_UVLO

Undervoltage lockout

Hysteresis on UVLO

V_AC: 0V → 4V

V_AC: 4V → 0V

3.2

3.45

300

V

V_HYS-UVLO

200

mV

(Input power detected if V_IN> V_BAT+ V_IN-DT) V_BAT= 3.6V,

V_IN: 3.5V → 4V

V_IN-DT

Input power detection threshold

Hysteresis on VIN-DT

40

20

140

mV

ms

V_HYS-INDT

t_DGL(PGOOD)

V_BAT= 3.6 V, V_IN: 4V → 3.5V

Time measured from V_IN: 0V → 5V 1μs

rise-time to PGOOD = LO

Deglitch time, input power detected status

2

V_OVP

Input over-voltage protection threshold

Hysteresis on OVP

V_AC: 5 V → 7 V

V_AC: 11V → 5V

6.4

6.6

105

50

6.8

V

V_HYS-OVP

t_BLK(OVP)

mV

μs

Input over-voltage blanking time

Time measured from V_AC: 11V → 5V 1μs

fall-time to <CH_PGOOD>=0

t_REC(OVP)

Input over-voltage recovery time

2

ms

I_SYS= 0.3A, V_AC= 4.35V, V_BAT=4.2V; YFF package

I_SYS= 0.3A, V_AC= 4.35V, V_BAT=4.2V; RSN package

I_SYS= 0.2A, V_AC= 0V, V_BAT> 3V; YFF package

I_SYS= 0.2A, V_AC= 0V, V_BAT> 3V; RSN package

00: V_AC> V_SYS+ V_DO(AC-SYS), V_BAT< 3.3V

170

210

285

325

80

mV

AC pin to SYS pin dropout voltage

V_AC– V_SYS

V_DO(AC-SYS)

Battery to SYS pin dropout voltage

V_BAT– V_SYS

V_DO(BAT-SYS)

120

5%

–5%

3.4

V_BAT

+

00: V_AC> V_SYS+ V_DO(AC-SYS), V_BAT>/= 3.3V

5%

200mV

SYS pin voltage regulation selectable register

V_SYS(REG)

V

01: V_AC> V_SYS+ V_DO(AC-SYS)

–5%

90

4.4

5.0

5.5

95

5%

100

500

10: V_AC> V_SYS+ V_DO(AC-SYS)

11: V_AC> V_SYS+ V_DO(AC-SYS)

Bit <AC input current1, AC input current0> = 00

Bit < AC input current1, AC input current0> = 01 or 10

mA

I_AC-MAX

Maximum Input Current Register <CHCONFIG0>

450

475

Input voltage threshold when input current is

reduced

Input current is reduced if voltage at AC falls below VAC-LOW

to keep the AC voltage above 4.5V

V_AC-LOW

4.35

4.5

4.65

V

Output voltage threshold when charging current is

reduced

V_O(REG)

–100mV

Bit <V_DPPM> = 1

Bit <V_DPPM> = 0

V

V_DPM

Register <CHCONFIG2>

4.3

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Product Folder Link(s): TPS65720 TPS65721

TPS65720

TPS65721

SLVS979 –OCTOBER 2009

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ELECTRICAL CHARACTERISTICS (continued)

V_SYS= 3.6V, V_DCDC1= 2.05V, PFM mode, L = 3.3μH, C_OUTDCDC1= 4.7μF, V_INLDO1=2.05V, V_LDO1=1.85V, T_A= –40°C to 85°C

typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OUT

≤

V_BSUP1

Enter battery supplement mode

V_BAT

V

–40mV

V_OUT

≥

V_BSUP2

V_O(SC1)

V_O(SC2)

Exit battery supplement mode

V_BAT

–20mV

V

Output short-circuit detection threshold, power-on

0.8

0.9

1

V

Output short-circuit detection threshold, supplement

mode

200

250

300

mV

V_BAT– V_OUT> V_O(SC2)indicates short-circuit

t_DGL(SC2)

t_REC(SC2)

Deglitch time, supplement mode short circuit

Recovery time, supplement mode short circuit

250

60

μs

ms

BATTERY CHARGER

QUIESCENT CURRENT

V_IN= 5V; ACinputcurrent[1,0]=11

60

80

μA

I_IACSTDBY)

Standby current into AC pin

V_IN= 28V; ACinputcurrent[1,0]=11

530

V_IN= 5V, no load on DCDC1, LDO1, SYS pin, VSYS[1,0]=11;

ACinputcurrent[1,0]=10; CH_EN=0

I_CC

Active supply current, AC pin

2

mA

IBAT(SC)

VBAT(SC)

Source current for BAT pin short-circuit detection

BAT pin short-circuit detection threshold

4

1.6

7.5

1.8

11

2.0

1%

3.1

mA

V

–1%

2.9

4.15

4.175

4.20

4.225

4.25

4.275

4.30

4.325

3.0

Depending on setting in CHGCONFIG3 And internal EEPROM

Default = 4.2V

V_o(BATREG)

Battery charger voltage

V

V_LOWV

Pre-charge to fast-charge transition threshold

V

Deglitch time on pre-charge to fast-charge

transition

t_DGL1(LOWV)

25

ms

Deglitch time on fast-charge to pre-charge

transition

t_DGL2(LOWV)

ms

Maximum battery fast charge current

Minimum battery fast charge current

300

mA

V_BAT(REG)> V_BAT> V_LOWV, V_IN= V_ACor V_USB= 5V

10

I_CHG

V_BAT> V_LOWV, V_IN= 5V, I_IN-MAX> I_CHG, No load on SYS pin,

thermal loop not active, DPPM loop not active

Battery fast charge current set factor

K_ISET/ R_ISET

450

A

at 300mA for ICH_SCL[1,0]=11 (charge current scaling is

100% of ISET value)

–15%

–20%

15%

20%

at 40mA for ICH_SCL[1,0]=11 (charge current scaling is 100%

of ISET value)

450

at 225mA range for ICH_SCL[1,0]=10 (charge current scaling

is 75% of ISET value)

–15%

338

15%

at 30mA for ICH_SCL[1,0]=10 (charge current scaling is 75%

of ISET value)

–20%

338

20%

K_ISET

Fast charge current factor

AΩ

at 150mA for ICH_SCL[1,0]=01 (charge current scaling is 50%

of ISET value)

–10%

225

10%

at 20mA for ICH_SCL[1,0]=01 (charge current scaling is 50%

of ISET value)

–15%

225

15%

at 75mA for ICH_SCL[1,0]=00 (charge current scaling is 25%

of ISET value)

–10%

112

10%

at 10mA for ICH_SCL[1,0]=00 (charge current scaling is 25%

of ISET value)

–20%

112

20%

for I_PRE[1,0]=11 (pre-charge current scaling is 20% of charge

current)

0.15×I_CHG

0.11×I_CHG

0.07×I_CHG

0.03×I_CHG

0.2×I_CHG

0.15×I_CHG

0.1×I_CHG

0.05×I_CHG

0.25×I_CHG

0.19×I_CHG

0.13×I_CHG

0.08×I_CHG

for I_PRE[1,0]=10 (pre-charge current scaling is 15% of charge

current)

I_PRECHG

Pre-charge current

for I_PRE[1,0]=01 (pre-charge current scaling is 10% of charge

current)

for I_PRE[1,0]=00 (pre-charge current scaling is 5% of charge

current)

6

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ELECTRICAL CHARACTERISTICS (continued)

V_SYS= 3.6V, V_DCDC1= 2.05V, PFM mode, L = 3.3μH, C_OUTDCDC1= 4.7μF, V_INLDO1=2.05V, V_LDO1=1.85V, T_A= –40°C to 85°C

typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

0.27×I_CHG

for I_TERM[1,0]=11 (termination current is 20% of charge

current)

0.15×I_CHG

0.2×I_CHG

for I_TERM[1,0]=10 (termination current is 15% of charge

current)

0.11×I_CHG

0.07×I_CHG

0.03×I_CHG

0.15×I_CHG

0.1×I_CHG

0.05×I_CHG

0.21×I_CHG

0.15×I_CHG

0.08×I_CHG

Charge current value for termination detection

threshold (internally set)

I_TERM

for I_TERM[1,0]=01 (termination current is 10% of charge

current)

for I_TERM[1,0]=00 (termination current is 5% of charge

current)

t_DGL(TERM)

V_RCH

Deglitch time, termination detected

Recharge detection threshold

25

100

ms

mV

ms

Voltage below nominal charger voltage

165

60

10

t_DGL(RCH)

Deglitch time, recharge threshold detected

62.5

VBAT = 3.6V. Time measured from VIN: 5V → 3.3V 1μs

fall-time

t_DGL(NO-IN)

Delay time, input power loss to charger turn-off

20

ms

I_BAT(DET)

t_DET

Sink current for battery detection

Battery detection timer

5

7.5

mA

ms

250

Safety timer range selectable by I2C; default setting without

DPPM or thermal loop active

T_CHG

Charge safety timer

Precharge timer

–35%

5

35%

h

T_PRECHG

Pre charge timer range; default setting

30

min

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ELECTRICAL CHARACTERISTICS (continued)

V_SYS= 3.6V, V_DCDC1= 2.05V, PFM mode, L = 3.3μH, C_OUTDCDC1= 4.7μF, V_INLDO1=2.05V, V_LDO1=1.85V, T_A= –40°C to 85°C

typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)

PARAMETER

BATTERY-PACK NTC MONITOR

TEST CONDITIONS

MIN

TYP

MAX UNIT

Thermistor high temperature detection resistance

(equals 45°C for 10k NTC; B=3380)

4.3

3.5

2.9

2.4

43

5

4.1

3.5

3

5.7

4.8

4.2

3.5

57

kΩ

Thermistor high temperature detection resistance

(equals 50°C for 10k NTC; B=3380)

Thermistor high temperature detection resistance

(equals 55°C for 10k NTC; B=3380 )

Thermistor high temperature detection resistance

(equals 60°C for 10k NTC; B=3380)

Hot temperature detected and charging suspended when the

resistance of the battery-NTC is lower than RNTC_HOT

RNTC_HOT

Thermistor high temperature detection resistance

(equals 45°C for 100k NTC)

50

Thermistor high temperature detection resistance

(equals 50°C for 100k NTC)

35

41

48

Thermistor high temperature detection resistance

(equals 55°C for 100k NTC)

29

35

42

Thermistor high temperature detection resistance

(equals 60°C for 100k NTC)

24

30

35

Thermistor low temperature detection resistance

(equals 0°C for 10k NTC; B=3380)

25

27

30

Thermistor low temperature detection resistance

(equals 5°C for 10k NTC; B=3380)

20

22

24

Thermistor low temperature detection resistance

(equals 10°C for 10k NTC; B=3380 )

16

18

20

Thermistor low temperature detection resistance

(equals 15°C for 10k NTC; B=3380)

13

15

16

Cold temperature detected and charging suspended when the

resistance of the battery-NTC is higher than RNTC_COLD

RNTC_COLD

Thermistor low temperature detection resistance

(equals 0°C for 100k NTC)

250

200

160

130

270

220

180

150

300

240

200

160

Thermistor low temperature detection resistance

(equals 5°C for 100k NTC)

Thermistor low temperature detection resistance

(equals 10°C for 100k NTC)

Thermistor low temperature detection resistance

(equals 15°C for 100k NTC)

V_HYS(COLD)

R_NOSENSOR

t_DGL(TS)

Low temperature trip point hysteresis

Thermistor not detected for 10k NTC

Thermistor not detected for 100k NTC

Deglitch time, pack temperature fault detection

For 10k NTC; B=3380

5

340

3400

50

°C

kΩ

ms

260

620

Hot temperature detected and charging suspended when the

resistance of the battery-NTC is higher than R_NOSENSOR

2500

6200

THERMAL REGULATION

T_J(REG)

Lower Temperature regulation limit

115

135

155

20

°C

T_J(REG)

Upper Temperature regulation limit

Thermal shutdown temperature

Thermal shutdown hysteresis

T_J(OFF)

T_J(OFF-HYS)

8

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DEVICE INFORMATION

Chip scale version (YFF package): PIN ASSIGNMENT (bottom view)

AC

ISET

SYS

RESET

PB_IN

SDAT

SCLK

A5

A4

SYS

GPIO0

GPIO1

BAT

INT

GPIO2

GPIO3

A3

A2

HOLD_

DCDC1

HOLD_

LDO1

L1

TS

GND

FB_

DCDC1

PGND

AGND

VINLDO1

VLDO1

E1

D1

C1

B1

A1

FUNCTIONAL BLOCK DIAGRAM

TPS65720

BAT

AC

BAT

1uF

LiIon

TS

charger / power path

NTC

ISET

R5

SYS

set

charge

current

SYS

4.7uF

2.2uH

22pF

L1

Vout 1

4.7uF

DCDC1

200mA

R1

FB_DCDC1

HOLD_DCDC1

R2

VINLDO1

VLDO1

Vout 2

LDO1

200mA

2.2uF

HOLD_LDO1

SYS

R6

RESET

INT

reset

generator /

startup logic

PB_IN

ON /

OFF

SCLK

SDAT

I2C interface

PGND

AGND

GPIO0

GPIO1

GPIO or

5mA current

sink

GPIO2

GPIO3

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PIN FUNCTIONS for CHIP SCALE VERSION (YFF package)

I/O

DESCRIPTION

NAME

NO.

AC

E5

I

Input power for power manager, connect to external DC supply.

SYS

BAT

ISET

TS

E4, D4

E3, D3

D5

O

System voltage; output of the power path manager. Power input for step-down converter DCDC1

I/O Connect to battery + terminal

I

Connect a resistor from this pin to GND to set fast charge current

Connect a thermistor from this pin to GND for battery temperature

Analog ground

C2

AGND

C1

PGND

E1

Power ground

GND

B2

Connect to AGND and PGND

L1

E2

O

I

Switch output of step-down converter

Feedback input of step-down converter

FB_DCDC1

HOLD_DCDC1

D1

D2

I

Power-On input for DCDC1 converter. When pulled HIGH, the DCDC converter is kept enabled after

PB_IN was released HIGH.

VINLDO1

VLDO1

B1

A1

A2

I

O

I

Input voltage for LDO1

Output voltage of LDO1

HOLD_LDO1

Power-On input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released

HIGH.

SDAT

SCLK

PB_IN

INT

B5

A5

C4

C3

C5

I/O Data line for the I2C interface

I

Clock input for the I2C interface

I

Push button input; Turns on DCDC1 and LDO1 if pulled to GND.

Open drain interrupt output

O

RESET

Open drain output of the reset generator; This output goes active LOW when the output voltage of

LDO1 falls 8% below its target voltage.

GPIO0

GPIO1

GPIO2

GPIO3

B4

A4

B3

A3

I/O General purpose I/O

I/O General purpose I/O or 5mA current sink

QFN version (RSN package): PIN ASSIGNMENT (top view)

24 23 22 21 20 19 18 17

16

15

14

ISET

HOLD_DCDC1

FB_DCDC1

TS

25

26

27

28

PB_IN

RESET

INT

TPS65721

AGND

13

12

11

10

GND

VINLDO1

VLDO1

NC

SDAT

29

30

31

32

MODE

NC

9

1

2 3 4 5 6 7 8

10

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FUNCTIONAL BLOCK DIAGRAM

TPS65721

AC

BAT

1uF

LiIon

TS

charger / power path

NTC

SYS

ISET

R5

set

charge

current

SYS

4.7uF

2.2uH

L1

4.7uF

Vout1

MODE

DCDC1

R1

200mA

HOLD_DCDC1

FB_DCDC1

22pF

R2

VINLDO1

VLDO1

Vout2

2.2uF

LDO1

200mA

FB_LDO1

HOLD_LDO1

R3

R4

SYS

R6

THRESHOLD

PB_IN

reset

generator /

startup logic

RESET

INT

ON /

OFF

SCLK

SDAT

I2C interface

PGND

AGND

GPIO0

GPIO1

GPIO or

5mA current

sink

GPIO2

GPIO3

PIN FUNCTIONS for QFN VERSION (RSN package)

DESCRIPTION

I/O

NAME

AC

NO.

17, 18

19, 20

21, 22

16

I

O

I/O

I

Input power for power manager, connect to external DC supply.

SYS

System voltage; output of the power path manager. Power input for step-down converter DCDC1

Connect to battery + terminal

BAT

ISET

Connect a resistor from this pin to GND to set fast charge current

Connect a thermistor from this pin to GND for battery temperature

Analog ground

TS

27

I

AGND

PGND

L1

28

24

Power ground

23

O

I

Switch output of step-down converter

FB_DCDC1

26

Feedback input of step-down converter

HOLD_DCDC1

25

I

Power-On input for DCDC1 converter. When pulled HIGH, the DCDC converter is kept enabled after

PB_IN was released HIGH.

VINLDO1

VLDO1

30

31

1

I

O

I

Input voltage for LDO1

Output voltage from LDO1

Feedback input for LDO1

FB_LDO1

HOLD_LDO1

2

I

Power-On input for LDO1. When pulled HIGH, LDO1 is kept enabled after PB_IN was released

HIGH.

SDAT

SCLK

PB_IN

INT

12

8

I/O

Data line for the I2C interface

I

Clock input for the I2C interface

15

13

Push button input; Turns on DCDC1 and LDO1 if pulled to GND.

Open drain interrupt output

O

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PIN FUNCTIONS for QFN VERSION (RSN package) (continued)

I/O

DESCRIPTION

NAME

RESET

NO.

14

3

O

Open drain output of the reset generator; This output goes active LOW when the input voltage at

pin THRESHOLD falls below the threshold voltage.

THRESHOLD

I

Input voltage to the reset comparator. When the input voltage falls below the threshold, the RESET

output is actively pulled LOW.

GPIO0

GPIO1

GPIO2

GPIO3

MODE

GND

7

I/O

I

General purpose I/O

6

General purpose I/O

5

General purpose I/O or 5mA current source

Pull HIGH to force the DCDC1 converter to PWM mode.

Connect to AGND and PGND

4

11

29

–

PowerPad

Connect to GND

PARAMETER MEASUREMENT INFORMATION

Setup

The graphs have been generated on the TPS65720YFF EVM with the inductors as mentioned in the

graphs. See the TPS65720 EVM users guide (SLVU324) for details on the layout.

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

TPS65720: Efficiency DCDC1 vs Load current / PWM mode

200mA; L= Murata LQM21P 3.3 μH

Vo = 2.05V; Vi = 3.0V, 3.6V, 4.2V, 5.0V

Vo = 3.3V; Vi = 3.0V, 3.6V, 4.2V, 5.0V

Vo = 1.8V; Vi = 3.0V, 3.6V, 4.2V, 5.0V

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

TPS65720: Efficiency DCDC1 vs Load current / PFM mode

200mA; L= Murata LQM21P 3.3 μH

TPS65720: Efficiency DCDC1 vs Load current / PWM mode

200mA; L= FDK MIPSA2520 2.2 μH

TPS65720: Efficiency DCDC1 vs Load current / PFM mode

200mA; L= FDK MIPSA2520 2.2 μH

TPS65721: Efficiency DCDC1 vs Load current / PWM mode; L=

FDK MIPSA2520 2.2 μH

TPS65721: Efficiency DCDC1 vs Load current / PFM mode

500mA; L= FDK MIPSA2520 2.2 μH

TPS65721: Efficiency DCDC1 vs Load current / PWM mode; L=

FDK MIPSA2520 2.2 μH

TPS65721: Efficiency DCDC1 vs Load current / PFM mode

500mA; L= FDK MIPSA2520 2.2 μH

Load transient response DCDC1;

Scope plot

L= FDK MIPSA2520 2.2 μH, PFM mode

Io = 20mA to 180mA; Vo = 2.05V; Vi =

3.6V

Load transient response DCDC1;

L =FDK MIPSA2520 2.2 μH, PWM mode

Scope plot

Io = 50 μA to 60mA; Vo = 2.05V; Vi =

3.6V

Figure 10

Figure 11

Load transient response DCDC1;

Scope plot

L= FDK MIPSA2520 2.2 μH, PWM mode

Io = 40mA to 360mA; Vo = 3.3V; Vi =

3.6V

Line transient response DCDC1;

L= FDK MIPSA2520 2.2 μH, PWM mode

Scope plot; Vo = 2.05V

Vi = 3.6V to 5V to 3.6V; Io = 60mA

Figure 12

Figure 13

Output voltage ripple in PFM mode; DCDC1

Scope plot: Vi = 3.6V

Vo = 2.05V;

Io = 50μA (PFM); Io = 60mA (PWM)

12

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TYPICAL CHARACTERISTICS (continued)

FIGURE

Output voltage ripple in PWM mode; DCDC1

Scope plot: Vi = 3.6V

Vo = 2.05V;

Figure 14

Io = 60mA (PWM)

Startup DCDC1 and LDO1

Scope plot using TPS65720 (battery

powered) for

Figure 15

/PB_IN; Vo_DCDC1; Vo_LDO1

Load transient response LDO1

Line transient response LDO1

Kset vs Riset

Scope plot; V = 1.85V; Vi = 2.05V

I = 50 μA to 60mA to 50 μA

Figure 16

Figure 17

Scope plot; Vo = 1.85V; Vi = 5V to 3.6V

to 5V

Figure 18–Figure 21

Figure 22

Efficiency vs Lout for DCDC1=2.05V, LDO1=1.85V,

VinLDO=VDCDC1

TPS65720 Efficiency of DCDC1

vs

Load Current; PWM Mode; inductor: LQM21P 3.3uH

Load Current; PFM Mode; inductor: LQM21P 3.3uH

100

V

= 2.05 V

V

= 2.05 V

V = 2.5 V

O

I

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

V = 2.5 V

V = 3 V

I

V = 3 V

I

V = 3.6 V

I

V = 3.6 V

I

V = 4.2 V

I

V = 4.2 V

I

V = 5 V

I

V = 5 V

I

10

0

10

0

0.01

0.1

1

0.01

0.1

1

0.00001

0.0001

0.001

0.00001

0.0001

0.001

I

- Output Current - A

I - Output Current - A

O

Figure 1.

Figure 2.

TPS65720 Efficiency of DCDC1

vs

TPS65720 Efficiency of DCDC1

vs

Load Current; PWM Mode; inductor: MIPSA2520 2.2uH

Load Current; PFM Mode; inductor: MIPSA2520 2.2uH

100

V

= 2.05 V

V

= 2.05 V

O

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

V = 2.5 V

I

V = 3 V

I

V = 3 V

I

V = 3.6 V

I

V = 3.6 V

I

V = 4.2 V

I

V = 4.5 V

I

V = 5 V

I

V = 5 V

I

10

0

10

0

0.01

- Output Current - A

0.1

1

0.01

0.1

1

0.00001

0.0001

0.001

0.00001

0.0001

0.001

I

- Output Current - A

O

Figure 3.

Figure 4.

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TPS65721 Efficiency of DCDC1

vs

Load Current; PWM Mode; inductor: MIPSA2520 2.2uH

Load Current; PFM Mode; inductor: MIPSA2520 2.2uH

100

V

= 3.3 V

V = 3.3 V

O

90

80

70

60

50

40

30

20

10

90

80

70

60

50

40

30

20

V = 3.4 V

I

V = 3.4 V

I

V = 3.6 V

I

V = 4.2 V

I

V = 3.6 V

I

V = 5 V

I

V = 4.2 V

I

V = 5 V

I

10

0

0.00001

0.01

- Output Current - A

0.1

1

0.01

I - Output Current - A

O

0.1

1

0.0001

0.001

0.00001

0.0001

0.001

I

O

Figure 5.

Figure 6.

TPS65721 Efficiency of DCDC1

vs

TPS65721 Efficiency of DCDC1

vs

Load Current; PWM Mode; inductor: MIPSA2520 2.2uH

Load Current; PFM mode; inductor: MIPSA2520 2.2uH

100

V

= 1.8 V

V

= 1.8 V

O

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

V = 2.5 V

I

V = 2.5 V

I

V = 3 V

I

V = 3 V

V = 3.6 V

I

V = 3.6 V

I

V = 4.2 V

I

V = 4.2 V

I

V = 5 V

I

V = 5 V

I

10

0

10

0

0.01

0.1

1

0.01

0.1

1

0.00001

0.0001

0.001

0.00001

0.0001

0.001

I

- Output Current - A

I

- Output Current - A

O

Figure 7.

Figure 8.

Load Transent Response PFM Mode

Load Transient Response PWM Mode

V = 3.6 V

I

V = 3.6 V

I

= 20 mA to 180 mA

O

I

= 50 mA to 60 mA

O

V

= 2.05 V

O

V

= 2.05 V

O

Time - 100 ms/div

Figure 9.

Figure 10.

14

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Load Transient Response PWM Mode

Line Transient Response PWM Mode

V = 3.6 V

I

= 60 mA

I

O

V = 3.6 V to 5 V to 3.6 V

I

= 40 mA to 360 mA

O

V

= 3.3 V

O

V

= 2.05 V

O

Time - 100 ms/div

Figure 11.

Figure 12.

Output Voltage Ripple on DCDC1

PFM Mode

Output Voltage Ripple on DCDC1

PWM Mode

VI = 3.6 V,

PWM

V = 3.6 V,

I

I = 60 mA

O

PFM

I = 50 mA

O

V

O

= 2.05 V

V

O

= 2.05 V

20 mV/div

Time - 2 ms/div

Time - 1 ms/div

Figure 13.

Figure 14.

Startup DCDC1 and LDO1

Load Transient Response LDO1

V

I

= V ,

ODCDC

V = 2.05 V

ILDO

I

= 200 mA

ODCDC

V

= 3.6 V

I

= 50 mA to 60 mA to 50 mA

Ibat

O

1 V/div

V

ODCDC

= 2.05 V

1 V/div

V

= 1.85 V

O

V

= 1.85 V

OLDO

1 V/div

Time - 200 ms/div

Time - 40 ms/div

Figure 15.

Figure 16.

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Kset

vs

Line Transient Response LDO1

Riset

150

145

I

= 60 mA

O

T

= 25°C

A

V = 5 V to 3.6 V to 5 V

I

140

135

130

125

120

T

= -40°C

A

T

= 85°C

A

V

= 1.85 V

O

115

110

Time - 100 ms/div

0

4000

8000

12000

- W

16000

20000

24000

R

ISET

Figure 17.

Figure 18. ICH_SCL[1,0]=00

Kset

vs

Kset

vs

Riset

260

255

250

245

395

390

385

380

375

370

365

360

355

T

= 25°C

A

T

= -40°C

A

T

= 25°C

A

T

= -40°C

A

T

= 85°C

A

T

= 85°C

A

240

235

230

350

345

0

4000

8000

12000

- W

16000

20000

24000

0

4000

8000

12000

- W

16000

20000

24000

R

ISET

Figure 19. ICH_SCL[1,0]=01

Figure 20. ICH_SCL[1,0]=10

16

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Kset

vs

Efficiency vs output current

for the complete system;

Riset

LDO1 powered by DCDC1 with VDCDC1=2.05V; VLDO1= 1.85V

505

500

495

490

485

480

475

470

465

100

V = 2.5 V

I

90

80

70

60

50

40

30

20

V = 3 V

I

T

= -40°C

V = 3.6 V

A

I

V = 4.2 V

I

T

= 25°C

A

T

= 85°C

V = 5 V

I

A

10

0

460

0

0.01

- Output Current - A

0.1

1

4000

8000

12000

- W

16000

20000

24000

0.00001

0.0001

0.001

I

R

O

ISET

Figure 21. ICH_SCL[1,0]=11

Figure 22.

DETAILED DESCRIPTION

BATTERY CHARGER AND POWER PATH

The TPS65720 integrates a Li-Ion linear charger and system power path management targeted at space-limited

portable applications. The TPS65720 powers the system while simultaneously and independently charging the

battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge

termination and enables the system to run with a defective or absent battery pack. It also allows instant system

turn-on even with a totally discharged battery. The input power source for charging the battery and running the

system can be an AC adapter or an USB port. The power-path management feature automatically reduces the

charging current if the system load increases. The power-path architecture also permits the battery to

supplement the system current requirements when the adapter cannot deliver the peak system currents.

POWER DOWN

The charger remains in power-down mode when the input voltage at the AC pin is below the under-voltage

lockout threshold (UVLO). During the power-down mode, the host commands through the I²C interface are

ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that connects BAT to SYS is ON.

(If <SYSOFF>=1, Q2 is off). During power-down mode, the VOUT(SC2) circuitry is active and monitors for

overload conditions on SYS.

SLEEP MODE

The charger enters sleep mode when V_ACis greater than UVLO, but below V_BAT+ V_IN(DT). In sleep mode, the

host commands are ignored. The Q1 FET connected between AC and SYS pins is off. The Q2 FET that

connects BAT to SYS is ON. (If <SYSOFF>=1, Q2 is off). During sleep mode, the V_OUT(SC2)circuitry is active and

monitors for overload conditions on SYS.

STANDBY MODE

When V_ACis greater than UVLO and VIN is greater than V_BAT+ V_IN(DT), the device is in standby mode.

<CH_PGOOD> =1 to indicate the valid power status and the host commands are read. The device enters

standby mode whenever <AC input current1, AC input current0> = (0,0) or if an input overvoltage condition

occurs. In standby mode, Q1 is OFF and Q2 is ON. (If <SYSOFF>=1, Q2 is off). During standby mode, the

V_OUT(SC2)circuitry is active and monitors for overload conditions on SYS.

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POWER-ON RESET MODE

The charger enters power-on reset mode when the input voltage at AC is within the valid range: VAC > UVLO

and VAC > VBAT + VIN(DT) and VAC < VOVP, and the Bits <AC input current1, AC input current0> indicate that

the USB suspend mode is not enabled [<AC input current1, AC input current0>≠ (0,0)]. During power-on reset

mode, all internal timers and other circuit blocks are activated. The device checks for short-circuits at the ISET

pin. If no short conditions exists, the device switches on the input FET Q1 with a 100-mA current limit to check

for a short circuit at SYS. If VOUT rises above VSC, the FET Q1 switches to the current-limit threshold set by

<AC input current1, AC input current0>, and the device enters into the Idle mode.

IDLE MODE

In the Idle mode, the system is powered by the input source (Q1 is on), and the device continuously monitors the

status of the host commands. It also continuously monitors the input voltage conditions. Q2 is turned on

whenever the input source cannot deliver the required load current (supplement mode). The device also enters

Idle mode whenever <CH_EN> =0 while the input voltage is in the valid range of operation.

POWER-PATH MANAGEMENT

The current at the input pin AC of the power path manager is shared between charging the battery and powering

the system load on the SYS pin. Priority is given to the system load. The input current is monitored continuously.

If the sum of the charging and system load currents exceeds the preset maximum input current (programmed

internally by I2C), the charging current is reduced automatically. The default value for the current limit is 500mA

for the AC pin.

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250mV

V _BAT

<VOUT_0>

<VOUT_1>

V _O(SC1

OUT-SC1

OUT-SC2

t_DGL(SC2)

)

Q1

AC

SYS

EN2

< I_PR_CH0>

< I_PR_CH1>

Short Detect

ISET

V _IPRECHG

V _ICHG

< I_CH_SCL0 >

V _IN

-LOW

USB 100

USB 500

T _J

< I_CH_SCL1>

T _J(REG)

V _REF

-

USB- susp

Short Detect

<TH_LOOP>

ILIM

<V_ DPM> V _DPPM

V_SYS

V _O(REG)

Q2

<CH_VLT0>

V _BAT(REG

<CH_VLT1>

<IN_CUR_LIM>

<USB_SUSP>

)

V _OUT

40mV

I_BIAS

I_BAT(SC

-

Supplement

ITERM

)

V _LOWV

V _REF

-

ITERM

T3L: ITERM

BAT

V _BAT(SC)

V _RCH

<I_TERM0>

<I_TERM1>

~3V

ITERM

floating

-

I_BAT

(DET)

V _AC

<TS_ON>

<TS_HOT>

<TS_COLD>

<E_I_TS>

I_NTC

BAT -SC

V _BAT+ V

AC -DT

t_DGL(NO

-

V _HOT

TS

IN

)

t_DGL(T

S

)

t_DGL(PGOOD

Charge Control

V _UVLO

V _OVP

V _COL

)

D

t_BLK(OVP

)

V _DIS(TS)

<USB_SUSP>

<CH_EN>

<TERM_DIS>

T3L : TD

T3L: /CE

Halt

<DYN_TMR>

<CH_DONE >

timers

Reset

timers

T3L: /GHG

V _IPRECHG

V _ICHG

Dynamical

ly

T3L: /PGOOD

Controlled

Oscillator

V _ISET

Fast - Charge

Timer

fault

Pre -Charge

Timer

<SFTY_TMR_0>

<SFTY_TMR1>

<PR_ CH_TMR>

<TMR_F>

~100mV

Timers

disabled

Figure 23. Charger Block Diagram

BATTERY CHARGING

When <CH_EN>=1, battery charging begins. First, the device checks for a short circuit on the BAT pin by

sourcing I_BAT(SC)to the battery and monitoring the voltage. When the BAT voltage exceeds V_BAT(SC), the battery

charging continues. The battery is charged in three phases: conditioning precharge, constant-current fast charge

(current regulation) and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control

loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is

exceeded.

Figure 24 shows what happens in each of the three phases:

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CC FAST CHARGE

CV TAPER

PRECHARGE

DONE

V

BAT(REG)

I

O(CHG)

Battery Current

Battery

Voltage

V

LOWV

TERM CURRENT = 1

I

(PRECHG)

I

(TERM)

Figure 24. Battery Charge

In the precharge phase, the battery is charged with the precharge current (IPRECHG). Once the battery voltage

crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage

reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off

as the battery approaches full charge. When the battery current reaches ITERM, the CHG pin indicates charging

done by going high impedance. Note that termination detection is disabled whenever the charge rate is reduced

from the set point because of the actions of the thermal loop, the DPM loop, or the VIN(LOW) loop. The value of

the fast-charge current is set by the resistor connected from the ISET pin to GND, and is given by the equation:

ICHG = KISET/RISET

The charge current limit is adjustable up to 300mA. The valid resistor range is 1500Ω to 11.25kΩ. Note that if

ICHG is programmed as greater than the input current limit, the battery does not charge at the rate of ICHG, but

at the slower rate of IACmax (minus the load current on the OUT pin, if any). In this case, the charger timers are

proportionately slowed down.

I-PRECHARGE

The value for the pre-charge current is defined with Bits <I_PRE1, I_PRE0> based on the charge current defined

with pin ISET and Bits <CH_SCL1, ICH_SCL0> in register CHCONFIG1. Pre-charge current is scaled to lower

currents in DPPM mode or when the charger is in thermal regulation.

ITERM

The value for the termination current threshold can be set in register CHGCONFIG1 using Bits <I_TERM1,

I_TERM0> based on the charge current defined with pin ISET and Bits <CH_SCL1, ICH_SCL0>. Termination

current is not scaled in DPPM mode or when the charger is in thermal regulation.

BATTERY DETECTION AND RECHARGE

The charger automatically detects if a battery is connected or removed. Once a charge cycle is complete, the

battery voltage is monitored. When the battery voltage falls below VRCH, the device determines if the battery has

been removed. A current, IBAT(DET), is pulled from the battery for a duration tDET. If the voltage on the BAT pin

remains above V_LOWV, it indicates that the battery is still connected, but has discharged. If <CH_EN>=1, the

charger is turned on again to top off the battery. During this recharge cycle, the CHG output remains

high-impedance. Recharge cycles are not indicated by the <CH_ACTIVE> Bit.

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If the BAT voltage falls below VLOWV during the battery detection test, it indicates that the battery has been

removed. The device then checks for battery insertion. The FET Q2 is turned on and sources I_PRECHGout of BAT

for the duration of t_DET. If the battery voltage does not rise above V_RCH, it indicates that a battery has been

inserted, and a new charge cycle begins. If the voltage rises above V_RCH, it is possible that a fully charged

battery has been inserted. To check for this, I_BAT(DET)is pulled from the battery for t_DET. If the voltage falls below

V_LOWV, a battery is not present. The device continuously checks for the presence of a battery.

CHARGE TERMINATION ON/OFF

Charge termination can be disabled by setting the Bit <TERM_EN>=0. When termination is disabled, the device

goes through the pre-charge, fast-charge, and CV phases, then remains in the CV phase. During the CV phase,

the charger behaves like an LDO with an output voltage equal to V_BAT(REG)and is able to source currents up to

I_CHGor I_INmax, whichever is less. Battery detection is not performed. The Bit <CH_ACTIVE>=0 once the current

falls below ITERM and does not go t o1 until the input power is toggled. When termination is disabled, the

pre-charge and fast-charge safety timers are also disabled. Battery pack temperature sensing (TS pin

functionality) is also disabled if Bit <TERM_EN>=0 and the TS pin is unconnected.

TIMERS

The charger in TPS65720 has internal safety timers for the pre-charge and fast-charge phases to prevent

potential damage to either the battery or the system. The default values for the timers can be changed in register

CHGCONFIG2.

The pre-charge timer and fast charge timer will run with their nominal speed defined in register CHCONFIG2 if

ICH_SCL[1,0]=01, which equals a charge current of 50% defined with the ISET resistor. If ICH_SCL[1,0] are set

to higher or lower fast- charge current, the fast charge timers and pre-charge timers are scaled automatically. For

instance, with ICH_SCL[1,0]=11, which equals 100% of fast charge current, the safety timers will time out in half

the time defined in register CHCONFIG2. Changing the pre-charge current with I_PRE[1,0] will not change the

pre-charge or fast-charge timers.

DYNAMIC TIMER FUNCTION

During the fast-charge phase, several events increase the timer durations.

1. The system load current activates the DPM loop which reduces the available charging current

2. The input current is reduced because the input voltage has fallen to V_IN(LOW)

3. The device has entered thermal regulation because the IC junction temperature has exceeded T_J(REG)

During each of these events, the internal timers are slowed down proportionately to the reduction in charging

current. For example, if the charging current is reduced by half, the fast-charge timer is twice as long as

programmed.

A modified charge cycle with the thermal loop active is shown in Figure 25

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PRECHARGE

THERMAL

REGULATION

CC FAST

CHARGE

CV TAPER

DONE

V

O(REG)

I

O(CHG)

Battery

Voltage

Battery

Current

V

(LOWV)

TERM CURRENT = 1

I

(PRECHG)

I

(TERM)

IC junction

T

temperature, Tj

J(REG)

Figure 25. Thermal Loop

TIMER FAULT

If the pre-charge timer expires before the battery voltage reaches V_LOWV, the charger indicates a fault condition.

Additionally, if the battery current does not fall to ITERM before the fast-charge timer expires, a fault is indicated

by setting Bit <TIMER_FAULT>=1.

THERMAL REGULATION AND THERMAL SHUTDOWN

The charger contains a thermal regulation loop that monitors the die temperature. If the temperature exceeds

T_J(REG), the device automatically reduces the charging current to prevent the die temperature from increasing

further. In some cases, the die temperature continues to rise despite the operation of the thermal loop,

particularly under high VAC and heavy system load conditions. Under these conditions, if the die temperature

increases to T_J(OFF), the input FET Q1 is turned OFF. FET Q2 is turned ON to ensure that the battery still powers

the load on SYS. Once the device die temperature cools by T_J(OFF-HYS), the input FET Q1 is turned on and the

device returns to thermal regulation. Continuous over-temperature conditions result in the pulsing of the Q1 FET.

Note that this feature monitors the die temperature of the charger. This is not synonymous with ambient

temperature. Self-heating exists due to the power dissipated in the IC because of the linear nature of the battery

charging algorithm and the LDO mode for SYS.

BATTERY PACK TEMPERATURE MONITORING

The TPS65720 features an external battery pack temperature monitoring input. The TS input connects to the

NTC resistor in the battery pack to monitor battery temperature and prevent dangerous over-temperature

conditions. During charging, I_NTCis sourced to TS and the voltage at TS is continuously monitored. If, at any

time, the voltage at TS is outside of the operating range (V_COLDto V_HOT), charging is suspended. The timers

maintain their values but suspend counting. When the voltage measured at TS returns to within the operation

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window, charging is resumed and the timers continue counting. When charging is suspended due to a battery

pack temperature fault, the CH_ACTIVE Bit remains 1 and continues to indicate charging. Battery pack

temperature sensing is disabled when termination is disabled (<TERM_EN=0>) and the voltage at TS is greater

than V_DIS(TS). The battery pack temperature monitoring is disabled by connecting a 10-kΩ resistor from TS to

GND.

TPS65720 contains a feature to shift the termination temperature to higher levels by setting Bits <TMP_SHIFT1,

TMP_SHIFT0>.

DCDC1 CONVERTER

The TPS65720 step down converter operates with typically 2.25 MHz fixed frequency pulse width modulation

(PWM) at moderate to heavy load currents. At light load currents the converter can automatically enter Power

Save Mode and operates then in PFM mode.

During PWM operation the converter use a unique fast response voltage mode control scheme with input voltage

feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output

capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is

turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor

to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the

control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current

limit of the High Side MOSFET switch is exceeded. After a dead time preventing shoot through current, the Low

Side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the

inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET

rectifier.

The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on

the on the High Side MOSFET switch.

The DCDC1 converters output voltage is externally adjustable using a resistor divider at FB_DCDC1.

POWER SAVE MODE

The Power Save Mode is enabled automatically with <F_PWM>=0 which is the default setting. If the load current

decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the

converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current

to maintain high efficiency. The converter will position the output voltage typically +1% above the nominal output

voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition

from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch becomes zero,

which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored

with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal +1%,

the device starts a PFM current pulse. The High Side MOSFET switch will turn on, and the inductor current

ramps up. After the On-time expires, the switch is turned off and the Low Side MOSFET switch is turned on until

the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the

load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal or higher

than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 15μA

current consumption.

If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are

generated until the PFM comparator threshold is reached. The converter starts switching again once the output

voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage

ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify

the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage

ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value.

Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency

decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode

is entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be

disabled by setting <F_PWM>=1. The converter will then operate in fixed frequency PWM mode.

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Dynamic Voltage Positioning

This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is

active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides

more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.

Soft Start

The step-down converter in TPS65720 has an internal soft start circuit that controls the ramp up of the output

voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250μs. This limits the

inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high

impedance power source is used.

EN

95%

5%

V

OUT

t

RAMP

Start

Figure 26. Soft Start

100% Duty Cycle Low Dropout Operation

The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output

voltage. In order to maintain the output voltage, the High Side MOSFET switch is turned on 100% for one or

more cycles. With further decreasing VIN the High Side MOSFET switch is turned on completely. In this case the

converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications

to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input

voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:

V_INmin= V_Omax+ I_Omax× ®_DS(on)max+ R_L)

With:

I_Omax= maximum output current plus inductor ripple current

R_DS(on)max= maximum high side switch RDSon.

R_L= DC resistance of the inductor

V_Omax= nominal output voltage plus maximum output voltage tolerance

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Under-Voltage Lockout

The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from

excessive discharge of the battery and disables the converters and LDOs. The under-voltage lockout threshold is

typically 2.2V.

SHORT-CIRCUIT PROTECTION

All outputs are short circuit protected with a maximum output current as defined in the electrical specifications.

THERMAL SHUTDOWN

There are two thermal sensors in TPS6572x located at the main sources of power dissipation - the charger and

the LDO. The maximum temperature of the charger is regulated by reducing its charge current. If the

temperature increases further, the charger is disabled - see details in the charger description.

The second sensor is enabled as soon as the LDO is enabled. As soon as the junction temperature, T_J, exceeds

typically 150°C, the device goes into thermal shutdown. In this mode, the low side and high side MOSFETs are

turned-off. A thermal shutdown for the LDO will disable both, LDO and the DCDC converter simultaneously.

LDO1

The low dropout voltage regulator is designed to operate well with low value ceramic input and output capacitors.

It operates with input voltages down to 1.8V. The LDOs offer a maximum dropout voltage of 160mV at rated

output current. LDO1 supports a current limit feature. Its output voltage is adjustable using a resistor divider at

FB_LDO1 for TPS65721. The LDO1 voltage is fixed to 1.85V for TPS65720.

Default Voltage Setting for LDOs and DCDC1

In TPS65721, both DCDC1 and LDO1 are externally adjustable.

For TPS65720, the output voltage of the DCDC1 converter is externally adjustable and for LDO1 it is fixed to

1.85V per default. The I2C registers do allow changing the default voltage for LDO1 in a range of 0.8V to 3.3V.

For DCDC1, the register also allows setting any voltage in the range from 0.8V to 3.3V, however for the

adjustable version of DCDC1, the change in the I2C register has no effect on the output voltage. The registers

will be set to the default value when the voltage at SYS drops below the undervoltage lockout threshold or by a

reset event (RESET output is actively pulled low). See the register description for more details.

GPIOs, LED Drivers

TPS65720 contains 4 standard input/output pins (GPIOs) named GPIO0 to GPIO3. The output driver/input buffer

is available in register GPIO_SSC while register GPIODIR selects the data direction and additional features.

After RESET, GPIO0 and GPIO1 are pre-defined as general purpose inputs while GPIO2 and GPIO3 are

configured as LED driver outputs which are high impedance. The LED driver outputs are designed to be constant

current sinks to GND, sinking a constant current of 5mA when enabled. The GPIOs do not have internal pull-up

resistors. External pull-up resistors might be required if configured as inputs or outputs.

RESET output

Actively low, open drain reset output. Connect external pull-up resistor. The reset pin will go high impedance

100ms after the reset condition is left. For TPS65720, reset is generated, depending on the power-good signal of

LDO1, when the output voltage is below the threshold or LDO1 is disabled. For TPS65721, reset is generated

depending on the voltage at pin THRESHOLD.

THRESHOLD INPUT (TPS65721 only)

This is an input to the comparator driving the Reset output. If the voltage applied at THRESHOLD is below the

threshold, Reset is pulled actively LOW. If the voltage rises above the threshold + hysteresis, the Reset output is

released after a delay time of 100ms (typically).

ENABLE for DCDC1 and LDO1

The DCDC1 converter and LDO1 are enabled as soon as PB_IN is pulled LOW OR input voltage at pin AC is

detected (<CH_PGOOD>=1).

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There is a power-hold pin for DCDC1 (HOLD_DCDC1) and one for LDO1 (HOLD_LDO1). When HOLD_DCDC1

is pulled HIGH, DCDC1 is kept enabled after PB_IN was released HIGH. HOLD_LDO1 serves the same function

and keeps LDO1 enabled after PB_IN was released HIGH. After first power-up by pulling PB_IN = LOW or

applying voltage at AC, the HOLD pins HOLD_DCDC1 and HOLD_LDO1 can also be used as enable pins, such

that they turn on LDO1 or DCDC1, respectively when they are pulled HIGH. This function is available as long as

there is a voltage at the battery. After the battery was removed or was discharged, first power-on needs to be

done by pulling PB_IN=LOW.

Disabling the DCDC converter or LDO, forces the device into shutdown, with a shutdown quiescent current as

defined in the electrical characteristics. In this mode, the low and high side MOSFETs are turned-off and the

entire internal control circuitry is switched-off. For proper operation the PB_IN, HOLD_DCDC1, EN_DLO1 pins

must be terminated and must not be left floating.

PB_IN Input

Enables DCDC1 and LDO1 if pulled to GND. Disables DCDC1 and LDO1 if pulled high. There is no internal

pull-up resistor, so a resistor is needed externally to SYS. SYS is preferred over BAT because it is powered by

either AC or BAT (whichever is higher). If BAT is used, the device may not get a valid HIGH signal if the battery

is deeply discharged even when there is voltage at AC.

The input signal is debounced internally by 50ms. When PB_IN is pulled low, the DCDC1 converter and LDO1

will power-up simultaneously. When PB_IN is de-asserted, both converters are turned off. To leave the

converters on, the HOLD_DCDC1 and HOLD_LDO1 pin need to be asserted high. The HOLD register Bit

<CONTROL1:B5> will keep both, DCDC1 and LDO1 enabled if set to 1. For proper operation the PB_IN,

HOLD_DCDC1 and HOLD_LDO1 pins must be terminated and must not be left floating.

PB_IN

(internally after

debounce)

HOLD_DCDC1

set HIGH by I2C write to

register (optional)

HOLD_DCDC1 Bit

<DEFDCDC1:B7>

VDCDC1

HOLD_LDO1

set HIGH by I2C write to

register (optional)

HOLD_LDO1 Bit

<LDO_CTRL:B7>

VLDO1

Figure 27. PB_IN Timing

HOLD_DCDC1 Input

Actively high hold input for DCDC1. Logically ORÂ´d with the DCDC1 hold Bit <DEFDCDC1:B7>. If the input is

driven HIGH after PB_IN was pulled LOW, the DCDC1 converter stays on after PB_IN was released.

HOLD_LDO1 Input

Actively high hold input for LDO1. Logically ORÂ´d with the LDO1 hold Bit <LDO_CTRL:B7>. If the input is driven

HIGH after PB_IN was pulled LOW, LDO1 stays on after PB_IN was released.

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INT Output

Actively low, open drain interrupt output. Connect external pull-up resistor. Interrupts are flagged in the registers

IR0, IR1 and IR2 if the interrupt is not masked by registers IRMASK0, IRMASK1 and IRMASK2. Per default, all

interrupts are masked. Interrupts which are unmasked will set the Bit in either on the rising edge or on both

edges. Details can be found in the register description for IR0, IR1 and IR2. Any Bit in IR0, IR1 and IR2, set to

“1” will drive the reset pin INT actively LOW.

The reset pin will go high impedance after the Bit, generating the reset is read.

Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to

400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements and charger status to be monitored.

Register contents remain intact as long as VCC remains above the UVLO threshold. The TPS65720 has a 7bit

address: ‘100 1000’, other addresses are available upon contact with the factory. Attempting to read data from

register addresses not listed in this section will result in 00h being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start

condition and terminated with a stop condition. When addressed, the TPS65720 device generates an

acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra

clock pulse that is associated with the acknowledge bit. The TPS65720 device must pull down the DATA line

during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the

acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock

pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of

data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this

case, the slave TPS65720 device must leave the data line high to enable the master to generate the stop

condition.

For the QFN version, the voltage the pull-up resistors for the I2C interface at SCLK and SDAT are connected to,

should be monitored by the reset circuitry. This is done by connecting THRESHOLD with a voltage divider to the

voltage the SDAT and SCLK pins are pulled-up to. This is needed to ensure a falling supply voltage will cause a

reset to the I2C interface. Otherwise a START condition may be detected and the first access to the I2C interface

may return NO ACK (no acknowledge).

SDAT

SCLK

Data line

stable;

data valid

Change

of data

allowed

Figure 28. Bit Transfer on the Serial Interface

SDAT

SCLK

STOP condition

START condition

Figure 29. START and STOP Conditions

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SCLK

SDAT

...

A6

A5 A4

A0 R/W ACK

R7

R6

R5

R0 ACK

0

D7

D6 D5

D0 ACK

0

Start

Slave Address

Register Address

Data

Stop

NOTE: SLAVE =TPS65720

Figure 30. Serial I/f WRITE to TPS65720 Device

SCLK

...

..

...

..

...

..

SDAT

..

A6

A0 R/W ACK

R7

R0 ACK

0

A6

A0 R/W ACK D7

D0 ACK

0

1

0

Start

Slave

Drives

the Data

Stop

Register

Address

Master

Drives

ACK and Stop

Slave Address

Repeated

Start

NOTE: SLAVE =TPS65720

Figure 31. Serial I/f READ From TPS65720: Protocol A

SCLK

SDAT

...

..

...

..

...

..

ACK

0

ACK

0

ACK

A6

A0 R/W ACK

R7

R0

A6

A0 R/W

1

D7

D0

0

Start

Stop Start

Stop

Slave

Drives

the Data

Register

Address

Master

Drives

ACK and Stop

Slave Address

NOTE: SLAVE=TPS65720

Figure 32. Serial I/f READ From TPS65720: Protocol B

DATA

t

(BUF)

t

h(STA)

t

(LOW)

t

r

f

CLK

t

h(STA)

t

(HIGH)

t

su(STO)

su(STA)

t

h(DATA)

su(DATA)

STO

STA

STO

Figure 33. Serial I/f Timing Diagram

28

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MIN

MAX

UNIT

kHz

ns

f_MAX

Clock frequency

400

t_wH(HIGH)

t_wL(LOW)

t_R

Clock high time

600

Clock low time

1300

ns

DATA and CLK rise time

300

ns

t_F

DATA and CLK fall time

ns

t_h(STA)

t_h(DATA)

t_su(DATA)

t_su(STO)

t_(BUF)

Hold time (repeated) START condition (after this period the first clock pulse is generated)

600

0

ns

Setup time for repeated START condition

Data input hold time

ns

Data input setup time

100

600

1300

ns

STOP condition setup time

Bus free time

ns

All registers are set to their default value by one of the following events:

•

Voltage at the SYS pin is below the undervoltage lockout voltage (UVLO)

RESET is active; RESET output is pulled LOW and goes high with a 100ms delay

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CHGSTATUS Register Address: 01h (read only)

CHGSTATUS

B7

TS_HOT

x

B6

TS_COLD

x

B5

OVP

x

B4

0

B3

B2

B1

BO

0

Bit name and function

Default

CH_ACTIVE

x

CH_PGOOD

x

CH_THLOOP

x

Default value loaded by:

Read/write

R

Bit 7

Bit 6

Bit 5

Bit 3

Bit 2

Bit 1

TS_HOT:

0 = battery temperature is below high temperature threshold (45°C/50°C/55°C/60°C).

1 = battery temperature is above high temperature threshold (45°C/50°C/55°C/60°C).

TS_COLD:

0 = battery temperature is above low temperature threshold (0°C/5°C/10°C/15°C)

1 = battery temperature is below low temperature threshold (0°C/5°C/10°C/15°C)

OVP:

0 = Input overvoltage protection is not active (VAC<6.6V)

1 = Input overvoltage protection is active (VAC>6.6V)

CH_ACTIVE:

0 = charger is not active

1 = charger is charging the battery

CH_PGOOD:

0 = no input voltage at pin AC or voltage not inside the voltage range for changing

1 = power source is present and in the range valid for charging

CH_THLOOP:

0 = thermal loop not active

1 = thermal loop active

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CHGCONFIG0 Register Address: 02h (read/write)

CHGCONFIG0

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and function

VSYS1

VSYS0

AC input

current1

AC input

current0

TH_LOOP

DYN_TMR

TERM_EN

CH_EN

Default

For TPS65720

For TPS65721

0

1

0

1

0

1

Default value loaded by:

Read/write

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

Bit 7..6 VSYS1..VSYS0:

00 = the output voltage of the power path at pin SYS tracks the battery voltage;

VSYS=VBAT+200mV (Vbat>3.3V); VSYS=3.4V (VBAT</=3.3V); V_DPPM=1 is forced in this case

01 = the output voltage of the power path at pin SYS is regulated to 4.4V

10 = the output voltage of the power path at pin SYS is regulated to 5.0V

11 = the output voltage of the power path at pin SYS is regulated to 5.5V

Bit 5..4 AC input current1.. AC input current0:

00 = 100mA, input voltage DPPM enabled

01 = 500mA, input voltage DPPM enabled

10 = 500mA, input voltage DPPM disabled

11 = USB suspend mode; standby

Bit 3

TH_LOOP:

0 = the thermal loop is disabled

1 = the thermal loop is enabled and the charge current is reduced if the temperature exceeds 125°C

Bit 2

DYN_TMR (dynamic timer function):

0 = safety timers run with their normal clock speed

1 = clock speed for the safety timers is reduced based on the actual charge current if DPPM or

thermal loop is active

Bit 1

Bit 0

TERM_EN (charge termination enable):

0 = charge termination will not occur and the charger will always be on

1 = charge termination enabled based on timers and termination current

CH_EN:

0 = the charger is disabled

1 = the charger is enabled

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CHGCONFIG1 Register Address: 03h (read/write)

CHGCONFIG1

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and function

I_PRE1

I_PRE0

ICH_SCL1

ICH_SCL0

I_TERM1

I_TERM0

Default

For TPS65720

For TPS65721

0

1

0

1

0

1

0

1

0

1

Default value loaded by:

Read/write

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

R

Bit 7..6 I_PRE1..I_PRE0 (Pre-charge current factor):

00 = 5% of value defined with ICH_SCL1, ICH_SCL0

01 = 10% of value defined with ICH_SCL1, ICH_SCL0

10 = 15% of value defined with ICH_SCL1, ICH_SCL0

11 = 20% of value defined with ICH_SCL1, ICH_SCL0

Bit 5..4 ICH_SCL1..ICH_SCL0 (charge current scaling factor):

00 = 25% of value defined with ISET resistor; safety timer will time out at 2x SFTY_TMR[0,1]

01 = 50% of value defined with ISET resistor; safety timer runs at its nominal time defined in

SFTY_TMR[0,1]

10 = 75% of value defined with ISET resistor; safety timer will time out at 0.66x SFTY_TMR[0,1]

11 = 100% of value defined with ISET resistor; safety timer will time out at 0.5x SFTY_TMR[0,1]

Bit 3..2 I_TERM1..I_TERM0 (termination current scaling factor):

00 = 5% of value defined with ICH_SCL1, ICH_SCL0

01 = 10% of value defined with ICH_SCL1, ICH_SCL0

10 = 15% of value defined with ICH_SCL1, ICH_SCL0

11 = 20% of value defined with ICH_SCL1, ICH_SCL0

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CHGCONFIG2 Register Address: 04h (read/write)

CHGCONFIG2

Bit name and function

Default

B7

SFTY_TMR1 0

0

B6

SFTY_TMR

1

B5

PRE_TMR

0

B4

B3

NTC

1

B2

V_DPPM

1

B1

VBAT_COMP_EN

0

BO

0

Default value loaded

by:

UVLO/R

Read/write

R/W

R

R/W

R

Bit 7..6 SFTY_TMR1..SFTY_TMR0 (charge safety timer value):

00 = 4h

01 = 5h

10 = 6h

11 = 8h

Bit 5

Bit 3

Bit 2

Bit 1

PRE_TMR (pre-charge timer value):

0 = 30min

1 = 60min

NTC (sensor resistance):

0 = 100k NTC (I=7.5uA)

1 = 10k NTC (I=75uA)

V_DPPM (dynamic power path threshold):

0 = VBAT+100mV

1 = 4.3V

VBAT_COMP_EN (battery voltage comparator enable):

0 = battery voltage comparator for Li-primary cells disabled; VBAT_COMP interrupt disabled

1 = battery voltage comparator for Li-primary cells enabled

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CHGCONFIG3 Register Address: 05h (read/write)

CHGCONFIG3

Bit name and function

Default

B7

CH_VLTG2

0

B6

CH_VLTG1

1

B5

CH_VLTG0

0

B4

TMP_SHIFT1

0

B3

TMP_SHIFT0

0

B2

VBAT1

0

B1

VBAT0

0

BO

VBAT_COMP

1

UVLO/R

R

Default value loaded by:

Read/write

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

Bit 7..5 CH_VLTG2..CH_VLTG0 (charge voltage selection):

000 = 4.15V

001 = 4.175V

010 = 4.20V

011 = 4.225V

100 = 4.25V

101 = 4.275V

110 = 4.30V

111 = 4.325V

Bit 4..3 TMP_SHIFT1..TMP_SHIFT0 (battery temperature shift):

00 = the temperature for TS_COLD and TS_HOT is at 0°C/45°C

01 = the temperature window is shifted by 5°C to TS_COLD/TS_HOT = 5°C/50°C

10 = the temperature window is shifted by 10°C to TS_COLD/TS_HOT = 10°C/55°C

11 = the temperature window is shifted by 15°C to TS_COLD/TS_HOT = 15°C/60°C

Bit 2..1 VBAT1..VBAT0 (battery voltage comparator threshold; for Li primary cells):

00 = 2.2V

01 = 2.3V

10 = 2.4V

11 = 2.5V

Bit 0

VBAT_COMP (battery voltage comparator output):

0 = voltage above the threshold

1 = voltage below the threshold or comparator disabled

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CHGSTATE Register Address: 06h (read only)

CHGSTATE

Bit name and function

Default

B7

B6

B5

B4

B3

CH_CC

X

B2

B1

BO

CH_SLEEP CH_RESET

CH_IDLE CH_PRECH

CH_LDO

CH_FAULT CH_SUSP

X

R

X

R

X

R

X

R

X

R

X

R

X

R

Read/write

R

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CH_SLEEP:

0 = charger is not in sleep state

1 = charger is in sleep state

CH_RESET:

0 = charger is not in reset state

1 = charger is in reset state

CH_IDLE:

0 = charger is not in idle state

1 = charger is in idle state

CH_PRECH:

0 = charger is not in pre-charge state

1 = charger is in pre-charge state

CH_CC:

0 = charger is not in constant current mode

1 = charger is in constant current mode

CH_LDO:

0 = charger is not in LDO mode

1 = charger is in LDO mode

CH_FAULT:

0 = charger is not in fault state

1 = charger is in fault state

CH_SUSP:

0 = charger is not in suspend state

1 = charger is in suspend state

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DEFDCDC1 Register Address: 07h (read/write)

DEFDCDC1

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and

function

HOLD_

DCDC1

DCDC_DISCH

DCDC1[5] DCDC1[4] DCDC1[3]

DCDC1[2]

DCDC1[1]

DCDC1[0]

Default

0

1

0

1

0

1

Default value loaded

by:

UVLO/R

Read/write

R/W

Bit 7

HOLD_DCDC1:

0 = DCDC1 is disabled when HOLD_DCDC1 pin is pulled LOW and PB_IN is released HIGH

1 = DCDC1 stays enabled when HOLD_DCDC1 pin is pulled LOW and PB_IN is released HIGH

Bit 6

DCDC_DISCH:

0 = DCDC1 output is not discharged when DCDC1 is disabled

1 = DCDC1 output is discharged when DCDC1 is disabled

Bit 5..0

Output voltage setting for DCDC1:

For reference only: A voltage change in the register will not have an effect on the output voltage for

TPS65720 and TPS65721 as the voltage is set by an external resistor divider. Contact TI in case a

fixed voltage version is needed.

A Voltage change during operation must not exceed 8% of the value set in the register for each I2C

write access as this may trigger the internal power good comparator and will trigger the Reset of

the device. This limitation is only for a voltage step to higher voltages. There is no limitation for

programming lower voltages by I2C.

OUTPUT VOLTAGE [V]

0.800

B5

0

B4

0

1

B3

0

1

0

1

B2

0

1

0

1

0

1

0

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

B0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.825

2

0.850

3

0.875

4

0.900

5

0.925

6

0.950

7

0.975

8

1.000

9

1.025

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

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OUTPUT VOLTAGE [V]

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.450

2.500

2.550

2.600

2.650

2.700

2.750

2.800

2.850

2.900

2.950

3.000

3.100

3.200

3.300

B5

0

1

B4

1

0

1

B3

1

0

1

0

1

B2

0

1

0

1

0

1

0

1

0

1

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

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LDO_CTRL Register Address: 08h (read/write)

LDO_CTRL

B7

B6

B5

LDO1[5]

1

B4

LDO1[4]

0

B3

LDO1[3]

0

B2

LDO1[2]

1

B1

LDO1[1]

0

BO

LDO1[0]

1

Bit name and function

Default

HOLD_LDO1 LDO1_DISCH

0

1

Default value loaded by:

Read/write

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

Bit 7

HOLD_LDO1:

0 = LDO1 is disabled when HOLD_LDO1 pin is pulled LOW and PB_IN is released HIGH

1 = LDO1 stays enabled when HOLD_LDO1 pin is pulled LOW and PB_IN is released HIGH

Bit 6

LDO1_DISCH:

0 = LDO1 output is not discharged when LDO1 is disabled

1 = LDO1 output is discharged when LDO1 is disabled

Bit 5..0

LDO1 output voltage setting according to the table listed for DCDC1:

The voltage setting is only valid for TPS65720. For TPS65721, the LDO1 voltage is set by an

external resistor divider. The voltage setting is according to the same table given for DEFDCDC1.

CONTROL0 Register Address: 09h (read/write)

CONTROL0

B7

F_PWM

0

B6

B5

B4

0

B3

0

B2

0

B1

0

BO

0

Bit name and function

Default

PGOODZ_DCDC1

PGOODDCDC1

PGOODZ_LDO1

PGOODLDO1

Default value loaded by:

Read/write

UVLO/R

R/W

R

Bit 7 F_PWM:

0 = DCDC converter is in PWM/PFM mode

1 = DCDC converter is in forced PWM mode

Bit 6 PGOODZ_DCDC1:

0 = indicates that the DCDC converters output voltage is within its nominal range

1 = range indicates that the DCDC converters output voltage is below the target regulation voltage or

disabled

Bit 5 PGOODZ_LDO1:

0 = indicates that the LDO1 output voltage is within its nominal range

1 = indicates that the LDO1 output voltage is below the target regulation voltage or disabled

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CONTROL1 Register Address: 0Ah (read/write)

CONTROL1

B7

0

B6

0

B5

HOLD

0

B4

B3

0

B2

1

B1

0

BO

RESET_DELAY

1

Bit name and function

Default

PB_STAT

Default value loaded by:

Read/write

UVLO/R

R

UVLO/R

R/W

UVLO/R

R/W

R

Bit 5

Bit 4

Bit 0

HOLD (ORed with PB_IN):

0 = DCDC1 and LDO1 switched off

1 = DCDC1 and LDO1 enabled

PB_STAT (push-button status, after debounce):

0 = push-button not pressed

1 = push-button pressed

RESET_DELAY:

0 = 11ms

1 = 90ms

GPIO_SSC Register Address: 0Bh (read/write)

GPIO_SSC

B7

0

B6

0

B5

0

B4

B3

B2

GPIO2

1

B1

GPIO1

1

BO

GPIO0

1

Bit name and function

Default

GPIO3

0

1

UVLO/R

R

Default value loaded by:

Read/write

UVLO/R

R

UVLO/R

R

UVLO/R

R/W

R

R/W

Bit 3

Bit 2

Bit 1

Bit 0

GPIO3:

0 = data in input buffer / actively pulled low when configured as an output or LED driver enabled

1 = data in input buffer / high impedance when configured as an output or LED driver

GPIO2:

0 = data in input buffer / actively pulled low when configured as an output or LED driver enabled

1 = data in input buffer / high impedance when configured as an output or LED driver

GPIO1:

0 = data in input buffer / actively pulled low when configured as an output

1 = data in input buffer / high impedance when configured as an output

GPIO0:

0 = data in input buffer / actively pulled low when configured as an output

1 = data in input buffer / high impedance when configured as an output

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GPIODIR Register Address: 0Ch (read/write)

GPIODIR

B7

GPIO3_LED

1

B6

GPIO2_LED

1

B5

1

B4

1

B3

GPIO3_DIR

0

B2

GPIO2_DIR

0

B1

GPIO1_DIR

1

BO

GPIO0_DIR

1

Bit name and function

Default

Default value loaded by:

Read/write

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

UVLO/R

R/W

R

Bit 7

Bit 6

Bit 3

Bit 2

Bit 1

Bit 0

GPIO3_LED:

0 = GPIO3 is configured as a standard GPIO

1 = GPIO3 is configured as 5mA LED driver

GPIO2_LED:

0 = GPIO2 is configured as a standard GPIO

1 = GPIO2 is configured as 5mA LED driver

GPIO3_DIR:

0 = GPIO3 is configured as an output / LED driver

1 = GPIO3 is configured as an input

GPIO2_DIR:

0 = GPIO2 is configured as an output / LED driver

1 = GPIO2 is configured as an input

GPIO1_DIR:

0 = GPIO1 is configured as an output

1 = GPIO1 is configured as an input

GPIO0_DIR:

0 = GPIO0 is configured as an output

1 = GPIO0 is configured as an input

IRMASK0 Register Address: 0Dh (read/write)

IRMASK0

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and

function

M_TS_HOT M_TS_COLD

M_OVP

M_TIMER_

FAULT

M_CH_

ACTIVE

M_CH_

PGOOD

M_VBAT_

COMP

M_THLOOP

Default

1

Default value

loaded by:

UVLO/R

Read/write

R/W

Bit 7..0

charger interrupt mask register:

0 = Interrupt not masked

1 = Interrupt masked (no interrupt based on the event)

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IRMASK1 Register Address: 0Eh (read/write)

IRMASK1

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and

function

M_CH_

SLEEP

M_CH_

RESET

M_CH_IDLE M_CH_PRECH M_CH_ CC M_CH_ LDO M_CH_ FAULT

M_CH_

SUSP

Default

1

Default value

loaded by:

UVLO/R

Read/write

R/W

Bit 7..0

charger state interrupt mask register:

0 = Interrupt not masked

1 = Interrupt masked (no interrupt based on the event)

IRMASK2 Register Address: 0Fh (read/write)

IRMASK2

B7

B6

B5

B4

B3

B2

B1

BO

Bit name

and function

M_GPIO3

M_GPIO2

M_GPIO1

M_GPIO0

M_PGOODZ_

DCDC1

M_PGOODZ_

LDO1

M_PB_ STAT

Default

1

Default

value

UVLO/R

loaded by:

Read/write

R/W

R

Bit 7..0

charger state interrupt mask register:

0 = Interrupt not masked

1 = Interrupt masked (no interrupt based on the event)

IR0 Register Address: 10h (read only)

IR0

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and

function

TS_HOT

TS_COLD

OVP

TIMER_FAULT

CH_ACTIVE

CH_PGOOD

VBAT_COMP

TH_LOOP

Default

0

Default value

loaded by:

UVLO/R

Set by:

Rising edge of

TS_HOT

Rising edge of

TS_COLD

Rising edge of

OVP

Rising edge of

Rising edge

Rising edge of

TH_LOOP

TIMER_FAULT and falling edge and falling edge VBAT_COMP*

of CH_ACTIVE of CH_PGOOD

Read/write

R

Bit 7..2

interrupt register:

0 = no interrupt

1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK0

The VBAT_COMP interrupt is automatically disabled when the battery voltage comparator is disabled by

clearing Bit 1 in register 04h (VBAT_COMP_EN)

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IR1 Register Address: 11h (read)

IR1

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and

function

CH_SLEEP

CH_RESET

CH_IDLE

CH_PRECH

CH_CC

CH_LDO

CH_FAULT

CH_SUSP

Default

0

Default value

loaded by:

UVLO/R

Set by:

Rising edge of

CH_SLEEP

Rising edge of

CH_RESET

Rising edge of

CH_IDLE

Rising edge of

CH_PRECH

Rising edge of

CH_CC

Rising edge of

CH_LDO

Rising edge of

VBAT_FAULT*

Rising edge of

TH_SUSP

Read/write

Bit 7..0

R

interrupt register:

0 = no interrupt

1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK1

IR2 Register Address: 12h (read)

IR2

B7

B6

B5

B4

B3

B2

B1

BO

Bit name and

function

GPIO3

GPIO2

GPIO1

GPIO0

PGOODZ_

DCDC1

PGOODZ_

LDO1

PB_STAT

Default

0

Default value

loaded by:

UVLO/R

Set by:

Rising and

falling edge of

GPIO3

Rising and

falling edge of falling edge of

Rising and

falling edge of

GPIO0

Rising edge of

PGOODZ_

DCDC1

Rising edge of

PGOODZ_

LDO1

Rising and

falling edge of

PB_ STAT

GPIO2

GPIO1

Read/write

R

Bit 7..4

GPIO interrupt register:

0 = GPIO status did not change

1 = GPIO status changed; cleared when read; interrupt not masked in register IRMASK2

Bit 3..2

Bit 1

power good interrupt register:

0 = no interrupt (power good)

1 = interrupt occurred (output voltage of DCDC converter or LDO too low); cleared when read

PB_STAT interrupt register:

0 = no interrupt

1 = interrupt occurred; cleared when read; interrupt not masked in register IRMASK2

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APPLICATION INFORMATION

OUTPUT VOLTAGE SETTING

DCDC1

The output voltage of the DCDC converter can be set with external resistor network on Pin FB_DCDC1. The

feedback voltage is 0.6V.

It is recommended to set the total resistance of R1 + R2 to less than 1MΩ. Route the FB_DCDC1 trace separate

from noise sources, such as the inductor trace (L1).

V_FB-DCDC1= 0.6V

R1 + R2

R2

æ

VOUT

ö

V_{O UT}= VFB_DCDC1 ´

R1 = R2 ´

- R2

ç

÷

VFB_DCDC1

è

ø

(1)

Typical resistor values:

OUTPUT VOLTAGE

R1

R2

NOMINAL VOLTAGE

3.32V

3.3V

3.0V

2.85V

2.5V

2.05V

2.0V

1.8V

1.6V

1.5V

1.2V

680k

510k

560k

510k

360k

470k

300k

200k

300k

330k

150k

130k

150k

160k

150k

200k

150k

120K

200k

330k

2.95V

2.84V

2.51V

2.04V

2.01V

1.80V

1.60V

1.50V

1.20V

A feed-forward capacitor in parallel to the resistor from Vout to FB_DCDC1 is required. It´s value should be

based on transient performance and will be in the range from 4.7pF to 22pF.

LDO1

For TPS65720, the output voltage of LDO1 is set by register LDO_CTRL with the I2C compatible interface. The

default output voltage is programmed to 1.85V. The programmable voltage range is 0.8V to 3.3V.

For the TPS65721, the output voltage for LDO1 is externally adjustable using a resistor divider at pin FB_LDO1.

The feedback voltage is 0.8V and the total resistance of the voltage divider should be kept in the 100kΩ to 1MΩ

range. A feed-forward capacitor in parallel to the resistor from Vout to FB_LDO1 is required. It´s value should be

based on transient performance and will be in the range from 4.7pF to 22pF.

The output voltage with an internal reference voltage V_FB-LDO1=0.8V is:

R3 + R4

R4

æ

VOUT

ö

VOUT = VFB_LDOx ´

R3 = R4 ´

- R4

ç

÷

VFB_LDO1

è

ø

(2)

Typical resistor values:

OUTPUT VOLTAGE

R3

R4

NOMINAL VOLTAGE

3.3V

1.85V

1.8V

470k

200k

300k

150k

240k

3.31V

1.86V

1.80V

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OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)

Inductor Selection

The converter operates typically with 3.3μH output inductor. Larger or smaller inductor values can be used to

optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for

its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency

of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.

Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is

recommended because during heavy load transient the inductor current will rise above the calculated value

Vout

1-

DI_L

Vin

DI_L= Vout ´

I_Lmax= I_{outm ax}+

L ´ ¦

2

(3)

With:

f = Switching Frequency (2.25MHz typical)

L = Inductor Value

ΔI_L= Peak to Peak inductor ripple current

I_Lmax= Maximum Inductor current

The highest inductor current will occur at maximum Vin.

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents

versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the

corresponding converter. It must be considered, that the core material from inductor to inductor differs and will

have an impact on the efficiency especially at high switching frequencies.

Refer to Table 1 and the typical applications for possible inductors.

Table 1. Tested Inductors

INDUCTOR TYPE

LQM21P

INDUCTOR VALUE

3.3uH

SUPPLIER

Murata

Comments

For TPS65720

BRC1608T2R2M

2.2uH

Taiyo Yuden

For TPS65720; Smallest solution size;

up to 150 mA of output current

VLS201610ET-2R2M

GLFR1608T2R2M-LR

2.2uH

TDK

For TPS65720, TPS65721

For TPS65720; Smallest solution size;

up to 150 mA of output current

MIPSA2520

2.2uH

FDK

For TPS65721; highest efficiency

Output Capacitor Selection

The advanced Fast Response voltage mode control scheme of the step-down converter allows the use of small

ceramic capacitors with a typical value of 10μF, without having large output voltage under and overshoots during

heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are

therefore recommended. For an inductor value of 3.3μH, an output capacitor with 4.7μF can be used. Refer to

recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application

requirements. Just for completeness the RMS ripple current is calculated as:

Vout

1-

1

Vin

I

= Vout ´

´

RMSCout

L ´ ¦

2 ´

3

(4)

At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is

the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and

discharging the output capacitor:

44

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Vout

Vin

1-

æ

ö

1

DVout = Vout ´

´

+ ESR

ç

÷

L ´ ¦

8 ´ Cout ´ ¦

è

ø

(5)

Where the highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents the converter operates in Power Save Mode and the output voltage ripple is dependent on

the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external

capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering and minimizing the interference with other circuits caused by high input

voltage spikes. The converters need a ceramic input capacitor of 4.7μF. The input capacitor can be increased

without any limit for better input voltage filtering.

Table 2. Tested Capacitors

TYPE

VALUE

4.7 μF

2.2 μF

4.7 μF

1 μF

VOLTAGE RATING

SIZE

0402

0603

SUPPLIER

Murata

MATERIAL

Ceramic X5R

GRM155R60G475ME47D

GRM155R60J225ME15D

GRM188R60J475K

GMK107BJ105K

4 V

6.3 V

35 V

Murata

Taiyo Yuden

CHARGER/POWER PATH

Charger Stability

In order to ensure stable operation of the charger including the power path, a list of components and their

recommended value is given below. Note that these values represent the capacitance or inductance value in the

application under the given operating conditions. For example, ceramic capacitors will typically show a drop in

capacitance when a dc voltage is applied. Due to this dc bias effect, the capacitance in the applications when

voltage is applied is much less than the nominal capacitor value. See the manufacturers data sheet on this.

At pin AC, a series inductance of may be used with a values as stated below.

Pins AC, SYS and BAT have been tested to be stable with the values given in the table:

PIN NAME

AC

Cmin (μF)

Cmax (μF)

Lmin (μH)

lmax (μH)

0.1

1

0

–

2

–

SYS

10

4.7

BAT

0.1

Setting the Charge Current

The charge current is set with an external resistor connected form ISET to GND.

The resulting charge current is:

KSET

ICHARGE =

RSET =

RSET

ISET

(6)

Additionally, the charge current can be scaled to 100%, 75%, 50% or 25% of the value set by Rset by software in

register CHCONFIG1 using Bits ICH_SCL[1,0]. Pre-charge current and termination current is scaled accordingly.

Dynamic Power Path Management (DPPM)

The charger/power path in TPS6572x contains two different features to ensure there is sufficient power at the

load and the input voltage supplying the charger/power path does not collapse.

First there is output voltage DPPM, which is a control loop to keep the voltage at the output of the power path

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above a certain limit. In TPS6572x, the voltage at the output of the power path (SYS) is regulated to what is

defined with VSYS[1,0] in register CHCONFIG0. When the current needed for the load and for charging the

battery exceeds the input current limit, the voltage at SYS will collapse. The DPPM loop will reduce the charge

current, such that the total current for the load and the charge current equals the input current limit. This is done

as soon as the voltage at SYS drops 100mV below the target voltage.

Second there is input voltage DPPM. For this, the input voltage to the charger/power path at pin AC is sensed to

avoid the voltage from a USB port or dedicated charger to drop below a certain limit. This control loop will reduce

the input current limit for pin AC as soon as the voltage at AC drops below 4.5V (typically). With Bits

ACinputcurrent[1,0] set to 00 or 01, input voltage DPPM is enabled, with ACinputcurrent=10, input voltage DPPM

is disabled.

Layout Considerations

As for all switching power supplies, the layout is an important step in the design. Proper function of the device

demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If

the layout is not carefully done, the regulators may show poor line and/or load regulation, and additional stability

issues as well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and

short traces for the main current paths. The input capacitors should be placed as close as possible to the IC pins

as well as the inductor and output capacitor.

For TPS65721, connect the PGND pin of the device to the PowerPAD™ land of the PCB and connect the analog

ground connection (GND) to the PGND at the PowerPAD™. Keep the common path to the GND pin, which

returns the small signal components, and the high current of the output capacitors as short as possible to avoid

ground noise. The FB line should be connected right to the output capacitor and routed away from noisy

components and traces (for example, the L1 line). See the EVM users guide for details about the layout.

46

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APPLICATION CIRCUITS

TPS65720

BAT

AC

1uF

10k

LiIon

TS

charger / power path

NTC

ISET

SYS

3k

for a charge

current of150mA

4.7uF / 6.3V

R5

2.2uH

VDCDC1=2.05

V

L1

R1

360k

FB_DCDC1

DCDC1

200mA

4.7uF

22pF

R2

150k

bluetooth chip

VINLDO1

2.2uF

VLDO1 = 1.85V

LDO1

200mA

VLDO1

Vin

4.7uF / 4V

2 x 100k

2 x 3.3k

RESET

INT

reset

generator /

startup logic

Reset

INT

SYS

HOLD_LDO1

R6

GPIO

PB_IN

HOLD_DCDC1

ON /

OFF

SCLK

SDAT

SCLK

SDAT

I2C interface

PGND

AGND

GPIO0

GPIO1

GPIO or

5mA current

sink

GPIO2

GPIO3

to SYS or VDCDC1

depending on LED

forward voltage

indication LEDs

Figure 34. Typical Bluetooth Application

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PACKAGE OPTION ADDENDUM

www.ti.com

13-Nov-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

DSBGA

QFN

Drawing

TPS65720YFFR

TPS65720YFFT

TPS65721RSNR

TPS65721RSNT

ACTIVE

YFF

25

32

3000

250

TBD

Call TI

YFF

RSN

3000

250

QFN

RSN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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Applications

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型号：	TPS65721RSNT
厂家：	TEXAS INSTRUMENTS
描述：	PMU for Bluetooth Headsets PMU蓝牙耳机蓝牙
文件：	总50页 (文件大小：1633K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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