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TPS65911

SWCS049S –JUNE 2010–REVISED AUGUST 2018

TPS65911 Integrated Power Management Unit Top Specification

1 Device Overview

1.1 Features

1

• Embedded Power Controller (EPC) With EEPROM

Programmability

• Nine Configurable GPIOs With Multiplexed Feature

Support:

• Two Efficient Step-Down DC-DC Converters for

Processor Cores (VDD1, VDD2)

• One Efficient Step-Down DC-DC Converter for I/O

Power (VIO)

• One Controller for External FETs (VDDCtrl)

• Dynamic Voltage Scaling (DVS) for Processor

Cores

– Four can be Used as Enable for External

Resources, Included in Power-Up Sequence

and Controlled by State Machine

– As GPI, GPIOs Support Logic-Level Detection

and can Generate Maskable Interrupt for

Wakeup

– Two of the GPIOs Have 10-mA Current Sink

Capability for Driving LEDs

– DC-DC Converters Switching Synchronization

Through an External 3-MHz Clock

• Eight LDO Voltage Regulators and One RTC LDO

(Supply for Internal RTC)

• One High-Speed I²C Interface for General-Purpose

Control Commands (CTL-I²C)

• Two Reset Inputs:

– Cold Reset (HDRST)

– Power Initialization Reset (PWRDN) for Thermal

Reset Input

• Two Independent Enable Signals for Controlling

Power Resources (EN1, EN2)

– Alternatively, the EN1 and EN2 Pins can be

Used as a High-Speed I²C Interface Dedicated

for Voltage Scaling for VDD1 and VDD2

• 32-kHz Clock and Reset (NRESPWRON) for

System and an Additional Output for Reset Signal

• Thermal Shutdown Protection and Hot-Die

Detection

• A Real-Time Clock (RTC) Resource With:

• Watchdog

• Two ON and OFF LED Pulse Generators and One

PWM Generator

– Oscillator for 32.768-kHz Crystal or 32-kHz

Built-in RC Oscillator

• Two Comparators for System Control, Connected

to VCCS Pin

– Date, Time, and Calendar

– Alarm Capability

• A JTAG and Boundary Scan (Not Accessible in

Functional Mode [Test Purpose])

1.2 Applications

Portable and Hand-Held Systems

1.3 Description

The TPS65911 device is an integrated power management IC (PMIC) available in a 98-pin 0.65-mm pitch

BGA package. The TPS65911 device is dedicated to applications powered by one Li-Ion or Li-Ion polymer

battery cell, 3-series Ni-MH cells, or a 5-V input, and applications that require multiple power rails. The

device provides three step-down converters, one controller for external FETs to support high current rail,

eight LDOs, and the device is designed to be a flexible PMIC for supporting different processors and

applications.

Two of the step-down converters provide power for dual processor cores and support dynamic voltage

scaling by a dedicated I²C interface for optimum power savings. The third converter provides power for the

I/Os and memory in the system.

The device includes eight general-purpose LDO regulators that provide a wide range of voltage and

current capabilities. Five of the LDO regulators support 1 to 3.3 V with a 100-mV step and three (LDO1,

LDO2, LDO4) support 1.0 to 3.3 V with a 50-mV step. All LDO regulators are fully controllable by the I²C

interface.

In addition to the power resources, the device contains an EPC to manage the power sequencing

requirements of systems and an RTC. Power sequencing is programmable by EEPROM.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65911

SWCS049S –JUNE 2010–REVISED AUGUST 2018

www.ti.com

Device Information⁽¹⁾

PACKAGE

PART NUMBER

BODY SIZE (NOM)

TPS65911⁽²⁾

BGA MicroStar Junior™ (98)

9.00 mm × 6.00 mm

(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.

(2) Refer to the corresponding user's guide for the complete EEPROM setting before ordering.

1.4 Functional Block Diagram

Figure 1-1 shows the top-level diagram of the device.

C_BB

VBACKUP

VCC7

1.5 A at 0.6 to 2.2 V⁽¹⁾

VDD1

VCC1

SW1

BACKUP

VRTC

Management

VRTC (LDO)

and POR

AGND

OSC32KIN

GND1

VFB1

Oscillator

32 kHz

OSC32KOUT

Real-Time Clock

(RTC)

0.6 V to 3.3 V

REFGND

CLK32KOUT

1.5 A at 0.6 to 1.5 V⁽¹⁾

VDD2

VDDIO

SDA_SDI

SCL_SCK

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

I²C

VCC2

SW2

Bus Control

GND2

0.6 V to 3.3 V

VFB2

VBST

C_boost

DRVH

SW

DRVL

I²C

EN1

EN2

VOUT

VFB

Controller

C1

INT1

V5IN

SLEEP

Power-Control

State Machine

R_trip

C_V5IN

TRIP

GNDC

PWRON

0.6 V to 1.4 V

VIO

BOOT1

PWRHOLD

PWRDN

VCCIO

HDRST

SWIO

NRESPWRON

NRESPWRON2

GNDIO

1.3 A at 1.5 V

1.2 A at 1.8 V

1.1 A at 2.5 and 3.3 V

VREF

TESTV

VFBIO

VDDIO

Analog

References

Connect to system

1.8V/3.3 V supply

Watchdog

REFGND

LDO1

320 mA

LDO1

VCC6

LDO2

1 to 3.3 V,

50-mV step

LDO3

200 mA

Test Interface

1 to 3.3 V,

100-mV step

LDO3

VCC5

LDO4

1 to 3.3 V,

50-mV step

LDO2

320 mA

1 to 3.3 V,

50-mV step

LDO4

1 to 3.3 V,

100-mV step

LDO7

300 mA

LDO7

VCC3

LDO8

50 mA

LDO5

300 mA

1 to 3.3 V,

100-mV step

LDO5

VCC4

VCCS

1 to 3.3 V,

100-mV step

LDO8

300 mA

COMP

1

1 to 3.3 V,

100-mV step

LDO6

COMP

2

LDO6

300 mA

(1) For details on supported levels, see the electrical characteristics for VDD1 SMPS and VDD2 SMPS, and the Power Sources table.

Figure 1-1. Top-Level Functional Block Diagram

2

Device Overview

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TPS65911

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

Table of Contents

1

Device Overview ......................................... 1

6

Detailed Description ................................... 45

6.1 Overview ............................................ 45

6.2 Functional Block Diagram........................... 46

6.3 Power Reference.................................... 47

6.4 Power Resources ................................... 47

6.5 Embedded Power Controller (EPC)................. 47

6.6 PWM and LED Generators ......................... 58

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram ............................ 2

Revision History ......................................... 3

Device Comparison Table.............................. 8

Pin Configuration and Functions..................... 9

4.1 Pin Attributes ........................................ 10

Specifications ........................................... 12

5.1 Absolute Maximum Ratings......................... 12

5.2 ESD Ratings ........................................ 12

5.3 Recommended Operating Conditions............... 13

5.4 Thermal Information................................. 13

2

3

4

6.7

Dynamic Voltage Frequency Scaling and Adaptive

Voltage Scaling Operation .......................... 58

6.8 32-kHz RTC Clock .................................. 58

6.9 Real Time Clock (RTC) ............................. 59

6.10 Backup Battery Management ....................... 62

6.11 Backup Registers ................................... 62

6.12 I²C Interface ......................................... 62

6.13 Thermal Monitoring and Shutdown ................. 64

6.14 Interrupts ............................................ 64

6.15 Register Maps....................................... 65

Applications, Implementation, and Layout ...... 120

7.1 Application Information ............................ 120

7.2 Typical Application ................................ 120

7.3 Power Supply Recommendations ................. 131

Device and Documentation Support.............. 132

8.1 Device Support..................................... 132

8.2 Documentation Support............................ 133

5

5.5

5.6

5.7

5.8

Electrical Characteristics: I/O Pullup and Pulldown. 14

Electrical Characteristics: Digital I/O Voltage ....... 14

Electrical Characteristics: Power Consumption..... 16

Electrical Characteristics: Power References and

Thresholds .......................................... 17

Electrical Characteristics: Thermal Monitoring and

Shutdown............................................ 18

7

8

5.9

5.10 Electrical Characteristics: 32-kHz RTC Clock....... 18

5.11 Electrical Characteristics: Backup Battery Charger. 19

5.12 Electrical Characteristics: VRTC LDO .............. 19

5.13 Electrical Characteristics: VIO SMPS............... 20

5.14 Electrical Characteristics: VDD1 SMPS............. 21

5.15 Electrical Characteristics: VDD2 SMPS............. 23

5.16 Electrical Characteristics: VDDCtrl SMPS .......... 25

5.17 Electrical Characteristics: LDO1 and LDO2......... 27

5.18 Electrical Characteristics: LDO3 and LDO4......... 29

5.19 Electrical Characteristics: LDO5 .................... 31

5.20 Electrical Characteristics: LDO6, LDO7, and LDO8 32

5.21 Timing and Switching Characteristics............... 35

8.3

Receiving Notification of Documentation Updates. 133

8.4 Community Resources............................. 133

8.5 Trademarks ........................................ 133

8.6 Electrostatic Discharge Caution ................... 133

8.7 Glossary............................................ 134

9

Mechanical, Packaging, and Orderable

Information............................................. 134

9.1 Package Description ............................... 134

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision R (May 2018) to Revision S

Page

•

Added TPS65911A to the device comparison table ............................................................................. 8

Changes from Revision Q (March 2016) to Revision R

Page

•

Changed Device Information table to a single row reflecting all orderable devices ......................................... 2

Changed the Functional Block Diagram ........................................................................................... 2

Deleted lead temperature from the Recommended Operating Conditions table ........................................... 13

Corrected VIO output voltage from 2.2 V to 2.5 V .............................................................................. 20

Changed the VDDCtrl slew rate from 100 mV/20µs to 5 mV/µs for clarity ................................................. 25

Added SEL options for V_OUT< 1 V ............................................................................................... 30

Added the Overview section ...................................................................................................... 45

Corrected VIO voltage from 2.2 V to 2.5 V ...................................................................................... 47

Corrected the SEL bits for 1 V selection for LDO1_REG and LDO2_REG ................................................. 87

Corrected the SEL bits for 0.8 V to 0.9 V options. Added the SEL bits for 0.95 V. ........................................ 90

Revision History

3

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TPS65911

SWCS049S –JUNE 2010–REVISED AUGUST 2018

www.ti.com

•

Added the Applications, Implementation, and Layout section .............................................................. 120

Added specific layout recommendations, and added layout diagrams which show the routing around the device .. 129

Changes from Revision P (August 2015) to Revision Q

Page

•

Added TPS659118 device .......................................................................................................... 1

Deleted TPS659116 device ......................................................................................................... 1

Deleted "Ordering" column from Device Comparison table ..................................................................... 8

Corrected wording in Thermal Metric column of Section 5.4 and added table note 1 ..................................... 13

Added disclaimer note to Applications, Implementation, and Layout section ............................................. 120

Changes from Revision O (March 2015) to Revision P

Page

•

Added TPS659114A2ZRCR device ................................................................................................ 1

Changes from Revision N (November 2014) to Revision O

Page

•

Corrected orderable part number for TPS65911062 in the Device Comparison Table ..................................... 8

Corrected column heading from "MAX" to "UNIT" ............................................................................. 35

Changes from Revision M (May 2014) to Revision N

Page

•

Added TPS6591133 device ........................................................................................................ 1

Changed data sheet to TI standard format. ....................................................................................... 1

4

Revision History

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

Detailed Revision History

Version

Literature Number

Date

Notes

(1)

*

SWCS049

SWCS049A

SWCS049B

SWCS049C

June 2010

See

.

(2)

(3)

(4)

A

B

C

February 2011

May 2011

(1) TPS65911 Data Manual, SWCS049 - Initial release.

(2) TPS65911 Data Manual, SWCS049A - Version A:

•

Update Figure 1-1: LDO1, LDO2, LDO3, LDO6, and LDO7.

Remove table, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS

Update Section 5.3: Adjust pin names and add exception.

Update Table 7-2: VDDCtrl SMPS, update FET part number.

Update: Section 5.6: Add updated BOOT1 characteristics.

Update: Section 5.17: Update LDO1 and LDO2 characteristics.

Update Section 5.19: Update LDO5.

Update Section 5.20: Update LDO6, LOD7, and LDO8.

Update Table 6-1: Update LDO1, LDO2, LDO3, LOD7, and LDO8

Update Table 6-2: Remove SEL [6:0] selection bits.

Update Section 6.5.3.6: Add more explanation and reorganize section.

Add explanation to: Section 6.5.3.6, Section 6.5.3.9, Section 6.5.3.10, and Section 6.5.3.11.

Update Section 6.12: Add Section 6.12.1.

Update Table 6-6, Register Rest values.

Update Register Table: Table 6-43, Table 6-44, Table 6-53, and Table 6-55.

Update : BGA Pin column.

Update Packaging Information.

(3) TPS65911 Data Manual, SWCS049B - Version B:

Update VCC6 in Section 5.1.

(4) TPS65911 Data Manual, SWCS049C - Version C:

Update , BGA Pins: NRESPWRON, VCC1, GND1, VCCIO, GNDIO, AGND, and AGND2.

•

Revision History

5

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

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Detailed Revision History (continued)

Version

Literature Number

Date

Notes

(5)

D

E

F

SWCS049D

SWCS049E

SWCS049F

July 2011

August 2011

See

.

(6)

See

(7)

See

(5) TPS65911 Data Manual, SWCS049D - Version D:

•

Update Section 5.1:

•

Add VBACKUP

Voltage range on balls HDRST - Replace "VRTCMAX + 0.32 by "7"

•

Update Section 5.3:

•

Add VCC4 and VBACKUP

Input voltage range on pins or balls - Remove VCC4

•

Update Section 5.5: Change "HDRST programmable.." to "HDREST, PWRDN programmable.."

Update Section 5.12: Specify Input voltage range of VCC7

Update Section 5.13: Add discharge resistance

Update Section 5.14:

•

Add DC output voltage maximum value

Add discharge resistance

Update VGAIN_SEL test conditions and typ value

•

Update Section 5.15:

•

Add DC output voltage maximum value

Add discharge resistance

Update VGAIN_SEL test conditions

•

Update Section 5.16: Add tablenote to Rated output current 6000 mA

Update Section 5.21.2:

•

Update introductory statement

Add note to Figure 5-1

Align Parameters in Table 5-3 with Figure 5-1

•

Update Section 5.21.3: Add note toFigure 5-2

Update Section 4: Add J3 to AGND in

Update Section 6:

•

Update Table 6-1: VDD1 and VDD2 voltages

Device POWER ON enable conditions: Add additional device power enable condition

Device SLEEP enable conditions: Replace "... keeping the SLEEP signal floating, or ..." with "... keeping the SLEEP signal in the

active polarity state, or..."

•

Device reset scenarios: Replace "VCC7 < VBNPR" with " VDD7 < VBNPR and BB < VBNPR"

Update introduction for Table 6-2

Update Table 6-2: Remove all values in EEPROM Boot column

Update Table 6-3:

•

Remove all values in EEPROM Boot column

Update INT_MSK_REG.VMBHI_MSK description

•

Update Package Thermal Characteristics: Pin count from 96 to 98

Update Section 6.15.1:

•

Update Table 6-37, Table 6-38, Table 6-40, and Table 6-41: SEL bit description

Update Table 6-67: Update VMBHI_IT_MSK bit description

Update Table 6-80: Update GPIO_SEL bit description - Replace LED1 out with PWM out

(6) TPS65911 Data Manual, SWCS049E - Version E: Update Packaging Information.

(7) TPS65911 Data Manual, SWCS049F - Version F:

•

Add Section 7.2.4.1.

Update Table 6-67: Update bit 1, VMBHI_IT_MSK description.

Update Section 6.5.1: Device reset scenarios: Replace "VDD7 < VBNPR" with " VCC7 < VBNPR"

Add Ordering Information.

6

Revision History

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

Detailed Revision History (continued)

Version

Literature Number

SWCS049G

SWCS049H

SWCS049I

Date

Notes

(8)

G

H

I

October 2011

May 2012

See

.

(9)

(10)

(11)

(12)

(13)

(14)

June 2012

J

SWCS049J

September 2012

December 2012

February 2014

May 2014

K

L

SWCS049K

SWCS049L

SWCS049M

M

(8) TPS65911 Data Manual, SWCS049G - Version G:

•

Update Section 5.17, Section 5.18, Section 5.19, Section 5.20:

•

Update turn-on time

Update DC line regulation

•

Update Section 5.13

Update rated output current I_OUTmax

Update Section 5.14 and Section 5.15

•

.

•

Update rated output current I_OUTmax

Update DC line regulation

Update DC load regulation

•

Update Section 5.6

Update Related Open-Drain I/Os: GPIO2, GPIO7

Update Section 5.16

•

Add Supply Current, Internal Reference Voltage, Output discharge, Output drivers, Boot strap switch, Duty and frequency control,

softstart, current sense protection, UVLO, and thermal shutdown.

Remove DC line regulation, DC load regulation, Transient load regulation, Overshoot/undershoot, Rated output I_OUTmax, and

Conversion efficiency.

•

Section 5.13 and Section 5.15 - Remove Iout = 1500 mA value

Table 6-1 - Update VIO, VDD1, VDD2, and VDDCtrl

Figure 1-1 - Update VIO, VDD1, and VDD2

(9) TPS65911 Data Manual, SWCS049H - Version H:

•

Update Section 5.13

•

Update Rated output current description- add ILMAX bit configuration

Update PMOS current limit (high-side) description

Update NMOS current limit (high-side) description

•

Update Figure 5-2 - CLK32KOUT out pin name (fixed typo)

Update Figure 6-1

Update Table 6-35, VIO_REG - Update ILMAX description

Update Table 6-36, VDD1_REG - Update ILMAX and and TSTEP field numbers and VGAIN_SEL description

Update Table 6-39, VDD2_REG - Update VGAIN_SEL description; align bit field numbering

Update Table 6-43, VDDCRTL_OP_REG - Update SEL description

Update Table 6-44, VDDCRTL_SR_REG - Update SEL description

Update Table 5-4 - t_dbPWRONF: PWRON falling-edge debouncing delay - Update unit of measure

Update Table 5-5 - Replace tACT2SLP by tACT2SLPCK32K

Update Figure 5-5 - Replace tdONVMBHI by tdONPWHOLD

Update Table 5-6 - Replace tdONVMBHI by tdONPWHOLD

Update Section 6.5.3.6 - Replace 100 µs by 100 ms

Update Table 6-56 - Add Bit 0,1, and 3 : TURN OFF RESET to the description

Update Table 6-57 - Add TSLOT_LENGTH: TURN OFF RESET to the description

Update Table 6-72 - Add footnote

(10) TPS65911 Data Manual, SWCS049I - Version I:

•

Update Section 5.1 - Add VDDIO

Update Section 5.3 - Add VDDIO

Update Section 5.5 - Remove PWRDN

Update - Remove PD from PWRDN

(11) TPS65911 Data Manual, SWCS049J - Version J:

•

Update Section 5.3: Fix typo on HDRST pin

Update Section 6.15.1: Update full reset:

•

Full reset: All digital logic of device is reset.

Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR

(12) TPS65911 Data Manual, SWCS049K - Version K

Update Table 6-3 - Changed VMBCH_REG to EEPROM

(13) TPS65911 Data Manual, SWCS049L - Version L

Update Device Comparison Table - Added TPS659116

(14) TPS65911 Data Manual, SWCS049M - Version M

Update Device Comparison Table - Added TPS65911062

•

Revision History

7

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

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3 Device Comparison Table

MEMORY SUPPORT

(DDR3 or DDR2)

DEVICE OPTION

PROCESSORS

DDR2

DDR3

NVIDIA T30

TPS659110⁽¹⁾

DM8168, DM8167, C6A8168, C6A8167, AM3894,

AM3892

TPS659112⁽¹⁾

TPS659113⁽¹⁾

TPS6591133⁽¹⁾

N/A

DM8148, DM8147, DM8146, C6A8148, C6A8147,

C6A8143, AM3874, AM3872, AM3871

DM8148, DM8147, DM8146, C6A8148, C6A8147,

C6A8143, AM3874, AM3872, AM3871

TPS659114⁽¹⁾

TPS659118⁽¹⁾

TPS65911A⁽¹⁾

DDR3

DDR3L

Freescale i.MX6

66AK2G02

66AK2G12

(1) Refer to the corresponding user's guide for the complete EEPROM setting before ordering.

8

Device Comparison Table

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

4 Pin Configuration and Functions

Figure 4-1 (top view) and Figure 4-2 (bottom view) show the 98-pin ZRC Plastic Ball-Grid Array (BGA).

Bottom view

Top view

VDD

IO

PWRD

N

VDD

IO

PWRHO

LD

PWRD

N

PWRHO

LD

AGND2

LDO1

VCC6

LDO2

VCC3

LDO7

INT1

N

LDO2

VCC6

LDO1

EN2

AGND2

VCC3

LDO7

N

M

L

SCL_S

CK

SDA_S

DI

M

SCL_S

CK

SDA_S

DI

AGND2

LDO6

LDO8

VCC4

EN1

EN2

LDO8

VCC4

LDO6

EN1

VCC

IO

VCC

IO

L

VCC

IO

VCC

IO

HDRST

GPIO7

GPIO2

GPIO0

GPIO8

GPIO2

INT1

GPIO7

GPIO0

GPIO8

HDRST

SWIO

AGND

VFB2

K

LDO5

VFB2

AGND

SWIO

LDO5

K

GND

IO

GND

IO

BOOT1

AGND

J

H

G

F

AGND

GND2

SW2

GND2

SW2

GND

IO

GND

IO

AGND

BOOT1

AGND

GND2

SW2

GND2

SW2

AGND

J

H

G

F

VFB

IO

NRESP

WRON

GPIO4

NRESP

WRON

VFB

IO

GPIO4

REFGN

D

AGND

VREF

GPIO5

GPIO1

AGND

GPIO6

VCC1

VCC2

REFGN

D

AGND

VCC2

GPIO6

VCC1

GPIO5

GPIO1

AGND

VREF

CLK32

KOUT

OSC32

KOUT

OSC32

KIN

AGND

EN

VCC1

SW1

SLEEP

VCC1

CLK32

KOUT

OSC32

KOUT

OSC32

KIN

SLEEP

VCC1

SW1

AGND

EN

PWRO

N

VCCS

VCC5

LDO3

E

PWRO

N

LDO3

VCCS

VCC5

E

D

VBACK

UP

GND1

SW1

VFB1

D

C

B

A

VBACK

UP

SW1

GND1

VFB1

NRESP

WRON2

LDO4

VFB

PGOOD

GND1

DGND

TRAN

NRESP

WRON2

GND1

DGND

GND1

DGND

PGOOD

VFB

LDO4

TESTV

GNDC

TRAN

VCC7

C

B

A

TESTV

GNDC

8

VCC7

DRVL

6

VRTC

V5IN

5

TRIP

DRVH

3

DGND

VBST

2

GPIO3

GNDC

7

VOUT

SW

4

TRIP

VRTC

GPIO3

GNDC

7

VOUT

SW

4

DGND

VBST

DRVH

V5IN

DRVL

1

SWCS049-002

1

2

3

5

6

8

SWCS049-003

Figure 4-1. 98-Pin ZRC BGA MicroStar™ Junior

(Top View)

Figure 4-2. 98-Pin ZRC BGA MicroStar™ Junior

(Bottom View)

Pin Configuration and Functions

9

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4.1 Pin Attributes

Pin Attributes

PULLUP

PULLDOWN

I/O

TYPE

SUPPLIES

DESCRIPTION

NAME

NO.

D6, E5, E6,

F5, G4, H5,

H6, J3, J4,

J6, K3

AGND

I/O

Power

AGND

Analog ground

No

AGND2

BOOT1

M8, N8

J5

I/O

I

Power

Digital

AGND

Analog ground

No

VRTC, DGND

Power-up sequence selection

PD disable in

ACTIVE or SLEEP

state

CLK32KOUT

F4

O

Digital

VDDIO, DGND

32-kHz clock output

DGND

DRVH

DRVL

EN

A1, B1, B2

I/O

O

I

Power

Analog

DGND

Digital ground

No

A3

A6

D5

VBST, GNDC

V5IN, GNDC

VCC7, GNDC

VDDCtrl, High-side FET driver output

VDDCtrl, FET driver output

Internal functional pin, leave floating

Enable for supplies or

EN1

EN2

M7

M6

I/O

Digital

VDDIO, DGND

External PU

voltage scaling dedicated I²C clock

Enable for supplies or

voltage scaling dedicated I²C data

GNDC

GNDIO

GND1

GND2

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

HDRST

INT1

A7, A8

J7, J8

C1, C2, D3

J1, J2

L5

I/O

Power

Digital

Power

GNDC

VDDCtrl, Controller ground

VIO DCDC Power ground

VDD1 DCDC Power ground

VDD2 DCDC Power ground

GPIO, push-pull or OD as output

GPIO or LED1 output

GPIO or DCDC clock synchronization

GPIO or LED2 output

GPIO

I/O

VCCIO, GNDIO

VCC1, GND1

VCC2, GND2

VCC7, DGND

VRTC, DGND

VDDIO, DGND

No

I/O

No

I/O

OD: External PU

OD: external PU

OD: External PU

PD

F6

I/O, OD

L2

I/O, OD

B7

I/O, OD

H7

I/O, OD

G6

I/O, OD

GPIO

G3

I/O; OD

GPIO

L4

I/O, OD

GPIO

K5

I/O, OD

GPIO

L6

I

Cold reset

L3

O

Interrupt flag

No

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

N6

VCC6, REFGND LDO Regulator output

VCC5, REFGND LDO Regulator output

VCC4, REFGND LDO Regulator output

VCC3, REFGND LDO Regulator output

No

N4

No

E7

PD 5 µA

C8

PD 5 µA

K1

PD 5 µA

M2

PD 5 µA

M3

PD 5 µA

M1

PD 5 µA

NRESPWRO

N

PD active during

device OFF state

H4

C7

O

Digital

VDDIO, DGND

Power off reset

PD active during

device OFF state.

External pullup in

ACTIVE state.

NRESPWRO

N2

O, OD

Digital

VRTC, DGND

Second NRESPWRON output

OSC32KIN

F8

F7

I

Analog

VRTC, REFGND 32-kHz crystal oscillator

No

OSC32KOUT

10

Pin Configuration and Functions

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Pin Attributes (continued)

PULLUP

PULLDOWN

I/O

TYPE

SUPPLIES

DESCRIPTION

NAME

NO.

VDDCtrl, internal signal, leave floating

(controller trimming only)

PGOOD

C4

O, OD

Analog

Digital

VCC7, GNDC

VRTC, DGND

Reset input (for example, thermal

reset)

PWRDN

N2

N1

I

Switch-on, switch off control signal or

GPI

Programmable PD

(default active)

PWRHOLD

Programmable PU

(default active)

PWRON

E4

G7

I

Digital

VCC7, DGND

REFGND

External switch-on control (ON button)

Reference ground

REFGND

I/O

Analog

No

I²C bidirectional clock signal or serial

peripheral interface clock input

(multiplexed)

SCL_SCK

M4

I/O

Digital

VDDIO, DGND

External PU

I²C bidirectional data signal or serial

peripheral interface data input

(multiplexed)

SDA_SDI

SLEEP

M5

F1

I/O

I

Digital

VDDIO, DGND

External PU

ACTIVE-SLEEP state transition control

signal

Programmable PD

(default active)

SW

A4

K7, K8

D1, D2, E2

H1, H2

B8

I

Analog

Power

Analog

VBST, GNDC

VCCIO, GNDIO

VCC1, GND1

VCC2, GND2

VCC7, AGND

VDDCtrl, Switch node

SWIO

SW1

SW2

TESTV

O

VIO DCDC switched output

VDD1 DCDC switched output

VDD2 DCDC switched output

Analog test output (DFT)

No

Internal functional pin, leave floating

(controller trimming only)

TRAN

C6

I

Analog

VCC7, GNDC

V5IN, GNDC

TRIP

B3

D7

I

Analog

Power

VDDCtrl, OCL detection threshold pin

VBACKUP

VBACKUP, AGND Backup battery input

No

VDDCtrl, supply for high-side FET

driver

VBST

A2

I

Analog

VBST, GNDC

VCCIO

VCCS

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

L7, L8

E8

I

Power

Analog

Power

VCCIO, GNDIO

VCC7, DGND

VCC1, GND1

VCC2, GND2

VCC3, AGND2

VCC4, AGND2

VCC5, AGND

VCC6, AGND2

VIO DCDC power Input

Input for two comparators

VDD1 DCDC power Input

VDD2 DCDC power Input

LDO6, LDO7, LDO8 power Input

LDO5 power Input

I/O

E1, F2, F3

G1, G2

N3

I

No

L1

D8

LDO3, LDO4 power Input

LDO1, LDO2 power Input

N5

VRTC power input and analog

references supply

VCC7

B6

I

Power

VCC7, REFGND

No

VDDIO

VFB

N7

C5

H8

D4

K2

B4

G8

B5

A5

I

Power

Analog

Power

VDDIO, DGND

VOUT, GNDC

VCC7, DGND

VOUT, GNDC

Digital Ios supply

VDDCtrl, slew rate control capacitance

VIO feedback voltage

VFBIO

VFB1

VFB2

VOUT

VREF

VRTC

V5IN

I

PD 5 µA

I

VDD1 feedback voltage

I

VDD2 DCDC feedback voltage

VDDCtrl, Feedback input

I

O

I

VCC7, REFGND Band-gap voltage

No

VCC7, REFGND LDO Regulator output

PD 5 µA

V5IN, GNDC

VDDCtrl, 5-V input

Pin Configuration and Functions

11

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5 Specifications

5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC7, VBACKUP,

V5IN, TRIP

–0.3

7

VCC6

VDDIO

VBST

SW

–0.3

–5

3.6

37

30

SW1, SW2, SWIO

–0.3

7

Voltage range on

pins

V

VFB1, VFB2, VFBIO

VOUT, VFB

3.6

7

OSC32KIN, OSC32KOUT, BOOT1

VRTCMAX + 0.3

SDA_SDI, SCL_SCK, EN2, EN1, SLEEP, INT1, CLK32KOUT,

NRESPWRON

–0.3

VDDIOMAX + 0.3

PWRON

–0.3

–5

7

PWRHOLD, GPIO0

GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8⁽²⁾

7

HDRST

7

Voltage range on

pins

NRESPWRON2⁽²⁾

PWRDN⁽³⁾

VCCS

7

V

7

Peak output current on all other pins than power resources

Functional junction temperature

5.0

150

mA

°C

–45

–65

Storage temperature, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) I/O supplied from VRTC, but can be driven from VCC7 or to VCC7 voltage level.

(3) Input supplied from VRTC, but can be driven from VCC7 voltage level.

5.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾

Charged device model (CDM), per JESD22-C101⁽²⁾

Electrostatic

discharge

V_ESD

V

(1) JEDEC document JEP155 statues that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP155 statues that 250-V HBM allows safe manufacturing with a standard ESD control process.

12

Specifications

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5.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

UNIT

VCC1, VCC2, VCCIO, VCC5, VCC7, VCCS, VCC4,

VBACKUP

2.7

3.8

5.5

VCC3

1.7

1.65

1.4

4.5

–0.1

–1

3.8

1.8/3.3

3.3

5.5

3.45

3.6

VDDIO

VCC6

V5IN

6.5

Input voltage range VBST

SW (<30% of repetitive period)

TRIP, VFB

3.45

28

V

–0.1

0

6.5

PWRON

3.8

VDDIO

VRTC

5.5

SDA_SDI, SCL_SCK, EN2, EN1, SLEEP, INT1,

CLK32KOUT

1.65

3.45

5.5

PWRHOLD, HDRST

GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6,

GPIO7, GPIO8, PWRDN

5.5

Input voltage range

Ambient temperature

V

VCCS

0

–40

5.5

85

27

°C

Junction temperature, T_J

125

(1) VCC7 should be connected to highest supply that is connected to device VCCx pin.

Exception: VCC4, VCC5, and V5IN inputs can be higher than VCC7. VCCS can be higher than VCC7 if VMBBUF_BYPASS = 0 (buffer

is enabled).

5.4 Thermal Information

TPS65911x

THERMAL METRIC^{(1) (2)}

ZRC (BGA)

UNIT

98 PINS

32

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

18

16

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

12

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [R_θJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.

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Specifications

13

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5.5 Electrical Characteristics: I/O Pullup and Pulldown

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SDA_SDI, SCL_SCK, SDASR_EN2,

SCLSR_EN1 external pullup resistor

Connected to VDDIO

1.2

kΩ

SDA_SDI, SCL_SCK, SDASR_EN2,

SCLSR_EN1 programmable pullup (DFT,

default inactive)

Grounded, VDDIO = 1.8 V

–45%

8

45%

kΩ

SLEEP, PWRHOLD, programmable

pulldown (default active)

At 1.8 V, VRTC = 1.8 V

2

4.5

10

µA

NRESPWRON, NRESPWRON2 pulldown

At 1.8 V, VCC7 = 5.5 V, OFF state

At 1.8 V, VRTC = 1.8 V, OFF state

32KCLKOUT pulldown (disabled in

ACTIVE-SLEEP state)

PWRON programmable pullup (default

active)

Grounded, VCC7 = 5.5 V

–40

–31

–15

µA

GPIO0-8 programmable pulldown (default

active except GPIO0)

At 1.8 V, VRTC = 1.8 V, OFF state

Connected to VDDIO

2

–20%

2

4.5

120

4.5

10

20%

10

µA

kΩ

µA

GPIO0-8 external pullup resistor

HDRST programmable pulldown (default

active)

At 1.8 V, VRTC = 1.8 V

(1) The internal pullups on the CTL-I²C and SR-I²C pins are used for test purposes or when the SR-I²C interface is not used. Discrete

pullups to the VIO supply must be mounted on the board in order to use the I²C interfaces. The internal I²C pullups must not be used for

functional applications.

5.6 Electrical Characteristics: Digital I/O Voltage

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

RELATED I/Os: PWRON

TEST CONDITIONS

MIN

0.7 × VBAT

1.3

TYP

MAX

UNIT

Low-level input voltage (V_IL)

High-level input voltage (V_IH

0.3 × VBAT

V

)

RELATED I/Os: PWRHOLD, GPIO0-8, PWRDN

Low-level input voltage (V_IL)

0.45

V

High-level input voltage (V_IH

)

VBAT

RELATED I/Os: BOOT1

Low level input – Impedance between

BOOT1 and GND

10

kΩ

High level input – Impedance between

BOOT1 and VRTC

HiZ level input – Impedance between

BOOT1 and GND

500

RELATED I/Os: SLEEP

0.35 ×

VDDIO

Low-level input voltage (V_IL)

V

0.65 ×

VDDIO

High-level input voltage (V_IH

RELATED I/Os: HDRST

Low-level input voltage (V_IL)

)

0.35 ×

VRTC

V

0.65 ×

VRTC

High-level input voltage (V_IH

)

RELATED I/Os: NRESPWRON, INT1, 32KCLKOUT

I_OL= 100 µA

I_OL= 2 mA

0.2

Low-level output voltage (V_OL

)

V

0.45

14

Specifications

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Electrical Characteristics: Digital I/O Voltage (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDIO –

0.2

I_OH= 100 µA

High-level output voltage (V_OH

)

V

VDDIO –

0.45

I_OH= 2 mA

RELATED I/Os: GPIO0 (PUSH-PULL MODE)

I_OL= 100 µA

I_OL= 2 mA

0.2

Low-level output voltage (V_OL

)

V

0.45

I_OH= 100 µA

VCC7 – 0.2

High-level output voltage (V_OH

)

VCC7 –

0.45

I_OH= 2 mA

RELATED OPEN-DRAIN I/Os: GPIO0, GPIO4, GPIO5, GPIO6, GPIO8, NRESPWRON2

I_OL= 100 µA

0.2

Low-level output voltage (V_OL

)

V

I_OL= 2 mA

RELATED OPEN-DRAIN I/Os: GPIO2, GPIO7

0.45

I_OL= 100 µA

I_OL= 1.9 mA

0.2

Low-level output voltage (V_OL

)

0.45

RELATED OPEN-DRAIN I/Os: GPIO1, GPIO3

I_OL= 100 µA

I_OL= 2 mA

0.2

0.4

Low-level output voltage (V_OL

)

I²C-SPECIFIC RELATED I/Os: SCL, SDA, EN1, EN2

0.3 ×

VDDIO

Low-level input voltage (V_IL)

–0.5

V

0.7 ×

VDDIO

High-level input voltage (V_IH

)

0.1 ×

VDDIO

Hysteresis

Low-level output voltage (V_OL) at 3 mA

(sink current), VDDIO = 1.8 V

0.2 ×

VDDIO

Low-level output voltage (V_OL) at 3 mA

(sink current), VDDIO = 3.3 V

0.4 ×

VDDIO

Specifications

15

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5.7 Electrical Characteristics: Power Consumption

Over operating free-air temperature range (unless otherwise noted)

All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage, COMP2 is off.

PARAMETER

TEST CONDITIONS

VBAT = 2.4 V, VBACKUP = 0 V,

MIN

TYP

MAX

UNIT

13

18

CK32K clock and RTC

digital running

(RTC_PWDN = 0)

Device BACKUP state

µA

VBAT = 0 V, VBACKUP = 3.2 V,

V5IN = 0 V

7

10

VBAT = 3.8 V

VBAT = 5 V

13

17

18

23

VBAT = 3.8 V, RTC digital running

(RTC_PWDN = 0)

CK32K clock running,

V5IN = 0

16

22

Device OFF state

µA

VBAT = 3.8 V, digital running

(RTC_PWDN = 0), backup battery

charger on, VBACKUP = 3.2 V

26

32

3 DCDCs on, 5 LDOs and VRTC on,

no load

292

279

VBAT = 3.8 V,

CK32K clock running:

3 DCDCs on, 3 LDOs and VRTC on,

no load

Device SLEEP state

µA

VBAT = 3.8 V, CK32K clock

and RTC digital running

(RTC_PWDN = 0)

3 DCDCs on, 5 LDOs and VRTC on,

no load

295

Additional current from V5IN = 5 V, if VDDCtrl is on, no load

320

1.2

500

3 DCDCs on, 5 LDOs and VRTC on,

no load

3 DCDCs on, 3 LDOs and VRTC on,

VBAT = 3.8 V, CK32K clock no load

1.05

running:

Device ACTIVE state

mA

3 DCDCs on PWM mode

(VDD1_PSKIP = VDD2_PSKIP =

VIO_PSKIP = 0),

5 LDOs and VRTC on, no load

23.6

0.32

Additional current from V5IN = 5 V, if VDDCtrl is on, no load

0.5

16

Specifications

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5.8 Electrical Characteristics: Power References and Thresholds

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output reference

voltage (VREF pin)

Device in active or low-

power mode

–1%

0.85

1%

V

VMBCH_SEL = 11000 to

11111

3.5

VMBCH_SEL = 10111

3.45

...

Main battery charged

threshold, VMBCH

(programmable)

Measured on VCCS pin

Triggering monitored

through NRESPRWON

VMBCH_SEL = 01110

...

–2%

3

2%

V

...

VMBCH_SEL = 00101

2.55

VMBCH_SEL = 00001 to

00100

2.5

VMBCH_SEL = 00000

Bypassed

Main battery charged

hysteresis threshold,

VMBDCH

VMBCH –

100 mV

Measured on VCCS pin

VMBDCH2_SEL = 11000 to

11111

3.5

VMBDCH2_SEL = 10111

3.45

...

Measured on VCC7 pin

(MTL)

Triggering monitored

through INT1

Main battery discharged

threshold, VMBDCH2

(programmable)

VMBDCH2_SEL = 01110

...

–2%

3

2%

...

VMBDCH2_SEL = 00101

2.55

VMBDCH2_SEL = 00001 to

00100

2.5

VMBDCH2_SEL = 00000

Bypassed

Main battery discharged

hysteresis threshold,

VMBCH2

VMBDCH2

– 100 mV

Measured on VCCS pin

V

Main battery low

threshold, VMBLO

measured on VCC7 pin (monitored on pin

NRESPWRON)

2.5

2.4

2.6

2.5

2.7

2.6

3

MB comparator

MTL

VBACKUP = 0 V, Measured on pin VCC7 (MB

comparator)

2.75

Main battery high

threshold, VMBHI

V

VBACKUP = 3.2 V, Measured on pin VCC7 (trigger

monitored though VCCS Idd, UPR comparator)

2.5

1.9

2.55

3

Main battery not present Measured on pin VCC7 (Triggering monitored on pin

threshold, VBNPR

2.1

8

2.2

VRTC)

Device in OFF state

Device in ACTIVE or SLEEP

state

15

Ground current (analog

references +

comparators + backup

battery switch)

V_CCx= VBAT = 3.8 V

except VCC6 = 3.6 V

COMP2 consumption when

enabled

µA

5

8

Buffer consumption if

COMP1 or COMP2 is active

and buffer enabled

Specifications

17

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5.9 Electrical Characteristics: Thermal Monitoring and Shutdown

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

Hot-die temperature rising threshold

Hot-die temperature hysteresis

TEST CONDITIONS

THERM_HDSEL[1:0] = 00

THERM_HDSEL[1:0] = 01

THERM_HDSEL[1:0] = 10

THERM_HDSEL[1:0] = 11

MIN

TYP

117

121

125

130

10

MAX

UNIT

°C

113

136

°C

µA

Thermal shutdown temperature rising

threshold

136

148

10

6

160

Thermal shutdown temperature hysteresis

Device in ACTIVE state, Temperature

= 27°C, VCC7 = 3.8 V

Ground current

5.10 Electrical Characteristics: 32-kHz RTC Clock

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

C_L= 35 pF

MIN

TYP

MAX

UNIT

CLK32KOUT rise and fall time

10

ns

BYPASS CLOCK (OSC32KIN: INPUT, OSC32KOUT FLOATING)

Input bypass clock frequency

Input bypass clock duty cycle

Input bypass clock rise and fall time

CLK32KOUT duty cycle

OSCKIN input

32

10

kHz

ns

OSCKIN input

40%

60%

20

10%–90%, OSC32KIN input

Logic output signal

32KCLKOUT output

Bypass mode

60%

1

Bypass clock setup time

Ground current

ms

µA

1.5

CRYSTAL OSCILLATOR (CONNECTED FROM OSC32KIN TO OSC32KOUT)

Crystal frequency

Crystal tolerance

At specified load capacitor value

At 27°C

32.768

0

kHz

–20

20

ppm

Oscillator contribution (not including

crystal variation)

Frequency temperature coefficient

–0.5

0.5

ppm/°C

Secondary temperature coefficient

Voltage coefficient

–0.04

–2

–0.035

–0.03

2

ppm/°C²

ppm/V

kΩ

Max crystal series resistor

Crystal load capacitor

At fundamental frequency

90

According to crystal data sheet

6

12

12.5

pF

Parallel mode including parasitic PCB

capacitor

Load crystal oscillator (C_OSCIN, C_OSCOUT

)

25

pF

Quality factor

8000

80000

2

Oscillator start-up time

Ground current

On power on

s

1.5

µA

RC OSCILLATOR (OSC32KIN: GROUNDED, OSC32KOUT FLOATING)

Output frequency

Output frequency accuracy

Cycle jitter (RMS)

Output duty cycle

Settling time

CK32KOUT output

At 25°C

32

kHz

–15%

40%

0%

15%

10%

60%

150

Oscillator contribution

50%

4

µs

Ground current

Active at fundamental frequency

µA

18

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

5.11 Electrical Characteristics: Backup Battery Charger

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Backup battery charging current

VBACKUP = 0 to 2.8 V, BBCHEN = 1

350

650

900

µA

VCC5 = 3.6 V, I_VBACKUP= –10 µA,

BBSEL = 10

–3%

3.15

3

3%

VCC5 = 3.6 V, I_VBACKUP= –10 µA,

BBSEL = 00

VCC5 = 3.6 V, I_VBACKUP= –10 µA,

BBSEL = 01

End-of-charge backup battery voltage

2.52

3%

V

VCC5 = 3.6 V, I_VBACKUP= –10 µA,

BBSEL = 11

VBAT – 0.3

V

VBAT

VCC5 = 3.0 V, I_VBACKUP= –10 µA,

BBSEL = 10

VBAT – 0.2

V

Ground current

On mode

10

µA

5.12 Electrical Characteristics: VRTC LDO

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

On mode

2.5

1.9

5.5

3

Input voltage on VCC7 (V_IN

)

V

Backup mode

On mode, 3.0 V < V_IN< 5.5 V

Backup mode, 2.3 V ≤ V_IN≤ 2.6 V

On mode

1.78

1.72

20

1.83

1.78

1.88

1.84

DC output voltage (V_OUT

)

V

Rated output current (I_OUTmax

DC load regulation

)

mA

mV

Backup mode

0.1

On mode, I_OUT= I_OUTmaxto 0

Backup mode, I_OUT= I_OUTmaxto 0

100

On mode, V_IN= 3.0 V to V_INmaxat I_OUT

I_OUTmax

=

2.5

DC line regulation

mV

Backup mode, V_IN= 2.3 V to 5.5 V at I_OUT

I_OUTmax

=

100

On mode, V_IN= V_INmin+ 0.2 V to V_INmax

I_OUT= I_OUTmax/ 2 to I_OUTmaxin 5 µs

and I_OUT= I_OUTmaxto I_OUTmax/ 2 in 5 µs

Transient load regulation

50⁽¹⁾

On mode, V_IN= V_INmin+ 0.5 V to V_INminin 30

µs

Transient line regulation

Turnon time

25⁽¹⁾

mV

ms

and V_IN= V_INminto V_INmin+ 0.5 V in 30 µs,

I_OUT= I_OUTmax/ 2

I_OUT= 0, V_INrising from 0 up to 3.6 V, at V_OUT

= 0.1 V up to V_OUTmin

2.2

55

35

ƒ = 217

V_IN= V_INDC+ 100 mV_pptone,

Hz

Ripple rejection

V_INDC+= V_INmin+ 0.1 V to V_INmax

dB

µA

ƒ = 50

kHz

at I_OUT= I_OUTmax/ 2

Device in ACTIVE state

23

3

Ground current

Device in BACKUP or OFF state

(1) These parameters are not tested. They are used for design specification only.

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Specifications

19

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5.13 Electrical Characteristics: VIO SMPS

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_OUT= 1.5 V, 1.8 V, or 2.5 V

MIN

2.7

TYP

MAX

5.5

UNIT

Input voltage on VCCIO

V

and VCC7 (V_IN

)

V_OUT= 3.3 V

V_OUT

–3%

5.5

VSEL= 00

VSEL = 01

VSEL = 10

VSEL = 11

1.5

1.8

2.5

3.3

0

3%

PWM mode (VIO_PSKIP =

0)

DC output voltage

(V_OUT

or pulse skip mode I_OUT

0 to I_MAX

=

V

)

Power down

VIO output voltage = 1.5 V

VIO output voltage = 1.8 V

VIO output voltage = 2.5 V

VIO output voltage = 3.3 V

1300

1200

1100

Rated output current

(I_OUTmax

ILMAX[1:0] =11

mA

)

P-channel MOSFET

On-resistance

V_IN= V_INmin

V_IN= 3.8 V

300

250

mΩ

400

2

(R_{DS(ON)_PMOS}

P-channel leakage

current (I_{LK_PMOS}

)

V_IN= V_INMAX, SWIO = 0 V

µA

mΩ

µA

)

N-channel MOSFET

On-resistance

V_IN= V_MIN

V_IN= 3.8 V

300

250

400

2

(R_{DS(ON)_NMOS}

N-channel leakage

current (I_{LK_NMOS}

)

V_IN= V_INmax, SWIO = V_INmax

)

ILMAX[1:0] = 00

ILMAX[1:0] = 01

ILMAX[1:0] = 10

ILMAX[1:0] = 00

ILMAX[1:0] = 01

ILMAX[1:0] = 10

ILMAX[1:0] = 00

ILMAX[1:0] = 01

ILMAX[1:0] = 10

650

1200

1700

650

PMOS current limit

(high-side)

Source current load,

V_IN= V_INminto V_INmax

mA

Source current load

V_IN= V_INminto V_INmax

1200

1700

800

NMOS current limit (low-

side)

mA

Sink current load

V_IN= V_INminto V_INmax

1200

1700

DC load regulation

DC line regulation

On mode, I_OUT= 0 to I_OUTmax

20

mV

On mode, V_IN= V_INminto V_INmax

at I_OUT= I_OUTmax

V_IN= 3.8 V, V_OUT= 1.8 V

I_OUT= 0 to 500 mA, maximum slew = 100 mA/µs

I_OUT= 700 to 1200 mA, maximum slew = 100 mA/µs

Transient load

regulation

50

mV

µs

Turnon time, t_on

Overshoot

I_OUT= 200 mA

350

3%

SMPS turned on

Power-save mode ripple

voltage

0.025 ×

V_OUT

PFM (Pulse skip mode) mode, I_OUT= 1 mA

V_PP

Switching frequency

Duty cycle

2.7

3

3.3

MHz

100%

Minimum on time

P-channel MOSFET

35

30

1

ns

Ω

(T_ON(MIN)

)

Discharge resistor for

power-down sequence

50

(R_DIS

)

VFBIO internal

resistance

0.5

MΩ

20

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

Electrical Characteristics: VIO SMPS (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Off

1

PWM mode, I_OUT= 0 mA, V_IN= 3.8 V, VIO_PSKIP = 0

7500

250

PFM (pulse skipping) mode, no switching, 3-MHz clock

on

Ground current (I_Q)

µA

Low-power (pulse skipping) mode,

no switching ST[1:0] = 11

63

I_OUT= 10 mA

40%

83%

85%

80%

75%

68%

80%

85%

I_OUT= 100 mA

PWM mode, DCR_L< 50

mΩ,

V_OUT= 1.8 V, V_IN= 3.6 V:

I_OUT= 400 mA

I_OUT= 800 mA

I_OUT= 1200 mA

I_OUT= 1 mA

Conversion efficiency

PFM mode, DCR_L< 50

mΩ,

V_OUT= 1.8 V, V_IN= 3.6 V

I_OUT= 10 mA

I_OUT= 400 mA

5.14 Electrical Characteristics: VDD1 SMPS

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

_OUT≤ 2.7 V

Input voltage on VCC1

V

and VCC7 (V_IN

)

V_OUT> 2.7 V

V_OUT

5.5

Max programmable voltage,

SEL[6:0] = 1001011

1.5

1.2

0.6

SEL[6:0] = 0110011

–3%

3%

VGAIN_SEL = 00,

I_OUT= 0 to I_OUTmax

Min programmable voltage,

SEL[6:0] = 0000011

DC output voltage

(V_OUT

V

SEL[6:0] = 000000: power

down

)

0

2.2

3.3

VGAIN_SEL = 10, SEL = 0101011 = 43, I_OUT= 0 to

I_OUTmax

–3%

3%

VGAIN_SEL = 11, SEL = 0101011 = 43, I_OUT= 0 to

I_OUTmax

DC output maximum

voltage maximum value

V

DC output voltage

programmable step

VGAIN_SEL = 00, 72 steps

12.5

mV

(V_OUTSTEP

)

VDD1 output voltage = (0.6 to 2.2 V)

VDD1 output voltage = 3.2 V

1500

1200

Rated output current

(I_OUTmax

mA

)

VDD1 output voltage = (1.2 V, 1.35 V, 1.5 V)

V_INmin= 3 V

2000

P-channel MOSFET

On-resistance

V_IN= V_INmin

V_IN= 3.8 V

300

250

mΩ

µA

400

2

(R_{DS(ON)_PMOS}

)

P-channel leakage

current

V_IN= V_INmax, SW1 = 0 V

(I_{LK_PMOS}

)

N-channel MOSFET

On-resistance

V_IN= V_MIN

V_IN= 3.8 V

300

250

mΩ

µA

400

2

(R_{DS(ON)_NMOS}

)

N-channel leakage

current

V_IN= V_INmax, SW1 = V_INmax

(I_{LK_NMOS}

)

Specifications

21

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Electrical Characteristics: VDD1 SMPS (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PMOS current limit

(high-side)

V_IN= V_INminto V_INmax

1800

mA

V_IN= V_INminto V_INmax, source current load

V_IN= V_INminto V_INmax, sink current load

1800

NMOS current limit (low-

side)

mA

On mode, V_IN= V_INminto V_INmax

at I_OUT= 1500 mA

VDD1 output voltage = (0.6 to 1.5 V)

20

30

On mode, V_IN= V_INminto V_INmax

at I_OUT= 2000 mA

VDD1 output voltage = (1.2 V, 1.35 V, 1.5 V)

V_INmin= 3 V

DC load regulation

mV

On mode, V_IN= V_INminto V_INmax

at I_OUT= 1500 mA

VDD1 output voltage = 2.2 V

30

20

On mode, V_IN= V_INminto V_INmax

at I_OUT= 1200 mA

VDD1 output voltage = 3.2 V

On mode, V_IN= V_INminto V_INmax

at I_OUT= 1500 mA

VDD1 output voltage = (0.6 to 1.5 V)

On mode, V_IN= V_INminto V_INmax

at I_OUT= 2000 mA

VDD1 output voltage = (1.2 V, 1.35 V, 1.5 V)

V_INmin= 3 V

30

DC line regulation

mV

On mode, V_IN= V_INminto V_INmax

at I_OUT= 1500 mA

VDD1 output voltage = 2.2 V

30

50

On mode, V_IN= V_INminto V_INmax

at I_OUT= 1200 mA

VDD1 output voltage = 3.2 V

V_IN= 3.8 V, V_OUT= 1.2 V

I_OUT= 0 to 500 mA , Maximum slew = 100 mA/µs

I_OUT= 700 mA to 1.2 A , Maximum slew = 100 mA/µs

Transient load

regulation

mV

µs

Turnon time (t_on) off to

on

I_OUT= 200 mA

350

TSTEP[2:0] = 001

12.5

7.5

From V_OUT= 0.6 V to 1.5 V

Output voltage transition

rate

and V_OUT= 1.5 V to 0.6 V TSTEP[2:0] = 011 (default)

mV/µs

I_OUT= 500 mA

TSTEP[2:0] = 111

2.5

Overshoot

SMPS turned on

3%

Power-save mode ripple

voltage

0.025 ×

V_OUT

PFM (pulse skip mode), I_OUT= 1 mA

V_PP

Switching frequency

Duty cycle

2.7

3

3.3

MHz

100%

Minimum on time

(t_ON(MIN)

)

35

ns

P-channel MOSFET

Discharge resistor for

power-down sequence

R_DIS

30

1

50

1

Ω

VFB1 internal resistance

0.5

MΩ

Off

PWM mode, I_OUT= 0 mA, V_IN= 3.8 V, VDD1_PSKIP = 0

Pulse skipping mode, no switching

7500

78

Ground current (I_Q)

µA

Low-power (pulse skipping) mode, no switching

ST[1:0] = 11

63

22

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

Electrical Characteristics: VDD1 SMPS (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_OUT= 10 mA

MIN

TYP

35%

78%

80%

74%

62%

59%

70%

80%

MAX

UNIT

I_OUT= 100 mA

PWM mode, DCR_L< 0.1

Ω, V_OUT= 1.2 V, V_IN= 3.6 I_OUT= 400 mA

V

I_OUT= 800 mA

Conversion efficiency

I_OUT= 1500 mA

I_OUT= 1 mA

PFM mode, DCR_L< 0.1 Ω,

I_OUT= 10 mA

V_OUT= 1.2 V, V_IN= 3.6 V

I_OUT= 400 mA

5.15 Electrical Characteristics: VDD2 SMPS

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

_OUT≤ 2.7 V

Input voltage on VCC2

V

and VCC7 (V_IN

)

V_OUT> 2.7 V

V_OUT

5.5

Max programmable voltage,

SEL[6:0] = 1001011

1.5

1.2

0.6

SEL[6:0] = 0110011

–3%

3%

Min programmable voltage,

SEL[6:0] = 0000011

DC output voltage

(V_OUT

VGAIN_SEL = 00,

I_OUT= 0 to I_OUTmax

V

SEL[6:0] = 000000: power

down

)

0

2.2

3.3

VGAIN_SEL = 10,

SEL = 0101011 = 43

–3%

3%

VGAIN_SEL = 11, SEL =

0101011 = 43

DC output maximum

voltage maximum value

V

DC output voltage

programmable step

VGAIN_SEL = 00, 72 steps

12.5

mV

(V_OUTSTEP

)

VDD2 output voltage = 0.6 to 1.5 V

VDD2 output voltage = 2.2 V

VDD2 output voltage = 3.2 V

V_IN= V_INmin

1500

1200

Rated output current

I_OUTmax

mA

P-channel MOSFET

On-resistance

300

250

mΩ

V_IN= 3.8 V

400

2

(R_{DS(ON)_PMOS}

P-channel leakage

current (I_{LK_PMOS}

)

V_IN= V_INmax, SW2 = 0 V

V_IN= V_MIN

µA

mΩ

)

N-channel MOSFET

On-resistance

300

250

V_IN= 3.8 V

400

2

(R_{DS(ON)_NMOS}

N-channel leakage

current (I_{LK_NMOS}

)

V_IN= V_INmax, SW2 = V_INmax

µA

)

PMOS current limit

(high-side)

V_IN= V_INminto V_INmax, source current load

1800

mA

V_IN= V_INminto V_INmax, source current load

V_IN= V_INminto V_INmax, sink current load

1800

NMOS current limit (low-

side)

mA

mV

On mode, V_IN= V_INminto V_INmaxat I_OUT= 1500 mA

VDD2 output voltage = 0.6 to 1.5V

20

30

DC load regulation

On mode, V_IN= V_INminto V_INmaxat I_OUT= 1200 mA

VDD2 output voltage = 2.2 to 3.3 V

Specifications

23

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Electrical Characteristics: VDD2 SMPS (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

On mode, V_IN= V_INminto V_INmaxat I_OUT= 1500 mA

VDD2 output voltage = 0.6 to 1.5V

20

DC line regulation

mV

On mode, V_IN= V_INminto V_INmaxat I_OUT= 1200 mA

VDD2 output voltage = 2.2 to 3.3 V

30

50

V_IN= 3.8 V, V_OUT= 1.2 V

I_OUT= 0 to 500 mA , Maximum slew = 100 mA/µs

I_OUT= 700 mA to 1.2 A , Maximum slew = 100 mA/µs

Transient load

regulation

mV

µs

Turnon time (t_on) Off to

on

I_OUT= 200 mA

350

TSTEP[2:0] = 001

12.5

7.5

From V_OUT= 0.6 V to 1.5 V

Output voltage transition

rate

and V_OUT= 1.5 V to 0.6 V TSTEP[2:0] = 011 (default)

mV/µs

I_OUT= 500 mA

TSTEP[2:0] = 111

2.5

Overshoot

SMPS turned on

3%

Power-save mode ripple

voltage

0.025 ×

V_OUT

PFM (pulse skip mode), I_OUT= 1 mA

V_PP

Switching frequency

Duty cycle

2.7

0.5

3

3.3

MHz

100%

Minimum on time

P-Channel MOSFET

35

ns

Discharge resistor for

power-down sequence

30

1

50

1

Ω

(R_DIS

)

VFB2 internal resistance

MΩ

Off

PWM mode, I_OUT= 0 mA, V_IN= 3.8 V, VDD2_PSKIP = 0

PFM (pulse skipping) mode, no switching

7500

78

Ground current (I_Q)

µA

Low-power (pulse skipping) mode, no switching ST[1:0] =

11

63

I_OUT= 10 mA

35%

78%

80%

74%

66%

62%

59%

70%

80%

39%

85%

91%

90%

86%

80%

82%

92%

I_OUT= 100 mA

PWM mode, DCR_L< 50

I_OUT= 400 mA

mΩ, V_OUT= 1.2 V, V_IN

3.6 V

=

I_OUT= 800 mA

I_OUT= 1200 mA

I_OUT= 1500 mA

I_OUT= 1 mA

PFM mode, DCR_L< 50

mΩ, V_OUT= 1.2 V, V_IN

3.6 V

=

I_OUT= 10 mA

I_OUT= 400 mA

I_OUT= 10 mA

I_OUT= 100 mA

Conversion efficiency

PWM mode, DCR_L< 50

mΩ, V_OUT= 3.3 V, V_IN= 5 I_OUT= 400 mA

V

I_OUT= 800 mA

I_OUT= 1200 mA

I_OUT= 1 mA

PFM mode, DCR_L< 50

mΩ, V_OUT= 3.3 V, V_IN= 5 I_OUT= 10 mA

V

I_OUT= 400 mA

24

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

5.16 Electrical Characteristics: VDDCtrl SMPS

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

3

TYP

MAX

25

UNIT

V

Input voltage for external

FETs

V_IN

Input voltage V5IN

DC output voltage

4.5

5.5

V

SEL[6:0] = 1000011 to

1111111

1.4

1.2

I_OUT= 0 to I_OUTmax: maximum

programmable voltage

...

SEL[6:0] = 0110001

...

V_OUT

V

SEL[6:0] = 0000001 to

0000011

0.6

0

I_OUT= 0 to I_OUTmax: minimum

programmable voltage

SEL[6:0] = 000000: power

down

DC output voltage

programmable step

V_OUTSTEP

t_on

12.5

900

5

mV

µs

Turnon time, off to on

From EN high to V_out= 95%

Output voltage transition

rate

From V_OUT= 0.6 V to 1.4 V and V_OUT= 1.4 V to 0.6 V I_OUT

500 mA

=

⁽¹⁾mV/µs

I_OUT= 100 mA

I_OUT= 1 A

10

100

340

Switching frequency

kHz

µA

I_OUT= 5 A

Ground current, off

1

I_Q

Ground current, no load

400

320

500

SUPPLY CURRENT

V5IN current, T_A= 25°C,

No load

V_(EN)= 5 V,

I_(V5IN)

V5IN supply current

500

1

µA

V

V_(VOUT)= 0.63 V

V5IN current,

T_A= 25°C,

No load,

I_SD(V5IN)

V5IN shutdown current

V_(EN)= 0 V

INTERNAL REFERENCE VOLTAGE

Reference

0.5974

0.603

0.6086

(–0.0063 ×

VOUT +

0.0035)%

0.001 ×

VOUT –

0.0003%

Mismatch of resistive

divider

Specified by design. Not production tested.

V_OUT= 0.6 V

VOUT%

1.25

...

Specified by design. Not

production tested.

I_(VOUT)= 10^–4× VOUT – 6 ×

10^–5

...

I_(VOUT)

Output current

V_OUT= 1 V

...

40

µA

...

V_OUT= 1.3875 V

78.75

OUTPUT DISCHARGE

Output discharge current

I_Dischg

V_(EN)= 0 V, V_(SW)= 0.5 V

5

13

mA

from SW pin

OUTPUT DRIVERS

Source, I_(DRVH)= –50 mA

Sink, I_(DRVH)= 50 mA

Source, I_(DRVL)= –50 mA

Sink, I_(DRVL)= 50 mA

DRVH-off to DRVL-on

1.5

0.7

1

3

1.8

2.2

1.2

30

R_(DRVH)

DRVH resistance

Ω

R(DRVL) DRVL resistance

0.5

17

22

7

t_D

Dead time

ns

10

35

BOOT STRAP SWITCH

V_(FBST)

I_lkg

Forward voltage

V_(V5IN-VBST), I_F= 10 mA, T_A= 25°C

0.1

0.2

1.5

V

VBST leakage current

V_(VBST) = 34.5 V, V_(SW)= 28 V, T_A= 25°C

0.01

µA

(1) The output voltage is changed with 50 mV/10 µs steps

Specifications

25

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Electrical Characteristics: VDDCtrl SMPS (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DUTY AND FREQUENCY CONTROL

t_OFF(min)

t_ON(min)

f_SW

Minimum off-time

Minimum on-time

Switching frequency

T_A= 25°C

150

260

86

400

ns

V_IN= 28 V, V_OUT= 0.6 V, T_A= 25°C

Specified by design. Not production tested.

T_A= 25°C

312

340

368

kHz

SOFTSTART

t_ss

Internal SS time

From V_(EN)= high to V_OUT= 95%

0.9

ms

PROTECTION: CURRENT SENSE

TRIP source current

V_(TRIP)= 1 V, T_A= 25°C

On the basis of 25°C

9

10

11

3

µA

V_(TRIP)

TRIP current temperature

coefficient

4700

ppm/°C

Current limit threshold

setting range

V_(TRIP)

V_(TRIP-GND)Voltage

0.2

V

V_(TRIP)= 3 V

V_(TRIP)= 1.6 V

V_(TRIP)= 0.2 V

V_(TRIP)= 3 V

V_(TRIP)= 1.6 V

V_(TRIP)= 0.2 V

Positive

355

185

17

375

200

25

395

215

V_OCL

Current limit threshold

mV

33

–395

–215

–33

3

–375

–200

–25

15

–355

–185

–17

Negative current limit

threshold

V_OCLN

mV

Auto zero cross adjustable

range

Negative

–15

–3

UVLO

Wake up

4.2

3.7

4.38

3.93

4.5

4.1

V5IN UVLO threshold

V

Shutdown

THERMAL SHUTDOWN

Shutdown temperature

Specified by design. Not production tested.

145

10

Thermal shutdown

threshold

T_SDN

°C

Hysteresis

Specified by design. Not production tested.

26

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

5.17 Electrical Characteristics: LDO1 and LDO2

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage on VCC6 (V_IN

LDO1

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT(LDO1) = 1.05 V at 320 mA

and V_OUT(LDO2) = 1.05 V at 160 mA

1.4

3.6

V_OUT(LDO1) = 1.2 V or 1.5 V at 100 mA

and V_OUT(LDO2) = 1.2 V or 1.1 V or 1.0 V

1.7

2.1

3.6

V_OUT(LDO1) = 1.5 V and V_OUT(LDO1, LDO2)

= 1.8 V at 200 mA

)

V

V_OUT(LDO1) = 1.8 V and V_OUT(LDO2) = 1.8 V

V_OUT(LDO1) = 2.7 V

2.7

3.2

3.5

3.6

V_OUT(LDO1) = V_OUT(LDO2) = 3.3 V

SEL[7:2] =

000100

1

SEL[7:2] =

000101

1.05

...

ON and Low-power mode, V_IN

DC output voltage (V_OUT

)

= V_INminto V_INmax(V_INmax3.6 ...

–3%

3%

V

V)

SEL[7:2] =

110001

3.25

SEL[7:2] =

110010

3.3

On mode

320

1

Rated output current I_OUTmax

mA

Low-power mode

Load current limitation (short-circuit

protection)

On mode, V_OUT= V_OUTmin– 100 mV

450

600

1000

ON mode, V_DO= V_IN– V_OUT

V_IN= 1.4 V, I_OUT= I_OUTmax

,

Dropout voltage V_DO

DC load regulation

DC line regulation

350

12

4

mV

On mode, I_OUT= I_OUTmaxto 0

On mode, V_IN= V_INminto V_INmaxat I_OUT

I_OUTmax

=

ON mode, V_IN= 1.5 V, V_OUT= 1.05 V

I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5

µs

Transient load regulation

Transient line regulation

20

5

40

mV

On mode, V_IN= 2.7 + 0.5 V to 2.7 in 30 µs,

and V_IN= 2.7 to 2.7 + 0.5 V in 30 µs, I_OUT

I_OUTmax

=

10

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

230

600

Turnon inrush current

Ripple rejection

300

70

mA

dB

Ω

V_IN= V_INDC+ 100 mV_pptone, ƒ = 217 Hz

V_INDC+= 1.8 V,

ƒ = 20 kHz

40

I_OUT= I_OUTmax/ 2

LDO1 internal resistance

LDO off

600

63

On mode, I_OUT= 0

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode (max 85°C)

75

2000

20

Ground current

µA

22

2.7

Specifications

27

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Electrical Characteristics: LDO1 and LDO2 (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LDO2

SEL[7:2] =

000100

1

SEL[7:2] =

000101

1.05

...

On and low-power mode, V_IN

= V_INminto V_INmax

DC output voltage V_OUT

...

–3%

3%

V

(V_INmax= 3.6 V)

SEL[7:2] =

110001

3.25

SEL[7:2] =

110010

3.3

On mode

320

1

Rated output current I_OUTmax

mA

Low-power mode

Load current limitation (short-circuit

protection)

On mode, V_OUT= V_OUTmin– 100 mV

450

600

1000

ON mode, V_DO= V_IN– V_OUT

V_IN= 1.4 V, I_OUT= I_OUTmax

,

Dropout voltage V_DO

DC load regulation

DC line regulation

350

12

4

mV

On mode, I_OUT= I_OUTmaxto 0

On mode, V_IN= V_INminto V_INmaxat I_OUT

I_OUTmax

=

ON mode, V_IN= 1.5 V, V_OUT= 1.05 V

I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5

µs

Transient load regulation

Transient line regulation

20

5

40

mV

On mode, V_IN= 2.7 + 0.5 V to 2.7 in 30 µs,

and V_IN= 2.7 to 2.7 + 0.5 V in 30 µs, I_OUT

I_OUTmax

=

10

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

230

600

Turnon inrush current

Ripple rejection

300

70

mA

dB

Ω

V_IN= V_INDC+ 100 mV_pptone, ƒ = 217 Hz

V_INDC+= 1.8 V,

ƒ = 20 kHz

40

I_OUT= I_OUTmax/ 2

LDO2 internal resistance

LDO off

600

63

On mode, I_OUT= 0

On mode, I_OUT= I_OUTmax

Low-power mode

75

2000

20

Ground current

µA

22

Off mode (maximum 85°C)

2.7

28

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

5.18 Electrical Characteristics: LDO3 and LDO4

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage on VCC5 (V_IN

LDO3

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT(LDO3) = 1.8 V and V_OUT(LDO4) = 1.8 V

or 1.1 V or 1.0 V

2.7

5.5

)

V

V_OUT(LDO3) = 2.6 V and V_OUT(LDO4) = 2.5 V

V_OUT(LDO3) = 2.8 V

3.0

3.2

5.5

SEL[6:2] =

00010

1

SEL[6:2] =

00011

1.1

...

On and low-power mode,

DC output voltage (V_OUT

)

V_OUT= 1.0 to 3.3 V,

V_IN= V_INminto V_INmax

...

–3%

3%

V

SEL[6:2] =

11000

3.2

SEL[6:2] =

11001

3.3

On mode

200

1

Rated output current (I_OUTmax

)

mA

Low-power mode

Load current limitation (short-circuit

protection)

On mode, V_OUT= V_OUTmin– 100 mV

400

550

150

650

On mode, V_OUTtyp= 3.3 V, V_DO= V_IN– V_OUT

V_IN= 3.6 V, I_OUT= I_OUTmax

,

Dropout voltage (V_DO

DC load regulation

DC line regulation

)

250

10

4

mV

On mode, I_OUT= I_OUTmaxto 0

On mode, V_IN= V_INminto V_INmaxat I_OUT

I_OUTmax

=

On mode, V_IN= 2.7 V, V_OUTtyp= 1.8 V

I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and

I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5 µs

Transient load regulation

Transient line regulation

15

22

mV

On mode, V_OUTtyp= 1.8V, I_OUT= I_OUTmax

V_IN= V_INmin+ 0.5 V to V_INminin 30 µs

,

0.5

1

and V_IN= V_INminto V_INmin+ 0.5 V in 30 µs,

I_OUT= I_OUTmax

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

200

450

Turnon inrush current

Ripple rejection

200

70

mA

dB

kΩ

V_IN= V_INDC+ 100 mV_pptone, ƒ = 217 Hz

V_INDC+= 3.8 V,

ƒ = 50 Hz

40

I_OUT= I_OUTmax/ 2

LDO3 internal resistance

LDO off

500

65

On mode, I_OUT= 0

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode

76

2000

22

Ground current

µA

14

1

LDO4

Specifications

29

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Electrical Characteristics: LDO3 and LDO4 (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SEL[7:2] =

000000

0.8

SEL[7:2] =

000001

0.85

0.9

0.95

1

SEL[7:2] =

000010

SEL[7:2] =

000011

On and low-power mode, V_IN

= V_INminto V_INmax

DC output voltage (V_OUT

)

SEL[7:2] =

000100

(1)

SEL[7:2] =

000101

1.05

...

–3%

3%

V

SEL[7:2] =

110001

3.25

SEL[7:2] =

110010

3.3

On mode

50

1

Rated output current (I_OUTmax

)

mA

Low-power mode

Load current limitation (short-circuit

protection)

On mode, V_OUT= V_OUTmin– 100 mV

200

400

100

500

On mode, V_OUTtyp= 2.5 V, V_DO= V_IN– V_OUT

V_IN= 3.6 V, I_OUT= I_OUTmax

Dropout voltage (V_DO

DC load regulation

DC line regulation

)

160

5

mV

On mode, I_OUT= I_OUTmaxto 0

On mode, V_IN= V_INminto V_INmaxat I_OUT

I_OUTmax

=

4

On mode, V_IN= 2.7 V, V_OUTtyp= 1.8 V

I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5

µs

Transient load regulation

Transient line regulation

6

10

1

mV

On mode, V_IN= V_INmin+ 0.5 V to V_INminin 30

µs

and V_IN= V_INminto V_INmin+ 0.5 V in 30 µs,

I_OUT= I_OUTmax/ 2

0.2

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

30

50

150

200

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of

V_OUT

V_IN= V_INDC+ 100 mV_pptone, ƒ = 217 Hz

V_INDC+= 3.8 V,

I_OUT= I_OUTmax/ 2

70

40

Ripple rejection

dB

ƒ = 50 kHz

LDO4 internal resistance

LDO off

500

55

kΩ

On mode, I_OUT= 0

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode

65

900

17

Ground current

µA

14

1

(1) Set DCDCCTRL_REG.TRACK=1 and disable VDD1 to achieve V_OUT< 1 V.

30

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

5.19 Electrical Characteristics: LDO5

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_OUT(LDO5) = 1.8 V

MIN

2.7

3.2

TYP

MAX

5.5

UNIT

V_OUT(LDO5) = 2.5 V

5.5

Input voltage on VCC4

V

(V_IN

)

V_OUT(LDO5) = 2.8 V at I_load= 200 mA

V_OUT(VAUX2) = 2.8 V at 300 mA

5.5

LDO5

SEL[6:2] = 00010

SEL[6:2] = 00011

...

1

1.1

...

On and low-power mode, V_OUT

1.0 V to 3.3 V,

V_IN= V_INminto V_INmax

=

DC output voltage

–3%

3%

V

(V_OUT

)

SEL[6:2] = 11000

SEL[6:2] = 11001

3.2

3.3

On mode

300

1

Rated output current

(I_OUTmax

mA

)

Low-power mode

Load current limitation

(short-circuit protection)

On mode, V_OUT= V_OUTmin– 100 mV

450

550

650

500

400

300

V_IN= 2.7 V, I_OUT

I_OUTmax

=

V_IN= 2.7 V, I_OUT

250 mA

=

Dropout voltage (V_DO

)

On mode, V_DO= V_IN– V_OUT

mV

V_IN= 2.7 V, I_OUT

200 mA

DC load regulation

DC line regulation

On mode, I_OUT= I_OUTmaxto 0

15

4

mV

On mode, V_IN= V_INminto V_INmaxat I_OUTmax

On mode, V_IN= 3.2 V, V_OUTtyp= 2.8 V

Transient load regulation I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5 µs

16

4

30

mV

On mode, V_IN= V_INmin+ 0.5 V to V_INminin 30 µs

Transient line regulation and V_IN= V_INminto V_INmin+ 0.5 V in 30 µs,

I_OUT= I_OUTmax

12

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

200

450

Turnon inrush current

200

70

mA

dB

Ω

V_IN= V_INDC+ 100 mV_pptone,

V_INDC+= 3.8 V,

I_OUT= I_OUTmax/ 2

ƒ = 217 Hz

ƒ = 20 kHz

Ripple rejection

40

LDO5 internal resistance LDO Off

On mode, I_OUT= 0

60

65

76

2000

22

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode

Ground current

µA

14

1

Specifications

31

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5.20 Electrical Characteristics: LDO6, LDO7, and LDO8

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT(LDO6) = 1.2 V at 150 mA, V_OUT(LDO7) = 1.1 V at

150 mA

1.7

5.5

and (VLDO8) = 1 V at 180 mA

V_OUT(LDO7) = 1.8 V or 2 V and V_OUT(LDO6) = 1.8 V

V_OUT(LDO7) = 2.8 V

2.7

3.2

3.6

3.2

3.6

5.5

Input voltage on VCC3

V

(V_IN

)

V_OUT(LDO7) = 3.3 V

V_OUT(LDO7) = 2.8 V at 250 mA

V_OUT(LDO7) = 3.0 V

V_OUT(LDO7) = 3.3 V at 250 mA

LDO6

SEL[6:2] = 00010

SEL[6:2] = 00011

1

1.1

...

DC Output voltage

On and low-power mode, V_IN

V_INminto V_INmax

=

...

–3%

3%

V

(V_OUT

)

SEL[6:2] = 11000

SEL[6:2] = 11001

3.2

3.3

On mode

300

1

Rated output current

(I_OUTmax

mA

)

Low-power mode

Load current limitation

(short-circuit protection)

On mode, V_OUT= V_OUTmin– 100 mV

450

550

650

500

400

300

700

500

300

V_IN= 2.7 V, I_OUT

I_OUTmax

=

V_IN= 2.7 V, I_OUT

250 mA

=

V_IN= 2.7 V, I_OUT

200 mA

Dropout voltage (V_DO

)

On mode, V_DO= V_IN– V_OUT

mV

V_IN= 1.7 V, I_OUT

180 mA

V_IN= 1.7 V, I_OUT

150 mA

V_IN= 1.7 V, I_OUT

100 mA

DC load regulation

DC line regulation

On mode, I_OUT= I_OUTminto 0

15

4

mV

On mode, V_IN= V_INminto V_INmaxat I_OUT= I_OUTmax

On mode, V_IN= 3.2 V, V_OUTtyp= 2.8 V

Transient load regulation I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5 µs

20

5

32

mV

On mode, V_IN= 2.7 V + 0.5 V to 2.7 V in 30 µs

Transient line regulation

15

and V_IN= 2.7 V to 2.7 V + 0.5 V in 30 µs, I_OUT= I_OUTmax

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

200

450

Turnon inrush current

Ripple rejection

200

70

mA

dB

Ω

V_IN= V_INDC+ 100 mV_pptone,

V_INDC+= 3.8 V,

I_OUT= I_OUTmax/ 2

ƒ = 217 Hz

ƒ = 20 kHz

40

LDO6 internal resistance LDO off

On mode, I_OUT= 0

60

65

76

2000

22

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode

Ground current

µA

14

1

32

Specifications

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

Electrical Characteristics: LDO6, LDO7, and LDO8 (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

LDO7

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SEL[6:2] = 00010

1

1.1

...

SEL[6:2] = 00011

...

DC output voltage

(V_OUT

On and low-power mode, V_IN

V_INminto V_INmax

=

–3%

3%

V

)

SEL[6:2] = 11000

SEL[6:2] = 11001

3.2

3.3

On mode

300

1

Rated output current

(I_OUTmax

mA

)

Low-power mode

Load current limitation

(short-circuit protection)

On mode, V_OUT= V_OUTmin– 100 mV

450

550

650

500

400

300

700

500

300

V_IN= 2.7 V, I_OUT

I_OUTmax

=

V_IN= 2.7 V, I_OUT

250 mA

=

V_IN= 2.7 V, I_OUT

200 mA

Dropout voltage (V_DO

)

On mode, V_DO= V_IN– V_OUT

mV

V_IN= 1.7 V, I_OUT

180 mA

V_IN= 1.7 V, I_OUT

150 mA

V_IN= 1.7 V, I_OUT

100 mA

DC load regulation

DC line regulation

On mode, I_OUT= I_OUTmaxto 0

15

4

mV

On mode, V_IN= V_INminto V_INmaxat I_OUT= I_OUTmax

On mode, V_IN= 3.6 V, V_OUTtyp= 3.3 V

Transient load regulation I_OUT= 0.1 × I_OUTmaxto 0.9 × I_OUTmaxin 5 µs

and I_OUT= 0.9 × I_OUTmaxto 0.1 × I_OUTmaxin 5 µs

16

5

25

mV

On mode, I_OUT= I_OUTmax/ 2, V_IN= 2.7 + 0.5 V to 2.7 in 30

Transient line regulation µs

15

and V_IN= 2.7 V + 0.5 V in 30 µs, I_OUT= I_OUTmax/ 2

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

200

450

Turnon inrush current

Ripple rejection

200

70

mA

dB

Ω

V_IN= V_INDC+ 100 mV_pptone,

V_INDC+= 3.8 V,

I_OUT= I_OUTmax/ 2

ƒ = 217 Hz

ƒ = 20 kHz

40

LDO7 internal resistance LDO off

On mode, I_OUT= 0

60

65

76

2000

22

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode

Ground current

µA

14

1

Specifications

33

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Electrical Characteristics: LDO6, LDO7, and LDO8 (continued)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

LDO8

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SEL[6:2] = 00010

1

1.1

...

SEL[6:2] = 00011

...

DC output voltage

(V_OUT

On and low-power mode, V_IN

V_INminto V_INmax

=

–3%

3%

V

)

SEL[6:2] = 11000

SEL[6:2] = 11001

3.2

3.3

On mode

300

1

Rated output current

(I_OUTmax

mA

)

Low-power mode

Load current limitation

(short-circuit protection)

On mode, V_OUT= V_OUTmin– 100 mV

450

550

650

500

400

300

700

500

300

V_IN= 2.7 V, I_OUT

I_OUTmax

=

V_IN= 2.7 V, I_OUT

250 mA

=

V_IN= 2.7 V, I_OUT

200 mA

Dropout voltage (V_DO

)

On mode, V_DO= V_IN– V_OUT

,

mV

V_IN= 1.7 V, I_OUT

180 mA

V_IN= 1.7 V, I_OUT

150 mA

V_IN= 1.7 V, I_OUT

100 mA

DC load regulation

DC line regulation

On mode, I_OUT= I_OUTmaxto 0

15

4

mV

On mode, V_IN= V_INminto V_INmaxat I_OUT= I_OUTmax

On mode, V_IN= 1.7 V, V_OUTtyp= 1.2 V

Transient load regulation I_OUT= 10 mA to 90 mA in 5 µs and I_OUT= 90 mA to 10 mA

in 5 µs

7

5

30

mV

On mode, I_OUT= 100 mA, V_IN= 2.7 V + 0.2 V to 2.7 V in

Transient line regulation 30 µs

15

and V_IN= 2.7 V to 2.7 v + 0.2 V in 30 µs, I_OUT= 100 mA

V_OUT= (1 to 1.8 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

30

50

150

Turnon time

µs

V_OUT= (1.9 to 3.3 V), at I_OUT= 0

measured from V_OUT= 0.1 V up to 97% of V_OUT

200

450

Turnon inrush current

200

70

mA

dB

Ω

V_IN= V_INDC+ 100 mV_pptone,

V_INDC+= 3.8 V,

I_OUT= I_OUTmax/ 2

ƒ = 217 Hz

ƒ = 20 kHz

Ripple rejection

40

LDO8 internal resistance LDO off

On mode, I_OUT= 0

60

65

76

2000

22

On mode, I_OUT= I_OUTmax

Low-power mode

Off mode

Ground current

µA

14

1

34

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5.21 Timing and Switching Characteristics

5.21.1 I²C Timing and Switching

In Table 5-1, SDA is the SDA_SDI or EN2 signal and SCL is the SCL_SCK or EN1 signal. The input

timing requirements are given by considering a rising or falling time of 80 ns in high–speed mode (3.4

Mbps), 300 ns in fast–speed mode (400 kbps), 1000 ns in standard mode (100 kbps). Values are over the

operating free-air temperature range unless otherwise noted.

Table 5-1. Timing Requirements: I²C Interface and Control Signals

NO.

MIN

5

NOM

10

MAX UNIT

INT1 rise and fall times

C_L= 5 to 35 pF

ns

NRESPWRON rise and fall times

5

10

SLAVE HIGH–SPEED MODE

SCL/EN1 and SDA/EN2 rise and

C_L= 10 to 100 pF

C_L= 10 to 400 pF

10

80

ns

fall time

Data rate

3.4

Mbps

ns

I3

I4

I7

I8

I9

t_su(SDA-SCLH)

t_h(SCLL-SDA)

Setup time, SDA valid to SCL high

Hold time, SDA valid from SCL low

Setup time, SCL high to SDA low

Hold time, SCL low from SDA low

Setup time, SDA high to SCL high

10

0

70

ns

t_{su(SCLH-SDAL)}

t_h(SDAL-SCLL)

t_{su(SDAH-SCLH)}

160

ns

SLAVE FAST MODE

20 +

0.1 ×

C_L

SCL/EN1 and SDA/EN2 rise and

fall time

250

400

ns

Data rate

Kbps

ns

I3

I4

I7

I8

I9

t_su(SDA-SCLH)

t_h(SCLL-SDA)

Setup time, SDA valid to SCL high

Hold time, SDA valid from SCL low

Setup time, SCL high to SDA low

Hold time, SCL low from SDA low

Setup time, SDA high to SCL high

100

0

0.9

µs

t_{su(SCLH-SDAL)}

t_h(SDAL-SCLL)

t_{su(SDAH-SCLH)}

0.6

µs

SLAVE STANDARD MODE

SCL/EN1 and SDA/EN2 rise and

fall time

250

100

ns

Data rate

Kbps

ns

I3

I4

I7

I8

I9

t_su(SDA-SCLH)

t_h(SCLL-SDA)

Setup time, SDA valid to SCL high

Hold time, SDA valid from SCL low

Setup time, SCL high to SDA low

Hold time, SCL low from SDA low

Setup time, SDA high to SCL high

250

0

µs

t_{su(SCLH-SDAL)}

t_h(SDAL-SCLL)

t_{su(SDAH-SCLH)}

4.7

4

µs

4

µs

Specifications

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In Table 5-2, SCL is the SCL_SCK or EN1 signal. The input timing requirements are given by considering

a rising or falling time of 80 ns in high–speed mode (3.4 Mbps), 300 ns in fast–speed mode (400 kbps),

1000 ns in standard mode (100 kbps). Values are over the operating free-air temperature range unless

otherwise noted.

Table 5-2. Switching Characteristics: I²C Interface and Control Signals

NO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SLAVE HIGH–SPEED MODE

I1

I2

t_w(SCLL)

t_w(SCLH)

Pulse duration, SCL low

Pulse duration, SCL high

160

60

ns

SLAVE FAST MODE

I1

I2

t_w(SCLL)

t_w(SCLH)

Pulse duration, SCL low

Pulse duration, SCL high

1.3

0.6

µs

SLAVE STANDARD MODE

I1

I2

t_w(SCLL)

t_w(SCLH)

Pulse duration, SCL low

Pulse duration, SCL high

4.7

4

µs

36

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5.21.2 Switch-ON and Switch-OFF Sequences and Timing

This section describes an example boot sequence. Each TPS65911x device supports a dedicated

EEPROM boot sequence to match specific processor requirements. Fixed boot mode is the same in all

TPS65911x devices. Boot mode selection is described in Section 6.5.2.

t_pd2

PWRHOLD

t_dsON1

VIO

LDO5

t_dsON2

VDD2

t_dsON3

VDD1

t_dsON4

LDO4

t_dsON5

LDO3

LDO8

t_dsON6

LDO6

t_dsON15

i

CLK32KOUT

NRESPWRON

NRESPWRON2

t_pd1

t_dsON16

t_ond: Switch-on sequence

NOTE: Figure 5-1 is for illustrative purposes only and does not describe any actual TPS65911x part number.

Switch-off sequence

SWCS049-004

Figure 5-1. Boot Sequence Example With 2-ms Time Slot and Simultaneous Switch-Off of Resources

Table 5-3. Switching Characteristics for Boot Sequence Example

PARAMETER

TEST CONDITIONS

LDO5 enable delay

MIN

TYP

MAX

UNIT

66 × t_CK32k

=

t_dsON1

t_dsON2

t_dsON3

t_dsON4

t_dsON5

t_dsON6

PWRHOLD rising edge to VIO

µs

2060

64 × t_CK32k

=

VIO to VDD2 enable delay

µs

2000

64 × t_CK32k

=

VDD2 to VDD1 enable delay

VDD1 to LDO4 enable delay

LDO4 to LDO3, LDO8 enable delay

LDO3 to LDO6 enable delay

2000

64 × t_CK32k

=

2000

64 × t_CK32k

=

2000

64 × t_CK32k

=

2000

9 × 64 ×

LDO6 to CLK32KOUT rising-edge

delay

t_dsON7

t_CK32k

=

µs

18000

64 × t_CK32k

=

t_dsON16

t_dsONT

t_pd1

CLK32KOUT to NRESPWON

Total switch-on delay

NRESPWON2 rising-edge delay

NRESPWON2 falling-edge delay

µs

ms

µs

2000

32

PWRHOLD falling edge to

NRESPWON

2 × t_CK32k

=

62.5

Specifications

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Table 5-3. Switching Characteristics for Boot Sequence Example (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

NRESPWON falling edge to

CLK32KOUT low delay

3 × t_CK32k

=

t_pd1b

t_pd2

µs

92

PWRHOLD falling edge to supplies

and reference disable delay

5 × t_CK32k

=

µs

154

5.21.3 Power Control Timing

5.21.3.1 Device State Control Through PWRON Signal

Figure 5-2 shows the device state control through PWRON signal.

PWRON

VIO

1.8 V

CLK32KOUT

NRESPWRON

Interrupt acknowledge

PWRON_IT=1

Interrupt acknowledge

INT1

PWRON_IT=1

Internal pulse t

dOINT1

PWRHOLD

t_dbPWRHOLDF

Switch-off

sequence

t_dbPWRONF

t_dONPWHOLD

t_dSONT

Switch On sequence

t_dbPWRONF

SWCS049-005

A. The DEV_ON or AUTODEV_ON control bits can be used instead of the PWRHOLD signal to maintain supplies

on after a switch-on sequence.

B. The internal POWER ON enable condition pulse, t_dOINT1, keeps device active until a PWRHOLD acknowledge.

C. Switch-off from PWRHOLD removal.

Figure 5-2. Device State Control Through PWRON Signal

PWRON

VIO

NRESPWRON

PWRON_IT=1

INT1

PWRON_IT=1

PWRON_LP_IT=1

PWRHOLD

Switch-off

sequence

t_dPWRONLP

t_dPWRONLPTO

t_dbPWRONF

SWCS049-006

Figure 5-3. PWRON Long-Press Turnoff

38

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Table 5-4 lists the power control timing characteristics.

Table 5-4. Power Control Timing Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWRON falling-edge debouncing

delay

t_dbPWRONF

t_dbPWRONR

t_dbPWRHOLD

100

ms

PWRON rising-edge debouncing

delay

3 × t_CK32k

=

µs

94

PWRHOLD rising-edge debouncing

delay

2 × t_CK32k

=

63

INT1 (internal) power-on pulse

duration after PWRON low-level

(debounced) event

t_dOINT1

1

s

Delay to set high PWRHOLD signal

t_dONPWHOLor DEV_ON control bit after

t_dOINT1

–

=

t_DSONT

ms

NRESPWON released to keep on

the supplies

970⁽¹⁾

D

PWRON falling-edge to

PWRON_LP_IT

t_dPWRONLPPWRON long-press delay

4

s

PWROW long-press interrupt

t_dPWRONLPT

PWRON_LP_IT to NRESPWRON

falling-edge

(PWRON_LP_IT) to supplies switch-

off

1

O

(1) T_dSONT= 30 ms, as in example boot sequence.

Specifications

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5.21.3.2 Device SLEEP State Control

t_ACT2SLP

t_SLP2ACT

SLEEP

1.8 V

Low Power mode

1.8 V

PWM mode

1.8 V

PWM mode

VIO/VFBIO

SWIO

LDO5

1.8 V

ACTIVE mode

1.8 V

ACTIVE mode

1.8 V

Low-power mode

3.3 V

Pulse skip mode

3.3 V

Pulse skip mode

3.3 V

Low-power mode

VDD2/VFB2

SW2

t_dONDCDCSLP

1.2 V

PWM mode

1.2 V

PWM mode

Off

VDD1/VFB1

SW1

Off

1.8 V

ACTIVE mode

1.8 V

ACTIVE mode

LDO4

LDO3

1.8 V

ACTIVE mode

1.8 V

ACTIVE mode

1.8 V

ACTIVE mode

1.8 V

ACTIVE mode

1.8 V

ACTIVE mode

LDO8

LDO6

3.3 V

ACTIVE mode

3.3 V

ACTIVE mode

3.3V

Low-power mode

t_SLP2ACTCK32K

CLK32KOUT

t_ACT2SLPCK32K

t _dSLPONST

t_dSLPONST

0, VDD1_SETOFF 1, LDO3_SETOFF = 1,

t_dSLPON1

SWCS049-007

NOTE: Register programming: VIO_PSKIP

=

0, VDD1_PSKIP

=

LDO4_SETOFF = 1, LDO8_KEEPON = 1.

Figure 5-4. Device SLEEP State Control

Table 5-5. Device SLEEP State Control Timing Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2 ×

3 ×

Low-power mode (SLEEP resynchronization

delay)

t_ACT2SLPSLEEP falling-edge to supply

t_ACT2SLPCSLEEP falling-edge to

t_CK32k

=

t_CK32k

=

µs

62

94

t_ACT2SLP+ 3

× t_CK32k

156

8 ×

188

9 ×

µs

CLK32KOUT low

K32K

t_SLP2ACTSLEEP rising edge to supply

High-power mode

t_CK32k

=

t_CK32k

=

250

281

t_SLP2ACTCSLEEP rising edge to

t_SLP2ACT+ 3

× t_CK32k

344

375

CLK32KOUT running

K32K

SLEEP rising edge to time step 1

t_dSLPON1of the turnon sequence from

SLEEP state

t_SLP2ACT+ 1

× t_CK32k

281

312

40

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Table 5-5. Device SLEEP State Control Timing Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TSLOT_LENGTH[1:0]

= 00

0

TSLOT_LENGTH[1:0]

= 01

200

500

t_dSLPONSTTurnon sequence step duration

From SLEEP state

µs

TSLOT_LENGTH[1:0]

= 10

TSLOT_LENGTH[1:0]

= 11

2000

t_dSLPONDCVDD1, VDD2, or VIO turnon

2 × t_CK32k

=

From turnon sequence time step

µs

delay

62

DC

Specifications

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5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage

VMBCH threshold

VMBHI threshold

VMBDCH2 threshold

VMBLO threshold

VBNPR threshold

VCC7

VRTC

1.8 V

VBACKUP > VBNPR

VIO

CLK32KOUT

NRESPWRON

1.8 V

t

dbVMBLO

Interrupt acknowledge

VMBHI_IT=1

t

INT1

dbVMBDCH

PWRHOLD

Switch-off

sequence

t

d32KON

t

dONPWHOLD

dbVMBHI

dSONT

Switch On sequence

SWCS049-008

A. To allow power-up from first supply insertion as shown here, VMBHI_IT_MSK is set to 0.

B. Power-up to active state is enabled when VMBHI interrupt is not masked (VMBHI_IT_MSK in boot configuration).

C. The DEV_ON or AUTODEV_ON control bits can be used instead of the PWRHOLD signal to maintain supplies on

after a switch-on sequence.

Figure 5-5. Device Turnon and Turnoff With Rising and Falling Input Voltage

Table 5-6. Device Turnon Voltage With Rising Input Voltage, Timing Characteristics

MIN

NOM

0.1

MAX

UNIT

RC oscillator

t_d32KON

32-kHz oscillator turnon time

Quartz oscillator

Bypass clock

200

0.1

ms

4 × t_CK32k

=

t_dbVMBHI

VMBHI rising-edge debouncing delay

3 × t_CK32k= 94

µs

s

125

INT1 power on pulse duration after VMBHI high level

(debounced) event

t_dOINT1

1

Delay to set high PWRHOLD signal or DEV_ON control bit

after NRESPWRON released in order to keep on the supplies

t_dOINT1

t_DSONT= 970

–

t_dONPWHOLD

t_dbVMBDCH

t_dbVMBLO

ms

s

Main battery voltage = VMBDCH threshold to INT1 falling-

edge delay

4 × t_CK32k

=

3 × t_CK32k= 94

125

Main battery voltage = VMBLO threshold to NRESPWRON

falling-edge delay

4 × t_CK32k

=

s

125

42

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5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals

Switch-on sequence

Switch-off sequence

Device on

NRESPWRON

t

dEN

EN1

t

dVEN

t

dEN

LDO1

EN2

t

1.2 V

dSOFF2

t

dEN

t

dEN

Low-power mode

1.8 V

LDO4

SWCS046-009

NOTE: Register setting: LDO1_EN1 = 1, LDO4_EN2 = 1, and LDO4_KEEPON = 1.

Figure 5-6. LDO Type Supplies State Control Through EN1 and EN2

Switch-off sequence

Switch-on sequence

Device on

NRESPWRON

t

dEN

EN2

t

dVDDEN

t

dOEN

VDD2/VFB2

0 V

3.3 V

t

dSOFF2

EN1

t

dEN

VDD1/VFB1

t

1.2 V

PWM mode

dEN

Low-power mode

PFM (pulse skipping) mode

SW1

SWCS049-010

NOTE: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] = hex00 in

VDD2_SR_REG.

Figure 5-7. VDD1 and VDD2 Supplies State Control Through EN1 and EN2

Table 5-7. Supplies State Control Through EN1 and EN2 Timing Characteristics

MIN

NOM

MAX

UNIT

t_dEN

NRESPWRON to supply state change delay, EN1 or EN2 driven

EN1 or EN2 edge to supply state change delay

0

ms

1 × t_CK32k

=

31

t_dOEN

µs

3 × t_CK32k

=

63

t_dVDDEN

EN1 or EN2 edge to VDD1 or VDD2 DCDC turnon delay

Specifications

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5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals

EN1

t_dDVSEN

t_dDVSENL

t_dDVSEN

t_dDVSENL

1.2 V

0.8 V

VDD1/VFB1

SW1

TSTEP[2:0]=001

TSTEP[2:0]=011

PFM (pulse skipping) mode

PFM (pulse

skipping) mode

PFM (pulse

skipping) mode

SWCS049-011

PWM mode

NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG

Figure 5-8. VDD1 Supply Voltage Control Through EN1

Table 5-8. VDD1 Supply Voltage Control Through EN1 Timing Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EN1 (or EN2) edge to VDD1 (or

VDD2) voltage change delay

2 × t_CK32k

=

t_dDVSEN

µs

62

TSTEP[2:0] = 001

32

0.4 / 7.5 = 53

160

VDD1 (or VDD2) voltage settling

delay

t_dDVSENL

TSTEP[2:0] = 011 (default)

TSTEP[2:0] = 111

µs

44

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6 Detailed Description

6.1 Overview

The TPS65911 device is an integrated power management IC (PMIC) available in a 98-pin 0.65-mm pitch

BGA package. It is designed for applications powered by powered by one Li-Ion or Li-Ion polymer battery

cell, 3-series Ni-MH cells, or a 5-V input supply. It provides three step-down converters, one step-down

controller with external FETs to support high current rails, eight LDOs, nine GPIOs, and EERPOM-

programmable power sequencing to support a variety of processors and system sequencing requirements.

Two of the step-down converters, VDD1 and VDD2, provide power for processor cores and support

dynamic voltage scaling using I2C interface. VDD1 and VDD2 have an output voltage range of 0.6 V to

3.3V. The converters have a 12.5-mV step size from 0.6 V to 1.5 V, and a VGAIN_SEL option to multiply

this voltage by 2 or 3, with 3.3 V maximum output voltage. The third converter, VIO, provides power for I/O

and memory. VIO has four selectable voltage outputs, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.

The device includes 8 general-purpose LDOs with an output voltage range from 1 V to 3.3 V. Three of the

LDOs (LDO1, LDO2, and LDO4) support 50-mV output voltage steps, and the remaining five LDOs

(LDO3, LDO5, LDO6, LDO7, and LDO8) support 100-mV output voltage steps. The LDO voltages and

other configuration are controlled by the I2C interface.

The power-up and power-down sequences are controlled by the embedded power controller and is pre-

programmed using EEPROM. The power-up and power-down sequences assign each output rail to a

sequence slot, and the delay time between slots is either 0.5 ms or 2 ms.

The device offers nine GPIOs. Four of the GPIOs (GPIO0, GPIO2, GPIO6, and GPIO7) can be configured

to enable external resources, and can be included in the power sequences. The device also includes

dedicated input and reset pins used to enable and disable the PMIC including PWRON, PWRHOLD,

HDRST, and PWRDN. The NRESPWRON pin is a dedicated power-on reset output for a processor

powered by the PMIC.

Detailed Description

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6.2 Functional Block Diagram

C_BB

VBACKUP

VCC7

1.5 A at 0.6 to 2.2 V⁽¹⁾

VDD1

VCC1

SW1

BACKUP

VRTC

Management

VRTC (LDO)

and POR

AGND

OSC32KIN

GND1

VFB1

Oscillator

32 kHz

OSC32KOUT

Real-Time Clock

(RTC)

0.6 V to 3.3 V

REFGND

CLK32KOUT

1.5 A at 0.6 to 1.5 V⁽¹⁾

VDD2

VDDIO

SDA_SDI

SCL_SCK

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

I²C

VCC2

SW2

Bus Control

GND2

0.6 V to 3.3 V

VFB2

VBST

C_boost

DRVH

SW

DRVL

I²C

EN1

EN2

VOUT

VFB

Controller

C1

INT1

V5IN

SLEEP

Power-Control

State Machine

R_trip

C_V5IN

TRIP

GNDC

PWRON

0.6 V to 1.4 V

VIO

BOOT1

PWRHOLD

PWRDN

VCCIO

HDRST

SWIO

NRESPWRON

NRESPWRON2

GNDIO

1.3 A at 1.5 V

1.2 A at 1.8 V

1.1 A at 2.5 and 3.3 V

VREF

TESTV

VFBIO

VDDIO

Analog

References

Connect to system

1.8V/3.3 V supply

Watchdog

REFGND

LDO1

320 mA

LDO1

VCC6

LDO2

1 to 3.3 V,

50-mV step

LDO3

200 mA

Test Interface

1 to 3.3 V,

100-mV step

LDO3

VCC5

LDO4

1 to 3.3 V,

50-mV step

LDO2

320 mA

1 to 3.3 V,

50-mV step

LDO4

1 to 3.3 V,

100-mV step

LDO7

300 mA

LDO7

VCC3

LDO8

50 mA

LDO5

300 mA

1 to 3.3 V,

100-mV step

LDO5

VCC4

VCCS

1 to 3.3 V,

100-mV step

LDO8

300 mA

COMP

1

1 to 3.3 V,

100-mV step

LDO6

COMP

2

LDO6

300 mA

(1) For details on supported levels, see Section 5.14, Section 5.15, and Table 6-1.

46

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6.3 Power Reference

The band-gap voltage reference is filtered by using an external capacitor connected across the VREF

output and the analog ground REFGND (see Section 5.3). The VREF voltage is distributed and buffered

inside the device.

6.4 Power Resources

The power resources provided by the TPS65911 device include inductor based switched mode power

supplies (SMPSs) and linear low-dropout voltage regulators (LDOs). These supply resources provide the

required power to the external processor cores and external components, and to modules embedded in

the TPS65911 device.

Two of the integrated SMPSs and the external FET SMPS have voltage scaling capability. These SMPSs

provide independent core voltage domains to the host processor. When changing the output voltage,

VDD1 and VDD2 reach the new value through successive steps of 2.5 to 12.5 mV. The size of the voltage

step is selected by the TSTEP bit. VDDCtrl has a target slew rate of 100 mV/20 µs. New output values are

reached in successive smaller steps of N × LSB, LSB = 12.5 mV, N = 1 to 4. A suitable combination of

steps is calculated internally based on current and new target value for output voltage.

The VIO SMPS provides supply voltage for the host processor I/Os.

Table 6-1 lists the power sources provided by the TPS65911 device.

Table 6-1. Power Sources

RESOURCE

TYPE

VOLTAGES

POWER

1300 mA

1200 mA

1100 mA

1500 mA

1200 mA

2000 mA

1.5 V

VIO

SMPS

1.8 V

2.5 or 3.3 V

0.6 to 2.2 V

3.2 V

VDD1

SMPS

1.2 or 1.35 or 1.5 V (V_INmin= 3 V)

0.6 ... 1.5 V in 12.5-mV steps

Programmable multiplication factor: ×2, ×3. Maximum output 3.3 V

0.6 to 1.5 V

2.2 / 3.2 V

1500 mA

1200 mA

VDD2

SMPS

0.6 ... 1.5 V in 12.5-mV steps

Programmable multiplication factor: ×2, ×3. Maximum output 3.3 V

External component

dependent

VDDCtrl

0.6 … 1.4 V in 12.5-mV steps

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

LDO

1.0–3.3 V, 0.05-V step

1.0–3.3 V, 0.1-V step

1.0–3.3 V, 0.05-V step

1.0–3.3 V, 0.1-V step

320 mA

200 mA

50 mA

300 mA

6.5 Embedded Power Controller (EPC)

The EPC manages the state of the device and controls the power-up sequence.

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6.5.1 State Machine

The EPC supports the following states:

•

NO SUPPLY: The primary battery supply voltage is not high enough to power the VRTC regulator. A

global reset is asserted in this case. Everything on the device is off.

•

BACKUP: The primary battery supply voltage is high enough to enable the VRTC domain but not

enough to switch on all the resources. In this state, the VRTC regulator is in backup mode and only the

32K oscillator and RTC module are operating (if enabled). All other resources are off or under reset.

•

OFF: The primary battery supply voltage is high enough to start the power-up sequence, but device

power on is not enabled. All power supplies are in the OFF state except VRTC.

ACTIVE: Device POWER ON enable conditions are met and regulated power supplies are on or can

be enabled with full current capability.

SLEEP: Device SLEEP enable conditions are met and some selected regulated power supplies are in

low-power mode.

Figure 6-1 shows the transitions for the state machine.

AUTODEV_ON

DEV_ON

PWRHOLD

HDRST

INT1

Pulse

generator

NRESPWRON

T_DOINT1

PWRON

POWER ON

ENABLE

THERM_TS

T_D

NO SUPPLY

PWRON_LP_IT

DEV_OFF

DEV_OFF_RST

HDRST

VCC7 and BB < VBNPR

PWRDN_POL

PWRDN

VCC7 > VMBHI

OFF

VCC7 < VMBLO

VCC7 and BB < VBNPR

SLEEPSIG_POL

VCC7 > VMBHI

POWER ON

Enabled

And VCCS > VMBCH

SLEEP

INT1

SLEEP

ENABLE

DEV_SLP

POWER ON

disabled

BACKUP

VCC7 or BB >

VBNPR

and

VCC7 < VMBLO

ACTIVE

POWER ON

disabled

VCC7 < VMBLO

SLEEP

enabled

SLEEP

disabled

VCC7 < VMBLO

BB: Backup battery voltage

SLEEP

SWCS049-024

NOTE: PWRHOLD enables power-on unless the pin is programmed as GPI.

Figure 6-1. Embedded Power Control State Machine

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6.5.1.1 Device POWER ON Enable Conditions

The device POWER ON enable conditions are as follows:

•

None of the device POWER ON disable conditions are met.

PWRON signal low level

Or PWRHOLD signal high level

Or DEV_ON control bit set to 1 (default inactive)

Or interrupt flag active (default INT1 low) generates a POWER ON enable condition during a fixed

delay (t_DOINT1pulse duration defined in Section 5.21.3). Interrupt sources expected (if enabled), when

the device is off:

–

RTC alarm interrupt

First-time input voltage rising above the VMBHI threshold (depending on the boot mode used) and

input voltage > VMBCH threshold. The interrupt corresponding to this last condition is VMBCH_IT

in the INT_STS_REG register.

–

Or HDRST reset release generates a POWER ON enable condition during a fixed delay t_DOINT1

Interrupt flag active generates a POWER ON enable condition pulse of length t_DOINT1only when the device

is in the OFF state (when the NRESPWRON signal is low). The POWER ON enable condition pulse

occurs only if the interrupt status bit is initially low (no previous interrupt pending in the status register).

The interrupt status register must first be cleared to let the device power off during the t_DOINT1pulse

duration.

GPIO2 cannot be used to turn on the device, even if its associated interrupt is not masked. The GPIO0,

GPIO1, GPIO3, GPIO4, or GPIO5 signals can be used to turn on the device, if its associated interrupt is

not masked.

NOTE

The watchdog interrupt is not a power-on event, but can wake up the device from sleep

mode.

6.5.1.2 Device POWER ON Disable Conditions

Device POWER ON disable conditions are as follows:

•

PWRON signal low level during more than the long-press delay: PWON_LP_DELAY (can be disabled

though register programming). The interrupt corresponding to this condition is PWRON_LP_IT in the

INT_STS_REG register.

•

Or die temperature has reached the thermal shutdown threshold (THERM_TS = 1).

Or DEV_OFF or DEV_OFF_RST control bit is set to 1 (DEV_OFF value is cleared when the device is

in OFF state).

NOTE

If the DEV_ON bit is set to 1, after switch-off, the device switches back on. To keep the

device off, DEV_ON must be cleared first.

6.5.1.3 Device SLEEP Enable Conditions

Device SLEEP enable conditions are as follows:

•

SLEEP signal low level (default, or high level depending on the programmed polarity)

And DEV_SLP control bit is set to 1.

And interrupt flag inactive (default INT1 high): no nonmasked interrupt is pending.

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The SLEEP state can be controlled by programming DEV_SLP bit and keeping the SLEEP signal in the

active polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 after

device turnon.

6.5.1.4 Device Reset Scenarios

The device has three reset scenarios:

•

Full reset: All digital logic of device is reset.

Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR

General reset: No impact on the RTC, backup registers, or interrupt status.

–

•

–

Caused by PWON_LP_RST bit set high

Or DEV_OFF_RST bit set high

Or HDRST input set high

•

Turnoff: Power reinitialization in off/backup mode.

A mapping of digital registers to these reset scenarios is described in Table 6-6.

6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences

The power sequence is the automated switch-on of the devices resources when an OFF-to-ACTIVE

transition occurs. The power-on sequence has 15 sequential time slots to which resources (DC-DC

converters, LDOs, 32-kHz clock, GPIO0, GPIO2, GPIO6, GPIO7) can be assigned. The time slot length

can be selected to be 0.5 ms or 2 ms. If a resource is not assigned to any time slot, it will be in off mode

after the power-on sequence and the voltage level can be changed through the register SEL bits before

enabling the resource.

Power off disables all power resources at the same time by default. By setting the PWR_OFF_SEQ

control bit to 1, power off will follow the power-up sequence in reverse order (the first resource to be

powered on will be last to power off).

The values of VDD1, VDD2, and VDDCtrl set in the boot sequence can be selected from 16 steps. For the

whole range, 100-mV steps are available: 0.6/0.7...1.4/1.5 V. From 0.8 to 1.4 V, additional values with

50-mV step resolution can be set: 0.85/1.05...1.35 V.

For LDO1, LDO2, and LDO4 all levels from 1.0 to 3.3 V are selectable in the boot sequence with 50-mV

steps. For other LDOs, the level is selectable with 100-mV steps, from 1.0 to 3.3 V.

The device supports three boot configurations, which define the power sequence and several device

control bits. The boot configuration is selectable by the device BOOT1 pin.

BOOT1

BOOT CONFIGURATION

Floating

Test boot mode

0

1

Fixed boot mode

EEPROM boot mode

The BOOT1 input pad is disabled after the boot mode is read at power up, to save power.

Table 6-2 and Table 6-3 describe the power sequence and general control bits defined in the boot

sequence, respectively.

Fixed boot mode is the same in all devices, while EEPROM boot mode is different in each device. For a

description of EEPROM boot mode, refer to the user's guide for the selected device. For a list of user's

guides, see Section 8.2.1 or the device product folder on ti.com.

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Table 6-2. Boot Configuration: Power Sequence Control Bits

TPS65911

REGISTER

BIT

DESCRIPTION

EEPROM

BOOT

FIXED BOOT

VDD1 voltage level selection for boot.

Levels available:

VDD1_OP_REG/

VDD1_SR_REG

1.2 V

x

0.6/0.7/0.8/0.85/0.9/0.95/.../1.35/1.4/1.5 V

VDD1 gain selection, ×1 or ×2

VDD1 time slot selection

VDD1_REG

EEPROM

VGAIN_SEL

×1

3

x

DCDCCTRL_REG

VDD1_PSKIP

VDD1 pulse skip mode enable

Enable skip

VDD2 voltage level selection for boot.

Levels available:

VDD2_OP_REG/

VDD2_SR_REG

1.5 V

x

0.6/0.7/0.8/0.85/0.9/0.95/.../1.35/1.4/1.5 V

VDD2 gain selection, ×1 or ×3

VDD2 time slot selection

VDD2_REG

EEPROM

VGAIN_SEL

×1

x

6

DCDCCTRL_REG

VIO_REG

VDD2_PSKIP

SEL[3:2]

VDD2 pulse skip mode enable

VIO voltage selection

Enable skip

1.8 V

EEPROM

VIO time slot selection

4

DCDCCTRL_REG

VIO_PSKIP

VIO pulse skip mode enable

Enable skip

VDDCtrl voltage level selection for boot.

Levels available:

VDDCtrl_OP_REG/

VDDCtrl_SR_REG

Off

x

0.6/0.7/0.8/0.85/0.9/0.95/../1.35/1.4 V

VDDCtrl time slot selection

LDO1 voltage selection

LDO1 time slot

EEPROM

LDO1_REG

EEPROM

Off

x

SEL[7:2]

SEL[6:2]

SEL[7:2]

SEL[6:2]

1.05 V

Off

LDO2_REG

EEPROM

LDO2 voltage selection

LDO2 time slot

1.2 V

7

LDO3_REG

EEPROM

LDO3 voltage selection

LDO3 time slot

LDO3 voltage: 1 V

Off

LDO4_REG

EEPROM

LDO4 voltage selection

LDO4 time slot

1.2 V

2

LDO5_REG

EEPROM

LDO5 voltage selection

LDO5 time slot

LDO5 voltage: 1 V

Off

LDO6_REG

EEPROM

LDO6 voltage selection

LDO6 time slot

LDO6 voltage: 1 V

Off

1.2 V

5

LDO7_REG

EEPROM

LDO7 voltage selection

LDO7 time slot

LDO8_REG

EEPROM

LDO8 voltage selection

LDO8 time slot

1 V

7

CLK32KOUT pin

CLK32KOUT time slot

5

NRESPWRON, NRESPWRON2

NRESPWRON time slot

10

x

GPIO0 pin

GPIO2 pin

GPIO6 pin

GPIO7 pin

GPIO0 time slot

GPIO2 time slot

GPIO6 time slot

GPIO7 time slot

1

Off

6

x

5

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Table 6-3. Boot Configuration: General Control Bits

TPS65911

REGISTER

BIT

DESCRIPTION

FIXED BOOT

EEPROM BOOT

0: VRTC LDO will be in low-power mode during

OFF state.

VRTC_REG

VRTC_OFFMASK

0

x

1: VRTC LDO will be in full-power mode during

OFF state.

0: Clock source is crystal/external clock.

1: Clock source is internal RC oscillator.

0: No impact

DEVCTRL_REG

CK32K_CTRL

DEV_ON

Crystal

0

x

1: Will keep device on, in ACTIVE or SLEEP

state

Boot sequence time slot duration:

DEVCTRL2_REG

TSLOTD

0: 0.5 ms

1: 2 ms

2 ms

1

x

0: Turn off device after PWRON long-press not

allowed.

PWON_LP_OFF

1: Turn off device after PWRON long-press.

0: No impact

DEVCTRL2_REG

PWON_LP_RST

IT_POL

1

0

x

1: Reset digital core when device is off

0: INT1 signal will be active-low.

1: INT1 signal will be active-high.

0: Device will automatically switch-on at NO

SUPPLY-to-OFF or BACKUP-to-OFF transition

(device will switch-on when supply is inserted)

INT_MSK_REG

VMBHI_IT_MSK

1

x

1: Start-up reason required before switch-on

(VMBHI event interrupt masked)

0: GPIO5 falling-edge detection interrupt not

masked

INT_MSK3_REG

GPIO5_F_IT_MSK

GPIO5_R_IT_MSK

GPIO4_F_IT_MSK

GPIO4_R_IT_MSK

1

0

1

0

x

1: GPIO5 falling-edge detection interrupt

masked

0: GPIO5 rising-edge detection interrupt not

masked

1: GPIO5 rising-edge detection interrupt

masked

0: GPIO4 falling-edge detection interrupt not

masked

1: GPIO4 falling-edge detection interrupt

masked

0: GPIO4 rising-edge detection interrupt not

masked

1: GPIO4 rising-edge detection interrupt

masked

0: GPIO0 configured as push-pull output

1: GPIO0 configured as open-drain output

0: Watchdog disabled

GPIO0_REG

GPIO_ODEN

Push-pull

1

x

WATCHDOG_REG

WATCHDOG_EN

1: Watchdog enabled, periodic operation with

100 s

0: Enable input buffer for external resistive

divider

EEPROM

VMBBUF_BYPASS

VMBCH_SEL[5:1]

Disable buffer

3.1 V

x

1: In single-cell system, disable buffer for low

power

Select threshold for boot gating comparator

COMP1, 2.5–3.5 V.

VMBCH_REG

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Table 6-3. Boot Configuration: General Control Bits (continued)

TPS65911

REGISTER

BIT

DESCRIPTION

FIXED BOOT

EEPROM BOOT

0: PWRHOLD pin is used as PWRHOLD

feature.

1, PWRHOLD

pin is GPI

EEPROM

AUTODEV_ON

PWRDN_POL

x

1: PWRHOLD pin is GPI. After power on,

DEV_ON set high internally, no processor

action required to keep supplies.

0: PWRDN signal will be active-low.

1: PWRDN signal will be active-high.

Active-low

x

6.5.3 Control Signals

6.5.3.1 SLEEP

When none of the device SLEEP-disable conditions are met, a falling edge (default, or rising edge,

depending on the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the

device. A rising edge (default, or falling edge, depending on the programmed polarity) causes a transition

back to the ACTIVE state. This input signal is level-sensitive and no debouncing is applied.

While the device is in the SLEEP state, predefined resources are automatically set in their low-power

mode or off. Resources can be kept in their active mode (full-load capability) by programming the

SLEEP_KEEP_LDO_ON and the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per

power resource. If the bit is set to 1, then that resource stays in active mode when the device is in the

SLEEP state.

32KCLKOUT is also included in the SLEEP_KEEP_RES_ON register and the 32-kHz clock output is

maintained in the SLEEP state if the corresponding mask bit is set.

The status (low or high) of GPO0, GPO6, GPO7, and GPO8 are also controlled by the SLEEP signal, to

allow enabling and disabling of external resources during sleep.

6.5.3.2 PWRHOLD

The PWRHOLD pin can be used as a PWRHOLD signal input or as a general purpose input (GPI). The

mode is selected by the AUTODEV_ON bit, which is part of the boot configuration. When

AUTODEV_MODE = 0, the PWRHOLD feature is selected.

Configured as PWRHOLD, when none of the device POWER ON disable conditions are met, a high level

of this signal causes an OFF-to-ACTIVE state transition of the device and a low level causes a transition

back to the OFF state.

This input signal is level-sensitive and no debouncing is applied. The rising and/or falling edge of

PWRHOLD is highlighted through an associated interrupt if interrupt is unmasked.

When AUTODEV_ON = 1, the pin is used as a GPI. As a GPI, this input can generate a maskable

interrupt from a rising or falling edge of the input. When AUTODEV_ON = 1, a rising edge of

NRESPWRON also automatically sets the DEV_ON bit to 1 to keep supplies after the switch-on

sequence, thus removing the need for the processor to set the PWRHOLD signal or the DEV_ON bit.

6.5.3.3 BOOT1

This signal determines with which processor the device is working and, hence, which power-up sequence

is needed. For more details, see Section 5.21.2. No debouncing is present on this input signal.

6.5.3.4 NRESPWRON, NRESPWRON2

The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain. It is held low

until the ACTIVE state is reached. For detailed timing, see Section 5.21.2.

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The NRESPWRON2 signal is a second reset output. It follows the state of NRESPWRON but has an

open-drain output with external pullup. The supply for the external pullup must not be activated before the

TPS65911 device is in control of the output state (that is, not earlier than during first power-up sequence

slot). In off mode, the NRESPWRON2 output has weak internal pulldown.

6.5.3.5 CLK32KOUT

This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,

depending on the boot mode. It can be enabled and disabled by register bit, during the ACTIVE state of

the device. The CLK32KOUT output can also be enabled or not during the SLEEP state of the device

depending on the programming of the SLEEPMASK register.

6.5.3.6 PWRON

The PWRON input is connected to an external button. If the device is in the OFF or SLEEP state, a

debounced falling edge (PWRON input low for minimum of 100 ms) causes an OFF-to-ACTIVE state or a

SLEEP-to-ACTIVE state transition of the device. If the device is in active mode, then a low level on this

signal generates an interrupt. If the PWRON signal is low for more than the PWON_TO_OFF_DELAY

delay and the corresponding interrupt is not acknowledged by the processor within 1 second, the device

goes into the OFF state. For PWRON behavior, see Figure 5-2 and Figure 5-3.

6.5.3.7 INT1

The INT1 signal (default active low) warns the host processor of any event that has occurred on the

TPS65911 device. The host processor can then poll the interrupt from the interrupt status register through

I²C to identify the interrupt source. A low level (default setting) indicates an active interrupt, highlighted in

the INT_STS_REG register. The polarity of INT1 can be set programming the IT_POL control bit. INT1

flag active is a POWER ON enable condition during a fixed delay, t_DOINT1(only), when the device is in the

OFF state (when NRESPWRON is low).

Any of the interrupt sources can be masked programming the INT_MSK_REG register. When an interrupt

is masked its corresponding interrupt status bit is still updated, but the INT1 flag is not activated. Interrupt

source masking can be used to mask a device switch-on event. Because interrupt flag active is a POWER

ON enable condition, during t_DOINT1delay, any interrupt not masked must be cleared to allow immediate

turn off of the device.

For a description of interrupt sources, see Table 6-5.

6.5.3.8 EN2 and EN1

EN2 and EN1 are the data and clock signals of the serial control interface dedicated to voltage scaling

applications.

These signals can also be programmed to be used as enable signals of one or several supplies, when the

device is on (NRESPWRON high). A resource assigned to EN2 or EN1 control automatically disables the

serial control interface.

Programming EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers: EN1

and EN2 signals can be used to control the turn on/off or SLEEP state of any LDO-type supplies.

Programming EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers:

EN1 and EN2 signals can be used to control the turn on/off or LOW-POWER state (PFM mode) of SMPS-

type supplies.

The EN2 and EN1 signals can be used to set the output voltage of VDD1 and VDD2 SMPS from a roof to

a

floor value, preprogrammed in the VDD1_OP_REG, VDD2_OP_REG and VDD1_SR_REG,

VDD2_SR_REG registers.

When a supply is controlled through the EN1 or EN2 signals, its state is no longer driven by the device

SLEEP state.

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6.5.3.9 GPIO0 to GPIO8

GPIO0, GPIO2, GPIO6, and GPIO7 can be programmed to be part of the power-up sequence and used

as enable signals for external resources.

GPIO0 is a configurable I/O in the VCC7 domain. By default, its output is push-pull, driving low. GPIO0

can also be configured as an open-drain output with external pullup.

GPIO1 through GPIO8 are configurable open-drain digital I/Os in the VRTC domain. GPIO directivity,

debouncing delay, and internal pullup can be programmed. By default, all are inputs with weak internal

pulldown; as open-drain output an external pullup is required.

GPIO0, GPIO1, and GPIO3 through GPIO5 can be used to turn on the device if the corresponding

interrupt is not masked. When configured as an input, GPIO2 cannot be used to turn on the device, even if

its associated interrupt is not masked. The GPIO interrupt is level sensitive. When an interrupt is detected,

before clearing the interrupt, it should first be disabled by masking it.

GPIO1 and GPIO3, which have current sink capability of 10 mA, can also be used to drive LEDs

connected to a 5-V supply.

GPIO2 can be used for synchronizing DC-DC converters to an external clock. Programming DCDCCKEXT

= 1, VDD1, VDD2, and VIO DCDC switching can be synchronized using a 3-MHz clock set though the

GPIO2 pin. VDD1 and VDD2 will be in-phase and VIO will be phase shifted by 180 degrees.

It is recommended not to connect noisy switching signals to GPIO4 and GPIO5.

6.5.3.10 HDRST Input

HDRST is a cold reset input for the PMIC. High level at input forces the TPS65911 device into off mode,

causing a general reset of device to the default settings. The default state is defined by the register reset

state and boot configuration. HDRST high level keeps the device in off mode. When reset is released and

HDRST input goes low, the device automatically transitions to active mode. The device is kept in active

mode for the period t_DONIT1, after which another power-on enable reason is required to keep the device on.

The HDRST input is in the VRTC domain and has a weak internal pulldown, which is active by default.

6.5.3.11 PWRDN

The PWRDN input is a reset input with selectable polarity (PWRDN_POL). High(low) level at input forces

the TPS65911 device into off mode, causing a power-off reset. Off mode is maintained until PWRDN is

released and a start-up reason (for example, PWRON button press or DEV_ON = 1) is detected. An

interrupt is generated to indicate the cause for shutdown. The PWRDN input is in the VRTC domain but

can tolerate a 5-V input.

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6.5.3.12 Comparators: COMP1 and COMP2

The TPS65911 device has three comparators for system status detection/control. One comparator detects

the voltage at pin VCC7. When VCC7 > VMBHI, the comparator initiates a NO SUPPLY-to-OFF transition

and the VMBHI_IT interrupt is generated. When VCC7 < VMBLO, the comparator initiates an

ACTIVE/SLEEP/OFF-to-BACKUP transition. When both VCC7 and backup battery are below VBPNR, the

device goes to the NO SUPPLY state.

Comparators COMP1 and COMP2 detect the voltage of VCCS. Programmable comparator COMP1 is

intended for detecting if battery voltage is high enough for an OFF-to-ACTIVE transition of the TPS65911

device. For an OFF-to-ACTIVE transition VCCS must be > VMBCH (primary battery charged) and a level

below the comparator threshold prevents the power-up sequence. The threshold can be set from 2.5 to

3.5 V with 50-mV steps through VMBCH_SEL. The comparator has debouncing so that VCCS must stay

above VMBDCH (VMBCH – 0.1 V) for a debouncing period of 61 µs. The comparator can be bypassed if

the threshold selection is set to 0. The default threshold is set in the boot configuration.

In a system with a multiple-cell battery, the battery level is sensed through an external resistor divider. The

TPS65911 device has an internal buffer at the VCCS input, which must be used with the external resistive

divider.

In a single-cell system, VCCS and VCC7 are connected directly to the battery. The VCCS input buffer can

be bypassed to minimize power consumption. The buffer bypass is controlled with the VMBBUF_BYPASS

bit in the boot configuration.

COMP2 is disabled by default and can be enabled by software. The comparator trigger generates an

interrupt which is programmable on the rising (VMBCH2_H_IT) or falling edge (VMBCH2_L_IT), hence the

comparator can be used for detecting high or low battery scenarios. COMP2 generates an interrupt for the

host. In sleep mode, this creates a wake-up interrupt for the host. In off mode, the comparator trigger

generates a turnon event. In backup or no supply modes, the comparator is not active.

The COMP2 threshold can be set from 2.5 to 3.5 V with 50-mV steps. Enabling the comparator is done

through the voltage threshold selection bit VMBDCH2_SEL, which is set to 0 by default.

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6.5.3.13 Watchdog

The watchdog has two modes of operation.

In periodic operation, an interrupt is generated with a regular period defined by the WTCHDG_TIME

setting. The IC initiates WTCHDOG shutdown if the interrupt is not cleared within the period. The

watchdog interrupt WTCHDOG counter is reinitialized when NRESPWRON is low.

In interrupt mode the IC initiates WTCHDOG counter when interrupt is set pending and is cleared when

interrupt is cleared. If no interrupt is cleared before watchdog expiration within WTCHDG_TIME, the

device goes to off mode.

By default, periodic watchdog functionality is enabled with the maximum WTCHDG_TIME period.

Periodic mode:

WTCHDG_CNT

0

1

N

0

1

N

WTCHDG_IT

WTCHDG_OFF

WTCHDG_IT clearing

interrupt clearing

Interrupt mode:

WTCHDG_CNT

WTCHDG_OFF

0

1

i

0

1

N

SWCS049-013

Figure 6-2. Watchdog Signals

6.5.3.14 Tracking LDO

LDO4 has an optional mode where its output level follows that of VDD1, from 0.6 to 1.5 V, when VDD1 is

active. When VDD1 is set to off, the LDO4 output is defined by the SEL[7:2] bits in LDO4_REG, and can

be set from 0.8 to 1.5 V.

Tracking mode is enabled by setting TRACK = 1 in DCDCCTRL_REG. In initial activation, VDD1 must be

enabled and allowed to settle before enabling tracking mode. After initial activation, tracking mode can be

kept enabled while VDD1 is turned off. The value of TRACK is set to default (0) after any turnoff event.

TRACK bit

Setting

time t_ON

VDD1 enable

LDO4 MODE

LDO4

No Tracking 1 to 3.3 V

Tracking 0.6 to 1.5 V

Tracking 0.8 V to 1.5 V

Tracking 0.6 V

(LDO4 has same

level as VDD1)

(LDO4 has same

level as VDD1)

SWCS049-019

Figure 6-3. Tracking LDO

Detailed Description

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6.6 PWM and LED Generators

The TPS65911 device has two LED ON/OFF signal generators, LED1 and LED2. LED1 and LED2 have

independently controllable periods from 125 ms to 8 s and ON time from 62.5 to 500 ms. Within the

period, one or two ON pulses can be generated (control bit LED1(2)_SEQ). The user must take care to

program period and ON time correctly, because no limitation on selected values is imposed. LED1 and

LED2 signals can be routed to GPIO1 and GPO3 open-drain outputs, respectively. These GPIOs have a

current sink capability of 10 mA.

The PWM generator frequency and duty cycle are set by the PWM_FREQ and PWM_DUTY_CYCLE bits,

respectively. The PWM generator signal can be connected to the GPIO3 or GPIO8 output. The PWM

generator uses the 3-MHz clock, which is not available in off mode. To enable the PWM in sleep mode,

the I2CHS_KEEPON bit must be set to 1.

6.7 Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation

Dynamic voltage frequency scaling (DVFS) operation: A supply voltage value corresponding to a targeted

frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers.

The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed

value is limited to 12.5 mV/µs, fixed value.

Adaptative voltage scaling (AVS) operation: A supply voltage value corresponding to a supply voltage

adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers. The supply voltage is then

intended to be tuned by the digital core supplied, based its performance self-evaluation. The slew rate of

VDD1 or VDD2 voltage supply reaching a new programmed value is programmable though the

VDD1_REG or VDD2_REG register, respectively.

A serial control interface (optional mode for EN1 and EN2 pins) can be dedicated to voltage scaling

applications, to give dedicated access to the VDD1_OP_REG, VDD1_SR_REG and VDD2_OP_REG,

VDD2_SR_REG registers.

A general-purpose serial control interface (CTL-I²C) also gives access to these registers, if the

SR_CTL_I2C_SEL control bit is set to 1 in the DEVCTRL_REG register (default inactive).

Both control interfaces are compliant with HS-I²C specification (100 Kbps, 400 Kbps, or 3.4 Mbps).

6.8 32-kHz RTC Clock

The TPS65911 device can provide a 32-kHz clock to the platform through the CLK32KOUT output, when

a crystal is connected.

Alternatively, the device can accept a square-wave 32-kHz clock signal applied to OSC32IN input

(OSC32KOUT kept floating) and gate the clock to CLK32OUT. This clock must be present for any state of

the EPC except the NO SUPPLY state. The TPS65911 device also has an internal 32-kHz RC oscillator to

decrease the BOM if an accurate clock is not needed by the system.

Default selection of a 32-kHz RC oscillator versus 32-kHz crystal oscillator or external square-wave

32-kHz clock depends on the boot configuration setting for the CK32K_CTRL bit.

Switching from the 32-kHz RC oscillator to the 32-kHz crystal oscillator or external square-wave 32-kHz

clock can also be programmed though the DEVCTRL_REG register.

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VRTC

32 kHz to

Digital Block

Biasing

and

Amplitude

Control

OSC32KIN

REFGND OSC32KOUT

Q

C_OSCIN

C_OSCOUT

SWCS049-014

Figure 6-4. Crystal Oscillator 32-kHz Clock

6.9 Real Time Clock (RTC)

The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC is

kept supplied when the device is in the OFF state or the BACKUP state.

The primary functions of the RTC block are:

•

Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) format

Calendar information (Day/Month/Year/Day of the week) directly in BCD code up to year 2099

Programmable interrupts generation: The RTC can generate two interrupts: a timer interrupt

RTC_PERIOD_IT periodically (1s/1m/1h/1d period) and an alarm interrupt RTC_ALARM_IT at a

precise time of the day (alarm function). These interrupts are enabled using IT_ALARM and IT_TIMER

control bits. Periodically interrupts can be masked during the SLEEP period to avoid host interruption

and are automatically unmasked after SLEEP wakeup (using the IT_SLEEP_MASK_EN control bit).

•

Oscillator frequency calibration and time correction

Detailed Description

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32-kHz Clock

Input

Frequency

Compensation

Week

Days

32-kHz

Counter

Control

Years

Days

Months

Seconds

Minutes

Hours

Interrupt

Alarm

INT_ALARM

INT_TIMER

SWCS049-015

Figure 6-5. RTC Digital Section Block Diagram

6.9.1 Time Calendar Registers

All the time and calendar information is available in these dedicated registers, called TC registers. Values

of the TC registers are written in BCD format.

1. Years data ranges from 00 to 99

–

Leap year = Year divisible by four (2000, 2004, 2008, 2012...)

Common year = other years

2. Months data ranges from 01 to 12

3. Days value ranges from:

–

1 to 31 when months are 1, 3, 5, 7, 8, 10, 12

1 to 30 when months are 4, 6, 9, 11

1 to 29 when month is 2 and year is a leap year

1 to 28 when month is 2 and year is a common year

4. Weeks value ranges from 0 to 6

5. Hours value ranges from 00 to 23 in 24-hour mode and ranges from 1 to 12 in AM/PM mode

6. Minutes value ranges from 0 to 59

7. Seconds value ranges from 0 to 59

To modify the current time, software writes the new time into TC registers to fix the time/calendar

information. The processor can write into the TC registers without stopping the RTC. In addition, software

can stop the RTC by clearing the STOP_RTC bit of the control register and check the RUN bit of the

status to be sure that the RTC is frozen, then update the TC values, and then restart the RTC by setting

STOP_RTC bit.

Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5, previous register values are:

Table 6-4. RTC Registers Example

Register

Value

0x36

0x54

SECONDS_REG

MINUTES_REG

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Table 6-4. RTC Registers Example (continued)

Register

Value

0x90

0x05

0x09

0x08

HOURS_REG

DAYS_REG

MONTHS_REG

YEARS_REG

The user can round to the nearest minute, by setting the ROUND_30S register bit. TC values are set to

the nearest minute value at the next second. The ROUND_30S bit is automatically cleared when the

rounding time is performed.

Example:

•

If current time is 10H59M45S, a round operation changes time to 11H00M00S.

If current time is 10H59M29S, a round operation changes time to 10H59M00S.

6.9.2 General Registers

Software can access the RTC_STATUS_REG and RTC_CTRL_REG registers at any time (except for the

RTC_CTRL_REG[5] bit, which must be changed only when the RTC is stopped).

6.9.3 Compensation Registers

The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must respect the available access

period. These registers must be updated before each compensation process. For example, software can

load the compensation value into these registers after each hour event, during an available access period.

Hours

3

4

6

Seconds

58 59

0

1

2

58 59

0

1

2

Compensation event

Hours

3

4

59

0

1

Seconds

Compensation event

SWCS046-016

Figure 6-6. RTC Compensation Scheduling

Detailed Description

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This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator. Software must

calibrate the oscillator frequency, calculate the drift compensation versus 1-hour time period; and then

load the compensation registers with the drift compensation value. Indeed, if the AUTO_COMP_EN bit in

the RTC_CTRL_REG is enabled, the value of COMP_REG (in twos-complement) is added to the RTC

32-kHz counter at each hour and 1 second. When COMP_REG is added to the RTC 32-kHz counter, the

duration of the current second becomes (32768 – COMP_REG)/32768s; so, the RTC can be

compensated with a 1/32768 s/hour time unit accuracy.

NOTE

The compensation is considered once written into the registers.

6.10 Backup Battery Management

The device includes a backup battery switch connecting the VRTC regulator input to a primary battery

(VCC7) or to a backup battery (VBACKUP), depending on the voltage value of the battery.

The VRTC supply can then be maintained during a BACKUP state as long as the input voltage is high

enough (> VBNPR threshold). Below the VBNPR voltage threshold, the digital core of the device is set

under reset by internal signal Power-on Reset (POR).

The backup domain functions which are always supplied from VRTC are:

•

The internal 32-kHz oscillator

Backup registers

The backup battery can be charged from the primary battery through an embedded charger. The backup

battery charge voltage and enable is controlled through BBCH_REG register programming. This register

content is maintained during the device BACKUP state.

Hence, when enabled, the backup battery charge is maintained as long as the primary battery voltage is

higher than the VMBLO threshold and the backup battery voltage.

6.11 Backup Registers

As part of the RTC, the device contains five 8-bit registers that can be used for storage by the application

firmware when the external host is powered down. These registers retain their content as long as the

VRTC is active.

6.12 I²C Interface

A general-purpose serial control interface (CTL-I²C) allows read and write access to the configuration

registers of all resources of the system.

A second serial control interface (optional mode for EN1 and EN2 pins) can be dedicated to DVFS.

Both control interfaces are compliant with the HS-I²C specification.

These interfaces support the standard slave mode (100 Kbps), fast mode (400 Kbps), and high-speed

mode (3.4 Mbps). The general-purpose I²C module using one slave hard-coded address (ID1 = 2Dh). The

voltage scaling dedicated I²C module uses one slave hard-coded address (ID0 = 12h). The master mode

is not supported.

Addressing:

The device supports seven-bit mode addressing.

It does not support the following features:

•

10-bit addressing

General call

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6.12.1 Access Protocols

For compatibility, the I²C interfaces in the TPS65911 device use the same read/write protocol as other TI

power ICs, based on an internal register size of 8 bits. Supported transactions are described in the

following sections.

6.12.1.1 Single Byte Access

A write access is initiated by a first byte including the address of the device (7 MSBs) and a write

command (LSB), a second byte provides the address (8 bits) of the internal register, and the third byte

represents the data to be written in the internal register, see Figure 6-7.

A read access is initiated by:

•

A first byte, including the address of the device (7 MSBs) and a write command (LSB)

A second byte, providing the address (8 bits) of the internal register

A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte representing the content of the internal register (see

Figure 6-8).

DAD: Device address

S

W

R

I

T

E

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

R

A

D

7

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

S

T

O

P

A

C

K

A

C

K

A

C

K

T

A

R

T

RAD: Register address

DAT: Data

SCL

SDA

Master drives SDA

Slave drives SDA

SWCS049-020

Figure 6-7. I²C Write Access Single Byte

S

T

A

R

T

W

R

I

S

D

A

D

4

D

A

D

3

D

A

D

0

R

A

D

7

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

D

A

D

7

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

R

E

A

D

A

T

7

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

S

T

A

C

K

A

C

K

A

C

K

T

A

R

T

A

D

6

A

D

5

A

D

2

A

D

1

A

T

6

C

O

P

T

E

K

SCL

SDA

SWCS049-021

Figure 6-8. I²C Read Access Single Byte

6.12.1.2 Multiple Byte Access to Several Adjacent Registers

A write access is initiated by:

•

A first byte, including the address of the device (7 MSBs) and a write command (LSB)

A second byte, providing the base address (8 bits) of the internal registers

The following N bytes represent the data to be written in the internal register starting at the base address

and incremented by one at each data byte (see Figure 6-9).

A read access is initiated by:

•

A first byte, including the address of the device (7 MSBs) and a write command (LSB)

A second byte, providing the base address (8 bits) of the internal register

A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte, representing the content of the internal registers, starting at

the base address and next consecutive ones (see Figure 6-10).

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S

T

A

R

T

W

R

I

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

R

A

D

7

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

D

A

T

7

D

A

T

6

D

A

D

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

3

D

A

T

2

D

A

T

1

D

A

T

0

S

A

C

K

A

C

K

A

C

K

A

T

O

P

C

T

E

K

SCL

SDA

SWCS049-022

Figure 6-9. I²C Write Access Multiple Bytes

S

T

A

R

T

W

S

D

A

D

6

D

A

D

4

D

A

D

1

D

R

A

D

6

R

A

D

5

R

A

D

4

R

A

D

3

R

A

D

2

R

A

D

1

R

A

D

0

D

A

D

7

D

A

D

6

D

A

D

5

D

A

D

4

D

A

D

3

D

A

D

2

D

A

D

1

D

A

D

0

R

E

A

D

A

T

7

D

A

T

6

D

A

T

5

D

A

T

4

D

A

T

2

D

A

T

1

D

A

T

5

D

A

T

2

D

A

T

1

D

A

T

0

S

T

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

R

I

T

A

R

T

A

D

5

A

D

3

A

D

2

A

D

0

A

D

7

A

T

3

A

T

0

A

T

7

A

T

6

A

T

4

A

T

3

O

P

T

E

SCL

SDA

SWCS049-023

Figure 6-10. I²C Read Access Multiple Bytes

6.13 Thermal Monitoring and Shutdown

A thermal protection module monitors the junction temperature of the device versus two thresholds:

•

Hot-die temperature threshold

Thermal shutdown temperature threshold

When the hot-die temperature threshold is reached, an interrupt is sent to software to close the noncritical

running tasks.

When the thermal shutdown temperature threshold is reached, the TPS65911 device is set under reset

and a transition to OFF state is initiated. Then the POWER ON enable conditions of the device are not

considered until the die temperature has decreased below the hot-die threshold. Hysteresis is applied to

the hot-die and shutdown thresholds, when detecting a falling edge of temperature, and both detections

are debounced to avoid any parasitic detection.

The TPS65911 device allows programming of four hot-die temperature thresholds to increase the flexibility

of the system.

By default, the thermal protection is enabled in ACTIVE state, but can be disabled through programming

the THERM_REG register. The thermal protection can be enabled in SLEEP state programming the

SLEEP_KEEP_RES_ON register. The thermal protection is automatically enabled during an OFF-to-

ACTIVE state transition and is kept enabled in OFF state after a switch-off sequence caused by a thermal

shutdown event. Transition to OFF state sequence caused by a thermal shutdown event is highlighted in

the INT_STS_REG status register. Recovery from this OFF state is initiated (switch-on sequence) when

the die temperature falls below the hot-die temperature threshold.

Hot-die and thermal shutdown temperature threshold detection states can be monitored or masked by

reading or programming the THERM_REG register. The hot-die interrupt can be masked by programming

the INT_MSK_REG register.

6.14 Interrupts

Table 6-5 lists the interrupt sources.

Table 6-5. Interrupt Sources

INTERRUPT

DESCRIPTION

RTC alarm event: Occurs at programmed determinate date and time

(running in ACTIVE, OFF, and SLEEP state, default inactive)

RTC_ALARM_IT

RTC_PERIOD_IT

RTC periodic event: Occurs at programmed regular period of time (each second or minute)

(running in ACTIVE, OFF, and SLEEP state, default inactive)

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Table 6-5. Interrupt Sources (continued)

INTERRUPT

DESCRIPTION

The embedded thermal monitoring module has detected a die temperature above the hot-die

detection threshold (running in ACTIVE and SLEEP state).

Level sensitive interrupt.

HOT_DIE_IT

PWRHOLD_R_IT

PWRHOLD_F_IT

PWRHOLD signal rising edge

PWRHOLD signal falling-edge

PWRON is low during more than the long-press delay: PWON_TO_OFF_DELAY (can be

disabled though register programming).

PWRON_LP_IT

PWRON_IT

VMBHI_IT

PWRON is low while the device is on (running in ACTIVE and SLEEP state). Level-sensitive

interrupt.

The battery voltage rise above the VMBHI threshold: NO SUPPLY-to-OFF or BACKUP-to-

OFF device states transition (first battery plug or battery voltage bounce detection)

The battery voltage fall down below the VMBDCH threshold: the minimum operating voltage

of power supplies.

VMBDCH_IT

GPIO0_R_IT

GPIO0_F_IT

VMBCH2_H_IT

VMBCH2_L_IT

GPIO1_R_IT

GPIO1_F_IT

GPIO2_R_IT

GPIO2_F_IT

GPIO3_R_IT

GPIO3_F_IT

GPIO4_R_IT

GPIO4_F_IT

GPIO5_R_IT

GPIO5_F_IT

WTCHDG_IT

PWRDN_IT

GPIO_CKSYNC rising-edge detection

GPIO_CKSYNC falling-edge detection

Comparator 2 input above threshold detection

Comparator 2 input below threshold detection

GPIO1 rising-edge detection

GPIO1 falling-edge detection

GPIO2 rising-edge detection

GPIO2 falling-edge detection

GPIO3 rising-edge detection

GPIO3 falling-edge detection

GPIO4 rising-edge detection

GPIO4 falling-edge detection

GPIO5 rising-edge detection

GPIO5 falling-edge detection

Watchdog interrupt

PWRDN reset interrupt

6.15 Register Maps

6.15.1 Functional Registers

The possible device reset domains are:

•

Full reset: All digital logic of device is reset.

Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR

General reset: No impact on RTC, backup registers or interrupt status.

–

•

–

Caused by PWON_LP_RST bit set high or

DEV_OFF_RST bit set high or

HDRST input set high

•

Turnoff OFF: Power reinitialization in off/backup mode.

In the following register description, the reset domain for each register is defined in the register table

heading.

NOTE

DCDCCTRL_REG and DEVCTRL2_REG have bits in two reset domains.

The comment Default value: See boot configuration indicates that bit default value is set in

boot configuration and not by the register reset value.

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6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary

Table 6-6. TPS65911_FUNC_REG Register Summary⁽¹⁾

Register Name

SECONDS_REG

Type

RW

RO

Register Width (Bits)

Register Reset

0x00

0x01

0x00

0x01

0x00

0x80

0x00

0x27

0x00

0x1F

0x01

0x05

0x0D

0x33

0x0D

0x4B

0x00

0x03

0x15

0x00

0x09

0x0D

0x21

0x00

Address Offset

8

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x30

0x31

0x32

0x33

0x34

0x35

0x36

MINUTES_REG

HOURS_REG

DAYS_REG

MONTHS_REG

YEARS_REG

WEEKS_REG

ALARM_SECONDS_REG

ALARM_MINUTES_REG

ALARM_HOURS_REG

ALARM_DAYS_REG

ALARM_MONTHS_REG

ALARM_YEARS_REG

RTC_CTRL_REG

RTC_STATUS_REG

RTC_INTERRUPTS_REG

RTC_COMP_LSB_REG

RTC_COMP_MSB_REG

RTC_RES_PROG_REG

RTC_RESET_STATUS_REG

BCK1_REG

BCK2_REG

BCK3_REG

BCK4_REG

BCK5_REG

PUADEN_REG

REF_REG

VRTC_REG

RW

VIO_REG

VDD1_REG

VDD1_OP_REG

VDD1_SR_REG

VDD2_REG

VDD2_OP_REG

VDD2_SR_REG

VDDCRTL_REG

VDDCRTL_OP_REG

VDDCRTL_SR_REG

LDO1_REG

LDO2_REG

LDO5_REG

LDO8_REG

LDO7_REG

LDO6_REG

LDO4_REG

(1) Register reset values are for fixed boot mode.

66 Detailed Description

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Table 6-6. TPS65911_FUNC_REG Register Summary⁽¹⁾(continued)

Register Name

Type

RW

RO

Register Width (Bits)

Register Reset

0x00

Address Offset

0x37

0x38

0x39

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x50

0x51

0x52

0x53

0x54

0x55

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x80

LD03_REG

8

THERM_REG

0x0D

0x00

BBCH_REG

DCDCCTRL_REG

DEVCTRL_REG

DEVCTRL2_REG

SLEEP_KEEP_LDO_ON_REG

SLEEP_KEEP_RES_ON_REG

SLEEP_SET_LDO_OFF_REG

SLEEP_SET_RES_OFF_REG

EN1_LDO_ASS_REG

EN1_SMPS_ASS_REG

EN2_LDO_ASS_REG

EN2_SMPS_ASS_REG

INT_STS_REG

0x39

0x0000 0014

0x0000 0036

0x00

0x06

INT_MSK_REG

0xFF

0xA8

0xFF

0x5A

0xFF

0x07

INT_STS2_REG

INT_MSK2_REG

INT_STS3_REG

INT_MSK3_REG

GPIO0_REG

GPIO1_REG

0x08

GPIO2_REG

0x08

GPIO3_REG

0x08

GPIO4_REG

0x08

GPIO5_REG

0x08

GPIO6_REG

0x05

GPIO7_REG

0x05

GPIO8_REG

0x08

WATCHDOG_REG

VMBCH_REG

0x07

0x1E

0x00

VMBCH2_REG

LED_CTRL1_REG

LED_CTRL2_REG1

PWM_CTRL1_REG

PWM_CTRL2_REG

SPARE_REG

0x00

VERNUM_REG

0x00

Detailed Description

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6.15.1.2 TPS65911_FUNC_REG Register Descriptions

Table 6-7. SECONDS_REG

Address Offset

Instance

0x00

Reset Domain: FULL RESET

RTC register for seconds

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

SEC1

SEC0

Bits

Field Name

Description

Type

Reset

7

Reserved

Reserved bit

RO

R returns

0s

0

6:4

3:0

SEC1

SEC0

Second digit of seconds (range is 0 up to 5)

First digit of seconds (range is 0 up to 9)

RW

0x0

Table 6-8. MINUTES_REG

Address Offset

Instance

0x01

Reset Domain: FULL RESET

RTC register for minutes

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

MIN1

MIN0

Bits

Field Name

Description

Type

Reset

7

Reserved

Reserved bit

RO

R returns

0s

0

6:4

3:0

MIN1

MIN0

Second digit of minutes (range is 0 up to 5)

First digit of minutes (range is 0 up to 9)

RW

0x0

68

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Table 6-9. HOURS_REG

Address Offset

Instance

0x02

Reset Domain: FULL RESET

RTC register for hours

RW

Description

Type

7

6

5

4

3

2

1

0

PM_NAM

Reserved

HOUR1

HOUR0

Bits

Field Name

Description

Type

Reset

7

PM_NAM

Only used in PM_AM mode (otherwise it is set to 0)

RW

0

0 is AM

1 is PM

6

Reserved

Reserved bit

RO

R returns

0s

0

5:4

3:0

HOUR1

HOUR0

Second digit of hours(range is 0 up to 2)

First digit of hours (range is 0 up to 9)

RW

0x0

Table 6-10. DAYS_REG

Address Offset

Instance

0x03

Reset Domain: FULL RESET

Description

Type

RTC register for days

RW

7

6

5

4

3

2

1

0

Reserved

DAY1

DAY0

Bits

Field Name

Description

Type

Reset

7:6

Reserved

Reserved bit

RO

R returns

0s

0x0

5:4

3:0

DAY1

DAY0

Second digit of days (range is 0 up to 3)

First digit of days (range is 0 up to 9)

RW

0x0

0x1

Table 6-11. MONTHS_REG

Address Offset

Instance

0x04

Reset Domain: FULL RESET

RTC register for months

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

MONTH1

MONTH0

Bits

Field Name

Description

Type

Reset

7:5

Reserved

Reserved bit

RO

R returns

0s

0x0

4

MONTH1

MONTH0

Second digit of months (range is 0 up to 1)

First digit of months (range is 0 up to 9)

RW

0

3:0

0x1

Detailed Description

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Table 6-12. YEARS_REG

Address Offset

Instance

0x05

Reset Domain: FULL RESET

RTC register for day of the week

RW

Description

Type

7

6

5

4

3

2

1

0

YEAR1

YEAR0

Bits

7:4

Field Name

Description

Type

RW

Reset

0x0

YEAR1

YEAR0

Second digit of years (range is 0 up to 9)

First digit of years (range is 0 up to 9)

3:0

RW

0x0

Table 6-13. WEEKS_REG

Address Offset

Instance

0x06

Reset Domain: FULL RESET

RTC register for day of the week

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

WEEK

Bits

Field Name

Description

Type

Reset

7:3

Reserved

Reserved bit

RO

R returns

0s

0x00

2:0

WEEK

First digit of day of the week (range is 0 up to 6)

RW

0

Table 6-14. ALARM_SECONDS_REG

Address Offset

Instance

0x08

Reset Domain: FULL RESET

Description

Type

RTC register for alarm programmation for seconds

RW

7

6

5

4

3

2

1

0

Reserved

ALARM_SEC1

ALARM_SEC0

Bits

Field Name

Reserved

Description

Type

Reset

7

Reserved bit

RO

0

R returns

0s

6:4

3:0

ALARM_SEC1

ALARM_SEC0

Second digit of alarm programmation for seconds (range is 0 up to 5)

First digit of alarm programmation for seconds (range is 0 up to 9)

RW

0x0

70

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Table 6-15. ALARM_MINUTES_REG

Address Offset

Instance

0x09

Reset Domain: FULL RESET

Description

Type

RTC register for alarm programmation for minutes

RW

7

6

5

4

3

2

1

0

Reserved

ALARM_MIN1

ALARM_MIN0

Bits

Field Name

Reserved

Description

Type

Reset

7

Reserved bit

RO

0

R returns

0s

6:4

3:0

ALARM_MIN1

ALARM_MIN0

Second digit of alarm programmation for minutes (range is 0 up to 5)

First digit of alarm programmation for minutes (range is 0 up to 9)

RW

0x0

Table 6-16. ALARM_HOURS_REG

Address Offset

Instance

0x0A

Reset Domain: FULL RESET

Description

Type

RTC register for alarm programmation for hours

RW

7

6

5

4

3

2

1

0

ALARM_PM_N

AM

Reserved

ALARM_HOUR1

ALARM_HOUR0

Bits

Field Name

ALARM_PM_

Description

Type

Reset

7

Only used in PM_AM mode for alarm programmation (otherwise it is set

RW

0

NAM

to 0)

0 is AM

1 is PM

6

Reserved

Reserved bit

RO

R returns

0s

0

5:4

3:0

ALARM_HOUR1

ALARM_HOUR0

Second digit of alarm programmation for hours(range is 0 up to 2)

First digit of alarm programmation for hours (range is 0 up to 9)

RW

0x0

Table 6-17. ALARM_DAYS_REG

Address Offset

Instance

0x0B

Reset Domain: FULL RESET

Description

Type

RTC register for alarm programmation for days

RW

7

6

5

4

3

2

1

0

Reserved

ALARM_DAY1

ALARM_DAY0

Bits

Field Name

Description

Type

Reset

7:6

Reserved

Reserved bit

RO

0x0

R Special

5:4

3:0

ALARM_DAY1

ALARM_DAY0

Second digit of alarm programmation for days (range is 0 up to 3)

First digit of alarm programmation for days (range is 0 up to 9)

RW

0x0

0x1

Detailed Description

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Table 6-18. ALARM_MONTHS_REG

Address Offset

Instance

0x0C

Reset Domain: FULL RESET

Description

Type

RTC register for alarm programmation for months

RW

7

6

5

4

3

2

1

0

ALARM_

MONTH1

Reserved

ALARM_MONTH0

Bits

Field Name

Reserved

Description

Type

Reset

7:5

Reserved bit

RO

R returns

0s

0x0

4

ALARM_MONTH1

ALARM_MONTH0

Second digit of alarm programmation for months (range is 0 up to 1)

First digit of alarm programmation for months (range is 0 up to 9)

RW

0

3:0

0x1

Table 6-19. ALARM_YEARS_REG

Address Offset

Instance

0x0D

Reset Domain: FULL RESET

Description

Type

RTC register for alarm programmation for years

RW

7

6

5

4

3

2

1

0

ALARM_YEAR1

ALARM_YEAR0

Bits

7:4

Field Name

Description

Type

RW

Reset

0x0

ALARM_YEAR1

ALARM_YEAR0

Second digit of alarm programmation for years (range is 0 up to 9)

First digit of alarm programmation for years (range is 0 up to 9)

3:0

RW

0x0

72

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Table 6-20. RTC_CTRL_REG

Address Offset

Instance

0x10

Reset Domain: FULL RESET

RTC control register:

Description

NOTES: A dummy read of this register is necessary before each I²C read in order to update the ROUND_30S bit

value.

Type

RW

7

6

5

4

3

2

1

0

SET_32_

COUNTER

RTC_V_OPT

GET_TIME

TEST_MODE

MODE_12_24

AUTO_COMP

ROUND_30S

STOP_RTC

Bits

Field Name

RTC_V_OPT

Description

Type

Reset

7

RTC date/time register selection:

RW

0

0: Read access directly to dynamic registers (SECONDS_REG,

MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG,

YEAR_REG, WEEKS_REG)

1: Read access to static shadowed registers: (see GET_TIME bit).

6

GET_TIME

When writing a 1 into this register, the content of the dynamic registers

(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG,

MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into

RW

0

static shadowed registers. Each update of the shadowed registers needs

to be done by re-asserting GET_TIME bit to 1 (that is: reset it to 0 and

then rewrite it to 1)

5

4

3

SET_32_COUNTER

TEST_MODE

0: No action

RW

0

1: set the 32-kHz counter with COMP_REG value.

It must only be used when the RTC is frozen.

0: functional mode

1: test mode (Auto compensation is enable when the 32-kHz counter

reaches at its end)

MODE_12_24

0: 24 hours mode

1: 12 hours mode (PM-AM mode)

It is possible to switch between the two modes at any time without

disturbed the RTC, read or write are always performed with the current

mode.

2

1

AUTO_COMP

ROUND_30S

0: No auto compensation

1: Auto compensation enabled

RW

0

0: No update

1: When a one is written, the time is rounded to the nearest minute.

This bit is a toggle bit, the microcontroller can only write one and RTC

clears it. If the microcontroller sets the ROUND_30S bit and then reads

it, the microcontroller will read one until rounded to the nearest value.

0

STOP_RTC

0: RTC is frozen

1: RTC is running

RW

0

Detailed Description

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Table 6-21. RTC_STATUS_REG

Address Offset

Instance

0x11

Reset Domain: FULL RESET

RTC status register:

Description

NOTES: A dummy read of this register is necessary before each I²C read in order to update the status register

value.

Type

RW

7

6

5

4

3

2

1

0

POWER_UP

ALARM

EVENT_1D

EVENT_1H

EVENT_1M

EVENT_1S

RUN

Reserved

Bits

Field Name

POWER_UP

Description

Type

Reset

7

Indicates that a reset occurred (bit cleared to 0 by writing 1).

POWER_UP is set by a reset, is cleared by writing one in this bit.

RW

1

6

ALARM

Indicates that an alarm interrupt has been generated (bit clear by writing

1).

RW

0

The alarm interrupt keeps its low level, until the microcontroller write 1 in

the ALARM bit of the RTC_STATUS_REG register.

The timer interrupt is a low-level pulse (15 µs duration).

5

4

3

2

1

EVENT_1D

EVENT_1H

EVENT_1M

EVENT_1S

RUN

One day has occurred

One hour has occurred

One minute has occurred

One second has occurred

RO

0

0: RTC is frozen

1: RTC is running

This bit shows the real state of the RTC, indeed because of STOP_RTC

signal was resynchronized on 32-kHz clock, the action of this bit is

delayed.

0

Reserved

Reserved bit

RO

R returns

0s

0

74

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Table 6-22. RTC_INTERRUPTS_REG

Address Offset

Instance

0x12

Reset Domain: FULL RESET

RTC interrupt control register

RW

Description

Type

7

6

5

4

3

2

1

0

IT_SLEEP_

MASK_EN

Reserved

IT_ALARM

IT_TIMER

EVERY

Bits

Field Name

Reserved

Description

Type

Reset

7:5

Reserved bit

RO

0x0

R returns

0s

4

IT_SLEEP_MASK_E 1: Mask periodic interrupt while the TPS65911 device is in SLEEP mode.

RW

0

N

Interrupt event is back up in a register and occurred as soon as the

TPS65911 device is no more in SLEEP mode.

0: Normal mode, no interrupt masked

3

2

IT_ALARM

IT_TIMER

Enable one interrupt when the alarm value is reached (TC ALARM

registers) by the TC registers

RW

0

Enable periodic interrupt

0: interrupt disabled

1: interrupt enabled

1:0

EVERY

Interrupt period

00: each second

01: each minute

10: each hour

11: each day

RW

0x0

Table 6-23. RTC_COMP_LSB_REG

Address Offset

Instance

0x13

Reset Domain: FULL RESET

Description

RTC compensation register (LSB)

Notes: This register must be written in 2-complement.

This means that to add one 32-kHz oscillator period each hour, microcontroller needs to write FFFF into

RTC_COMP_MSB_REG and RTC_COMP_LSB_REG.

To remove one 32-kHz oscillator period each hour, microcontroller needs to write 0001 into

RTC_COMP_MSB_REG and RTC_COMP_LSB_REG.

The 7FFF value is forbidden.

Type

RW

7

6

5

4

3

2

1

0

RTC_COMP_LSB

Bits

Field Name

Description

Type

Reset

7:0

RTC_COMP_LSB

This register contains the number of 32-kHz periods to be added into the

32-kHz counter each hour [LSB]

RW

0x00

Detailed Description

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Table 6-24. RTC_COMP_MSB_REG

Address Offset

Instance

0x14

Reset Domain: FULL RESET

Description

RTC compensation register (MSB)

Notes: See RTC_COMP_LSB_REG Notes.

Type

RW

7

6

5

4

3

2

1

0

RTC_COMP_MSB

Bits

Field Name

Description

Type

Reset

7:0

RTC_COMP_MSB

This register contains the number of 32-kHz periods to be added into the

32-kHz counter each hour [MSB]

RW

0x00

Table 6-25. RTC_RES_PROG_REG

Address Offset

Instance

0x15

Reset Domain: FULL RESET

Description

Type

RTC register containing oscillator resistance value

RW

7

6

5

4

3

2

1

0

Reserved

SW_RES_PROG

Bits

Field Name

Description

Type

Reset

7:6

Reserved

Reserved bit

RO

R returns

0s

0x0

5:0

SW_RES_PROG

Value of the oscillator resistance

RW

0x27

Table 6-26. RTC_RESET_STATUS_REG

Address Offset

Instance

0x16

Reset Domain: FULL RESET

RTC register for reset status

RW

Description

Type

7

6

5

4

3

2

1

0

RESET_

STATUS

Reserved

Bits

Field Name

Reserved

Description

Type

Reset

7:1

Reserved bit

RO

R returns

0s

0x0

0

RESET_STATUS

This bit can only be set to one and is cleared when a manual reset or a

POR (VBAT < 2.1) occurs. If this bit is reset it means that the RTC has

lost its configuration.

RW

0

76

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Table 6-27. BCK1_REG

Address Offset

Instance

0x17

Reset Domain: FULL RESET

Description

Backup register which can be used for storage by the application firmware when the external host is powered down.

These registers will retain their content as long as the VRTC is active.

Type

RW

7

6

5

4

3

2

1

0

BCKUP

Bits

Field Name

BCKUP

Description

Type

Reset

7:0

Backup bit

RW

0x00

Table 6-28. BCK2_REG

Address Offset

Instance

0x18

Reset Domain: FULL RESET

Description

Backup register which can be used for storage by the application firmware when the external host is powered down.

These registers will retain their content as long as the VRTC is active.

Type

RW

7

6

5

4

3

2

1

0

BCKUP

Bits

Field Name

BCKUP

Description

Type

Reset

7:0

Backup bit

RW

0x00

Table 6-29. BCK3_REG

Address Offset

Instance

0x19

Reset Domain: FULL RESET

Description

Backup register which can be used for storage by the application firmware when the external host is powered down.

These registers will retain their content as long as the VRTC is active.

Type

RW

7

6

5

4

3

2

1

0

BCKUP

Bits

Field Name

BCKUP

Description

Type

Reset

7:0

Backup bit

RW

0x00

Detailed Description

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Table 6-30. BCK4_REG

Address Offset

Instance

0x1A

Reset Domain: FULL RESET

Description

Backup register which can be used for storage by the application firmware when the external host is powered down.

These registers will retain their content as long as the VRTC is active.

Type

RW

7

6

5

4

3

2

1

0

BCKUP

Bits

Field Name

BCKUP

Description

Type

Reset

7:0

Backup bit

RW

0x00

Table 6-31. BCK5_REG

Address Offset

Instance

0x1B

Reset Domain: FULL RESET

Description

Backup register which can be used for storage by the application firmware when the external host is powered down.

These registers will retain their content as long as the VRTC is active.

Type

RW

7

6

5

4

3

2

1

0

BCKUP

Bits

Field Name

BCKUP

Description

Type

Reset

7:0

Backup bit

RW

0x00

78

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Table 6-32. PUADEN_REG

Address Offset

Instance

0x1C

Reset Domain: GENERAL RESET

Pullup/pulldown control register.

RW

Description

Type

7

6

5

4

3

2

1

0

NRESPWRON

2P

Reserved

I2CCTLP

I2CSRP

PWRONP

SLEEPP

PWRHOLDP

HDRSTP

Bits

7

Field Name

Description

Type

RO

Reset

Reserved

I2CCTLP

0

6

SDACTL and SCLCTL pullup control:

1: Pullup is enabled

RW

0: Pullup is disabled

5

4

3

2

1

0

I2CSRP

SDASR and SCLSR pullup control:

1: Pullup is enabled

0: Pullup is disabled

RW

0

1

PWRONP

SLEEPP

PWRON pad pullup control:

1: Pullup is enabled

0: Pullup is disabled

SLEEP pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

PWRHOLDP

HDRSTP

PWRHOLD pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

HDRST pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

NRESPWRON2P

NRESPWRON2 pad control:

1: Pulldown is enabled

0: Pulldown is disabled

Table 6-33. REF_REG

Address Offset

Instance

0x1D

Reset Domain: TURNOFF OFF RESET

Description

Type

Reference control register

RO

7

6

5

4

3

2

1

0

Reserved

ST

Bits

Field Name

Description

Type

Reset

7:2

Reserved

Reserved bit

RO

R returns

0s

0x00

1:0

ST

Reference state:

ST[1:0] = 00: Off

RO

0x1

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Reserved

ST[1:0] = 11: On low power (SLEEP)

(Write access available in test mode only)

Detailed Description

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Table 6-34. VRTC_REG

Address Offset

Instance

0x1E

Reset Domain: GENERAL RESET

Description

Type

VRTC internal regulator control register

RW

7

6

5

4

3

2

1

0

VRTC_

OFFMASK

Reserved

ST

Bits

Field Name

Reserved

Description

Type

Reset

7:4

Reserved bit

RO

R returns

0s

0x0

3

VRTC_OFFMASK

VRTC internal regulator off mask signal:

RW

0

when 1, the regulator keeps its full-load capability during device OFF

state.

when 0, the regulator will go to low-power mode during device OFF

state.

Note that VRTC is put in low-power mode when the device is on backup

even if this bit is set to 1

(Default value: See boot configuration)

2

Reserved

ST

Reserved bit

RO

R returns

0s

0

1:0

Reference state:

RO

0x1

ST[1:0] = 00: Reserved

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Reserved

ST[1:0] = 11: On low power (SLEEP)

(Write access available in test mode only)

80

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Table 6-35. VIO_REG

Address Offset

Instance

0x20

Reset Domain: TURNOFF OFF RESET

Description

Type

VIO control register

RW

7

6

5

4

3

2

1

0

ILMAX

Reserved

SEL

ST

Bits

Field Name

Description

Type

Reset

7:6

ILMAX

Select maximum load current:

when 00: 0.6 A

RW

0x0

when 01: 1.0 A

when 10: 1.3 A

when 11: 1.3 A

5:4

3:2

Reserved

SEL

Reserved bit

RO

R returns

0s

0x0

Output voltage selection (EEPROM bits):

SEL[1:0] = 00: 1.5 V

RW

SEL[1:0] = 01: 1.8 V

SEL[1:0] = 10: 2.5 V

SEL[1:0] = 11: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Detailed Description

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Table 6-36. VDD1_REG

Address Offset

Instance

0x21

Reset Domain: TURNOFF OFF RESET

Description

Type

VDD1 control register

RW

7

6

5

4

3

2

1

0

VGAIN_SEL

ILMAX

TSTEP

ST

Bits

Field Name

Description

Type

Reset

7:6

VGAIN_SEL

Select output voltage multiplication factor: G (EEPROM bits):

RW

0x0

when 00: ×1

when 01: ×1

when 10: ×2

when 11: ×3

(Default value: See boot configuration)

5

ILMAX

TSTEP

Select maximum load current:

when 0: 1.0 A

when 1: > 1.5 A

RW

0

4:2

Time step: when changing the output voltage, the new value is reached

through successive 12.5-mV voltage steps (if not bypassed). The

equivalent programmable slew rate of the output voltage is then:

TSTEP[2:0] = 000: step duration is 0, step function is bypassed

TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)

0x3

TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)

TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)

TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)

TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)

TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)

TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On, high-power mode

ST[1:0] = 10: Off

ST[1:0] = 11: On, low-power mode

82

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Table 6-37. VDD1_OP_REG

Address Offset

Instance

0x22

Reset Domain: TURNOFF OFF RESET

VDD1 voltage selection register.

Description

This register can be accessed by both control and voltage scaling I²C interfaces depending on SR_CTL_I2C_SEL

register bit value.

Type

RW

7

6

5

4

3

2

1

0

CMD

SEL

Bits

Field Name

Description

Type

Reset

7

CMD

when 0: VDD1_OP_REG voltage is applied

when 1: VDD1_SR_REG voltage is applied

RW

0

6:0

SEL

Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

12.5 mV per LSB):

RW

0x00

SEL[6:0] = 1001011 to 1111111: 1.5 V

...

SEL[6:0] = 0111111: 1.35 V

...

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0000001 to 0000011: 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G

(Default value: See boot configuration)

Note: Vout maximum value is 3.3 V

Table 6-38. VDD1_SR_REG

Address Offset

Instance

0x23

Reset Domain: TURNOFF OFF RESET

VDD1 voltage selection register.

Description

This register can be accessed by both control and voltage scaling dedicated I²C interfaces depending on

SR_CTL_I2C_SEL register bit value.

Type

RW

7

6

5

4

3

2

1

0

Reserved

SEL

Bits

Field Name

Description

Type

Reset

7

Reserved

Reserved bit

RO

R returns

0s

0

6:0

SEL

Output voltage selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111: 1.5 V

...

RW

0x00

SEL[6:0] = 0111111: 1.35 V

...

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0000001 to 0000011: 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G

(Default value: See boot configuration)

Note: Vout maximum value is 3.3 V

Detailed Description

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Table 6-39. VDD2_REG

Address Offset

Instance

0x24

Reset Domain: TURNOFF OFF RESET

Description

Type

VDD2 control register

RW

7

6

5

4

3

2

1

0

VGAIN_SEL

ILMAX

TSTEP

ST

Bits

Field Name

Description

Type

Reset

7:6

VGAIN_SEL

Select output voltage multiplication factor (×1, ×3 included in EEPROM

RW

0x0

bits): G

when 00: ×1

when 01: ×1

when 10: ×2

when 11: ×3

5

ILMAX

TSTEP

Select maximum load current:

when 0: 1.0 A

when 1: > 1.5 A

RW

0

4:2

Time step: when changing the output voltage, the new value is reached

through successive 12.5-mV voltage steps (if not bypassed). The

equivalent programmable slew rate of the output voltage is then:

TSTEP[2:0] = 000: step duration is 0, step function is bypassed

TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)

0x1

TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)

TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)

TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)

TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)

TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)

TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On, high-power mode

ST[1:0] = 10: Off

ST[1:0] = 11: On, low-power mode

84

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Table 6-40. VDD2_OP_REG

Address Offset

Instance

0x25

Reset Domain: TURNOFF OFF RESET

VDD2 voltage selection register.

Description

This register can be accessed by both control and voltage scaling dedicated I²C interfaces depending on

SR_CTL_I2C_SEL register bit value.

Type

RW

7

6

5

4

3

2

1

0

CMD

SEL

Bits

Field Name

Description

Type

Reset

7

CMD

Command:

RW

0

when 0: VDD2_OP_REG voltage is applied

when 1: VDD2_SR_REG voltage is applied

6:0

SEL

Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

RW

0x00

12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111: 1.5 V

...

SEL[6:0] = 0111111: 1.35 V

...

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0000001 to 0000011: 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G

Note: Vout maximum value is 3.3 V

Table 6-41. VDD2_SR_REG

Address Offset

Instance

0x26

Reset Domain: TURNOFF OFF RESET

VDD2 voltage selection register.

Description

This register can be accessed by both control and voltage scaling dedicated I²C interfaces depending on

SR_CTL_I2C_SEL register bit value.

Type

RW

7

6

5

4

3

2

1

0

Reserved

SEL

Bits

Field Name

Description

Type

Reset

7

Reserved

Reserved bit

RO

R returns

0s

0

6:0

SEL

Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

12.5 mV per LSB):

RW

0x00

SEL[6:0] = 1001011 to 1111111: 1.5 V

...

SEL[6:0] = 0111111: 1.35 V

...

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0000001 to 0000011: 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G

Note: Vout maximum value is 3.3 V

Detailed Description

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Table 6-42. VDDCRTL_REG

Address Offset

Instance

0x27

Reset Domain: TURNOFF OFF RESET

VDDCtrl, external FET controller

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

ST

Bits

Field Name

Description

Type

Reset

7:2

Reserved

Reserved bit

RO

R returns

0s

0x00

1:0

ST

Supply state (EEPROM dependent):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On

ST[1:0] = 10: Off

ST[1:0] = 11: On

Table 6-43. VDDCRTL_OP_REG

Address Offset

Instance

0x28

Reset Domain: TURN OFF RESET

VDDCtrl voltage selection register.

Description

This register can be accessed by both control and voltage scaling dedicated I²C interfaces depending on

SR_CTL_I2C_SEL register bit value.

Type

RW

7

6

5

4

3

2

1

0

CMD

SEL

Bits

Field Name

Description

Type

Reset

7

CMD

Command:

RW

0

when 0: VDDctrl_OP_REG voltage is applied

when 1: VDDctrl_SR_REG voltage is applied

6:0

SEL

Output voltage (4 EEPROM bits) selection:

SEL[6:0] = 1000011 to 1111111: 1.4 V

...

RW

0x00

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0010011: 0.8 V

...

SEL[6:0] = 0000001: 0000011 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 64 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V)

(Default value: See boot configuration)

86

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Table 6-44. VDDCRTL_SR_REG

Address Offset

Instance

0x29

Reset Domain: TURN OFF RESET

VDDCtrl voltage selection register.

Description

This register can be accessed by both control and voltage scaling dedicated I²C interfaces depending on

SR_CTL_I2C_SEL register bit value.

Type

RW

7

6

5

4

3

2

1

0

Reserved

SEL

Bits

7

Field Name

Description

Type

RO

Reset

0

Reserved

SEL

6:0

Output voltage (4 EEPROM bits) selection:

SEL[6:0] = 1000011 to 1111111: 1.4 V

...

RW

0x03

SEL[6:0] = 0110011: 1.2 V

...

SEL[6:0] = 0010011: 0.8 V

...

SEL[6:0] = 0000001: 0000011: 0.6 V

SEL[6:0] = 0000000: Off (0.0 V)

Note: from SEL[6:0] = 3 to 64 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 V)

(Default value: See boot configuration)

Table 6-45. LDO1_REG

Address Offset

Instance

0x30

Reset Domain: TURNOFF OFF RESET

LDO1 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

SEL

ST

Bits

Field Name

SEL

Description

Type

Reset

7:2

Supply voltage (EEPROM bits):

RW

0x0

SEL[7:2] = 000000 to 000011: 1 V

SEL[7:2] = 000100: 1 V

SEL[7:2] = 000101: 1.05 V

...

SEL[7:2] = 110001: 3.25 V

SEL[7:2] = 110010: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Detailed Description

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Table 6-46. LDO2_REG

Address Offset

Instance

0x31

Reset Domain: TURNOFF OFF RESET

LDO2 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

SEL

ST

Bits

Field Name

SEL

Description

Type

Reset

7:2

Supply voltage (EEPROM bits):

SEL[7:2] = 000000 to 000011: 1 V

SEL[7:2] = 000100: 1 V

RW

0x0

SEL[7:2] = 000101: 1.05 V

...

SEL[7:2] = 110001: 3.25 V

SEL[7:2] = 110010: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Table 6-47. LDO5_REG

Address Offset

Instance

0x32

Reset Domain: TUROFF RESET

LDO5 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

SEL

ST

Bits

Field Name

Description

Type

Reset

7

Reserved

RO

R returns

0s

0

6:2

SEL

Supply voltage (EEPROM bits):

SEL[6:2] = 00000 to 00010: 1 V

SEL[6:2] = 00011: 1.1 V

...

RW

0x00

SEL[6:2] = 11000: 3.2 V

SEL[6:2] = 11001: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

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Table 6-48. LDO8_REG

Address Offset

Instance

0x33

Reset Domain: TURNOFF OFF RESET

LDO8 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

SEL

ST

Bits

Field Name

Description

Type

Reset

7

Reserved

RO

R returns

0s

0

6:2

SEL

Supply voltage (EEPROM bits):

SEL[6:2] = 00000 to 00010: 1 V

SEL[6:2] = 00011: 1.1 V

...

RW

0x00

SEL[6:2] = 11000: 3.2 V

SEL[6:2] = 11001: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Table 6-49. LDO7_REG

Address Offset

Instance

0x34

Reset Domain: TURNOFF OFF RESET

LDO7 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

SEL

ST

Bits

Field Name

Description

Type

Reset

7

Reserved

RO

R returns

0s

0

6:2

SEL

Supply voltage (EEPROM bits):

SEL[6:2] = 00000 to 00010: 1 V

SEL[6:2] = 00011: 1.1 V

...

RW

0x00

SEL[6:2] = 11000: 3.2 V

SEL[6:2] = 11001: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Detailed Description

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Table 6-50. LDO6_REG

Address Offset

Instance

0x35

Reset Domain: TURNOFF OFF RESET

LDO6 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

SEL

ST

Bits

Field Name

Description

Type

Reset

7

Reserved

RO

R returns

0s

0

6:2

SEL

Supply voltage (EEPROM bits):

SEL[6:2] = 00000 to 00010: 1 V

SEL[6:2] = 00011: 1.1 V

...

RW

0x00

SEL[6:2] = 11000: 3.2 V

SEL[6:2] = 11001: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Table 6-51. LDO4_REG

Address Offset

Instance

0x36

Reset Domain: TURNOFF OFF RESET

LDO4 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

SEL

ST

Bits

Field Name

SEL

Description

Type

Reset

7:2

Supply voltage (EEPROM bits):

RW

0x00

SEL[7:2] = 000000: 0.8 V

SEL[7:2] = 000001: 0.85 V

SEL[7:2] = 000010: 0.9 V

SEL[7:2] = 000011: 0.95 V

SEL[7:2] = 000100: 1 V

SEL[7:2] = 000101: 1.05 V

...

SEL[7:2] = 110001: 3.25 V

SEL[7:2] = 110010: 3.3 V

Applicable voltage selection

TRACK LDO 0: 1 V to 3.3 V

TRACK LDO 1: 0.8 V to 1.5 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

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Table 6-52. LDO3_REG

Address Offset

Instance

0x37

Reset Domain: TURNOFF OFF RESET

LDO3 regulator control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

SEL

ST

Bits

Field Name

Description

Type

Reset

7

Reserved

RO

R returns

0s

0

6:2

SEL

Supply voltage (EEPROM bits):

SEL[6:2] = 00000: 1 V

SEL[6:2] = 00001: 1 V

SEL[6:2] = 00010: 1 V

SEL[6:2] = 00011: 1.1 V

...

RW

0x00

SEL[6:2] = 11000: 3.2 V

SEL[6:2] = 11001: 3.3 V

(Default value: See boot configuration)

1:0

ST

Supply state (EEPROM bits):

ST[1:0] = 00: Off

RW

0x0

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

Detailed Description

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Table 6-53. Therm_REG

Address Offset

Instance

0x38

Reset Domain:

bits[5:2]: GENERAL RESET

bit[0]: TURNOFF OFF RESET

Description

Type

Thermal control register

RW

7

6

5

4

3

2

1

0

THERM_

STATE

Reserved

THERM_HD

THERM_TS

THERM_HDSEL

Reserved

Bits

Field Name

Description

Type

Reset

7:6

Reserved

Reserved bit

RO

R returns

0s

0x0

5

4

THERM_HD

THERM_TS

Hot die detector output:

when 0: the hot die threshold is not reached

when 1: the hot die threshold is reached

RO

RW

0

Thermal shutdown detector output:

when 0: the thermal shutdown threshold is not reached

when 1: the thermal shutdown threshold is reached

3:2

THERM_HDSEL

Temperature selection for hot die detector:

when 00: Low temperature threshold

…

0x3

when 11: High temperature threshold

1

0

Reserved

RO

R returns

0s

0

1

THERM_STATE

Thermal shutdown module enable signal:

when 0: thermal shutdown module is disable

when 1: thermal shutdown module is enable

RW

Table 6-54. BBCH_REG

Address Offset

Instance

0x39

Reset Domain: GENERAL RESET

Backup battery charger control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

BBSEL

BBCHEN

Bits

Field Name

Description

Type

Reset

7:3

Reserved

Reserved bit

RO

R returns

0s

0x00

2:1

0

BBSEL

Back up battery charge voltage selection:

BBSEL[1:0] = 00: 3.0 V

BBSEL[1:0] = 01: 2.52 V

BBSEL[1:0] = 10: 3.15 V

BBSEL[1:0] = 11: VBAT

RW

0x0

0

BBCHEN

Back up battery charge enable

RW

92

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Table 6-55. DCDCCTRL_REG

Address Offset

Instance

0x3E

RESET DOMAIN:

bits [7:3]: TURNOFF OFF RESET

bits [2:0]: GENERAL RESET

Description

Type

DCDC control register

RW

7

6

5

4

3

2

1

0

Reserved

TRACK

VDD2_PSKIP

VDD1_PSKIP

VIO_PSKIP

DCDCCKEXT

DCDCCKSYNC

Bits

Field Name

Description

Type

Reset

7

Reserved

Reserved bit

RO

R returns

0s

0

6

TRACK

0 = Normal LDO operation without tracking

RW

0

1 = Tracking mode: LDO4 output follows VDD1 setting when VDD1

active. See Section 6.5.3.14 for more information.

5

4

3

2

VDD2_PSKIP

VDD1_PSKIP

VIO_PSKIP

VDD2 pulse skip mode enable (EEPROM bit)

Default value: See boot configuration

RW

1

0

VDD1 pulse skip mode enable (EEPROM bit)

Default value: See boot configuration

VIO pulse skip mode enable (EEPROM bit)

Default value: See boot configuration

DCDCCKEXT

This signal control the muxing of the GPIO2 pad:

When 0: this pad is a GPIO

When 1: this pad is used as input for an external clock used for the

synchronisation of the DCDCs

1:0

DCDCCKSYNC

DCDC clock configuration:

RW

0x1

DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks

DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift

DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks

DCDCCKSYNC[1:0] = 11: DCDC synchronous clock

Detailed Description

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Table 6-56. DEVCTRL_REG

Address Offset

Instance

0x3F

Reset Domain: GENERAL RESET

Bit 0,1, and 3: TURN OFF RESET

Description

Type

Device control register

RW

7

6

5

4

3

2

1

0

PWR_OFF_

SEQ

SR_CTL_I2C_

SEL

DEV_OFF_

RST

RTC_PWDN

CK32K_CTRL

DEV_ON

DEV_SLP

DEV_OFF

Bits

Field Name

PWR_OFF_SEQ

Description

Type

Reset

7

When 1, power-off will be sequential, reverse of power-on sequence (first

resource to power on will be the last to power off).

RW

0

When 0, all resources disabled at the same time

6

5

RTC_PWDN

When 1, disable the RTC digital domain (clock gating and reset of RTC

registers and logic).

This register bit is not reset in BACKUP state.

RW

0

CK32K_CTRL

Internal 32-kHz clock source control bit (EEPROM bit):

when 0, the internal 32-kHz clock source is the crystal oscillator or an

external 32-kHz clock in case the crystal oscillator is used in bypass

mode

when 1, the internal 32-kHz clock source is the RC oscillator.

4

SR_CTL_I2C_SEL

Voltage scaling registers access control bit:

RW

1

when 0: access to registers by voltage scaling I²C

when 1: access to registers by control I²C. The voltage scaling registers

are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG,

VDD2_SR_REG, VDDCtrl_OP_REG, and VDDCtrl_SR_REG.

3

2

DEV_OFF_RST

DEV_ON

Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state

transition (switch-off event) and activate reset of the digital core.

This bit is cleared in OFF state.

RW

0

Write 1 will keep the device on (ACTIVE or SLEEP device state) (if

DEV_OFF = 0 and DEV_OFF_RST = 0).

EEPROM bit

(Default value: See boot configuration)

1

0

DEV_SLP

DEV_OFF

Write 1 allows SLEEP device state (if DEV_OFF = 0 and

DEV_OFF_RST = 0).

Write 0 will start an SLEEP-to-ACTIVE device state transition (wake-up

event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in

OFF state.

RW

0

Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state

transition (switch-off event). This bit is cleared in OFF state.

94

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Table 6-57. DEVCTRL2_REG

Address Offset

Instance

0x40

Reset Domain: GENERAL RESET

TSLOT_LENGTH: TURN OFF RESET

Description

Type

Device control register

RW

7

6

5

4

3

2

1

0

DCDC_SLEEP

_LVL

SLEEPSIG_

POL

PWON_LP_

OFF

PWON_LP_

RST

Reserved

TSLOT_LENGTH

IT_POL

Bits

Field Name

Reserved

Description

Type

Reset

7

RO

R returns

0s

0

6

DCDC_SLEEP_LVL

TSLOT_LENGTH

When 1, DCDC output level in SLEEP mode is VDDx_SR_REG, to be

other than 0 V.

When 0, no effect

RW

0

5:4

Time slot duration programming (EEPROM bit):

When 00: 0 µs

RW

0x3

When 01: 200 µs

When 10: 500 µs

When 11: 2 ms

(Default value: See boot configuration)

3

2

SLEEPSIG_POL

PWON_LP_OFF

When 1, SLEEP signal active-high

When 0, SLEEP signal active-low

RW

0

1

When 1, allows device turnoff after a PWON Long Press (signal low)

(EEPROM bits).

(Default value: See boot configuration)

1

0

PWON_LP_RST

IT_POL

When 1, allows digital core reset when the device is OFF (EEPROM bit).

(Default value: See boot configuration)

RW

0

INT1 interrupt pad polarity control signal (EEPROM bit):

When 0, active low

When 1, active high

(Default value: See boot configuration)

Detailed Description

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Table 6-58. SLEEP_KEEP_LDO_ON_REG

Address Offset

Instance

0x41

Reset Domain: GENERAL RESET

Description

When corresponding control bit = 0 in EN1_ LDO_ASS register (default setting): Configuration Register keeping the

full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.

When control bit = 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.

When control bit = 0, the LDO regulator is set or stay in low-power mode during device SLEEP state(but then

supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO regulator is off.

When corresponding control bit = 1 in EN1_ LDO_ASS register: Configuration Register setting the LDO regulator

state driven by SCLSR_EN1 signal low level (when SCLSR_EN1 is high the regulator is on, full power):

- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)

- the regulator is set in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register

Type

RW

7

6

5

4

3

2

1

0

LDO3_

KEEPON

LDO4_

KEEPON

LDO7_KEEPO

N

LDO8_

KEEPON

LDO5_KEEPO

N

LDO2_

KEEPON

LDO1_

KEEPON

LDO6_

KEEPON

Bits

Field Name

LDO3_KEEPON

Description

Type

Reset

7

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

RW

0

6

5

4

3

2

1

0

LDO4_KEEPON

LDO7_KEEPON

LDO8_KEEPON

LDO5_KEEPON

LDO2_KEEPON

LDO1_KEEPON

LDO6_KEEPON

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

RW

0

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

Setting supply state during device SLEEP state or when SCLSR_EN1 is

low

96

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Table 6-59. SLEEP_KEEP_RES_ON_REG

Address Offset

Instance

0x42

Description

Configuration Register keeping, during the SLEEP state of the device (but then supply state can be overwritten

programming ST[1:0]):

- the full load capability of LDO regulator (ACTIVE mode),

- The PWM mode of DCDC converter

- 32-kHz clock output

- Register access though I²C interface (keeping the internal high speed clock on)

- Die Thermal monitoring on

Control bit value has no effect if the resource is off.

Type

RW

7

6

5

4

3

2

1

0

THERM_

KEEPON

CLKOUT32K_

KEEPON

VRTC_

KEEPON

I2CHS_

KEEPON

VDD2_

KEEPON

VDD1_

KEEPON

VIO_

KEEPON

Reserved

Bits

Field Name

Description

Type

Reset

7

THERM_KEEPON

When 1, thermal monitoring is maintained during device SLEEP state.

When 0, thermal monitoring is turned off during device SLEEP state.

RW

0

6

5

CLKOUT32K_KEEPO When 1, CLK32KOUT output is maintained during device SLEEP state.

RW

0

N

When 0, CLK32KOUT output is set low during device SLEEP state.

VRTC_KEEPON

When 1, LDO regulator full load capability (ACTIVE mode) is maintained

during device SLEEP state.

When 0, the LDO regulator is set or stays in low-power mode during

device SLEEP state.

4

I2CHS_KEEPON

When 1, high speed internal clock is maintained during device SLEEP

RW

0

state.

When 0, high speed internal clock is turned off during device SLEEP

state.

3

2

Reserved

RO

0

VDD2_KEEPON

When 1, VDD2 SMPS PWM mode is maintained during device SLEEP

state. No effect if VDD2 working mode is PFM.

RW

When 0, VDD2 SMPS PFM mode is set during device SLEEP state.

1

0

VDD1_KEEPON

VIO_KEEPON

When 1, VDD1 SMPS PWM mode is maintained during device SLEEP

state. No effect if VDD1 working mode is PFM.

When 0, VDD1 SMPS PFM mode is set during device SLEEP state.

RW

0

When 1, VIO SMPS PWM mode is maintained during device SLEEP

state. No effect if VIO working mode is PFM.

When 0, VIO SMPS PFM mode is set during device SLEEP state.

Detailed Description

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Table 6-60. SLEEP_SET_LDO_OFF_REG

Address Offset

Instance

0x43

Reset Domain: GENERAL RESET

Description

Configuration Register turning-off LDO regulator during the SLEEP state of the device.

Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this *_SET_OFF

control bit effective

Type

RW

7

6

5

4

3

2

1

0

LDO3_SETOFF LDO4_SETOFF LDO7_SETOFF LDO8_SETOFF LDO5_SETOFF LDO2_SETOFF LDO1_SETOFF LDO6_SETOFF

Bits

Field Name

Description

Type

Reset

7

LDO3_SETOFF

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

RW

0

6

5

4

3

2

1

0

LDO4_SETOFF

LDO7_SETOFF

LDO8_SETOFF

LDO5_SETOFF

LDO2_SETOFF

LDO1_SETOFF

LDO6_SETOFF

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

RW

0

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

98

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Table 6-61. SLEEP_SET_RES_OFF_REG

Address Offset

Instance

0x44

Reset Domain: GENERAL RESET

Description

Configuration Register turning-off SMPS regulator during the SLEEP state of the device.

Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this *_SET_OFF

control bit effective. Supplies voltage expected after their wake-up (SLEEP-to-ACTIVE state transition) can also be

programmed.

Type

RW

7

6

5

4

3

2

1

0

DEFAULT_

VOLT

SPARE_

SETOFF

VDDCTRL_

SETOFF

VDD2_

SETOFF

VDD1_

SETOFF

VIO_

SETOFF

Reserved

Bits

Field Name

Description

Type

Reset

7

DEFAULT_VOLT

When 1, default voltages (register value after switch-on) will be applied

to all resources during SLEEP-to-ACTIVE transition.

When 0, voltages programmed before the ACTIVE-to-SLEEP state

transition will be used to turned-on supplies during SLEEP-to-ACTIVE

state transition.

RW

0

6:5

Reserved

RO

R returns

0s

0x0

4

3

SPARE_SETOFF

Spare bit

RW

0

VDDCTRL_SETOFF When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

2

1

0

VDD2_SETOFF

VDD1_SETOFF

VIO_SETOFF

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

RW

0

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

Detailed Description

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Table 6-62. EN1_LDO_ASS_REG

Address Offset

Instance

0x45

Reset Domain: TURNOFF RESET

Description

Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.

When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined though

SLEEP_KEEP_LDO_ON register setting:

When SCLSR_EN1 is high the regulator is on,

When SCLSR_EN1 is low:

- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register

- the regulator is working in low-power mode if its corresponding control bit = 1 in

SLEEP_KEEP_LDO_ON register

When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state

Any control bit of this register set to 1 will disable the I²C SR Interface functionality

Type

RW

7

6

5

4

3

2

1

0

LDO3_EN1

LDO4_EN1

LDO7_EN1

LDO8_EN1

LDO5_EN1

LDO2_EN1

LDO1_EN1

LDO6_EN1

Bits

7

Field Name

LDO3_EN1

Description

Type

RW

Reset

Setting supply state control though SCLSR_EN1 signal

0

6

LDO4_EN1

LDO7_EN1

LDO8_EN1

LDO5_EN1

LDO2_EN1

LDO1_EN1

LDO6_EN1

5

4

3

2

1

0

100

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Table 6-63. EN1_SMPS_ASS_REG

Address Offset

Instance

0x46

Reset Domain: TURNOFF RESET

Description

Configuration Register setting the SMPS Supplies driven by the multiplexed SCLSR_EN1 signal.

When control bit = 1, SMPS Supply state and voltage is driven by the SCLSR_EN1 control signal and is also

defined though SLEEP_KEEP_RES_ON register setting.

When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state.

Any control bit of this register set to 1 will disable the I²C SR Interface functionality

Type

RW

7

6

5

4

3

2

1

0

VDDCTRL_

EN1

Reserved

SPARE_EN1

VDD2_EN1

VDD1_EN1

VIO_EN1

Bits

Field Name

Reserved

Description

Spare bit

Type

Reset

7:5

RO

R returns

0s

0x0

4

3

SPARE_EN1

RW

0

VDDCTRL_EN1

When control bit = 1:

When EN1 is high the supply voltage is programmed though

VDDCtrl_OP_REG register, and it can also be programmed off.

When EN1 is low the supply voltage is programmed though

VDDCtrl_SR_REG register, and it can also be programmed off.

When control bit = 0: No effect: Supply state is driven though registers

programming and the device state

2

1

0

VDD2_EN1

VDD1_EN1

VIO_EN1

When control bit = 1:

RW

0

When SCLSR_EN1 is high the supply voltage is programmed though

VDD2_OP_REG register, and it can also be programmed off.

When SCLSR_EN1 is low the supply voltage is programmed though

VDD2_SR_REG register, and it can also be programmed off.

When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is

working in low-power mode, if not tuned off through VDD2_SR_REG

register.

When control bit = 0 No effect: Supply state is driven though registers

programming and the device state

When 1:

When SCLSR_EN1 is high the supply voltage is programmed though

VDD1_OP_REG register, and it can also be programmed off.

When SCLSR_EN1 is low the supply voltage is programmed though

VDD1_SR_REG register, and it can also be programmed off.

When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is

working in low-power mode, if not tuned off though VDD1_SR_REG

register.

When control bit = 0 no effect: supply state is driven though registers

programming and the device state

When control bit = 1, supply state is driven by the SCLSR_EN1 control

signal and is also defined though SLEEP_KEEP_RES_ON register

setting:

When SCLSR_EN1 is high the supply is on,

When SCLSR_EN1 is low:

- the supply is off (default) or the SMPS is working in low-power mode if

its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register

When control bit = 0 No effect: SMPS state is driven though registers

programming and the device state

Detailed Description

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Table 6-64. EN2_LDO_ASS_REG

Address Offset

Instance

0x47

Reset Domain: TURNOFF RESET

Description

Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.

When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also defined though

SLEEP_KEEP_LDO_ON register setting:

When SDASR_EN2 is high the regulator is on,

When SCLSR_EN2 is low:

- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register

- the regulator is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register

When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state

Any control bit of this register set to 1 will disable the I²C SR Interface functionality

Type

RW

7

6

5

4

3

2

1

0

LDO3_EN2

LDO4_EN2

LDO7_EN2

LDO8_EN2

LDO5_EN2

LDO2_EN2

LDO1_EN2

LDO6_EN2

Bits

7

Field Name

LDO3_EN2

Description

Type

RW

Reset

Setting supply state control though SDASR_EN2 signal

0

6

LDO4_EN2

LDO7_EN2

LDO8_EN2

LDO5_EN2

LDO2_EN2

LDO1_EN2

LDO6_EN2

5

4

3

2

1

0

102

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Table 6-65. EN2_SMPS_ASS_REG

Address Offset

Instance

0x48

Reset Domain: TURNOFF RESET

Description

Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.

When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is also

defined though SLEEP_KEEP_RES_ON register setting.

When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state

Any control bit of this register set to 1 will disable the I²C SR Interface functionality

Type

RW

7

6

5

4

3

2

1

0

VDDCTRL_

EN2

Reserved

SPARE_EN2

VDD2_EN2

VDD1_EN2

VIO_EN2

Bits

Field Name

Reserved

Description

Spare bit

Type

Reset

7:5

RO

R returns

0s

0x0

4

3

SPARE_EN2

RW

0

VDDCTRL_EN2

When control bit = 1:

When EN2 is high the supply voltage is programmed though

VDDCtrl_OP_REG register, and it can also be programmed off..

When EN2 is low the supply voltage is programmed though

VDDCtrl_SR_REG register, and it can also be programmed off.

When EN2 is low and VDDCtrl_KEEPON = 1 the SMPS is working in

low-power mode, if not tuned off though VDDCtrl_SR_REG register.

When control bit = 0 no effect: Supply state is driven though registers

programming and the device state

2

1

0

VDD2_EN2

VDD1_EN2

VIO_EN2

When control bit = 1:

RW

0

When SDASR_EN2 is high the supply voltage is programmed though

VDD2_OP_REG register, and it can also be programmed off.

When SDASR_EN2 is low the supply voltage is programmed though

VDD2_SR_REG register, and it can also be programmed off.

When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS

is working in low-power mode, if not tuned off though VDD2_SR_REG

register.

When control bit = 0 no effect: Supply state is driven though registers

programming and the device state

When control bit = 1:

When SDASR_EN2 is high the supply voltage is programmed though

VDD1_OP_REG register, and it can also be programmed off.

When SDASR_EN2 is low the supply voltage is programmed though

VDD1_SR_REG register, and it can also be programmed off.

When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS

is working in low-power mode, if not tuned off though VDD1_SR_REG

register.

When control bit = 0 no effect: supply state is driven though registers

programming and the device state

When control bit = 1,

supply state is driven by the SCLSR_EN2 control signal and is also

defined though SLEEP_KEEP_RES_ON register setting:

When SDASR _EN2 is high the supply is on,

When SDASR _EN2 is low :

- the supply is off (default) or the SMPS is working in low-power mode if

its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register

When control bit = 0 no effect: SMPS state is driven though registers

programming and the device state

Detailed Description

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Table 6-66. INT_STS_REG

Address Offset

Instance

0x50

Reset Domain: FULL RESET

Interrupt status register:

Description

The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by

writing 1.

Type

RW

7

6

5

4

3

2

1

0

RTC_PERIOD_ RTC_ALARM_

IT IT

PWRHOLD_R_

IT

PWRHOLD_F_

IT

HOTDIE_IT

PWRON_LP_IT

PWRON_IT

VMBHI_IT

Bits

Field Name

Description

Type

Reset

7

RTC_PERIOD_IT

RTC_ALARM_IT

HOTDIE_IT

RTC period event interrupt status.

RTC alarm event interrupt status.

Hot-die event interrupt status.

RW

W1 to Clr

0

6

5

4

3

2

1

0

RW

W1 to Clr

0

RW

W1 to Clr

PWRHOLD_R_IT

PWRON_LP_IT

PWRON_IT

Rising PWRHOLD event interrupt status.

PWRON Long Press event interrupt status.

PWRON event interrupt status.

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

VMBHI_IT

VBAT > VMHI event interrupt status

Falling PWRHOLD event interrupt status.

RW

W1 to Clr

PWRHOLD_F_IT

RW

W1 to Clr

104

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Table 6-67. INT_MSK_REG

Address Offset

Instance

0x51

Reset Domain: GENERAL RESET

Interrupt mask register:

Description

When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt

status bit is updated.

When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.

Type

RW

7

6

5

4

3

2

1

0

RTC_PERIOD_ RTC_ALARM_

IT_MSK IT_MSK

HOTDIE_

IT_MSK

PWRHOLD_R_ PWRON_LP_

IT_MSK IT_MSK

PWRON_

IT_MSK

VMBHI_

IT_MSK

PWRHOLD_F_

IT_MSK

Bits

Field Name

Description

Type

Reset

7

RTC_PERIOD_IT_MS RTC period event interrupt mask.

K

RW

1

6

RTC_ALARM_IT_MS RTC alarm event interrupt mask.

K

RW

1

5

4

HOTDIE_IT_MSK

Hot die event interrupt mask.

RW

1

PWRHOLD_R_IT_MS PWRHOLD rising-edge event interrupt mask.

K

3

2

1

PWRON_LP_IT_MSK PWRON Long Press event interrupt mask.

RW

1

PWRON_IT_MSK

VMBHI_IT_MSK

PWRON event interrupt mask.

VBAT > VMBHI interrupt event mask bit

When 0, interrupt not masked. Device automatically switches on at NO

SUPPLY-to-OFF BACKUP-to-OFF transition

When 1, interrupt is masked. Device does not switch on until a start

reason is received.

(EEPROM bit. Default value: See boot configuration)

0

PWRHOLD_F_IT_MS PWRHOLD falling-edge event interrupt mask.

K

RW

1

Detailed Description

105

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Table 6-68. INT_STS2_REG

Address Offset

Instance

0x52

Reset Domain: FULL RESET

Interrupt status register:

Description

The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by

writing 1.

Type

RW

7

6

5

4

3

2

1

0

GPIO3_F_IT

GPIO3_R_IT

GPIO2_F_IT

GPIO2_R_IT

GPIO1_F_IT

GPIO1_R_IT

GPIO0_F_IT

GPIO0_R_IT

Bits

Field Name

GPIO3_F_IT

Description

Type

Reset

7

GPIO3 falling-edge detection interrupt status

GPIO3 rising-edge detection interrupt status

GPIO2 falling-edge detection interrupt status

GPIO2 rising-edge detection interrupt status

GPIO1 falling-edge detection interrupt status

GPIO1 rising-edge detection interrupt status

GPIO0 falling-edge detection interrupt status

GPIO0 rising-edge detection interrupt status

RW

W1 to Clr

0

6

5

4

3

2

1

0

GPIO3_R_IT

GPIO2_F_IT

GPIO2_R_IT

GPIO1_F_IT

GPIO1_R_IT

GPIO0_F_IT

GPIO0_R_IT

RW

W1 to Clr

0

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

Table 6-69. INT_MSK2_REG

Address Offset

Instance

0x53

Reset Domain: GENERAL RESET

Interrupt mask register:

Description

When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt

status bit is updated.

When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.

Type

RW

7

6

5

4

3

2

1

0

GPIO3_F_

IT_MSK

GPIO3_R_

IT_MSK

GPIO2_F_

IT_MSK

GPIO2_R_

IT_MSK

GPIO1_F_

IT_MSK

GPIO1_R_

IT_MSK

GPIO0_F_

IT_MSK

GPIO0_R_

IT_MSK

Bits

7

Field Name

Description

Type

RW

Reset

GPIO3_F_IT_MSK

GPIO3_R_IT_MSK

GPIO2_F_IT_MSK

GPIO2_R_IT_MSK

GPIO1_F_IT_MSK

GPIO1_R_IT_MSK

GPIO0_F_IT_MSK

GPIO0_R_IT _MSK

GPIO3 falling-edge detection interrupt mask.

GPIO3 rising-edge detection interrupt mask.

GPIO2 falling-edge detection interrupt mask.

GPIO2 rising-edge detection interrupt mask.

GPIO1 falling-edge detection interrupt mask.

GPIO1 rising-edge detection interrupt mask.

GPIO0 falling-edge detection interrupt mask.

GPIO0 rising-edge detection interrupt mask.

1

6

5

4

3

2

1

0

106

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Table 6-70. INT_STS3_REG

Address Offset

Instance

0x54

Reset Domain: FULL RESET

Interrupt status register:

Description

The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by

writing 1.

Type

RW

7

6

5

4

3

2

1

0

PWRDN_IT

VMBCH2_L_IT VMBCH2_H_IT WTCHDG_IT

GPIO5_F_IT

GPIO5_R_IT

GPIO4_F_IT

GPIO4_R_IT

Bits

Field Name

PWRDN_IT

Description

Type

Reset

7

PWRDN reset input high detected

RW

0

W1 to Clr

6

5

4

3

2

1

0

VMBCH2_L_IT

VMBCH2_H_IT

WTCHDG_IT

GPIO5_F_IT

GPIO5_R_IT

GPIO4_F_IT

GPIO4_R_IT

Comparator2 input below threshold detection interrupt status

Comparator2 input above threshold detection interrupt status

Watchdog interrupt status

RW

W1 to Clr

0

RW

W1 to Clr

RW

W1 to Clr

GPIO5 falling-edge detection interrupt status

GPIO5 rising-edge detection interrupt status

GPIO4 falling-edge detection interrupt status

GPIO4 rising-edge detection interrupt status

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

Table 6-71. INT_MSK3_REG

Address Offset

Instance

0x55

Reset Domain: GENERAL RESET

Interrupt mask register:

Description

When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt

status bit is updated.

When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.

Type

RW

7

6

5

4

3

2

1

0

PWRDN_

IT_MSK

VMBCH2_L_

IT_MSK

VMBCH2_H_

IT_MSK

WTCHDG_

IT_MSK

GPIO5_F_

IT_MSK

GPIO5_R_

IT_MSK

GPIO4_F_

IT_MSK

GPIO4_R_

IT_MSK

Bits

7

Field Name

Description

Type

RW

Reset

PWRDN_IT_MSK

PWRDN interrupt mask

1

6

VMBCH2_L_IT_MSK Comparator2 input below threshold detection interrupt mask

VMBCH2_H_IT_MSK Comparator2 input above threshold detection interrupt mask

5

4

WTCHDG_IT_MSK

GPIO5_F_IT_MSK

GPIO5_R_IT_MSK

GPIO4_F_IT_MSK

GPIO4_R_IT_MSK

Watchdog interrupt mask.

3

GPIO5 falling-edge detection interrupt mask.

GPIO5 rising-edge detection interrupt mask.

GPIO4 falling-edge detection interrupt mask.

GPIO4 rising-edge detection interrupt mask.

2

1

0

Detailed Description

107

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Table 6-72. GPIO0_REG

Address Offset

Instance

0x60

Reset Domain: GENERAL RESET

GPIO0 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

GPIO_SLEEP

Reserved

GPIO_ODEN

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

GPIO_SLEEP⁽¹⁾

Description

Type

Reset

7

1: as GPO, force low

RW

0

0: No impact, keep as in active mode

6

5

Reserved

Reserved bit

RO

R returns

0s

0

GPIO_ODEN

Selection of output mode, EEPROM bit

0: Push-pull output

RW

1: Open-drain output

(Default value: See boot configuration)

GPIO assigned to power-up sequence, this bit will be set to 1 by a

TURNOFF reset

4

3

2

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

0

GPIO pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

(Default value: See boot configuration)

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

GPIO assigned to power-up sequence, this bit will be in TURNOFF reset

(1) The GPIO_SLEEP bit is a bit available only for GPIO_0/2/6/7.This bit will be take into account and be effective only if the GPIO_0/2/6/7

is associated to a TIME_SLOT. It means that this bit is useful only if the GPIO is part of the POWER UP SEQUENCE. Note that in this

case the associated GPIO will be set as GPO. GPIO_SLEEP bit is a bit related to the PMU sleep mode only, No action in ACTIVE

mode. It is used to define SLEEP mode state for GPIO 0/2/6/7.

108

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Table 6-73. GPIO1_REG

Address Offset

Instance

0x61

Reset Domain: GENERAL RESET

GPIO1 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

GPIO_SEL

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

Description

Type

Reset

7:6

Reserved

RO

R returns

0s

0x0

5

4

3

2

GPIO_SEL

GPIO_DEB

GPIO_PDEN

GPIO_CFG

Select signal to be available at GPIO when configured as output:

0: GPIO_SET

1: LED1 out

RW

0

1

0

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

GPIO pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

Detailed Description

109

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Table 6-74. GPIO2_REG

Address Offset

Instance

0x62

Reset Domain: GENERAL RESET

GPIO2 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

GPIO_SLEEP

Reserved

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

GPIO_SLEEP

Description

Type

Reset

7

1: as GPO, force low

RW

0

0: no impact, keep as in active mode

6:5

4

Reserved

RO

R returns

0s

0x0

0

GPIO_DEB

GPIO_PDEN

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

3

GPIO pad pulldown control:

RW

1

1: Pulldown is enabled

0: Pulldown is disabled

GPIO assigned to power-up sequence, this bit will be set to 0 by a

TURNOFF reset

2

GPIO_CFG

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

(Default value: See boot configuration)

GPIO assigned to power-up sequence, this bit will be set to 1 by a

TURNOFF reset

RW

0

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

GPIO assigned to power-up sequence, this bit will be in TURNOFF reset

110

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Table 6-75. GPIO3_REG

Address Offset

Instance

0x63

Reset Domain: GENERAL RESET

GPIO3 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

GPIO_SEL

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

Description

Type

Reset

7

Reserved

RO

R returns

0s

0

6:5

GPIO_SEL

Select signal to be available at GPIO when configured as output:

RW

0x0

00: GPIO_SET

01: LED2 out

10: PWM out

4

3

2

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

0

1

0

GPIO pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

Table 6-76. GPIO4_REG

Address Offset

Instance

0x64

Reset Domain: GENERAL RESET

GPIO4 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

Reserved

Description

Type

Reset

7:5

RO

R returns

0s

0x0

4

3

2

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

0

1

0

GPIO pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

Detailed Description

111

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Table 6-77. GPIO5_REG

Address Offset

Instance

0x65

Reset Domain: GENERAL RESET

GPIO5 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

Reserved

Description

Type

Reset

7:5

RO

R returns

0s

0x0

4

3

2

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

0

1

0

GPIO pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

112

Detailed Description

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Table 6-78. GPIO6_REG

Address Offset

Instance

0x66

Reset Domain: GENERAL RESET

GPIO6 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

GPIO_SLEEP

Reserved

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

GPIO_SLEEP

Description

Type

Reset

7

1: as GPO, force low

RW

0

0: no impact, keep as in active mode

6:5

4

Reserved

RO

R returns

0s

0x0

0

GPIO_DEB

GPIO_PDEN

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

3

GPIO pad pulldown control:

RW

1

1: Pulldown is enabled

0: Pulldown is disabled

GPIO assigned to power-up sequence, this bit will be set to 0 by a

TURNOFF reset

2

GPIO_CFG

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

(Default value: See boot configuration)

GPIO assigned to power-up sequence, this bit will be set to 1 by a

TURNOFF reset

RW

0

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

GPIO assigned to power-up sequence, this bit will be in TURNOFF reset

Detailed Description

113

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Table 6-79. GPIO7_REG

Address Offset

Instance

0x67

Reset Domain: GENERAL RESET

GPIO7 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

GPIO_SLEEP

Reserved

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

GPIO_SLEEP

Description

Type

Reset

7

1: as GPO, force low

RW

0

0: no impact, keep as in active mode

6:5

4

Reserved

RO

R returns

0s

0x0

0

GPIO_DEB

GPIO_PDEN

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

RW

3

GPIO pad pulldown control:

RW

1

1: Pulldown is enabled

0: Pulldown is disabled

GPIO assigned to power-up sequence, this bit will be set to 0 by a

TURNOFF reset

2

GPIO_CFG

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

(Default value: See boot configuration)

GPIO assigned to power-up sequence, this bit will be set to 1 by a

TURNOFF reset

RW

0

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

GPIO assigned to power-up sequence, this bit will be in TURNOFF reset

114

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Table 6-80. GPIO8_REG

Address Offset

Instance

0x68

Reset Domain: GENERAL RESET

GPIO8 configuration register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

GPIO_SEL

GPIO_DEB

GPIO_PDEN

GPIO_CFG

GPIO_STS

GPIO_SET

Bits

Field Name

Description

Type

Reset

7:6

Reserved

RO

R returns

0s

0x0

5

4

3

2

GPIO_SEL

GPIO_DEB

GPIO_PDEN

GPIO_CFG

Select signal to be available at GPIO when configured as output:

0: GPIO_SET

1: PWM out

RW

0

1

0

GPIO input debouncing time configuration:

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

GPIO pad pulldown control:

1: Pulldown is enabled

0: Pulldown is disabled

Configuration of the GPIO pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

1

0

GPIO_STS

GPIO_SET

Status of the GPIO pad

RO

1

0

Value set on the GPIO output when configured in output mode

RW

Detailed Description

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Table 6-81. WATCHDOG_REG

Address Offset

Instance

0x69

Reset Domain: GENERAL RESET

Description

Type

Watchdog

RW

7

6

5

4

3

2

1

0

WTCHDG_

MODE

Reserved

WTCHDG_TIME

Bits

Field Name

Reserved

Description

Type

Reset

7:4

RO

R returns

0s

0x0

3

WTCHDG_MODE

0: Periodic operation:

RW

0

A periodical interrupt is generated based on WTCHDG_TIME setting. IC

will generate WTCHDOG shutdown if interrupt is not cleared during the

period.

1: Interrupt mode:

IC will generate WTCHDOG shutdown if an interrupt is pending (no

cleared) more than WTCHDG_TIME s.

2:0

WTCHDG_TIME

000: Watchdog disabled

001: 5 seconds

RW

0x0

010: 10 seconds

011: 20 Seconds

100: 40 seconds

101: 60 seconds

110: 80 seconds

111: 100 seconds (EEPROM bit)

(Default value: See boot configuration)

Table 6-82. VMBCH_REG

Address Offset

Instance

0x6A

Reset Domain: GENERAL RESET

Comparator control register

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

VMBCH_SEL

Reserved

Bits

Field Name

Description

Type

Reset

7:6

Reserved

RO

R returns

0s

0x0

5:1

VMBCH_SEL

Battery voltage comparator threshold (EEPROM)

RW

0x00

11000 to 11111: 3.5 V

10111: 3.45 V

...

01110: 3 V (default)

...

00101: 2.55 V

00001 to 00100: 2.5 V

00000: Bypass

(Default value: See boot configuration)

0

Reserved

RO

R returns

0s

0

116

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Table 6-83. VMBCH2_REG

Address Offset

Instance

0x6B

Reset Domain: GENERAL RESET

Description

Type

Comparator for detecting battery discharge below threshold level

RW

7

6

5

4

3

2

1

0

VMBDCH2_

DEB

Reserved

VMBDCH2_SEL

Bits

Field Name

Description

Type

Reset

7:6

Reserved

RO

R returns

0s

0x0

5:1

VMBDCH2_SEL

Battery voltage comparator threshold

11000 to 11111: 3.5 V

10111: 3.45 V

RW

0x00

...

00101: 2.55 V

00001 to 00100: 2.5 V

00000: Bypass

0

VMBDCH2_DEB

Comp2 input debouncing time configuration:

RW

0

When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

Table 6-84. LED_CTRL1_REG

Address Offset

Instance

0x6C

Reset Domain: GENERAL RESET

LED ON/OFF control register.

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

LED2_PERIOD

LED1_PERIOD

Bits

Field Name

Description

Type

Reset

7:6

Reserved

RO

R returns

0s

0x0

5:3

LED2_PERIOD

Period of LED2 signal:

000: LED2 OFF

001: 0.125 s

010: 0.25 s

...

RW

0x0

110: 4 s

111: 8 s

2:0

LED1_PERIOD

Period of LED1 signal:

000: LED1 OFF

001: 0.125 s

010: 0.25 s

...

RW

0x0

10: 2 s

110: 4 s

111: 8 s

Detailed Description

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Table 6-85. LED_CTRL2_REG1

Address Offset

Instance

0x6D

Reset Domain: GENERAL RESET

LED ON/OFF control register.

RW

Description

Type

7

6

5

4

3

2

1

0

Reserved

LED2_SEQ

LED1_SEQ

LED2_ON_TIME

LED1_ON_TIME

Bits

Field Name

Description

Type

Reset

7:6

Reserved

RO

R returns

0s

0x0

5

4

LED2_SEQ

LED1_SEQ

When 1, LED2 will repeat 2 pulse sequence: ON (ON_TIME) - OFF (ON

TIME) - ON (ON TIME) - OFF remainder of the period

When 0, LED2 will generate 1 pulse: ON (ON_TIME) - OFF (ON TIME))

RW

0

When 1, LED1 will repeat 2 pulse sequence: ON (ON_TIME) - OFF (ON

TIME) - ON (ON TIME) - OFF remainder of the period.

When 0, LED1 will generate 1 pulse: ON (ON_TIME) - OFF (ON TIME))

3:2

LED2_ON_TIME

LED1_ON_TIME

LED2 ON time:

00: 62.5 ms

01: 125 ms

10: 250 ms

11: 500 ms

0x0

1:0

LED1 ON time:

00: 62.5 ms

01: 125 ms

10: 250 ms

11: 500 ms

RW

0x0

Table 6-86. PWM_CTRL1_REG

Address Offset

Instance

0x6E

Reset Domain: GENERAL RESET

Description

Type

PWM frequency

RW

7

6

5

4

3

2

1

0

Reserved

PWM_FREQ

Bits

Field Name

Description

Type

Reset

7:2

Reserved

Reserved bit

RO

R returns

0s

0x00

1:0

PWM_FREQ

Frequency of PWM:

00: 500 Hz

RW

0x0

01: 250 Hz

10: 125 Hz

11: 62.5 Hz

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Table 6-87. PWM_CTRL2_REG

Address Offset

Instance

0x6F

Reset Domain: GENERAL RESET

Description

Type

PWM duty cycle.

RW

7

6

5

4

3

2

1

0

FREQ_DUTY_CYCLE

Bits

Field Name

Description

Type

Reset

7:0

FREQ_DUTY_CYCLE Duty cycle of PWM:

RW

0x00

00000000: 0/256

...

11111111: 255/256

Table 6-88. SPARE_REG

Address Offset

Instance

0x70

Reset Domain: FULL RESET

Spare functional register

RW

Description

Type

7

6

5

4

3

2

1

0

SPARE

Bits

Field Name

SPARE

Description

Type

Reset

7:0

Spare bits

RW

0x00

Table 6-89. VERNUM_REG

Address Offset

Instance

0x80

Reset Domain: FULL RESET

Silicon version number

RW

Description

Type

7

6

5

4

3

2

1

0

READ_BOOT

Reserved

VERNUM

Bits

Field Name

READ_BOOT

Description

Type

Reset

7

To enable the read of the BOOT mode if you want to go to JTAG mode,

this be must set to 1.

RW

0

6:4

3:0

Reserved

VERNUM

Reserved bit

RO

R returns

0s

0x0

Value depending on silicon version number 0000 - Revision 1.0

RO

Detailed Description

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7 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

7.1 Application Information

The TPS65911 device is an integrated power management IC (PMIC) available in a 98-pin 0.65-mm pitch

BGA MicroStar Junior package. The device is designed for applications powered by one Li-Ion or Li-Ion

polymer battery cell, 3-series Ni-MH cells, or a 5-V input supply. The device has three step-down

converters, one step-down controller with external FETs to support high current rails, eight LDO

regulators, nine GPIOs, and EERPOM-programmable power sequencing to support a variety of

processors and system sequencing requirements.

The following sections include a typical application diagram, description of the recommended external

components, and PCB layout guidelines. The TPS65911x Schematic Checklist is available and provides

recommended connections for each pin.

7.2 Typical Application

The default voltages in Figure 7-1 reflect the TPS65911A configuration. Other TPS65911 device options

may have different default voltages.

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< 12V

GNDC

VBST

DRVH

SW

TPS65911A

GND

66AK2G12

V5IN

GND

1 …F

Default 1.0 V, DVS

CVDD

GND

VREF

DRVL

VOUT

GND

100 nF

GND

REFGND

VFB

To V5IN

+5 V

VDDCtrl

TRIP

VCC1

VCC2

10 …F

GND

Default 1.0 V

Default 1.35 V

Default 3.3 V

SW1

CVDD1

VDD1

1500 mA

DVS

2.2 …H

10 …F

VFB1

GND

VCCIO

VCC3

GND1

SW2

GND

10 …F

DVDD_DDR

DVDD33

VDD2

1500 mA

DVS

GND

10 …F

VFB2

4.7 …F

GND2

SWIO

GND

VCC4

VIO

1100 mA

4.7 …F

10 …F

VFBIO

GND

GNDIO

VDDIO

VCC5

GND

4.7 …F

Connects to system 1.8V/3.3V IO supply

VCC6

2.7V < Vin < 3.6V

If LDO1 or LDO2 used

GND

LDO1

320 mA

Default 1.8 V

VCC6

DVDD18

AVDDA_XPLL

4.7 …F

2.2 …F

GND

LDO2

320 mA

Default 1.8 V

VCC7

4.7 …F

2.2 …F

VCC5

GND

LDO3

200 mA

Default 1.8 V

VCCS

VBACKUP

2.2 …F

GND

LDO4

50 mA

Default 1.8 V

5-2000 mF

GND

2.2 …F

GND

12 pF

LDO5

VCC4

300 mA

VCC3

Default 3.3 V

OSC32KIN

OSC32KOUT

BOOT1

GND

2.2 …F

(crystal is optional)

GND

12 pF

LDO6

300 mA

Default 3.3 V

GND

2.2 …F

GND

LDO7

300 mA

Default 3.3 V

VRTC

2.2 …F

GND

LDO8

300 mA

Default 3.3 V

5V

10 kꢀ

(leave GPIO floating if not used)

GPIO1/3/4/5/8

2.2 …F

VDDIO

GND

VRTC

20 mA

1.8 V (Always-ON)

VCC7

VRTC

PWRON

GND

2.2 …F

1.2 kꢀ

GND

(If not used, connect to VRTC)

(leave floating if not used)

(leave floating)

PWRDN

HDRST

EN

SDA_SDI

SCL_SCK

INT1

I2CSDA

I2CSCL

GPIO

(leave floating)

TRAN

EN2

PGOOD

TESTV

EN1

SLEEP

PWRHOLD

GPIO

(leave floating)

PORZ

NRESPWRON2

CLK32KOUT

Figure 7-1. TPS65911A Typical Application

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7.2.1 Design Requirements

For a typical application shown in Figure 7-1, Table 7-1 lists the primary design parameters of the power

resources.

Table 7-1. Design Parameters

DESIGN PARAMETER

Supply voltage

VDD1 voltage

VDD1 current

VDD2 voltage

VDD2 current

VDDCtrl voltage

VDDCtrl current

VIO voltage

VALUE

2.7 V to 5.5 V

1 V

Up to 1.5 A

1.35 V

Up to 1.5 A

1 V

(1)

See

3.3 V

Up to 1.1 A

1.8 V

VIO current

LDO1 voltage

LDO1 current

LDO2 voltage

LDO2 current

LDO3 voltage

LDO3 current

LDO4 voltage

LDO4 current

LDO5 voltage

LDO5 current

LDO6 voltage

LDO6 current

LDO7 voltage

LDO7 current

LDO8 voltage

LDO8 current

Up to 320 mA

1.8 V

Up to 320 mA

1.8 V

Up to 200 mA

1.8 V

Up to 50 mA

3.3 V

Up to 300 mA

3.3 V

Up to 300 mA

3.3 V

Up to 300 mA

3.3 V

Up to 300 mA

(1) Value is dependent on external FETs.

7.2.2 Detailed Design Procedure

7.2.2.1 External Component Recommendation

For crystal oscillator components, see Section 5.10. If RTC domain is expected to be maintained after

shutdown, VCC7 must have enough capacitance to make sure that when supply is switched off, voltage

does not fall at a rate faster than 10 mV/ms. This makes sure that RTC domain data is maintained.

Table 7-2. External Component Recommendation

PARAMETER

POWER REFERENCES

VREF filtering capacitor (C_O(VREF)

VDD1 SMPS

TEST CONDITIONS

MIN

NOM

MAX

UNIT

)

Connected from VREF to REFGND

100

nF

Input capacitor (C_I(VCC1)

)

X5R or X7R dielectric

ƒ = 3 MHz

10

µF

Output filter capacitor (C_O(VDD1)

)

4

12

C_Ofilter capacitor ESR

300

mΩ

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Table 7-2. External Component Recommendation (continued)

PARAMETER

Inductor (L_O(VDD1)

TEST CONDITIONS

MIN

NOM

MAX

UNIT

µH

)

2.2

L_Oinductor DC resistor (DCR_L)

125

mΩ

VDD2 SMPS

Input capacitor (C_I(VCC2)

)

X5R or X7R dielectric

10

µF

Output filter capacitor (C_O(VDD2)

)

X5R or X7R dielectric

ƒ = 3 MHz

4

12

C_Ofilter capacitor ESR

10

300

mΩ

µH

mΩ

Inductor (L_O(VDD2)

)

2.2

L_Oinductor DC resistor (DCR_L)

125

VIO SMPS

Input capacitor (C_I(VCCIO)

)

X5R or X7R dielectric

ƒ = 3 MHz

10

µF

Output filter capacitor (C_O(VIO)

C_Ofilter capacitor ESR

)

4

12

10

300

mΩ

µH

mΩ

Inductor (L_O(VIO)

)

2.2

L_Oinductor DC resistor (DCR_L)

125

VDDCtrl SMPS

Input capacitor (C_VIN

High-side drive boost capacitor

(C_boost

Input capacitor for V5IN supply

(C_V5IN

)

4 × 10

0.1

µF

)

1

µF

)

Output filter capacitor (C_O(VDDCtrl)

)

330

9

µF

mΩ

µH

mΩ

kΩ

C_Ofilter capacitor ESR

15

Inductor (L_O(VDDCtrl)

L_OInductor DC resistor (DCR_L)

Trip resistance (R_trip

)

2.7

20

)

40

Feed forward capacitor (C₁)

FET FDMC7660

LDO1

330

pF

Input capacitor (C_I(VCC6)

)

X5R or X7R dielectric

4.7

2.2

µF

Output filtering capacitor (C_O(LDO1)

C_Ofiltering capacitor ESR

LDO2

)

0.8

0

2.64

500

mΩ

Output filtering capacitor (C_O(LDO2)

C_Ofiltering capacitor ESR

LDO3

)

0.8

0

2.2

2.64

500

µF

mΩ

Input capacitor (C_I(VCC5)

)

X5R or X7R dielectric

4.7

2.2

µF

Output filtering capacitor (C_O(LDO3)

C_Ofiltering capacitor ESR

LDO4

)

0.8

0

2.64

500

mΩ

Output filtering capacitor (C_O(LDO4)

C_Ofiltering capacitor ESR

LDO5

)

0.8

0

2.2

2.64

500

µF

mΩ

Input capacitor (C_I(VCC4)

)

X5R or X7R dielectric

4.7

2.2

µF

Output filtering capacitor (C_O(LDO5)

C_Ofiltering capacitor ESR

LDO6

)

0.8

0

2.64

500

mΩ

Input capacitor (C_I(VCC3)

)

4.7

2.2

µF

Output filtering capacitor (C_O(LDO6)

)

0.8

2.64

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Table 7-2. External Component Recommendation (continued)

PARAMETER

C_Ofiltering capacitor ESR

LDO7

TEST CONDITIONS

MIN

NOM

MAX

UNIT

0

500

mΩ

Output filtering capacitor (C_O(LDO7)

C_Ofiltering capacitor ESR

LDO8

)

0.8

0

2.2

2.64

500

µF

mΩ

Output filtering capacitor (C_O(LDO8)

C_Ofiltering capacitor ESR

VRTC LDO

)

0.8

0

2.2

2.64

500

µF

mΩ

Input capacitor (C_I(VCC7)

)

X5R or X7R dielectric

4.7

2.2

µF

Output filtering capacitor (C_O(VRTC)

C_Ofiltering capacitor ESR

BACKUP BATTERY

)

0.8

0

2.64

500

mΩ

Backup battery capacitor (C_BB

)

5

10

2000

1500

mF

Series resistors

C_BB= 5 mF to 15 mF

10

Ω

7.2.2.2 Controller Design Procedure

Follow these steps to design the controller:

1. Design the output filter

2. Select the FETs

3. Select the bootstrap capacitor

4. Select the input capacitors

5. Set the current limits

VDDCtrl requires a 5-V supply at the V5IN pin with an input capacitor. For most applications, a 1-μF, X5R,

20%, 10-V, or similar capacitor must be used for decoupling.

7.2.2.2.1 Inductor Selection

An inductor must be placed between the external FETs and the output capacitors. Together, the inductor

and output capacitors make the double-pole that contributes to stability. In addition, the inductor is directly

responsible for the output ripple, efficiency, and transient performance. As the inductance increases, the

ripple current decreases, which typically results in an increased efficiency. However, with an increase in

inductance, the transient performance decreases. Finally, the selected inductor must be rated for the

appropriate saturation current, core losses, and DC resistance (DCR). Use Equation 1 to calculate the

recommended inductance for the controller (L).

V_OUTì V_IN- V_OUT

(

)

L =

V

_INì f_SWì I_OUTmaxì K_IND

where

•

V_OUTis the typical output voltage.

V_INis the typical input voltage.

f_SWis the typical switching frequency.

I_OUTmaxis the maximum load current.

K_INDis the ratio of I_Lrippleto the I_OUTmax. For this application, TI recommends that K_INDis set to a value

from 0.2 to 0.4.

(1)

After selecting the value of the inductor, use Equation 2 to calculate the peak current for the inductor in

steady state operation, I_Lmax. The rated saturation current of the inductor must be greater than the I_Lmax

current.

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V_OUTì V_IN- V_OUT

(

)

I_Lmax

=

V

ì f_SWì I_OUTmaxì K_IND

IN

(2)

Following Equation 1 and Equation 2, the preferred inductor for VDDCtrl is 2.7 µH, with a DCR of

approximately 20 mΩ.

7.2.2.2.2 Selecting the R_TRIPResistor

The TRIP pin is used to set the VDDCtrl current limit. The load current is sensed by measuring the voltage

over the low-side FET and comparing it to the voltage at the TRIP pin, V_TRIP, with an 8:1 ratio. If the low-

side FET is greater than an eighth of V_TRIP, the VDDCtrl rail shuts down.

The TRIP resistor then adjusts the range of the VDDCtrl load current monitoring. Use Equation 3 to

calculate the value of the TRIP resistor (R_TRIP) for the application and selected external FETs.

8 ì I_OUTmaxì R_DS(on)

R_TRIP

=

I_TRIP

where

•

I_OUTmaxis the maximum load current.

I_TRIPis the current through the TRIP pin, estimated at 10 µA.

R_DS(on)is the on resistance from the external FETs.

(3)

7.2.2.2.3 Selecting the Output Capacitors

Texas Instruments recommends using ceramic capacitors with low ESR values to provide the lowest

output voltage ripple. The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric

capacitors, aside from their wide variation in capacitance over temperature, become resistive at high

frequencies. At light load currents, the controller operates in PFM mode, and the output voltage ripple is

dependent on the output-capacitor value and the PFM peak inductor current. Higher output-capacitor

values minimize the voltage ripple in PFM mode. To achieve specified regulation performance and low

output voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective

capacitance of ceramic capacitors drops with increasing DC bias voltage. TI recommends the use of small

ceramic capacitors placed between the inductor and load with many vias to the power-ground (PGND)

plane for the output capacitors of the controller. This solution typically provides the smallest and lowest

cost solution available for DCAP controllers. The selection of the output capacitor is typically driven by the

output transient response. Equation 4 provides a rough estimate of the minimum required capacitance to

make sure the transient response is correct.

2

I_TRAN(max)ì L

C_OUT

>

V

_IN- V_OUTì V

(

)

OVER

where

•

I_TRAN(max)is the maximum load current step.

L is the selected inductance.

V_OUTis the minimum programmed output voltage.

V_INis the maximum input voltage.

V_OVERis the maximum allowable overshoot from programmed voltage.

(4)

Because the transient response is affected significantly by the board layout, some experimentation is

expected to confirm that values derived in this section are applicable to any particular use case.

Equation 4 is not provided as an absolute requirement, but as a starting point. Alternatively, lists

recommended capacitor values.

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7.2.2.2.4 Selecting FETs

This controller is designed to drive two n-channel MOSFETs. Typically, lower R_DS(on)values are better for

improving the overall efficiency of the controller, however higher gate-charge thresholds result in lower

efficiency so these two values must be balanced for optimal performance. As the R_DS(on)for the low-side

FET decreases, the minimum current limit increases. Therefore, make sure the appropriate values are

selected for the FETs, inductor, output capacitors, and current limit resistor. The Texas Instruments'

CSD87330Q3D device is a recommended for the controller, depending on the required maximum current.

7.2.2.2.5 Bootstrap Capacitor

To make sure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a

capacitor must be connected between the SW pin and the VBST pin. TI recommends placing ceramic

capacitors with a value of 0.1 μF for the controller. TI recommends reserving a small resistor in series with

the bootstrap capacitor in case the turnon and turnoff of the FETs must be slowed to decrease voltage

ringing on the switch node, which is a common practice for controller design.

7.2.2.2.6 Selecting Input Capacitors

Because of the nature of the switching controller with a pulsating input current, a low ESR input capacitor

is required for the best input-voltage filtering and also to minimize the interference with other circuits

caused by high input-voltage spikes. For the controller, a typical 1-μF capacitor can be used for the V5IN

pin to support the transients on the driver. For the FET input, 40 μF of input capacitance is recommended

for most applications. To achieve the low ESR requirement, a ceramic capacitor is recommended.

However, the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For

better input-voltage filtering, the input capacitor can be increased without any limit. TI recommends placing

a ceramic capacitor as near as possible to the FET across the respective VSYS and PGND pins of the

FETs.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

7.2.2.3 Converter Design Procedure

7.2.2.3.1 Selecting the Inductor

An inductor must be placed between the external FETs and the output capacitors. Together, the inductor

and output capacitors form a double pole in the control loop that contributes to stability. In addition, the

inductor is directly responsible for the output ripple, efficiency, and transient performance. As the

inductance increases, the ripple current decreases, which typically results in an increase in efficiency.

However, with an increase in inductance, the transient performance decreases. Finally, the selected

inductor must be rated for the appropriate saturation current, core losses, and DC resistance (DCR).

NOTE

The internal parameters for the converters are optimized for a 2.2-µH inductor, however

using other inductor values is possible as long as they are carefully selected and thoroughly

tested.

Use Equation 5 to calculate the recommended inductance for the converter.

V_OUTì V_IN- V_OUT

(

)

L =

V

_INì f_SWì I_OUTmaxì K_IND

where

•

V_OUTis the typical output voltage.

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•

V_INis the typical input voltage.

f_SWis the typical switching frequency.

I_OUTmaxis the maximum load current.

K_INDis the ratio of I_Lrippleto the I_OUTmax. For this application, TI recommends that K_INDis set to a value

from 0.2 to 0.4.

(5)

After selecting the value of the inductor, use Equation 6 to calculate the peak current for the inductor in

steady state operation, I_Lmax. The rated current of the inductor must be greater than the I_Lmaxcurrent.

V_OUTì V_IN- V_OUT

(

)

I_Lmax

=

2 ì V ì f_SWì L

IN

(6)

7.2.2.3.2 Selecting Output Capacitors

TI recommends ceramic capacitors with low ESR values because they provide the lowest output voltage

ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside from the

wide variation in capacitance over temperature, become resistive at high frequencies. At light load

currents, the converter operates in PFM mode and the output voltage ripple is dependent on the output-

capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage

ripple in PFM mode. To achieve specified regulation performance and low output voltage ripple, the DC-

bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic

capacitors drops with increasing DC-bias voltage. For the output capacitors of the BUCK converters, TI

recommends placing small ceramic capacitors between the inductor and load with many vias to the PGND

plane. This solution typically provides the smallest and lowest-cost solution available for the converters.

The output capacitance must equal to or greater than the minimum capacitance listed for VDD1, VDD2,

and VIO (assuming quality layout techniques are followed). The recommended value is 10 µF.

7.2.2.3.3 Selecting Input Capacitors

Because of the nature of the switching converter with a pulsating input current, a low ESR input capacitor

is required for the best input-voltage filtering and to minimize the interference with other circuits caused by

high input-voltage spikes. For the VCC1, VCC2, and VCCIO pins, 10 μF of input capacitance (after

derating) is required for most applications. A ceramic capacitor is recommended to achieve the low ESR

requirement. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be

considered. The input capacitor can be increased without any limit for better input-voltage filtering.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

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7.2.3 Application Curves

VCC1 = 3.8 V

Vout = 1.2 V

PWM Mode

VCC1 = 3.8 V

Vout = 1.2 V

PWM Mode

Figure 7-2. VDD1 Falling Load Transient Response

Figure 7-3. VDD1 Rising Load Transient Response

VCC2 = 3.8 V

Vout = 1.2 V

PWM Mode

VCC2 = 3.8 V

Vout = 1.2 V

PWM Mode

Figure 7-4. VDD2 Falling Load Transient Response

Figure 7-5. VDD2 Rising Load Transient Response

VCCIO = 3.8 V

Vout = 1.8 V

PWM Mode

VCCIO = 3.8 V

Vout = 1.8 V

PWM Mode

Figure 7-7. VDDIO Rising Load Transient Response

Figure 7-6. VDDIO Falling Load Transient Response

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SWCS049S –JUNE 2010–REVISED AUGUST 2018

7.2.4 Layout Guidelines

7.2.4.1 PCB Layout

As with all switching power supplies, the layout is an important step in the design. Proper layout is

important for stability, EMI, as well as achieve higher efficiency and load transient response.

•

Place the input capacitors as close as possible to the input pins on the IC, and on the same side of the

board as the IC.

•

Place the inductor and output capacitor close to the switch node of the IC.

Use a solid ground plane for the GND of the buck converters and controller, and use plenty of vias.

Keep the loop area formed by switch node, inductor, output capacitor, and ground as small as

possible.

•

Route the analog grounds separately from the power grounds, and connect them at the ground plane.

Use short, wide traces for any trace which carries high current like regulator input, output, and ground

traces.

For more detailed guidelines, refer to the TPS65911 Layout Guidelines.

7.2.5 Layout Example

Figure 7-8. VDD1 Layout

Applications, Implementation, and Layout

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Figure 7-9. VDD2 Layout

Figure 7-10. VDDIO Layout

130

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Figure 7-11. VDDCtrl Layout

7.3 Power Supply Recommendations

The TPS65911 device uses a supply voltage from 2.7 V to 5.5 V. The input supply should be well

regulated and connected to the VCC input pins. Add external capacitors at each of the device supply pins

as described in Table 7-2.

Applications, Implementation, and Layout

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

For development support, see the following:

•

66AK2G02 DSP + ARM Processor Audio Processing Reference Design

66AK2G02 DSP + ARM Processor Power Solution Reference Design

DDR ECC Reference Design to Improve Memory Reliability in 66AK2G02-based Systems

Freescale i.MX6 Dual&Quad Power Reference Design with TPS65911

Freescale i.MX6 Power Reference Design for Electronic Point of Sale Applications

8.1.2 Device Nomenclature

Table 8-1 lists the acronyms and abbreviations used in this document.

Table 8-1. Acronyms, Abbreviations, and Definitions

ACRONYM OR

DEFINITION

ABBREVIATION

DDR

ES

Dual-Data Rate (memory)

Engineering Sample

ESD

FET

Electrostatic Discharge

Field Effect Transistor

Embedded Power Controller

Finite State Machine

EPC

FSM

GND

GPIO

HBM

HD

Ground

General-Purpose I/O

Human Body Model

Hot-Die

HS-I²C

I²C

High-Speed I²C

Inter-Integrated Circuit

Integrated Circuit

IC

ID

Identification

IDDQ

IEEE

IR

Quiescent supply current

Institute of Electrical and Electronics Engineers

Instruction Register

I/O

Input/Output

JEDEC

JTAG

LBC7

LDO

LP

Joint Electron Device Engineering Council

Joint Test Action Group

Lin Bi-CMOS 7 (360 nm)

Low Drop Output voltage linear regulator

Low-Power application mode

Least Significant Bit

LSB

MMC

MOSFET

NVM

OD

Multimedia Card

Metal Oxide Semiconductor Field Effect Transistor

Nonvolatile Memory

Open Drain

OMAP™

RTC

Open Multimedia Application Platform™

Real-Time Clock

132

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Table 8-1. Acronyms, Abbreviations, and Definitions (continued)

ACRONYM OR

ABBREVIATION

DEFINITION

SMPS

SPI

Switched Mode Power Supply

Serial Peripheral Interface

Power-On Reset

POR

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, CSD87330Q3D Synchronous Buck NexFET™ Power Block data sheet

Texas Instruments, Empowering Designs With Power Management IC (PMIC) for Processor

Applications application report

•

Texas Instruments, Basic Calculation of a Buck Converter's Power Stage application report

Texas Instruments, TPS65911x Schematic Checklist

Texas Instruments, TPS65911 Layout Guidelines

Texas Instruments, TPS65911A User's Guide for 66AK2G12 Processor

Texas Instruments, TPS659114 for Freescale i.MX6 Dual/Quad User's Guide

Texas Instruments, TPS659118 User’s Guide for 66AK2G02 Processor

Texas Instruments, TPS6591133 Centaurus User Guide

Texas Instruments, TPS659113 Centaurus User Guide

Texas Instruments, TPS659112 Netra User Guide

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the

upper right corner, click on Alert me to register and receive a weekly digest of any product information that

has changed. For change details, review the revision history included in any revised document.

8.4 Community Resources

8.4.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools

and contact information for technical support.

8.5 Trademarks

MicroStar Junior, OMAP, NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Device and Documentation Support

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8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 Package Description

The following table lists the package descriptions for the TPS65911 PMU devices:

PACKAGE

TPS65911

Type

ZRC98 BGA MicroStar Junior™

Size (mm)

6 × 9

1 layer

0.65 mm

98

Substrate layers

Pitch ball array (mm)

Number of balls

Thickness (mm) (maximum height including balls)

1 mm

134

Mechanical, Packaging, and Orderable Information

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PACKAGE MATERIALS INFORMATION

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14-Jan-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS6591102A2ZRCR

BGA MI

CROSTA

R JUNI

OR

ZRC

98

2500

330.0

16.4

6.3

9.3

1.5

12.0

16.0

Q1

TPS6591104A2ZRCR

BGA MI

CROSTA

R JUNI

OR

2500

TPS6591104EA2ZRCR BGA MI

CROSTA

R JUNI

OR

TPS6591106A2ZRCR

TPS6591109A2ZRCR

TPS659110A2ZRCR

BGA MI

CROSTA

R JUNI

OR

BGA MI

CROSTA

R JUNI

OR

BGA MI

CROSTA

R JUNI

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jan-2020

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OR

TPS659112A2ZRCR

TPS6591133A2ZRCR

TPS659113A2ZRCR

TPS659114A2ZRCR

TPS65911AA2ZRCR

TPS65911AA2ZRCT

BGA MI

CROSTA

R JUNI

OR

ZRC

98

2500

250

330.0

16.4

6.3

9.3

1.5

12.0

16.0

Q1

BGA MI

CROSTA

R JUNI

OR

BGA MI

CROSTA

R JUNI

OR

BGA MI

CROSTA

R JUNI

OR

BGA MI

CROSTA

R JUNI

OR

BGA MI

CROSTA

R JUNI

OR

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jan-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS6591102A2ZRCR

BGA MICROSTAR

JUNIOR

ZRC

98

2500

336.6

31.8

TPS6591104A2ZRCR

BGA MICROSTAR

JUNIOR

2500

250

TPS6591104EA2ZRCR BGA MICROSTAR

JUNIOR

TPS6591106A2ZRCR

TPS6591109A2ZRCR

TPS659110A2ZRCR

TPS659112A2ZRCR

TPS6591133A2ZRCR

TPS659113A2ZRCR

TPS659114A2ZRCR

TPS65911AA2ZRCR

TPS65911AA2ZRCT

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

BGA MICROSTAR

JUNIOR

Pack Materials-Page 3

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS659110A2NMAR
厂家：	TEXAS INSTRUMENTS
描述：	TPS65911 Integrated Power Management Unit Top Specification
文件：	总142页 (文件大小：2253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS659110A2NMAR [TI]

相关型号：

TPS659110A2ZRC

TPS659112A2NMAR

TPS659112A2ZRC

TPS6591131A2ZRCR

TPS6591133A2NMA

TPS6591133A2NMAR

TPS659114A2NMAR

TPS659114A2ZRCT

TPS659116A2ZRC

TPS659116A2ZRCR

TPS659118A2ZRCT

TPS659119-Q1