TPS65921BZBHR [TI]
TPS65921 Power Management and USB Single Chip;
| 型号： | TPS65921BZBHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS65921 Power Management and USB Single Chip |
| 文件： | 总66页 (文件大小：737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
TPS65921 Power Management and USB Single Chip
1 Device Overview
1.1 Features
1
– 32-kHz Crystal Oscillator
• Three Step-Down Converters:
– Clock Slicer for 26, 19.2, and 38.4 MHz
– HF Clock Output Buffer
• USB:
– Up to 1.2 A of Output Current for VDD1
•
•
TPS65921B Supports VDD1 up to 1.2 A
TPS65921B1 Supports VDD1 up to 1.4 A
(Necessary for 1-GHz Operation)
– USB HS 2.0 Transceiver
– USB 1.3 OTG-Compliant
– 12-Bit ULPI 1.1 Interface
– USB Power Supply (5-V CP for VBUS)
– SmartReflex™ Dynamic Voltage Management
– 3.2-MHz Fixed Frequency Operation
– VIN Range from 2.7 to 4.5 V
• Control
– Typical 30 µA Quiescent per Converter
• Four General-Purpose Configurable LDOs:
– Dynamic Voltage Scaling
– High-Speed I2C Interface
– All Resource Configurable by I2C
• Keypad Interface up to 8 × 8
• 10-Bit A/D Converter
– 220-mA Maximum Current for One LDO
– VIN Range from 2.7 to 4.5 V
• Hot-Die, Thermal Shutdown Protection
• µ*BGA 120 Balls ZQZ
– 2 LDOs With Low Noise and High PSRR
• RTC With Alarm Wake-Up Mechanism
• Clock Management
1.2 Applications
•
•
•
Mobile Phones and Smart Phones
MP3 Players
•
•
E-Books
OMAP™ and Low-Power DSP Supply
Handheld Devices
1.3 Description
The TPS65921 device is a highly integrated power-management circuit (IC) that supports the power and
peripheral requirements of the OMAP application processors. The device contains power management, a
universal serial bus (USB) high-speed (HS) transceiver, an analog-to-digital converter (ADC), a real-time
clock (RTC), a keypad interface, and an embedded power control (EPC). The power portion of the device
contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple
low-dropout (LDO) regulators, an EPC to manage the power-sequencing requirements of OMAP, and an
RTC module. The USB module provides an HS 2.0 transceiver suitable for direct connection to the OMAP
universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump
(CP).
The device also provides auxiliary modules: ADC, keypad interface, and general-purpose inputs/outputs
(GPIOs) muxed with the JTAG functions. The keypad interface implements a built-in scanning algorithm to
decode hardware-based key presses and to reduce software use, with multiple additional GPIOs that can
be used as interrupts when they are configured as inputs.
Device Information(1)
PART NUMBER
TPS65921ZQZ
PACKAGE
BODY SIZE
ZQZ (120)
6.00 mm × 6.00 mm
(1) For more information, see Section 7, Mechanical Packaging and Orderable Information.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
AGND
VBAT
REFS
TEST/MUXed I/O’s
VDD1_IN
VINTANA2
VRTC
VINTANA1
VDD1_L
VDD1
VDD2
VIO
IO.1P8
DGND
VDD1_FDBK
VDD1_GND
VDD2_IN
SRI2C_SCL
SRI2C_SDA
2
I C Smart-Reflex
VDD2_L
32KXIN
Xtal
32K
VDD2_FDBK
32KXOUT
32KCLKOUT
HFCLKIN
RTC
Clock sys
VDD2_GND
VIO_IN
Clock
slicer
HFCLKOUT
MSECURE
VIO_L
VIO_FDBK
BOOT0
BOOT1
VIO_GND
RESPWRON
NRESWARM
VPLLA3RIN
Power control
PWRON
NSLEEP
Control I/Os
VPLL1OUT
VPLL1
INT
SYSEN
REGEN
CLKEN
VDAC.IN
TESTRESET
CLKREQ
VDAC.OUT
VDAC
CTLI2C_SCL
CTLI2C_SDA
2
I C control
Control, Data
and Test
logic
VMMC1_IN
ADCIN0
10- bit
ADC
VMMC1OUT
VMMC1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
VAUX12SIN
VAUX2_OUT
VAUX2
USB 2.0
OTG
DATA6
DATA7
NXT
DIR
STP
UCLK
ID
VBUS
CP_IN
CP_CAPP
DP
USB
CP
USB
PHY
DM
CP_CAPM
CP_GND
AVSS1
KPD_R0
KPD_R1
KPD_R2
KPD_R3
KPD_R4
KPD_R5
AVSS2
AVSS3
AVSS4
KEY
PAD
VINTDIG
VUSB3P1
VINTUSB1P8
VINTUSB1P5
KPD_R6
KPD_R7
SWCS048-010
Figure 1-1. Functional Block Diagram
2
Device Overview
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Table of Contents
Device Overview ......................................... 1
1
4.18 Battery Threshold Levels............................ 24
4.19 Power Consumption................................. 25
4.20 USB Charge Pump ................................. 25
4.21 Hot-Die Detection and Thermal Shutdown.......... 26
4.22 USB ................................................. 26
4.23 MADC ............................................... 31
4.24 TPS65921 Interface Target Frequencies ........... 33
4.25 JTAG Interfaces ..................................... 36
Detailed Description ................................... 38
5.1 Functional Block Diagram........................... 38
5.2 Clock System ....................................... 39
5.3 32-kHz Oscillator.................................... 39
5.4 Clock Slicer ......................................... 40
5.5 Power Path .......................................... 43
5.6 Charger Detection................................... 54
5.7 MADC ............................................... 57
5.8 JTAG Interfaces ..................................... 58
Device and Documentation Support ............... 60
6.1 Device Support ...................................... 60
6.2 Documentation Support ............................. 61
6.3 Trademarks.......................................... 61
6.4 Electrostatic Discharge Caution..................... 61
6.5 Export Control Notice ............................... 61
6.6 Glossary ............................................. 61
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 2
Revision History ......................................... 4
Terminal Configuration and Functions.............. 5
3.1 Signal Descriptions ................................... 6
Specifications ........................................... 10
4.1 Absolute Maximum Ratings......................... 10
4.2 Handling Ratings.................................... 10
4.3 Recommended Operating Conditions............... 10
2
3
4
5
4.4
Thermal Resistance Characteristics for ZQZ
Package ............................................. 13
4.5 Crystal Oscillator .................................... 13
4.6 Clock Slicer ......................................... 14
4.7 32KCLKOUT Output Clock.......................... 14
4.8 HFCLKOUT Output Clock........................... 15
4.9 VDD1 DC-DC Converter ............................ 17
4.10 VDD2 DC-DC Converter ............................ 18
4.11 VIO DC-DC Converter .............................. 19
4.12 VMMC1 Low Dropout Regulator .................... 20
4.13 VDAC Low Dropout Regulator ...................... 21
4.14 VAUX2 Low Dropout Regulator..................... 22
4.15 VPLL1 Low Dropout Regulator ..................... 23
4.16 Internal LDOs ....................................... 24
4.17 Voltage References ................................. 24
6
7
Mechanical Packaging and Orderable
Information .............................................. 62
7.1 Packaging Information .............................. 62
Copyright © 2010–2014, Texas Instruments Incorporated
Table of Contents
3
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2012) to Revision G
Page
•
Changed the format to the latest TI standards ................................................................................... 1
4
Revision History
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
3 Terminal Configuration and Functions
shows the ball locations for the 120-ball plastic ball grid array (PBGA) package and is used in conjunction
with ball description to locate signal names and ball grid numbers.
1
2
3
4
5
6
7
8
9
10
11
VINTANA2.
OUT
VMODE2/
I2C.SR.SCL
VMMC1.OUT
AVSS4
DIR/GPIO.10 VPLLA3R.IN
VINT.IN
VPLL1.OUT
INT1
IO.1P8
VDD1.GND
A
B
C
D
E
F
A
B
C
D
E
F
I2C.CNTL.
SCL
DATA0/
VRTC.OUT
VINTDIG.
OUT
VMMC1.IN
VDAC.IN
KPD.C3
KPD.C4
KPD.C1
KPD.C2
ADCIN0
KPD.C0
DGND
SYSEN
VDD1.GND
VDD1.L
VDD1.L
VDD1.IN
CLKEN
VREF
VDD1.GND
VDD1.L
UART4.TXD
I2C.CNTL.
SDA
DATA1/ DATA2/
UART4.RXD UART4.RTSI
#N/A
TEST
NXT/GPIO.11
HFCLKIN
CLKREQ
TESTV2
DATA3/
UART4.
UCLK
VINTANA1.
OUT
PWROK2/
12C.SR.SDA
DATA7/
GPIO.5
PWRON
BOOT0
KPD.R7
KPD.R3
KPD.R0
VDD1.OUT
VDD1.IN
CTSO/
GPIO.12
DATA6/
GPIO.4
VDAC.OUT
VAUX12S.IN
VAUX2.OUT
VIO.OUT
KPD.C6
AVSS1
REGEN
VPROG
CP.GND
VBAT
KPD.C5
KPD.C7
KPD.R1
KPD.R2
KPD.R4
NSLEEP1
STP/GPIO.9 NRESPWRON
VDD1.IN
AVSS3
BKBAT
JTAG.TCK/
BOOT1
DATA4/
GPIO.14
DATA5/
GPIO.3
BERCLK
GPIO.2/
TEST1
32KCLKOUT
AVSS2
KPD.R6
MSECURE
32KXOUT
32KXIN
G
H
J
G
H
J
TESTV1
VIO.GND
VIO.IN
STARTADC NRESWARM VDD2.OUT
AGND
VINTUSB1P5. VINTUSB1P8.
OUT
VIO.GND
VIO.L
ID
KPD.R5
TEST.RESET VDD2.GND
VDD2.GND
VDD2.L
OUT
GPIO.1/CD2/
VDD2.IN
VBUS
VBAT.USB
GND_AGND HFCLKOUT
K
L
K
L
JTAG.TMS
DP/UART3.
RXD
DN/UART3. GPIO.0/CD1/
JTAG.TD0
VIO.L
VIO.IN
CP.CAPM
CP.IN
CP.CAPP
VUSB.3P1
VDD2.IN
VDD2.L
TXD
1
2
3
4
5
6
7
8
9
10
11
SWCS048-009
Figure 3-1. Ball Placement (Top View)
Copyright © 2010–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
5
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
3.1 Signal Descriptions
Table 3-1. Signal Descriptions
NAME
BALL
SUPPLIES
TYPE
I/O
DESCRIPTION
PU/PD
ADCIN0
F2
Analog
I/O
General-purpose ADC input
NO
ADC conversion
request/JTAG test data
input
STARTADC
H7
VDDIO/DGND
Digital
I
NO
I2C.CNTL.SDA
I2C.CNTL.SCL
C4
B3
VDDIO/DGND
VDDIO/DGND
Digital
Digital
I/O
I/O
I2C bidirectional data signal
I2C bidirectional clock
signal
External PU
External PU
HS I2C bidirectional data
signal
HS I2C bidirectional Clock
signal
I2C.SR.SDA
I2C.SR.SCL
D4
A3
VDDIO/DGND
VDDIO/DGND
Digital
Digital
I/O
I/O
External PU
External PU
Input detects a control
command to start or stop
the system.
PWRON
D5
VBAT/GND
Digital
I
External PU
Enable signal for external
LDO
REGEN
G3
G8
Digital
Digital
O
I
PU
NO
Security and digital rights
management
MSECURE
VDDIO/DGND
VBAT/GND
Programmable
PD (default
active)
Power-up sequence
selection
BOOT0
E5
F6
E7
Digital
Digital
Digital
I
I
Programmable
PD (default
active)
Power-up sequence
selection
BOOT1
VBAT/GND
Output control the
NRESPWRON of the
application processor
NRESPWRON
VDDIO/DGND
O
NO
NRESWARM
NSLEEP1
H8
K4
VDDIO/DGND
VDDIO/DGND
Digital
Digital
I
I
Warm reset signal
PU
NO
ACTIVE-SLEEP state
transition control signal
INT1
A9
B9
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
Digital
Digital
Digital
O
O
O
Output line interrupt
System enable output
Clock Enable
NO
NO
NO
SYSEN
CLKEN
F10
PD disabled in
ACTIVE state
32KCLKOUT
G6
VDDIO/DGND
Digital
O
32-kHz clock output
32KXOUT
32KXIN
G11
H11
VRTC/REFGND
VRTC/REFGND
Analog
Analog
I
I
32-kHz crystal oscillator
32-kHz crystal oscillator
NO
NO
Sine wave or square wave
input
HFCLKIN
C8
K8
VDDIO/DGND
VDDIO/DGND
Analog
Digital
I
NO
NO
50% duty cycle square
wave output
HFCLKOUT
O
VREF
G10
K7
VREF/REFGND
AGND
Analog
Analog
Analog
Power
O
Bandgap voltage
Substrate ground
Reference ground
Digital ground
NO
NO
NO
NO
GND_AGND
AGND
I/O
I/O
I/O
H10
B8
REFGND
DGND
DGND
Supply for I/O buffers
(VDDIO)
IO.1P8
A10
Power
I
NO
Not used. Must be
grounded
BKBAT
G9
VBACKUP/AGND
Power
Power
Power
I
I
NO
NO
NO
VDD1.IN
VDD1.GND
E9, E10, E11
VDD1 DC-DC input
A11, B10,
B11
VDD1 DC-DC power
ground
I/O
6
Terminal Configuration and Functions
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Table 3-1. Signal Descriptions (continued)
NAME
BALL
SUPPLIES
TYPE
I/O
DESCRIPTION
PU/PD
C10, C11,
D10
VDD1 DC-DC switched
output
VDD1.L
Power
O
NO
VDD1.OUT
VDD2.IN
D11
Analog
Power
I
I
VDD1 feedback voltage
VDD2 DC-DC input
PD
NO
K10, L10
VDD2 DC-DC power
ground
VDD2.GND
VDD2.L
J10, J11
K11, L11
Power
Power
I/O
O
NO
NO
VDD2 DC-DC switched
output
VDD2.OUT
VIO.IN
H9
Analog
Power
Power
I
I
VDD2 feedback voltage
VIO DC-DC input
PD
NO
NO
K2, L2
J1, J2
VIO.GND
I/O
VIO DC-DC power ground
VIO DC-DC switched
output
VIO.L
K1, L1
Power
O
NO
VIO.OUT
H1
F1
G1
A6
Analog
Power
Power
Power
I
I
VIO feedback voltage
VAUX2 LDO input
PD
NO
PD
NO
VAUX12S.IN
VAUX2.OUT
VPLLA3R.IN
O
I
VAUX2 regulator output
VPLL1/VRTC LDO input
VPLL1 LDO regulator
output
VPLL1.OUT
A8
Power
O
PD
VRTC internal LDO
regulator output (internal
use only)
VRTC.OUT
VINT.IN
B5
A7
D1
Power
Power
Power
O
I
PD
NO
PD
VINTDIG LDO input
VINTANA1 internal LDO
regulator output (internal
use only)
VINTANA1.OUT
O
VINTANA2 internal LDO
regulator output (internal
use only)
VINTANA2.OUT
A2
Power
O
PD
VDAC/VINTANA1/VINTAN2
LDO input
VDAC.IN
C1
E1
Power
Power
I
NO
PD
VDAC.OUT
O
VDAC LDO regulator output
VINTDIG internal LDO
regulator output (internal
use only)
VINTDIG.OUT
B7
Power
O
PD
VMMC1 LDO regulator
output
VMMC1.OUT
VBAT.USB
A1
K6
L6
J6
J5
Power
Power
Power
Power
Power
O
I
PD
NO
PD
PD
PD
VINTUSBiP5,VINTUSB1P8,
VUSB.3P1 input regulator
VUSB.3P1 LDO regulator
output
VUSB.3P1
O
O
O
VUSB1P8 LDO regulator
output (internal use only)
VINTUSB1P8.OUT
VINTUSB1P5.OUT
VUSB1P5 LDO regulator
output (internal use only)
TESTV1
TESTV2
H2
C9
Analog
Analog
IO
IO
Analog test pin 1
Analog test pin 2
NO
NO
Selection between JTAG
mode and application mode
TEST
D3
VDDIO/DGND
Digital
IO
PD
AVSS1
AVSS2
AVSS3
AVSS4
VBUS
F3
H6
F9
A4
K5
AGND
AGND
AGND
AGND
Power
Power
Power
Power
Power
I/O
I/O
I/O
I/O
Analog ground
Analog ground
Analog ground
Analog ground
VBUS power rail
NO
NO
NO
NO
NO
Copyright © 2010–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
7
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Table 3-1. Signal Descriptions (continued)
NAME
DP/UART3.RXD
DN/UART3.TXD
ID
BALL
L7
SUPPLIES
TYPE
Analog
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
USB differential data line
USB differential data line
USB ID
PU/PD
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
L8
J7
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
UCLK
D6
E6
A5
C5
B6
C6
C7
HS USB Clock
STP/GPIO.9
HS USB Stop
DIR/GPIO.10
NXT/GPIO.11
DATA0/UART4.TXD
DATA1/UART4.RXD
DATA2/UART4.RTSI
HS USB Direction
HS USB Next
HS USB Data0
HS USB Data1
HS USB Data2
DATA3/UART4.CTSO/
GPIO.12
D7
VDDIO/DGND
Digital
I/O
HS USB Data3
NO
DATA4/GPIO.14
DATA5/GPIO.3
DATA6/GPIO.4
DATA7/GPIO.5
CP.IN
F8
F11
E8
D9
L4
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
Digital
Digital
I/O
I/O
I/O
I/O
I/O
I/O
HS USB Data4
NO
NO
NO
NO
NO
NO
HS USB Data5
Digital
HS USB Data6
Digital
HS USB Data7
Power
Charge pump input voltage
Charge pump ground
CP.GND
J3
Power Gnd
Charge pump flying
capacitor P
CP.CAPP
CP.CAPM
L5
L3
Analog
Analog
I/O
I/O
NO
NO
Charge pump flying
capacitor M
KPD.C0
KPD.C1
KPD.C2
KPD.C3
KPD.C4
KPD.C5
KPD.C6
KPD.C7
KPD.R0
KPD.R1
KPD.R2
KPD.R3
KPD.R4
KPD.R5
KPD.R6
KPD.R7
B4
D2
E2
B2
C2
E4
E3
F4
H5
G4
H4
G5
J4
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
VDDIO/DGND
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Digital
O
O
O
O
O
O
O
O
I
Keypad column 0
Keypad column 1
Keypad column 2
Keypad column 3
Keypad column 4
Keypad column 5
Keypad column 6
Keypad column 7
Keypad row 0
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Digital
I
Keypad row 1
Digital
I
Keypad row 2
Digital
I
Keypad row 3
Digital
I
Keypad row 4
J8
Digital
I
Keypad row 5
G7
F5
Digital
I
Keypad row 6
Digital
I
Keypad row 7
Battery input voltage
(Sense)
VBAT
K3
D8
J9
Power
Digital
Digital
I/O
NO
PD
PD
CLKREQ
TEST.RESET
VDDIO/DGND
VBAT/GND
I
I
Clock request line
Reset the device (except
the state-machine)
Reserved. Must be
grounded.
VPROG
H3
F7
L9
Analog
Digital
Digital
I
I
NO
NO
PD
JTAG/TCK/BERCLK
VDDIO/DGND
VDDIO/DGND
JTAG clock input
GPIO.0/CD1/JTAG.TD
O
JTAG test output or
GPIO0/card detection 1
I/O
GPIO.1/CD2/JTAG.TM
S
JTAG test mode state or
GPIO1/card detection 2
K9
VDDIO/DGND
Digital
I/O
PD
8
Terminal Configuration and Functions
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Table 3-1. Signal Descriptions (continued)
NAME
BALL
SUPPLIES
TYPE
I/O
DESCRIPTION
PU/PD
Programmable
PD
GPIO.2/TEST1
G2
VDDIO/DGND
Digital
I
GPIO/Digital test pin
VMMC1.IN
N/A
B1
C3
Power
N/A
I
VMMC1 input LDO
N/A
NO
N/A
N/A
N/A
Copyright © 2010–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
9
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Main battery supply
voltage(2)
0.0
5.0
V
Where supply represents the voltage
applied to the power supply pin
associated with the input(4)
Voltage on any input(3)
–0.3
1.0 × Supply + 0.3
V
VBUS input
–0.3
–40
7
V
Operating ambient
temperature (TA)
85
°C
Operating junction
temperature (TJ)
Absolute maximum rating
For parametric compliance
–40
–40
–40
125
150
85
°C
°C
°C
Operating junction
temperature (TJ)
Ambient temperature for
parametric compliance
With maximum 125°C as junction
temperature (TJ)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
(2) The product will have negligible reliability impact if voltage spikes of 5.2 V occur for a total (cumulative over lifetime) duration of 10
milliseconds.
(3) Excepts VBAT input pads and VBUS pad.
(4) Supply equals the reference level of each pin.
4.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–55
125
°C
Human Body Model (HBM), per ANSI/ESDA/JEDEC
JS001(1)
–1
1
kV
V
Electrostatic discharge (ESD)
performance:
VESD
Charged Device Model (CDM),
All pins
–250
250
per JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Power and USB Path
HFCLKIN Input Clock
VBAT/VBAT.USB main battery supply voltage and
VBUS
2.7
0
3.6
4.5
7
V
V
Frequency 1/tC(HFCLKIN)
19.2, 26 or 38.4
MHz
ns
0.55 ×
tC(HFCLKIN)
Pulse duration, HFCLKIN low or high (BP)
0.45 × tC(HFCLKIN)
HFCLKIN stability
–150
0
150
5
ppm
ns
Rise time of HFCLKIN (BP)
Fall time of HFCLKIN (BP)
0
5
ns
LP/HP (sine wave)
Input dynamic range
0.3
0
0.7
1.45
1.85(1)
Vpp
Vpp
BP/PD (square wave)
Harmonic content of input signal (with 0.7-VPP amplitude): Second
component - LP/HP (sine wave)
–25
dBc
V
VIH voltage input
BP (square mode)
high(1)
0.65 × IO.1P8
(1) Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
10 Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VIL voltage input low(1) BP (square mode)
0.35 × IO.1P8
V
Crystal Oscillator
Parallel resonance crystal frequency 1/tC(32KHZ)
Input voltage, Vin (normal mode)
Crystal tolerance at room temperature, 25°C
Crystal tolerance versus temperature range (–40°C to 85°C)
Crystal quality factor
32.768
1.3
kHz
V
1.0
–30
–200
13k
1.55
30
ppm
ppm
200
54k
1
Maximum drive power
µW
µW
Operating drive level
0.5
32KXIN 32KXOUT
duty cycle
Crystal
40%
45%
60%
55%
Square wave
32-kHz clock rise/fall
time
Square wave with capacitive load equivalent to
30 pF
Square wave in bypass mode(2)
Square wave in bypass mode(2)
0.1 × tC(32KHZ)
0.35 × VBRTC
4.5
µs
VIH voltage input high
VIL voltage input low
0.65 × VBRTC
V
V
DC-DC Converters and LDOs
VDD1.IN, VDD2.IN, VDD3.IN input voltage range for step-down converter
VDD1, VDD2, VIO
2.7
3.6
V
Maximum (2.7,
output voltage
selected + 250 mV)
VMMC1.IN input voltage range for LDO VMMC1
VDAC.IN input voltage range for LDO VDAC
VAUX12S.IN input voltage range for LDO VAUX2
3.6
3.6
3.6
4.5
4.5
4.5
V
V
V
2.7
Maximum (2.7,
output voltage
selected + 250 mV)
Maximum (2.7,
output voltage
selected + 200 mV)
VINT.IN input voltage range for LDO VINTANA1, VINTANA2, VINTDIG
and VRTC
3.6
3.6
4.5
V
VPLLA3R.IN input voltage range for LDO VPLL1
2.7
0.6
0.6
4.5
1.45
1.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD1.OUT ouput voltage range for VDD1 step-down converter
VDD2.OUT ouput voltage range for VDD2 step-down converter
VIO.OUT ouput voltage range for VIO step-down converter
VMMC1.OUT output voltage range for LDO VMMC1
VDAC.OUT output voltage range for LDO VDAC
1.8/1.85
1.85
1.2
3.15
1.8
VAUX2.OUT output voltage range for LDO VAUX2
VPLL1.OUT output voltage range for LDO VPLL1
VINTANA1.OUT output voltage for LDO VINTANA1
VINTANA2.OUT output voltage for LDO VINTANA2
VINTUSB1P5V.OUT output voltage for LDO VINTUSB1P5
VINTUSB1P8V.OUT output voltage for LDO VINTUSB1P8
VUSB3P1V.OUT output voltage for LDO VUSB3P1
VINTDIG.OUT output voltage range for LDO VINTDIG
1.3
2.8
1.0
1.8
1.5
2.5/2.75
1.5
1.35
1.62
1.65
1.98
1.8
3.1
1.35
1.45
1.0
1.5
1.65
1.55
1.55
Normal mode
Backup mode
1.5
VRTC.OUT output
voltage range
1.3
External Components
Crystal: Nominal load cap on each oscillator input CXIN and CXOUT (3)
9
10
12.5
pF
(2) Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
(3) Nominal load capacitor on each oscillator input defined as CXIN = CXOUT = Cosc × 2 – (Cint + Cpin). Cosc is the load capacitor
defined in the crystal oscillator specification, Cint is the internal capacitor, and Cpin is the parallel input capacitor.
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
11
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Crystal ESR (4)
MIN
TYP
MAX
90
UNIT
kΩ
pF
µH
Ω
Crystal shunt capacitance, CO
Value
1
0.7
1
1.3
0.1
DCR
External coil for VDD1
Saturation current for TPS65921B
1.8
2.1
0.7
A
Saturation current for TPS65921B1
Value
A
1
1.3
0.1
µH
Ω
External coil for VDD2
and VIO
DCR
Saturation current
Value(5)
900
5
mA
μF
External capacitor for
VDD1, VDD2, VIO
connected to VDD1.IN,
VDD2.IN, VDD3.IN,
and VDD1.OUT,
10
15
20
ESR at switching frequency
1
mΩ
VDD2.OUT, VIO.OUT
Filtering capacitor for Value
VMCC1.IN, VDAC.IN,
VAUX12S.IN,
0.3
1
2.7
µF
VPPLA3R.IN, VINT.IN,
VBAT.USB,
VMMC1.OUT,
VDAC.OUT,
ESR
20
600
mΩ
VAUX2.OUT, VPPL1,
VINTDIG, VINTANA1,
VINTANA2, VRRTC
Filtering capacitor for Value
VUSB3V1, VUSB1V8,
VUSB1V5
0.5
20
2.2
1
6.5
µF
ESR
600
mΩ
Filtering capacitor for
voltage reference
Connected from VREF to REFGND
0.3
2.7
6.5
µF
µF
1.41 (The minimum
can be reduced to
1.2 µF, provided the
charge-pump is only
used to supply
Filtering capacitor (Connected between
VBUS.CPOUT and GND) and called CVBUS
4.7
2.2
VUSB3V1 LDO)
1.32 (The minimum
can be reduced to
External capacitor for
charge pump and
VBUS
Flying capacitor (Connected between CP.CAPP 1.2 µF, provided the
and CP.CAPM) called CVBUS.FC
3.08
µF
charge-pump is only
used to supply
VUSB3V1 LDO)
Filtering capacitor ESR for CVUSB.IN and
CVBUS.FC
20
15
mΩ
µF
Filtering capacitor CVBUS.IN
5
10
1
External capacitor for
power reference filter
Filtering capacitor
0.3
2.7
µF
(4) The crystal motional resistance Rm relates to the equivalent series resistance (ESR) by the following formula:
æ
ö2
÷
C0
ESR= R 1+
m ç
CL ø
è
Measured with the load capacitance specified by the crystal manufacturer. In fact, if CXIN = CXOUT = 10 pF, then CL = 5 pF. Parasitic
capacitance from the package and board must also be considered.
(5) For TPS65921B1, in case of OMAP frequency ≥ 1 GHz, replace 10-µF capacitor on VDD1.OUT by two 22-µF capacitors. One capacitor
must be placed near the PMIC and one near the OMAP device.
12
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.4 Thermal Resistance Characteristics for ZQZ Package
NAME
RΘJC
RΘJB
RΘJA
PsiJT
PsiJB
DESCRIPTION
°C/W(1) (2)
AIR FLOW (m/s)(3)
Junction-to-case
20
17
46
0.3
16
0.00
0.00
0.00
0.00
0.00
Junction-to-board
Junction-to-free air
Junction-to-package top
Junction-to-board
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(3) m/s = meters per second.
4.5 Crystal Oscillator
When selecting a crystal, the system designer must consider the temperature and aging characteristics of a
crystal versus the user environment and expected lifetime of the system. The following table lists the switching
characteristics of the oscillator.
Table 4-1. Base Oscillator Switching Characteristics
PARAMETER
Crystal: Internal capacitor on each input (Cint)
Crystal: Parallel input capacitance (Cpin)
Parallel resonance crystal frequency
Pin-to-pin capacitance
MIN
TYP
MAX
12
UNIT
pF
8
10
1.0
pF
32.768
1.6
kHz
pF
1.8
1.0
0.5
54k
500
360
1.8
0.8
Maximum drive power
µW
µW
Operating drive level
Crystal quality factor
13k
Start-up time, all conditions
tSX
ms
µA
µA
Start-up time, 25°C
Active current
High jitter mode
Low jitter mode
IDDA
consumption (configured
through the LOJIT bit)
Low battery mode (1.2 V)
Startup
1
8
IDDQ
Current consumption
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
13
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.6 Clock Slicer
PARAMETER
MODE(1)
MIN
4.2
15
TYP
MAX
5.7
60
UNIT
pF
Internal coupling capacitor
5
LP
HP
kΩ
Parallel input resistance over 10 to 40 MHz range
Parallel input capacitance over 10 to 40 MHz range
30
75
kΩ
BP/PD
LP
1
100
0.8
0.7
1
MΩ
0.3
0.3
0.08
40
HP
pF
BP/PD
BP/PD
LP/HP
LP
230
60%
18
Output duty cycle with VIN = 0.2 VPP
Propagation delay
40%
4
50%
HP
3
15
ns
BP/PD
LP/HP
0.2
26
3
Power supply rejection ratio sideband (1% RMS of supply voltage added
sine 5 MHz)
dBc
LP
175
235
39
µA
µA
nA
ms
Current consumption at maximum input of 40 MHz
Power-up time
HP
BP/PD
LP/HP
1
Output peak-to-peak jitter with an input peak-to-peak jitter < 0.1% and for
jitter frequency below 300 kHz
LP/HP
LP/HP
0.2%
1.0%
Output peak-to-peak jitter with an input peak-to-peak jitter < 0.1% and for
jitter frequency above 300 kHz
(1) Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface.
4.7 32KCLKOUT Output Clock
NAME
PARAMETER DESCRIPTION
MIN
TYP
MAX
UNIT
kHz
pF
f
Frequency
32.768
CL
Load capacitance
40
VOUT
Output clock voltage, depending on output
reference level IO.1P8
1.8(1)
V
VOH
VOL
Voltage output high
Voltage output low
VOUT – 0.45
0
VOUT
0.45
V
V
(1) The output voltage depends on output reference level which is IO.1P8.
The following table details the output clock timing characteristics. The following figure shows the 32KCLKOUT
output clock waveform.
NAME
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
CK0
1/tC(32KCLKOUT)
Frequency
32.768
kHz
CK1
Pulse duration,
32KCLKOUT low or high
0.40 ×
tC(32KCLKOUT)
0.60 ×
tC(32KCLKOUT)
tW(32KCLKOUT)
ns
CK2
CK3
tR(32KCLKOUT)
tF(32KCLKOUT)
Rise time, 32KCLKOUT (1)
Fall time, 32KCLKOUT (1)
16
16
ns
ns
At 1-kHz offset from the
carrier
SSB Phase Noise
–110
dBc/Hz
(1) The output capacitive load is equivalent to 30 pF.
CK0
CK1
CK1
32KCLKOUT
SWCS048-001
Figure 4-1. 32KCLKOUT Output Clock
14
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.8 HFCLKOUT Output Clock
The following table summarizes the HFCLKOUT output clock electrical characteristics.
Table 4-2. HFCLKOUT Output Clock Electrical Characteristics
NAME
PARAMETER DESCRIPTION
Frequency
MIN
TYP
MAX
UNIT
MHz
pF
f
19.2, 26, or 38.4
CL
Load capacitance
30
VOUT
Output clock voltage, depending on
output reference level IO.1P8
1.8(1)
V
VOH
VOL
Voltage output high
Voltage output low
VOUT – 0.45
0
VOUT
0.45
V
V
(1) The output voltage depends on output reference level which is IO.1P8.
The following table details the HFCLKOUT output clock timing characteristics.
Table 4-3. HFCLKOUT Output Clock Switching Characteristics
NAME
CHO1
PARAMETER
DESCRIPTION
Frequency
MIN
TYP
MAX
UNIT
1/tC(HFCLKOUT)
19.2, 26, or 38.4
MHz
Pulse duration, HFCLKOUT low
or high
0.4 ×
tC(HFCLKOUT)
0.6 ×
tC(HFCLKOUT)
CHO2
tW(HFCLKOUT)
ns
Rise time, HFCLKOUT, low
drive(1)
- Load: 5 pF
3.8
5.5
- Load: 10 pF
CHO3
tR(HFCLKOUT)
ns
Rise time, HFCLKOUT, high
drive(1)
- Load: 10 pF
- Load: 20 pF
2.9
5.0
Fall time, HFCLKOUT, low
drive(1)
- Load: 5 pF
3.5
5.1
- Load: 10 pF
CHO4
tF(HFCLKOUT)
ns
Fall time, HFCLKOUT, high
drive(1)
- Load: 10 pF
- Load: 20 pF
2.7
4.7
(1) Low drive: MISC_CFG[CLK_HF_DRV] = 0 (default)
High drive: MISC_CFG[CLK_HF_DRV] = 1
Figure 4-2 shows the HFCLKOUT output clock waveform.
CHO1
CHO1
CHO2
HFCLKOUT
SWCS048-002
Figure 4-2. HFCLKOUT Output Clock
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
15
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Figure 4-3 shows the 32KCLKOUT and HFCLKOUT clock stabilization time.
XIN
Starting_Event
Tstartup
CLK32KOUTEN
CLK32KOUT
CLKEN
Delay1
HFCLKOUTEN
HFCLKOUT
Delay2
NRESPWRON
SWCS048-003
A. Tstartup, Delay1, Delay2, and Delay3 depend on the boot mode (See Power timing chapter).
Figure 4-3. 32KCLKOUT and HFCLKOUT Clock Stabilization Time
HFCLKIN
HFCLKOUT
SWCS048-004
Figure 4-4. HFCLKOUT Behavior
16
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.9 VDD1 DC-DC Converter
PARAMETER
COMMENTS
MIN
2.7
TYP
MAX
4.5
UNIT
V
Input voltage range
3.6
Output voltage
0.6
1.45
V
Output voltage step
Output accuracy(1)
0.6 to 1.45 V
0.6 to < 0.8 V
12.5
mV
–6%
–5%
6%
5%
0.8 to 1.45 V
Switching frequency
3.2
MHz
IO = 10 mA, sleep
82%
85%
80%
75%
100 mA < IO < 400 mA
400 mA < IO < 600 mA
600 mA < IO < 800 mA
Conversion efficiency(2)
Active mode
Output voltage 0.6 V to 1.45 V
for TPS65921B/TPS65921B1
1.2
1.4
A
A
Output current
Active mode
Output Voltage 1.2 V to 1.45 V
for TPS65921B1
Sleep mode
10
3
mA
µA
Off at 30°C
Ground current (IQ)
Sleep, unloaded
Active, unloaded, not switching
VIN = VMAX
30
50
300
Short-circuit current
Load regulation
2.2
A
0 < IO < IMAX
20
50
10
10
mV
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
Transient load regulation at 1.2 A(3)
Line regulation
–65
mV
mV
mV
300 mVPP ac input, 10-μs rise and fall
time
Transient line regulation
Start-up time
0.25
< 10
8
1
ms
µs
Recovery time
Slew rate (rising or falling)(4)
From sleep to on with constant load
100
16
4
mV/µs
mV
Active (PWM and PSM)
Sleep (PFM)
–10
–2%
10
Output ripple
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
mA
Overshoot
Softstart
5%
Output pulldown resistance
In Off mode
500
700
Ω
(1) Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process).
(2) VBAT = 3.6 V, VDD1 = 1.2 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
(3) For negative transient load, the output voltage must discharge completely and settle to its final value within 100 ms. Transient load is
specified at Vout max with a ±50% external capacitor accuracy and includes temperature and process variation.
(4) Load current varies proportional to the output voltage. The slew rate is for increasing and decreasing voltages and the load current is 1.1
A.
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
17
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.10 VDD2 DC-DC Converter
PARAMETER
COMMENTS
MIN
2.7
TYP
3.6
MAX
4.5
UNIT
V
Input voltage range
Output voltage
0.6
1.0
1.5
V
Output voltage step
Output accuracy(1)
0.6 to 1.45 V
12.5
mV
0.6 to < 0.8 V
0.8 to 1.45 V
–6%
–5%
6%
5%
Switching frequency
3.2
MHz
IO = 10 mA, sleep
100 mA < IO < 300 mA
300 mA < IO < 500 mA
Active mode
82%
85%
80%
Conversion efficiency(2)
600
10
1
mA
mA
Output current
Sleep mode
Off at 30°C
Ground current (IQ)
Sleep, unloaded
Active, unloaded, not switching
VIN = VMAX
30
50
300
µA
Short-circuit current
Load regulation
1.2
A
0 < IO < IMAX
20
50
10
10
mV
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
Transient load regulation(3)
Line regulation
–65
mV
mV
mV
300 mVPP ac input, 10-μs rise and fall
time
Transient line regulation
Output pulldown resistance
Start-up time
In OFF mode
500
0.25
25
700
1
Ω
ms
Recovery time
Slew rate (rising or falling)(4)
From sleep to on with constant load
100
16
µs
4
8
mV/µs
mV
Active (PWM and PSM)
Sleep (PFM)
–10
–2%
10
Output ripple
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
5%
mA
Overshoot
Softstart
(1) Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process).
(2) VBAT = 3.8 V, VDD1 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
(3) Output voltage must be able to discharge the load current completely and settle to its final value within 100 μs.
(4) Load current varies proportional to the output voltage. The slew rate is for increasing and decreasing voltages and the load current is 1.1
A.
18
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.11 VIO DC-DC Converter
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
Input voltage range
2.7
3.6
4.5
V
1.8
1.85
Output voltage(1)
V
DC accuracy only
–3%
–4%
3%
4%
Including all variations (line and load
regulations, line and load transients,
temperature, and process)
Output accuracy
Switching frequency
3.2
MHz
IO = 10 mA, sleep
100 mA < IO < 400 mA
400 mA < IO < 600 mA
On mode
85%
85%
80%
Conversion efficiency(2)
700
10
1
mA
mA
Output current
Sleep mode
Off at 30°C
Ground current (IQ)
Sleep, unloaded
Active, unloaded, not switching
0 < IO < IMAX
30
50
300
20
10
µA
Load regulation
Line regulation
mV
mV
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
Transient load regulation
Transient line regulation
–65
50
10
mV
mV
300 mVPP ac input, 10-μs rise and fall
time
Start-up time
0.25
< 10
8
1
ms
µs
Recovery time
From sleep to on with constant load
100
16
Slew rate (rising or falling)
4
mV/µs
mV
Active (PWM and PSM)
Sleep (PFM)
–10
–2%
10
Output ripple
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
mA
Overshoot
Softstart
5%
Output pulldown resistance
In Off mode
500
700
Ω
(1) This voltage is tuned according to the platform and transient requirements.
(2) VBAT = 3.8 V, VIO = 1.8 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Specifications
19
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.12 VMMC1 Low Dropout Regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
2.7
3.6
5.5
V
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
1.7945
2.7645
2.91
1.85
2.85
3.0
1.9055
2.9355
3.09
VOUT
V
3.0555
3.15
3.2445
On mode
220
5
IOUT
Rated output current
mA
Low-power mode
On mode: 0 < IO < IMAX
DC load regulation
DC line regulation
20
mV
mV
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
IOUT = 0, CL = 1 μF (within 10%
Turn-on time
Wake-up time
100
10
µs
µs
of VOUT
)
Full load capability
f < 10 kHz
50
40
25
10 kHz < f < 100 kHz
f = 1 MHz
Ripple rejection
dB
VIN = VOUT + 1 V, IO = IMAX
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
Low-power mode, IOUT = 5 mA
Off mode at 55°C
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
70
290
17
Ground current
µA
20
1
VDO
Dropout voltage(1)
250
mV
mV
Transient load regulation(2)
–40
250
40
10
Slew: 40 mA/μs
VIN drops 500 mV
Slew: 40 mV/μs
Transient line regulation
mV
Overshoot
Softstart
3%
Pulldown resistance
Default in off mode
320
450
Ω
(1) For nominal output voltage
(2) Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
20
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.13 VDAC Low Dropout Regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
2.7
3.6
4.5
V
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
1.164
1.261
1.746
12
1.3
1.8
1.236
1.339
1.854
VOUT
V
On mode
70
5
IOUT
Rated output current
mA
Low-power mode
DC load regulation
DC line regulation
On mode: 0 < IO < IMAX
20
mV
mV
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
IOUT = 0, CL = 1 μF (within 10% of
Turn-on time
Wake-up time
100
10
µs
µs
VOUT
)
Full load capability
f < 20 kHz
65
45
40
20 kHz < f < 100 kHz
f = 1 MHz
Ripple rejection
Output noise
dB
VIN = VOUT + 1 V, IO = IMAX
200 Hz < f < 5 kHz
5 kHz < f < 400 kHz
400 kHz < f < 10 MHz
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
Low-power mode, IOUT = 1 mA
Off mode at 55°C
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
400
125
50
nV/√Hz
150
350
15
Ground current
µA
25
1
VDO
Dropout voltage(1)
250
mV
mV
Transient load regulation(2)
–40
250
40
10
Slew: 60 mA/μs
VIN drops 500 mV
Slew: 40 mV/μs
Transient line regulation
mV
Overshoot
Softstart
3%
Pull down resistance
Default in off mode
320
450
Ω
(1) For nominal output voltage
(2) Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
21
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.14 VAUX2 Low Dropout Regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
2.7
3.6
4.5
V
1.3
1.5
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.8
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
VOUT
–3%
+3%
V
On mode
100
5
IOUT
Rated output current
mA
Low-power mode
DC load regulation
DC line regulation
On mode: 0 < IO < IMAX
20
mV
mV
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
IOUT = 0, CL = 1 μF (within 10% of
Turn-on time
Wake-up time
100
10
µs
µs
VOUT
)
Full load capability
f < 10 kHz
50
40
30
10 kHz < f < 100 kHz
f = 1 MHz
Ripple rejection
dB
VIN = VOUT + 1 V, IO = IMAX
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
Low-power mode, IOUT = 5 mA
Off mode at 55°C
70
170
17
Ground current
µA
20
1
VDO
Dropout voltage(1)
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
250
mV
mV
Transient load regulation(2)
–40
40
10
Slew: 40 mA/μs
VIN drops 500 mV
Transient line regulation
Overshoot
mV
Slew: 40 mV/μs
Softstart
3%
Default in off mode
Configurable as HighZ in off mode
250
100
320
450
Ω
Pulldown resistance
MΩ
(1) For nominal output voltage
(2) Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
22
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.15 VPLL1 Low Dropout Regulator
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
3.6
1.0
1.2
1.3
1.8
MAX
4.5
UNIT
VIN
Input voltage
V
0.97
1.03
1.236
1.339
1.854
40
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
1.164
1.261
1.746
VOUT
V
On mode
IOUT
Rated output current
mA
Low-power mode
5
DC load regulation
DC line regulation
On mode: 0 < IO < IMAX
20
mV
mV
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
IOUT = 0, CL = 1 μF (within 10% of
Turn-on time
Wake-up time
100
10
µs
µs
VOUT
)
Full load capability
f < 10 kHz
50
40
30
10 kHz < f < 100 kHz
f = 1 MHz
Ripple rejection
dB
VIN = VOUT + 1 V, IO = IMAX
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode, IOUT = 0
Low-power mode, IOUT = 1 mA
Off mode at 55°C
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
70
110
15
Ground current
µA
16
1
VDO
Dropout voltage(1)
250
mV
mV
Transient load regulation(2)
–40
250
40
10
Slew: 60 mA/μs
VIN drops 500 mV
Slew: 40 mV/μs
Transient line regulation
mV
Overshoot
Softstart
3%
Pulldown resistance
Default in off mode
320
450
Ω
(1) For nominal output voltage
(2) Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
23
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.16 Internal LDOs
Internal LDOs (except USBCP, which is a boost) are described in following table.
NAME
USAGE
TYPE
VOLTAGE RANGE
(V)
DEFAULT
VOLTAGE (V)
MAXIMUM
CURRENT
VINTANA1
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
LDO
LDO
1.5
2.5, 2.75
1.5
1.5
2.75
1.5
5
50 mA
VINTANA2
VINTDIG
USBCP
250 mA
100 mA
100 mA
30 mA
LDO
Charge pump
LDO
5
VUSB1V5
VUSB1V8
VUSB3V1
VRRTC
1.5
1.5
1.8
3.1
1.5
1.3
LDO
1.8
30 mA
LDO
3.1
14 mA
LDO
1.5
30 mA
VBRTC
LDO
1.3
100 μA
4.17 Voltage References
PARAMETER
TEST CONDITONS
MIN
TYP
MAX
UNIT
Internal bandgap reference
voltage
On mode, measured through
TESTV terminal
1.272
1.285
1.298
V
Reference voltage (VREF
terminal)
On mode
On mode
0.7425
0.75
0.7575
V
Retention mode reference
IREF NMOS sink
0.492
0.9
0.5
1.0
0.508
1.1
25
V
µA
Bandgap
IREF block
20
Ground current
Preregulator
VREF buffer
15
µA
10
Retention reference buffer
100 Hz
10
Output spot noise
A-weighted noise (rms)
P-weighted noise (rms)
Integrated noise
1
μV/√Hz
nV (rms)
nV (rms)
µV
200
150
2.2
20 Hz to 100 kHz
IBIAS trim bit LSB
Ripple rejection
0.1
1
µA
< 1 MHz from VBAT
60
dB
Start-up time
ms
4.18 Battery Threshold Levels(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Main battery charged
threshold VMBCH
Measured on VBAT terminal
3.14
3.2
2.7
3.3
V
Main battery low threshold
VMBLO
Measured on VBAT terminal (monitored
on terminal ONNOFF)
2.55
2.8
V
Main battery high threshold
VMBHI
Measured on terminal VBAT
Measured on terminal VBAT
2.5
1.6
2.65
1.8
3.0
2.6
2.6
V
V
V
Batteries not present
threshold VBNPR
Measured on terminal VBAT in slave
mode
1.95
2.1
(1) Backup ball must always be tied to ground.
24
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.19 Power Consumption
The typical power consumption is obtained in the nominal operating conditions and with the TPS65921
standalone.
TYPICAL
CONSUMPTION
MODE
DESCRIPTION
The phone is apparently off for the user, a
main battery is present and well-charged.
The RTC registers, registers in backup
domain are maintained. The wakeup
capabilities (like the PWRON button) are
available.
VBAT = 3.8 V and
Quartz present
64 µA × 3.8 V =
C021 boot mode
WAIT-ON
243.2 μW
ACTIVE No Load
HFCLK = 26 MHz
Subsystem is powered by the main battery.
All supplies are enabled with no external
load, internal reset is released, and the
associated processor is running. USB
interrupt handler consumes 433 µA (typ).
(2995 + 433) µA ×
3.8 V = 13026 µW
VBAT = 3.8 V
VBAT = 3.8 V
ACTIVE No Load
HFCLK = 38.4 MHz
(3879 + 433) µA ×
3.8 V = 16386 µW
The main battery powers subsystem.
Selected supplies are enabled but in low-
consumption mode and associated
processor is in low-power mode.
492 µA × 3.8 V =
1870 µW
SLEEP No Load
4.20 USB Charge Pump
PARAMETER
TEST CONDITIONS
MIN
2.7
4.625
0
TYP
3.6
MAX
4.5
UNIT
V
VIN
VO
Input voltage
On mode: VIN = VBAT
Output voltage
5.0
5.25
100
50
V
VBAT > 3 V at VBUS
Iload
Rated output current
mA
2.7 V < VBAT < 3 V, at VBUS
ILOAD = 100 mA, VBAT = 3.6 V
ILOADmax/2 to ILOADmax in 5 μs
0
Efficiency
Setting time
55%
100
400
3
µs
ms
mA
mV
Start-up time
Short-circuit limitation current
DC load regulation
250
350
250
450
500
ILOADmin to ILOADmax
3.0 V to VBATmax
DC line regulation
250
300
350
350
mV
ILOAD = 100 mA
IVBUS_5Vmax/2 – IVBUS_5Vmax
50 μs, C = 2 × 4.7 μF
Transient load regulation
Transient line regulation
mV
mV
0 – IVBUS_5Vmax/2, 50 μs, C = 2
× 4.7 μF
350
350
VBATmin to VBATmax in 50 μs,
C = 2 × 4.7 μF
300
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
25
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.21 Hot-Die Detection and Thermal Shutdown
PARAMETER
THRESHOLD (NOMINAL)(1)
Threshold (nominal)(1)
Thermal hot-die selection THERM_HDSEL[1:0]
Rising temp: 120°C
00 (1st hot-die threshold)
01 (2nd hot-die threshold)
Falling temp: 111°C
Rising temp: 130°C
Falling temp: 121°C
Rising temp: 140°C
10 (3rd hot-die threshold)
11 (4th hot-die threshold)
Thermal shutdown enable
Falling temp: 131°C
Not used
Threshold (nominal)(1) - Rising temp: 150°C
Threshold (nominal)(1) - Falling temp: 140°C
(1) The minimum/maximum range is ±5%
4.22 USB
4.22.1 LS/FS Single-Ended Receivers
PARAMETER
COMMENTS
USB Single-Ended Receivers
Driver outputs unloaded
MIN
TYP
MAX
UNIT
Skew
SKWVP_VM
between VP
and VM
–2
0
2
ns
Single-ended VSE_HYS
hysteresis
50
2
mV
High (driven) VIH
V
V
Low
VIL
0.8
2
Switching
threshold
VTH
0.8
V
4.22.2 LS/FS Differential Receiver
PARAMETER
COMMENTS
MIN
TYP
TYP
MAX
UNIT
Differential input sensitivity
VDI
Ref. USB2.0
200
mV
Differential common mode
range
VCM
Ref. USB2.0
0.8
2.5
V
4.22.3 LS/FS Transmitter
PARAMETER
COMMENTS
MIN
0
MAX
300
3.6
UNIT
mV
V
Low
VOL
Ref. USB2.0
Ref. USB2.0
High (driven)
VOH
VCRS
2.8
Output signal crossover
voltage
Ref. USB2.0, covered by eye
diagram
1.3
2.0
V
Rise time
Fall time
TFR
75
75
300
300
ns
ns
TFF
Ref. USB2.0, covered by eye
diagram
Differential rise and fall time
matching
TFRFM
80%
125%
Low-speed data rate
TFDRATE
Ref. USB2.0, covered by eye
diagram
1.4775
1.5225
Mbps
ns
Source jitter total (including
frequency tolerance):
- To next transition
TDJ1
TDJ2
Ref. USB2.0, covered by eye
diagram
–25
–10
25
10
- For paired transitions
26
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
Source SE0 interval of EOP
TFEOPT
VCM
Ref. USB2.0, covered by eye
diagram
1.25
1.5
µs
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Differential common mode
range
Ref. USB2.0
0.8
2.5
V
4.22.4 FS Transmitter
PARAMETER
COMMENTS
Ref. USB2.0
MIN
0
TYP
MAX
300
3.6
UNIT
mV
V
Low
VOL
High (driven)
VOH
Ref. USB2.0
2.8
Output signal crossover
voltage
VCRS
Ref. USB2.0, covered by eye
diagram
1.3
2.0
V
Rise time
Fall time
TFR
Ref. USB2.0
Ref. USB2.0
4
4
20
20
ns
ns
TFF
Differential rise and fall time
matching
TFRFM
Ref. USB2.0, covered by eye
diagram
90%
28
111.11%
44
Driver output resistance
Full-speed data rate
ZDRV
Ref. USB2.0
Ω
TFDRATE
Ref. USB2.0, covered by eye
diagram
11.97
12.03
Mbps
Source jitter total (including
frequency tolerance):
- To next transition
TDJ1
Ref. USB2.0, covered by eye
diagram
–2
–1
2
1
ns
ns
- For paired transitions
TDJ2
Source SE0 interval of EOP
TFEOPT
Ref. USB2.0, covered by eye
diagram
160
175
Downstream eye diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
4.22.5 HS Differential Receiver
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
High-speed squelch detection VHSSQ
threshold (differential signal
amplitude)
Ref. USB2.0
100
150
mV
High-speed disconnect
detection threshold
(differential signal amplitude)
VHSDSC
Ref. USB2.0
525
–50
625
V
High-speed differential input
signaling levels
Ref. USB2.0, specified by
eye pattern templates
mV
mV
ps
High-speed data signaling
common mode voltage range
(guidelines for receiver)
VHSCM
Ref. USB2.0
600
150
Receiver jitter tolerance
Ref. USB2.0, specified by
eye pattern templates
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
27
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.22.6 HS Transmitter
PARAMETER
COMMENTS
Ref. USB2.0
MIN
TYP
MAX
UNIT
High-speed idle level
VHSOI
–10
10
mV
High-speed data signaling
high
VHSOH
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
Ref. USB2.0
360
–10
700
–825
500
500
440
10
mV
mV
mV
mV
High-speed data signaling
low
VHSOL
VCHIRPJ
VCHIRPK
THSR
Chirp J level (differential
voltage)
1100
–500
Chirp K level (differential
voltage)
Rise Time (10% – 90%)
Ref. USB2.0, covered by eye
diagram
Fall time (10% – 90%)
THSR
Ref. USB2.0, covered by eye
diagram
Driver output resistance
(which also serves as high-
speed termination)
ZHSDRV
Ref. USB2.0
40.5
49.5
Ω
High-speed data range
THSDRAT
Ref. USB2.0, covered by eye
diagram
479.76
480.24
Mbps
Data source jitter
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
Ref. USB2.0, covered by eye
diagram
4.22.7 UART Transceiver
PARAMETER
MIN
MAX
UNIT
tPH_DP_CON
tPH_DISC_DET
fUART_DFLT
Phone D+ connect time
100
150
ms
ms
Phone D+ disconnect time
Default UART signaling rate (typical rate)
9600
TYP
bps
PARAMETER
COMMENTS
MIN
MAX
UNIT
UART Transmitter CEA-2011
DP_PULLDOWN asserted
ISOURCE = 4 mA
Phone UART edge rates
Serial interface output high
Serial interface output low
tPH_UART_EDGE
VOH_SER
1
ms
V
2.4
0
3.3
0.1
3.6
0.4
VOL_SER
ISINK = –4 mA
V
UART Receiver CEA-2011
DP_PULLDOWN asserted
DP_PULLDOWN asserted
Serial interface input high
Serial interface input low
Switching threshold
VIH_SER
VIL_SER
VTH
2.0
0.8
V
V
V
0.8
2.0
28
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.22.8 Pullup/Pulldown Resistors
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
Pullup Resistors
Bus pullup resistor on
upstream port (idle bus)
RPUI
Bus idle
0.9
1.1
2.2
1.575
3.09
kΩ
Bus pullup resistor on
upstream port (receiving)
RPUA
Bus driven/driver's outputs
unloaded
1.425
High (floating)
VIHZ
Pullups/pulldowns on both
DP and DM lines
2.7
3.0
3.6
3.6
V
V
Phone D+ pullup voltage
VPH_DP_UP
Driver's outputs unloaded
3.3
18
Pulldown Resistors
Phone D+/– pulldown
High (floating)
RPH_DP_DWN
RPH_DM_DWN
VIHZ
Driver's outputs unloaded
14.25
2.7
24.8
3.6
kΩ
Pullups/pulldowns on both
DP and DM lines
V
D+/– Data line
Upstream facing port
CINUB
[1.0]
[2]
22
75
pF
V
On-the-go device leakage
VOTG_DATA_LKG
ZINP
0.342
Input impedance exclusive
of pullup/pulldown
Driver’s outputs unloaded
300
kΩ
4.22.9 OTG VBUS
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
VBUS Wakeup Comparator
VBUS wake-up delay
DELVBUS_WK_
UP
15
µs
VBUS Comparators
A-device session valid
A-device VBUS valid
B-device session end
B-device session valid
VA_SESS_VLD
VA_VBUS_VLD
VB_SESS_END
VB_SESS_VLD
0.8
1.1
4.5
0.5
2.4
1.4
4.625
0.8
V
V
V
V
4.4
0.2
2.1
2.7
VBUS Line
A-device VBUS input
impedance to ground
SRP (VBUS pulsing) capable
A-device not driving VBUS
RA_BUS_IN
13.77
0.656
0.85
100
kΩ
kΩ
kΩ
B-device VBUS SRP
pulldown
5.25 V / 8 mA, pullup voltage
= 3 V
RB_SRP_DWN
RB_SRP_UP
10
B-device VBUS SRP pullup
(5.25 V – 3 V) / 8 mA, pullup
voltage = 3 V
1.3
1.75
34
B-device VBUS SRP rise
time maximum for OTG-A
communication
tRISE_SRP_UP_
MAX
0 to 2.1 V with < 13 μF load
0.8 to 2.0 V with > 97 μF load
ms
ms
B-device VBUS SRP rise
time minimum for standard
host connection
tRISE_SRP_UP_
MIN
46
4.22.10 OTG ID
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
VBUS Wakeup Comparator
ID wake-up comparator
Wakeup when ID shorted to
ground.
RID_WK_UP
30
100
kΩ
ID Comparators — ID External Resistors Specifications
ID ground comparator
ID Float comparator
RID_GND
ID_GND interrupt
4
20
25
kΩ
kΩ
RID_FLOAT
ID_FLOAT interrupt
200
500
ID Line
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
29
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
PARAMETER
COMMENTS
MIN
70
TYP
MAX
286
3.2
UNIT
kΩ
V
Phone ID pullup to VPH_ID_UP RPH_ID_UP
ID unloaded (VRUSB)
Connected to VRUSB
90
Phone ID pullup voltage
ID line maximum voltage
VPH_ID_UP
2.5
5.25
V
4.22.11 USB Charger Detection
USB Charger Detection Debounce Time
REQUIREMENT
Minimum 10 ms
Minimum 20 ms
PARAMETER
NB CLOCK
448
TEST CONDITIONS
ACTIVE/SLEEP mode
ACTIVE/SLEEP mode
MIN
13.7
27.3
TYP
MAX
13.7
27.3
UNIT
ms
DEBVBUS_TIME
DEBUSBCHG_TIM
E
896
ms
Table 4-4. Voltages
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNIT
REF
Logic Threshold
VLGC
0.8
2.0
V
1.4.4
Output current
> 250 µA
D+ Source Voltage
VDP_SRC
0.5
0.675
V
Data Detect Voltage
VDAT_REF
VDAT_LKG
0.25
0
0.4
3.6
V
V
Data Line Leakage Voltage
3.9
Table 4-5. Currents
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNIT
REF
Portable Device Current from
Charging Host Port during chirp
IDEV_HCHG_CHRP
710
mA
3.6.2
Data Contact Detect Current
Source
IDP_SRC
IDM_SINK
7
13
µA
µA
D- Sink Current
50
150
Table 4-6. Resistances
PARAMETER
D+ pulldown resistance
D- pulldown resistance
SYMBOL
RDP_DWN
RDM_DWN
CONDITIONS
MIN
MAX
UNIT
kΩ
14.25
14.25
24.8
24.8
kΩ
Table 4-7. USB Charger Detection (Wait and Debounce Timing)
USB Charger Detection (Wait and Debounce Timing)
Requirement
Minimum 200 us
Minimum 40 ms
Minimum 40 ms
Minimum 2 s
PARAMETER
NB
CLOCK
TEST CONDITIONS
MIN
244.1
54.7
54.7
2.73
TYP
MAX
UNIT
µs
D+ Current source on-
time
TIDP_SRC_ON
ACTIVE/SLEEP
mode(1)
8
244.1
54.7
54.7
2.73
D+ Voltage source on-
time
TVDP_SRC_ON
ACTIVE/SLEEP
mode(1)
1792
1792
89600
ms
ms
s
D+ Voltage source off
to high current
TVDP_SRC_HICRNT
ACTIVE/SLEEP
mode(1)
DATA_CONTACT_DET
ECT Timeout
TDCD_TIMEOUT
ACTIVE/SLEEP
mode(1)
(1) Note: LS Device mode not supported
30
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.23 MADC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Bit
Resolution
10
Input dynamic range for external
input ADCIN0
0
1.5
V
MADC voltage reference
Differential nonlinearity
Integral nonlinearity
Offset
1.5
1
V
–1
–2
1
2
LSB
LSB
mV
μA
Best fitting
Best fitting
–28.5
28.5
Input bias
Input capacitor CBANK
Input current leakage
10
1
pF
μA
4.23.1 MADC Analog Input Range and Prescaler Ratio
MADC CHANNEL
INT/EXT
ANALOG INPUT RANGE
(V)
PRESCALER
OUTPUT RANGE (V)
DIVIDER
RATIO
MIN
MAX
NOTE
No prescaler
Not used
MIN
N/A
N/A
MAX
ADCIN0: General-
purpose input (1)
External
Internal
0.0
1.5
N/A
1
ADCIN1:7 Reserved
N/A
N/A
N/A
N/A
ADCIN8: VBUS Voltage Internal
(VBUS)
Prescaler in USB
subchip.
0.0
6.5
0.0
1.5
3/14
Rdivider = (6 × 2.76
kΩ)/(28 × 2.76 kΩ)
(typ)(2)
ADCIN9: Reserved
Internal
Internal
Internal
Not used
ADCIN10:11 Reserved
N/A
2.7
N/A
4.7
N/A
0.675
N/A
N/A
1.175
N/A
N/A
0.25
N/A
ADCIN12: Main battery
voltage (VBAT)
Prescaler integrated
Rdivider = 9.85 kΩ/(4 ×
9.85 kΩ) (typ)(3)
ADCIN13:15 Reserved
Internal
N/A
N/A
(1) General-purpose input has to be tied to ground when TPS65921 internal power supply (VINTANA1) is off.
(2) Tolerance for resistors-type (PL_VHSR): ±19%
(3) Tolerance for resistors-type (PL_HR): ±12%
The table below summarizes the sequence conversion timing characteristics. Figure 4-5 shows one conversion
sequence general timing diagram.
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
31
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Table 4-8. Sequence Conversion Timing Characteristics
PARAMETER
COMMENTS
Running frequency
MIN
TYP
1
MAX
UNIT
MHz
μs
F
T = 1/F
N
Clock period
1
Number of analog inputs to convert in a
single sequence
0
3
16
4
Tstart
SW1, SW2, or USB asynchronous request
or real-time STARTADC request
μs
μs
Tsettling time
Settling time to wait before sampling a
stable analog input (capacitor bank charge
time)
Tsettling is calculated from the max((Rs +
Ron)*Cbank) of all possible input sources
(internal or external). Ron is the resistance
of the selection analog input switches (5
kΩ). This time is software programmable by
OCP register; default value is 12 µs.
5
12
260
Tstartsar
Tadc time
Tcapture time
Tstop
The successive approximation registers
ADC start time
1
10
2
μs
μs
The successive approximation registers
ADC conversion time
Tcapture time is the conversion result
capture time.
μs
μs
1
2
Full Conversion
Sequence Time
Only one channel (N = 1) (1)
All channels(2)
22
39
μs
352
624
Conversion
Sequence Time
Without Tstart and Tstop: Only one channel
(N = 1) (1)
18
33
μs
μs
Without Tstart and Tstop: All channels(1)
288
0.33
528
STARTADC pulse
duration
STARTADC period is T
(1) General-purpose input ADCIN0 must be tied to ground when TPS65921 internal power supplies (VINTANA1) is off.
(2) Total Sequence Conversion Time General Formula: Tstart + N × (1 + Tsettling + Tadc + Tcapture) + Tstop.
32
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
This table is illustrated in Figure 4-5. The Busy parameter indicates that a conversion sequence is running, and
the channel N result register parameter corresponds to the result register of RT/GP selected channel.
T one conversion
Tstartsar
Tstart
Tcapture
Tstop
Tsettling
Tadc
madc_clk
Busy
mux_sel_lowv[3:0]
Channel N selected
Acquire_lowv
start_sar_lowv
New channel N value
New value
out_lowv[9:0]
Channel X value
Channel N
Old value
result register
SWCS048-005
Figure 4-5. One Conversion Sequence General Timing Diagram
4.23.2 MADC Power Consumption
PARAMETER
Power on consumption
Power down consumption
TEST CONDITIONS
MIN
TYP
1(1)
1
MAX
UNIT
mA
Running frequency f = 1 MHz
μA
(1) The consumption is given in stand-alone mode.
4.24 TPS65921 Interface Target Frequencies
Table below assumes testing over the recommended operating conditions.
I/O INTERFACE
INTERFACE DESIGNATION
TARGET FREQUENCY
1.5 V
SmartReflex I2C
Slave high-speed mode
3.6 Mbps
400 kbps
100 kbps
480 Mbps
12 Mbps
General-purpose I2C
I2C Interface
USB
Slave fast-speed mode
Slave standard mode
High speed
USB
Full speed
Low speed
1.5 Mbps
30 MHz
Real/View® ICE tool
XDS560 and XDS510 tools
Lauterbach™ tool
JTAG
30 MHz
30 MHz
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
33
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.24.1 I2C Timing
The TPS65921 provides two I2C HS slave interfaces (one for general-purpose and one for SmartReflex). These
interfaces support the standard mode (100 kbps), fast mode (400 kbps), and HS mode (3.5 Mbps). The general-
purpose I2C module embeds four different slave hard-coded addresses (ID1 = 48h, ID2 = 49h, ID3 = 4Ah, and
ID4 = 4Bh). The SmartReflex I2C module uses one slave hard-coded address (ID5). The master mode is not
supported.
Table 4-9 and Table 4-10 assume testing over the recommended operating conditions.
START
I1
RESTART
STOP
I2
1
I2C.SCL
I2C.SDA
8
9
1
8
9
I8
I8
I7
I3
I4
I9
ACK
MSB
LSB
ACK
MSB
LSB
SWCS048-006
Figure 4-6. I2C Interface—Transmit and Receive in Slave Mode
34
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Table 4-9. I2C Interface Timing Requirements(1)(2)
NO.
PARAMETER
MIN
MAX
UNIT
Slave High-Speed Mode
I3
I4
I7
I8
I9
tsu(SDA-SCLH)
th(SCLL-SDA)
Setup time, SDA valid to SCL high
Hold time, SDA valid from SCL low
Setup time, SCL high to SDA low
Hold time, SCL low from SDA low
Setup time, SDA high to SCL high
10
0
ns
ns
ns
ns
ns
70
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tsu(SDAH-SCLH)
160
160
160
Slave Fast-Speed Mode
I3
I4
I7
I8
I9
tsu(SDA-SCLH)
th(SCLL-SDA)
Setup time, SDA valid to SCL high
Hold time, SDA valid from SCL low
Setup time, SCL high to SDA low
Hold time, SCL low from SDA low
Setup time, SDA high to SCL high
Slave Standard Mode
100
0
ns
µs
µs
µs
µs
0.9
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tsu(SDAH-SCLH)
0.6
0.6
0.6
I3
I4
I7
I8
I9
tsu(SDA-SCLH)
th(SCLL-SDA)
Setup time, SDA valid to SCL high
Hold time, SDA valid from SCL low
Setup time, SCL high to SDA low
Hold time, SCL low from SDA low
Setup time, SDA high to SCL high
250
0
ns
ns
µs
µs
µs
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tsu(SDAH-SCLH)
4.7
4
4
(1) The input timing requirements are given by considering a rising or falling time of:
80 ns in high-speed mode (3.4 Mbits/s)
300 ns in fast-speed mode (400 Kbits/s)
1000 ns in standard mode (100 Kbits/s)
(2) SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
Table 4-10. I2C Interface Switching Requirements(1)(2)
NO.
PARAMETER
MIN
MAX
UNIT
Slave High-speed Mode
I1
I2
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
160
60
ns
ns
Slave Fast-speed Mode
I1
I2
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
1.3
0.6
µs
µs
Slave Standard Mode
I1
I2
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
µs
µs
(1) The capacitive load is equivalent to:
100 pF in high-speed mode (3.4 Mbits/s)
400 pF in fast-speed mode (400 Kbits/s)
400 pF in standard mode (100 Kbits/s)
(2) SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
Copyright © 2010–2014, Texas Instruments Incorporated
Specifications
35
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
4.25 JTAG Interfaces
Table 4-11 and Table 4-12 assume testing over the recommended operating conditions.
JL1
JL2
JL2
JTAG.TCK
JTAG.TDI
JTAG.TMS
JTAG.TDO
JL3
JL5
JL4
JL6
JL7
SWCS048-007
Figure 4-7. JTAG Interface Timing
The input timing requirements are given by considering a rising or falling edge of 7 ns.
4.25.1 JTAG Interface Timing Requirements
Table 4-11. JTAG Interface Timing Requirements
NO.
PARAMETER
MIN
MAX
UNIT
Clock
JL1
JL2
tc(TCK)
tw(TCK)
Cycle time, JTAG.TCK period
30
ns
ns
Pulse duration, JTAG.TCK high or
low (1)
0.48 × P
0.52 × P
Read Timing
JL3
JL4
JL5
JL6
tsu(TDIV-TCKH)
th(TDIV-TCKH)
tsu(TMSV-TCKH)
th(TMSV-TCKH)
Setup time, JTAG.TDI valid before
JTAG.TCK high
8
5
8
5
ns
ns
ns
ns
Hold time, JTAG.TDI valid after
JTAG.TCK high
Setup time, JTAG.TMS valid before
JTAG.TCK high
Hold time, JTAG.TMS valid after
JTAG.TCK high
(1) P = JTAG.TCK clock period
The capacitive load is equivalent to 35 pF.
36
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
4.25.2 JTAG Interface Switching Characteristics
Table 4-12. JTAG Interface Switching Characteristics
NO.
NO.
PARAMETER
MIN
MAX
UNIT
Write Timing
td(TCK-TDOV))
Delay time, JTAG, TCK active edge to
JTAG.TDO valid
JL7
0
14
ns
PARAMETER
MIN
MAX
UNIT
Clock
JL1
JL2
tc(TCK)
tw(TCK)
Cycle time, JTAG.TCK period
30
ns
ns
Pulse duration, JTAG.TCK high or
low(1)
0.48 × P
0.52 × P
Read Timing
tsu(TDIV-TCKH)
th(TDIV-TCKH)
tsu(TMSV-TCKH)
th(TMSV-TCKH)
Setup time, JTAG.TDI valid before
JTAG.TCK high
JL3
JL4
JL5
JL6
8
5
8
5
ns
ns
ns
ns
Hold time, JTAG.TDI valid after
JTAG.TCK high
Setup time, JTAG.TMS valid before
JTAG.TCK high
Hold time, JTAG.TMS valid after
JTAG.TCK high
(1) P = JTAG.TCK clock period
4.25.3 Debouncing Time
Debounce times are listed in Table 4-13.
Table 4-13. Debouncing Time
DEBOUNCING FUNCTIONS
BLOCK
PROGRAMMABLE
DEBOUNCING
TIME
DEFAULT
Main battery charged threshold (<3.2 V)
Main battery low threshold detection (<2.7 V)
Main battery plug detection
Battery monitoring
No
No
No
580 μs
60 μs
60 μs
580 μs
60 μs
60 μs
Debouncing functions interrupt generation
debounce
POWER
USB
No
125.6 μs
125.6 μs
0 to 250 ms
(32/32768-second
stgif)
Plug/unplug detection VBUS (1)
Plug/unplug detection ID(2)
Yes
30 ms
0 to 250 ms
(32/32768-second
stgif)
USB
Yes
Yes
50 ms
28 ms
Debouncing functions interrupt generation
debounce for VBUS and ID(3)
POWER
0 to 233 ms
Hot-die detection
Thermal shutdown detection
PWRON(4)
Thermistor
No
No
No
No
60 μs
60 μs
60 μs
60 μs
Start/stop button
Button reset
31.25 ms
60 μs
31.25 ms
60 μs
NRESWARM
0 or 28 ms ± 2
ms
MMC1/2 (plug/unplug)
GPIO
Yes
0 ms
(1) Programmable in the VBUS_DEBOUNCE register.
(2) Programmable in the ID_DEBOUNCE register.
(3) Programmable in the RESERVED_E[2:0] CFG_VBUSDEB register
(4) The PWRON signal is debounced 1024 × CLK32K (maximum 1026 × CLK32K) falling edge in master mode.
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Specifications
37
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
5 Detailed Description
5.1 Functional Block Diagram
Figure 5-1 shows the functional block diagram of the device.
AGND
VBAT
REFS
TEST/MUXed I/O’s
VDD1_IN
VINTANA2
VRTC
VINTANA1
VDD1_L
VDD1
VDD2
VIO
IO.1P8
DGND
VDD1_FDBK
VDD1_GND
VDD2_IN
SRI2C_SCL
SRI2C_SDA
2
I C Smart-Reflex
VDD2_L
32KXIN
Xtal
32K
VDD2_FDBK
32KXOUT
32KCLKOUT
HFCLKIN
RTC
Clock sys
VDD2_GND
VIO_IN
Clock
slicer
HFCLKOUT
MSECURE
VIO_L
VIO_FDBK
BOOT0
BOOT1
VIO_GND
RESPWRON
NRESWARM
VPLLA3RIN
Power control
PWRON
NSLEEP
Control I/Os
VPLL1OUT
VPLL1
INT
SYSEN
REGEN
CLKEN
VDAC.IN
TESTRESET
CLKREQ
VDAC.OUT
VDAC
CTLI2C_SCL
CTLI2C_SDA
2
I C control
Control, Data
and Test
logic
VMMC1_IN
ADCIN0
10- bit
ADC
VMMC1OUT
VMMC1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
VAUX12SIN
VAUX2_OUT
VAUX2
USB 2.0
OTG
DATA6
DATA7
NXT
DIR
STP
UCLK
ID
VBUS
CP_IN
CP_CAPP
DP
USB
CP
USB
PHY
DM
CP_CAPM
CP_GND
AVSS1
KPD_R0
KPD_R1
KPD_R2
KPD_R3
KPD_R4
KPD_R5
AVSS2
AVSS3
AVSS4
KEY
PAD
VINTDIG
VUSB3P1
VINTUSB1P8
VINTUSB1P5
KPD_R6
KPD_R7
SWCS048-010
Figure 5-1. Functional Block Diagram
38
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
5.2 Clock System
Figure 5-2 shows the TPS65921 clock overview.
Device
32KXIN
OR
32KCLKOUT
OR
32KXOUT
32 kHz
OR
HFCLKIN
HFCLKOUT
SWCS048-011
Figure 5-2. TPS65921 Clock Overview
The TPS65921 accepts two sources of high-stability clock signals:
•
32KXIN/32KXOUT: on-board 32-kHz crystal oscillator (optionally, an external 32-kHz input clock can
be provided)
•
HFCLKIN: an external high-frequency clock (19.2, 26, or 38.4 MHz)
The TPS65921 has the capability to provide:
•
•
32KCLKOUT digital output clock
HFCLKOUT digital output clock with the same frequency as HFCLKIN input clock
5.3 32-kHz Oscillator
It is possible to use the 32-kHz input clock with either an external crystal or clock source. There are four
configuration, one with the external crystal and three without.
•
An external 32.768-kHz crystal connected on the 32KXIN / 32KXOUT balls. This configuration is
available for the master mode only.
•
A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The
32KXOUT pin can be driven to a dc value of the square- or sine-wave amplitude divided by 2. This
configuration is recommended if a large load is applied on the 32KXOUT pin.
•
•
A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The
32KXOUT pin can be left floating. This configuration is used if no charge is applied on the 32KXOUT
pin.
The oscillator is in bypass mode and a square-wave input can be applied to the 32KXIN pin with
amplitude of 1.8 V. The 32KXOUT pin can be left floating. This configuration is used if the oscillator is
in bypass mode (default configuration in Slave mode).
Figure 5-3 shows the block diagram for the 32.768-kHz clock output.
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Detailed Description
39
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
IO_1P8
(1.8 V)
OR
32KXIN
32-kHz
OSC
OR
32KCLKOUT
32 kHz
32KXOUT
RTC
SWCS048-014
Figure 5-3. 32.768-kHz Clock Output Block Diagram
The TPS65921 device has an internal 32.768-kHz oscillator connected to an external 32.768-kHz crystal
through the 32KXIN/32KXOUT balls or an external digital 32.768-kHz clock through the 32KXIN input (see
Figure 5-3). The TPS65921 device also generates a 32.768-kHz digital clock through the 32KCLKOUT pin
and can broadcast it externally to the application processor or any other devices. The 32KCLKOUT clock
is broadcast by default in the TPS65921 active mode but can be disabled if it is not used.
The 32.768-kHz clock (or signal) is also used to clock the RTC (real-time clock) embedded in the
TPS65921. The RTC is not enabled by default. It is up to the host processor to set the correct date and
time and to enable the RTC functionality.
The 32KCLKOUT output buffer can drive several devices (up to 40-pF load). At start-up, the 32.768-kHz
output clock (32KCLKOUT) must be stabilized (frequency/duty cycle) prior to the signal output. Depending
on the start-up condition, this may delay the start-up sequence.
5.4 Clock Slicer
Figure 5-4 shows the clock slicer block diagram.
BYPASS, PWRDN, PWRSEL
PL_HR resistance
HFCLKOUT
HFCLKIN
Cc
CDM
clamp
OR
PWRDN, PWRSEL
SWCS048-015
Figure 5-4. Clock Slicer Block Diagram
40
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
The clock slicer is disabled by default and enabled when the CLKEN pad is high. The slicer transforms the
HFCLKIN clock input signal into a squared clock signal used internally by the TPS65921 device and also
outputs it for external use. The HFCLKIN input signal can be:
•
•
A sinusoid with peak-to-peak amplitude varying from 0.3 to 1.45 V
A square clock signal of amplitude 1.85 V maximum. In the case of a square clock signal, the slicer is
configured in bypass or power-down mode. If a square-wave input clock is provided, it is
recommended to switch the block to bypass mode when possible to avoid loading the clock.
The HFCLKIN input clock frequency must be 19.2, 26, or 38.4 MHz.
Four different modes are programmable by register. By default, the slicer is in high-performance
application mode:
•
•
•
•
Bypass mode (BP): In BP mode, which overrides all the other modes, the input signal is directly
connected to the output through some buffers. The input is a rail-to-rail square wave.
Power-down mode (PD): During PD mode, the cell does not consume any current if bypass mode is
not active.
Low-power application mode (LP): In LP mode, the input sine wave is converted to a CMOS signal
(square wave) with low power consumption.
High-performance application mode (HP): In HP mode, the input sine wave is converted to a CMOS
signal (square wave). It has lower duty cycle degradation and lower input-to-output delay in
comparison to the low-power mode, but it consumes more current. The drive of the squaring inverter is
increased by connecting additional inverters in parallel. Details can be found in the clock slicer
electrical characteristics table.
Figure 5-5 shows the HFCLKIN clock distribution.
HFCLKIN
Slicer
HFCLKOUT
Clock
generator
Slicer bypass
SLICER_OK
Timer
CLKEN
Main state-machine
CLKREQ
SLEEP1
Optional request
configurable by software
only for legacy support
SWCS048-016
Figure 5-5. HFCLKIN Clock Distribution
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
41
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the
CLKREQ pin. As a result, the TPS65921 device immediately sets CLKEN to 1 to warn the clock provider
in the system about the clock request and starts a timer (maximum of 10 ms and uses the 32.768-kHz
clock). Once the timer expires, the TPS65921 device opens a gated clock, the timer automatically reloads
the defined value and a high-frequency output clock signal is available through the HFCLKOUT pin. The
output drive of HFCLKOUT is programmable (low drive (MISC_CFG[CLK_HF_DRV] = 0) maximum load
20 pF, high drive (MISC_CFG[CLK_HF_DRV] = 1) maximum load 30 pF), by default it is programmed to
support Low Drive.
CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request.
Figure 5-6 shows an example of the wired-OR clock request.
PERIPH1
Device
VIO
CLKREQ
PERIPH2
VIO
PERIPHn
VIO
SWCS048-017
Figure 5-6. Example of Wired-OR Clock Request
The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround
support, the NSLEEP1 signal can also be used as a clock request even if it is not its primary goal. By
default, this feature is disabled and must be enabled individually by setting the register bits associated
with each signal.
42
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
5.5 Power Path
5.5.1 Step-Down Converters
Depending on the system requirements, and also to optimize mean consumption, three operating modes
are allowed for each step-down converter:
•
•
•
Off/power-down mode: Output voltage is not maintained, and power consumption is null
Active: DC-DC can deliver its nominal output voltage with a full load current capability.
Sleep: The nominal output voltage is maintained with low power consumption, but also with a low load-
current capability.
The SMPS operates with three modulation schemes:
•
•
•
Light pulse frequency modulation (PFM)
Pulse skipping mode (PSM)
Continuous pulse-width modulation (PWM)
Each DC-DC converter, all of which have the same electrical characteristics, has an integrated RC
oscillator. The use of these RC oscillators is configurable through register bits, and by default the RC
oscillator of VDD1 is used for all DC-DC converters.
5.5.2 LDO
The VPLL1 programmable LDO regulator is high-PSRR, low-noise, linear regulator used for the host
processor PLL supply.
The VDAC programmable LDO regulator is a high-PSRR, low-noise, linear regulator that powers the host
processor dual-video DAC. It is controllable with registers through I2C and can be powered down.
The VMMC1 LDO regulator is a programmable linear voltage converter that powers the MMC slot. It
includes a discharge resistor and over-current protection (short circuit). This LDO regulator can also be
turned off automatically when the MMC card extraction is detected (through one dedicated GPIO). The
VMMC1 LDO can be powered through an independent supply other than the battery; for example, a
charge pump. In this case, the input from the VMMC1 LDO can possibly be higher than the battery
voltage.
The VAUX2 general-purpose LDO regulator powers the auxiliary devices.
The VRRTC voltage regulator is a programmable, LDO, linear voltage regulator supplying (1.5 V) the
embedded RTC (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart. The VRRTC
regulator is also the supply voltage of the power-management digital state-machine. The VRRTC regulator
is supplied from the UPR line, switched on by the main battery. The VRRTC output is present as long as a
valid energy source is present. The VRRTC line is supplied by an LDO when VBAT > 2.7 V, and a clamp
circuit when VBAT < 2.7 V.
The VINTDIG LDO regulator supplies the TPS65921 digital blocks.
To supply the TPS65921 analog blocks, there are two LDOs: VINTANA1 (1.5 V) and VINTANA2 (2.75
V/2.5 V). The 2.5-V setting is selected when the battery voltage falls below 3.0 V.
The VUSB3V1 internal LDO regulator powers the USB PHY, charger detection, and OTG of the USB
subchip inside the TPS65921 device.
It can take its power from two possible sources:
•
•
VBAT.USB (only for high battery voltages)
VBUS (only in low-power mode)
See Charge-pump section for more details.
The USB standard requires data lines to be biased with pullups biased from a > 3.0 V supply, USB PHY
cannot directly operate from VBAT.USB for battery voltages lower than 3.3 V.
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
43
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
In such case, VBUS should be supplied by a boosted voltage to ensure enough overhead for USB LDO
operation. An internal charge pump (whose output is connected to VBUS) can be used for this purpose.
To select between these two power sources, a power mux is connected to the VUSB3V1 LDO supply.
The VUSB1V8 and VUSB1V5 internal LDO regulators power the USB subchip inside the TPS65921
device.
The short-circuit current for the LDOs and DC-DCs in the TPS65921 device is approximately twice the
maximum load current. In certain cases when the output of the block is shorted to ground, the power
dissipation can exceed the 1.2 W requirement if no action is taken. A short-circuit protection scheme is
included in the TPS65921 device to ensure that if the output of an LDO or DC-DC converter is short-
circuited, then the power dissipation does not exceed the 1.2-W level.
The three USB LDOs VUSB3V1, VUSB1V8, and VUSB1V5 are included in this short circuit protection
scheme which monitors the LDO output voltage at a frequency of 1 Hz, and generates an interrupt when a
short circuit is detected.
The scheme compares the LDO output voltage to a reference voltage and detects a short circuit if the
LDO voltage drops below this reference value (0.5 V or 0.75 V programmable). In the case of the
VUSB3V1 and VUSB1V8 LDOs, the reference is compared with a divided down voltage (1.5 V typical).
If a short circuit is detected on VUSB3V1, then the power subchip FSM switches this LDO to sleep-mode.
If a short circuit is detected on VUSB1V8 or VUSB1V5, then the power subchip FSM switches the relevant
LDO off.
5.5.3 Power Reference
The bandgap voltage reference is filtered (RC filter), using an external capacitor connected across the
VREF output and an analog ground (REFGND). The VREF voltage is scaled, distributed, and buffered
inside the device. The bandgap is started in fast mode (not filtered) and is set automatically by the power
state-machine in slow mode (filtered, less noisy) after switch on.
5.5.4 Power Use Cases
The TPS65921 device has two modes:
•
Master: The TPS65921 device decides to power up or down the system and control the other power
ICs in the system with the SYSEN output.
•
Slave: The TPS65921 device is controlled by another power IC with a digital signal on the PWRON
input. There is no battery management in slave mode.
The modes corresponding to BOOT0–BOOT1 combination value are:
NAME
DESCRIPTION
Master_C021_Generic 10
Slave_C021_Generic 11
BOOT0
BOOT1
MC021(1)
SC021
1
1
0
1
(1) Boot mode for OMAP3430 is c021 Master boot mode.
Process modes define:
•
•
•
The boot voltage for the host core
The boot sequence associated with the process
The DVFS protocol associated with the process
MODE
C021.M
Boot core voltage
Power sequence
DVFS protocol
1.2 V
VIO followed by VPLL1, VDD2, VDD1
SmartReflex interface (I2C high speed)
44
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Regulator states depending on use cases:
REGULATOR
MODE: C021 (MASTER/SLAVE)
BACKUP
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
WAIT ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
SLEEP NO LOAD
OFF
ACTIVE NO LOAD
VAUX2
OFF
OFF
ON
VMMC1
VPLL1
OFF
SLEEP
OFF
VDAC
OFF
ON
VINTANA1
VINTANA2
VINTDIG
VIO
SLEEP
SLEEP
SLEEP
SLEEP
SLEEP
SLEEP
OFF
ON
ON
ON
VDD1
ON
VDD2
ON
VUSB1V5
VUSB1V8
VUSB3V1
OFF
OFF
ON
OFF
SLEEP
5.5.5 Power Timing
Sequence start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 5-7.
Sequence start timing depends on the TPS65921 starting event. If the starting event is:
•
•
Main battery insertion, event time is 1.126 ms (time to set up internal LDO and relax internal reset)
VBUS insertion, event time is 25 cycles of 32k
Starting_Event is main battery insertion
Vbat
1.126 ms
Sequence_Start
Starting_Event is VBUS insertion
Vbus
782 ms = 25 cycle32k
Sequence_Start
Starting_Event is PWRON button
PWRON
Pushbutton debouncing - 30 ms
Sequence_Start
Starting_Event is PWRON rising when device is in slave mode
PWRON
0 ms
Sequence_Start
SWCS048-018
Figure 5-7. Timings Before Sequence Start
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
45
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
5.5.5.1 Switch On In MASTER_C021_GENERIC Mode
Figure 5-8 describes the timing and control that must occur in Master_C021_Generic mode.
Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 5-7.
Sequence_Start
4608 ms battery detection
REGEN
VIO
1068 ms - 3 MHz oscillator setting + clock switch
1.8 V
1179 ms for VIO stabilization
VPLL1
VDD2
VDD1
1.8 V
1022 ms for LDO stabilization and start DC-DC ramping
1.2 V
1099 ms for VDD2 stabilization and VDD1 start ramping
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
SYSEN
61 ms
1179 ms for VIO stabilization
CLKEN
29.053 ms
32.410 ms
HFCLKOUT
T1
NRESPWRON
SWCS048-019
Figure 5-8. Timings—Switch On in Master_C021_Generic Mode
PARAMETER
MIN
MAX
UNIT
32k clock cycles
T1
10
11
46
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
5.5.5.2 Switch On In SLAVE_C021_GENERIC Mode
Figure 5-9 describes the timing and control that must occur in Slave_C021_Generic mode.
Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 5-7.
PWRON
4791 ms – 3 MHz oscillator setting + internal reg
REGEN
1068 ms for external supply ramp
VIO
1.8 V
1179 ms for VIO DC-DC stablilization
VPLL1
VDD2
1.8 V
1022 ms
1.2 V
1099 ms for VDD2 stabilization
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
SYSEN
61 ms
1099 ms for VDD2 stabilization
29.053 ms
CLKEN
1953 ms for digital clock setting
HFCLKOUT
NRESPWRON
T1
SWCS048-020
Figure 5-9. Timings—Switch On in Slave_C021_Generic Model
PARAMETER
MIN
MAX
UNIT
T1
10
11
32k clock cycles
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
47
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
5.5.5.3 Switch-Off Sequence
This section describes the signal behavior required to switch off the system.
48
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
5.5.5.3.1 Switch-Off Sequence In Master Modes
Figure 5-10 describes the timing and control that occur during the switch-off sequence in master modes.
VBAT
DEVOFF (register)
18 ms
NRESPWRON
1,2 ms
REGEN
18 ms
32KCLKOUT
1,2 ms
DCDCs
1,2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
126 ms
CLKEN
3.42 ms before detection of starting event
NEXT_Startup_event
SWCS048-021
NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between
power domains, state machinery priority, and so forth).
Figure 5-10. Switch-Off Sequence in Master Modes
In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set
accordingly inside the CFG_BOOT register), then the delay between DEVOFF and
NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by 2 (meaning around 9 μs). This is due to
the internal frequency used by POWER STM switching from 3 MHz to 1.5 MHz in case the value of the
HF clock is 19.2 MHz.
The DEVOFF event is the PWRON falling edge in slave mode and the DEVOFF internal register write in
master mode.
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
49
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
5.5.5.3.2 Switch-Off Sequence in Slave Mode
Figure 5-11 describes the timing and control that occur during the switch off-sequence in slave mode.
VBAT
PWRON
18 ms
NRESPWRON
1,2 ms
REGEN
18 ms
32KCLKOUT
1,2 ms
DCDCs
1,2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
3.42 ms before detection of starting event
NEXT_Startup_event
6 ms (see comment in notes
about reducing this interval)
VIO
6 ms
32KXIN
SWCS048-022
NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between
power
domains,
state
machinery
priority,
and
so
forth).
If necessary, the 6-ms period to maintain VIO and 32KXIN after PWRON goes low can be reduced to 150 μs.
Figure 5-11. Switch-Off Sequence in Slave Mode
In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set
accordingly inside the CFG_BOOT register), then the delay between DEVOFF and
NRESPWRON/CLK32KOUT/ SYSEN/HFCLKOUT is divided by 2 (meaning around 9 μs). This is due to
the internal frequency used by POWER STM switching from 3 MHz into 1.5 MHz in case the value of the
HF clock is 19.2 MHz.
5.5.5.4 Charge Pump
The charge pump generates a 5.0-V (nominal) power supply voltage from battery to the VBUS
CP.OUT/VUSB.IN pin. The input voltage range is 2.7 to 4.5 V for the battery voltage. The charge pump
operating frequency is 1 MHz.
The charge pump tolerates 6 V on VBUS when it is in power down mode. The charge pump integrates a
short-circuit current limitation at 450 mA.
Figure 5-12 shows the charge pump.
50
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Switched 3.3 V
USB connector
VBAT.USB
VBUS
CP.IN
CP.GND
CPOUT
Normal operation
USB @ VBUS > 4.4 V
5.0-V CP
Power-up
USB @ VBAT > 3.20 V
USBIN
USB3P3
TPS65921
DP
DM
ID
USB PHY
SWCS048-023
Figure 5-12. General Overview of the Charge Pump and Its Interfaces
The charge pump can be used to supply USB 3.1 V LDO when battery voltage is lower than this LDO
VBATmin voltage (see Section 4).
5.5.6 USB Transceiver
The TPS65921 device includes a USB OTG transceiver that support USB 480 Mbps HS, 12 Mbps FS, and
USB 1.5 Mbps LS through a 4-pin UTMI+ ULPI.
It also includes a module covering Battery Charging Specification v1.0. Figure 5-13 shows the USB 2.0
PHY highlight block diagram.
USB OTG device
OMAP
(LINK)
Device
USB PHY
ULPI
Phone connector
(USB)
PC
ADC inputs
(optional)
Charger
SWCS048-024
Figure 5-13. USB 2.0 PHY Highlight
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
51
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Figure 5-14 shows the USB system application schematic.
VBAT
C
C
VBUS.IN
VBUS.PC
C
USB.1P3
C
USB.1P5
C
USB3P1
VBAT
VBAT.USB
C
VBAT.USB
C
VBUS
VBUS
ULPI_CLK
ULPI_STP
ULPI_DIR
ULPI_NXT
TPS65921
D+ / RXD
D– / TXD
USB
PLL
USB
PWR
USB
CP
USB OTG
connector
ID
GND
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
USB 2.0 HS-OTG
transceiver (PHY)
ULPI
OMAP
host
processor
(LINK)
Registers
OTG
TXEN
DAT
SE0
SWCS048-025
Figure 5-14. USB System Application Schematic
5.5.7 PHY
The PHY is the physical signaling layer of the USB 2.0. It contains all the drivers and receivers required
for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard digital interface called the universal
transceiver macro cell interface (UTMI).
The transmitters and receivers inside the PHY are classified into two main classes:
•
•
The FS and LS transceivers. These are the legacy USB1.x transceivers.
The HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry consisting
of:
•
A DPLL, which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for
USB, and also the clock required for the switched capacitor resistance block.
•
A switched capacitor resistance block used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry that protects it from an accidental 5 V short on the DP and
DM lines.
52
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
5.5.7.1 LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the
FS/LS modes of operation.
5.5.7.2 LS/FS Differential Receiver
A differential input receiver (RX) retrieves the LS/FS differential data signaling. The differential voltage on
the line is converted into digital data by a differential comparator on DP/DM. This data is then sent to a
clock and data recovery circuit, which recovers the clock from the data. In an additional serial mode, the
differential data is directly output on the RXRCV pin.
5.5.7.3 LS/FS Transmitter
The USB transceiver (TX) uses a differential output driver to drive the USB data signal D+/– onto the USB
cable. The outputs of the driver support 3-state operation to achieve bidirectional half-duplex transactions.
5.5.7.4 HS Differential Receiver
The HS receiver consists of the following blocks:
•
•
•
A differential input comparator to receive the serial data
A squelch detector to qualify the received data
An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and
serial-to-parallel converter to generate the UTMI DATAOUT
5.5.7.5 HS Differential Transmitter
The HS transmitter is always operated on the UTMI parallel interface. The parallel data on the interface is
serialized, bit-stuffed, NRZI-encoded, and transmitted as a DC output current on DP or DM depending on
the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for
signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes
the impedance seen by the transmitter to double, thereby doubling the differential amplitude seen on the
DP and DM lines.
5.5.7.6 UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a
direct access to the FS/LS analog transmitter and receiver.
ULPI
Device
USB connector
DATA0: UART_TX
DATA1: UART_RX
DP/RXD/MIC
DM/TXD/SPKR
SWCS048-026
Figure 5-15. USB UART Data Flow
The OTG block integrates three main functions:
•
•
•
The USB plug detection function on VBUS and ID
The ID resistor detection
The VBUS level detection
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
53
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
5.6 Charger Detection
To support Battery Charging Specification v1.1 [BCS v1.1], a charger detection module is included in the
TPS65921 USB module.
The detection mechanism aims distinguishing several types of power sources that can be connected on
VBUS line:
•
•
•
Dedicated charger port
Standard host port
Charging host port
The hardware includes:
•
•
•
•
A dedicated voltage referenced pullup on DP line
A dedicated current controlled pulldown on DM line
A detection comparator on DM line
A control/detection state-machine including timers
Additional circuitry is added on DP/DM respectively for data line symmetry (required for HS operation) and
for possible future extension
ID pin status detection (as defined per OTG v1.3 standard) and DP/DM single-ended receivers (as defined
per USB v2.0 standard) are also used to determine the type of device plugged on the USB connector.
For details on the detection mechanism, refer to [BCS v1.1] (1).
The charging detection feature has two modes (description of each mode follows):
1. Software CTL mode: Software has direct control of current source and USB charger detection
comparator on DP/DM (enabled when USB_SW_CTRL_EN=1) using USB_CHRG_CTRL registers
bits.
2. Software FSM mode: Software can start and stop USB charger detection state-machine.
For both modes, DPPULLDOWN and DMPULLDOWN bits in OTG_CTRL register are 1 by default. This
can cause errors in charger detection. Therefore, both bits must be cleared to 0 before software begins
charger detection sequence.
1- Software CTL Mode (Manual detection):
When in this mode the charger detection circuitry is fully under control of software. Refer to
POWER_CONTROL
Conditions:
register
bits
as
to
how
to
control
the
detection
circuitry.
•
•
•
The TPS65921 device is powered and is in active mode.
USB_SW_CHRG_CTRL_EN = 1, register bit set by the software
USB_CHG_DET_EN_SW = 1, register bit set by the software
Control the USB_SW_CHRF_CTRL register to achieve charger detection.
2- Software FSM Mode (Automatic detection):
The TPS65921 also supports automated battery charger detection through the USB battery charger
detection FSM in Figure 5-16 while the chip is in active mode. This mode is set by software using the
SW_USB_DET bit. When in this mode, the automated charger detection finite state-machine (FSM) is
enabled.
Refer
to
the
state-machine
diagram
for
details.
Conditions:
•
•
The TPS65921 device is powered and is in active mode.
USB_HW_CHRG_DET_EN = 1
See the Register Map for more details.
54
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
The TPS65921 device also supports automated data contact detection in the FSM through the
DATA_CONTACT_DET_EN bit which should be set at the same time as SW_USB_DET above, before
setting SW_CONTROL bit. This enables a block of the FSM, which performs data contact detect for a
maximum of DCD_TIMEOUT before automatically skipping to charger detection.
See Figure 5-16,USB Battery Charger FSM, for details of how context is stored if SW_CONTROL bit is set
while in software FSM mode.
USB_DET_ON
CHGD_INIT
INIT
DATA_CONTACT_DET_EN=0
CHGDCTRL=”000_0000"
CHGDCTRL=”011_0110"
DATA_CONTACT_DET_EN=1
CHGD_SETUP
DCD_INIT
Wait TVDP_SCR_ON
CHGDCTRL=”011_1010"
Dcounter=DCD_TIMEOUT
Or
CHGD_SERX_DP_DEB=0
End wait
DCD_SETUP
CHGD CH_ECK
Always ON
Dcounter=0
Wait TIDP_SRC_ON
End wait
CHGD_SERX_DM_DEB=0
and
CHGD_VDM_DEB=1
DCD_CHECK
Dcounter=Dcounter+1
USB500_WAIT
CHGDCTRL=010_0000
Wait TVDP_SRC_HICRNT
End wait
Dcounter<DCD_TIMEOUT
USB500_DETECTED
CHGDCTRL=100_0000
USP_P=0
USP_P=1
and
(USB_HW_CHRG_DET_EN=1 or
USB_SW_CHRG_DET_EN=1)
(USB_HW_CHRG_DET_EN=0 and
USB_SW_CHRG_DET_EN=0)
USB_P=0
or
(USB_HW_CHRG_DET_EN=0 and
USB_SW_CHRG_DET_EN=0)
USB_DET_STS
USB_DET_OFF
CHGDCTRL=xxx_0000
USB charger status is memorized
CHGDCTRL=000_0000
SWCS048-027
Figure 5-16. USB Battery Charger Detection FSM
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
55
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
USB charger detection status bit definition:
•
USBVBUS_PRES: Detect presence of valid VBUS. Comparator output is debounced for
DEBVBUS_TIME (minimum 10 ms) on CKCHG and generates a USB_P signal. USB_P is computed
only if a battery presence is detected.
•
USBCHRG_PRES: Detect presence of USB charger on DP/DM. The feature is enabled through the
USB_DET_EN signal, then USBPHY performs checks on DP/DM and return status
USB_DET_RESULT:
–
–
1 : USB 500-mA charger is detected.
0 : USB 100-mA charger is detected.
•
•
USB_DET_STATUS: 500-mA/100-mA USB charger detect presence comparator output is debounced
during DEBUSBCHG_TIME (minimum 20 ms) on CKCHG, debounced signal is USB_DET_RESULT
(set to 1 in case of 500-mA charger)
Two signals are the result of the charger detection state machine:
–
–
USB100_P: Valid 100-mA charger (VBUS supplier) is detected.
USB500_P: Valid 500-mA charger (USB charger) is detected.
5.6.1 USB Battery Charger FSM
The FSM uses the control signals CHGDCTRL[6:0] described below to control and observe battery
charger detection.
When the SW_CONTROL bit is set to 1, the current context of the FSM and the state of charger detection
is latched in POWER_CONTROL register bits HWDETECT, DP_VSRC_EN, VDAT_DET, and
DET_COMP, after which FSM control signals CHGDCTRL[6:0] are ignored, and charger detection
hardware and the CHGR_DET pin are controlled by the software.
The CHGD_IDP_SRC_EN bit is not latched when the SW_CONTROL bit is set (for example, if the FSM is
performing data-contact detection at the time the SW_CONTROL is set to 1, the CHGD_IDP_SRC_EN bit
is unchanged — its default value is 0).
56
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
5.6.2 FSM Control Signals
Table 5-1. USB Charger Detect FSM I/O Control Signals
CONTROL SIGNAL
CONTROL SIGNAL
USB500_P
DESCRIPTION
TYPE
Input
Bit(6)
Bit(5)
Bit(4)
500-mA USB charging can be enabled
100-mA USB charging can be enabled
USB100_P
Input
CHGD_DET_EN
Enable charger detection (used to enable
CHGD IBIAS block)
Output
Bit(3)
Bit(2)
CHGD_IDP_SRC_EN
CHGD_VDP_SRC_EN
Enable IDP_SRC and RDM_DWN
Output
Output
Enable VDP_SRC buffer, IDM_SINK, and
VDAT_REF_DM comp
Bit(1)
Bit(0)
CHGD_SERX_EN
Reserved
Enable SERX comparators on DP and DM
Reserved
Output
Output
Table 5-1 shows control signals used to control the charger detection analog block from the FSM. The bit
number in the left-handed column indicates control bit position used in the charger detection state-
machine. Both SERX comparator outputs (CHGD_SERX_DP, CHGD_SERX_DM) are available for
register read in the VENDOR_SPECIFIC3 register.
Example:
State: DCD_INIT
Control: CHGDCTRL[6:0] = 011_1010
Bit(6): USB500_P = 0
Bit(5): USB100_P = 1
Bit(4): CHGD_DET_EN = 1
Bit(3): CHGD_IDP_SRC_EN = 1
Bit(2): CHGD_VDP_SRC_EN = 0
Bit(1): CHGD_SERX_EN = 1
Bit(0): Reserved = 0
5.7 MADC
The Monitoring Analog-to-Digital Convertor (MADC) enables the host processors to monitor analog signals
using Analog-to-Digital Conversion (ADC). After the conversion is complete, the host processor reads the
results of the conversion through the inter-integrated circuit (I2C) interface.
The MADC has the following features:
•
•
•
•
•
•
10-bit ADC
External input (ADCIN0)
Internal inputs (VBUS and battery voltage)
MADC resource shared among multiple users, including system host processors and the internal USB
Four ways of starting analog-to-digital (ADC) conversion
Quarter-bit accuracy if the averaging function is used for modem-initiated real-time (RT) conversion
requests
•
•
•
Management of potential concurrent conversion requests and priority between different resource users
Interrupt signal to the primary interrupt handler (PIH) module at the end-of-sequence of conversions
Averaging feature to sample the input channel on four consecutive conversion cycles instead of once,
and to provide the average value of four conversions
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
57
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Because the MADC is shared by users, there are four ways to start the ADC conversion. Three of these
requests can be triggered by external host processors, and one request is issued by USB:
•
Hardware or RT conversion request: This request is initiated by the external host processor to request
RT signal conversion. This conversion request is most useful when tied to a modem processor request
for battery voltage level, in synchronization with a signal frame boundary. The host processor can
request conversion on all ADC input channels using this conversion request.
•
SW1 software conversion request: This request can be initiated by the first external host processor to
request non-RT conversions. This request is also called an asynchronous or GP conversion (GPC)
request.
•
•
SW2 software conversion request: This request can be initiated by the second external host processor
to request non-RT conversions. This request is also called an asynchronous or GPC request.
USB conversion request: This is a GPC request triggered by the USB through TPS65921 internal
signals. This conversion request is for the ADCIN12 channel.
It is possible to delay the conversion by programming the acquisition time (ACQUISITION register).
5.8 JTAG Interfaces
The TPS65921 JTAG TAP controller handles standard IEEE JTAG interfaces. This section describes the
timing requirements for the tools used to test the TPS65921 power management.
The JTAG/TAP module provides a JTAG interface according to IEEE Std1149.1a. This interface uses the
four I/O pins TMS, TCK, TDI, and TDO. The TMS, TCK, and TDI inputs contain a pullup device, which
makes their state high when they are not driven. The output TDO is a 3-state output, which is high
impedance except when data are shifted between TDI and TDO.
•
•
•
•
TCK is the test clock signal.
TMS is the test mode select signal.
TDI is the scan path input.
TDO is the scan path output.
TMS and TDO are multiplexed at the top level with the CPIO0 and CPIO1 pins. The dedicated external
TEST pin switches from functional mode (GPIO0/GPIO1) to JTAG mode (TMS/TDO). The JTAG
operations are controlled by a state-machine that follows the IEEE Std1149.1a state diagram. This state-
machine is reset by the TPS65921 internal power-on reset. A test mode is selected by writing a 6-bit word
(instruction) into the instruction register and then accessing the related data register.
5.8.1 Keyboard
The keyboard is connected to the chip using:
•
•
KBR (7:0) input pins for row lines
KBC (7:0) output pins for column lines
Figure 5-17 shows the keyboard connection.
58
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
Device
VCC
Internal
pullup
8 x 8
Keyboard matrix
kbd_r_0
kbd_r_1
kbd_r_2
Keyboard controller
kbd_r_3
kbd_r_4
kbd_r_5
kbd_r_6
kbd_r_7
kbd_c_0
kbd_c_1
kbd_c_2
kbd_c_3
kbd_c_4
kbd_c_5
kbd_c_6
kbd_c_7
SWCS048-028
Figure 5-17. Keyboard Connection
When a key button of the keyboard matrix is pressed, the corresponding row and column lines are shorted
together. To allow key press detection, all input pins (KBR) are pulled up to VCC and all output pins (KBC)
driven to a low level.
Any action on a button generates an interrupt to the sequencer.
The decoding sequence is written to allow detection of simultaneous press actions on several key buttons.
The keyboard interface can be used with a smaller keyboard area than 8 × 8. To use a 6 × 6 keyboard,
KBR(6) and KBR(7) must be tied high to prevent any scanning process distribution.
Copyright © 2010–2014, Texas Instruments Incorporated
Detailed Description
59
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
6 Device and Documentation Support
6.1 Device Support
6.1.1 Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the TPS65921 device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any TPS65921 device application.
Hardware Development Tools: Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the TPS65921 platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
6.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, TPS65921). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
P
Marking used to note prototype (X), preproduction (P), or qualified/production device (Blank).
Blank in the symbol or part number are collapsed so there are no gaps between characters.
A
Mask set version descriptor (initial silicon = BLANK, first silicon revision = A, second silicon
revision = B,...) Initial silicon version is ES1.0; first revision can be named ES2.0, ES1.1, or
ES1.01 depending on the level of change. NOTE: Device name maximum is 10 characters.
YM
Year month
LLLLS
$
Lot code
Fab planning code
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZQZ). provides a legend for reading the complete device name for any
TPS65921 device.
60
Device and Documentation Support
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
For orderable part numbers of TPS65921 devices in the ZQZ package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
6.2 Documentation Support
The following documents describe the TPS65921 processor/MPU. Copies of these documents are
available on the Internet at www.ti.com.
SWCU067 TPS65921 Register Manual
SWCZ003 TPS65921 Silicon Errata
SWCA091 TPS65921 PCB Layout Guidelines (Rev. A)
6.2.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
6.3 Trademarks
SmartReflex, OMAP, Code Composer Studio, E2E are trademarks of Texas Instruments.
6.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
6.5 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
6.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2010–2014, Texas Instruments Incorporated
Device and Documentation Support
61
Submit Documentation Feedback
Product Folder Links: TPS65921
TPS65921
SWCS048G –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
7 Mechanical Packaging and Orderable Information
7.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
62
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: TPS65921
Copyright © 2010–2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2000
2000
(1)
(2)
(3)
(4/5)
(6)
TPS65921B1ZBHR
TPS65921B1ZQZR
PREVIEW
NFBGA
ZBH
120
120
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
65921B1ZBH
NRND
BGA
ZQZ
Green (RoHS
& no Sb/Br)
SNAGCU
TPS65921B1
MICROSTAR
JUNIOR
TPS65921BZBHR
TPS65921BZQZR
PREVIEW
NRND
NFBGA
ZBH
ZQZ
120
120
2000
2000
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
65921BZBH
TPS65921B
BGA
MICROSTAR
JUNIOR
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
TPS6594-Q1
TPS6594-Q1 Power Management IC (PMIC) with 5 Bucks and 4 LDOs for Safety-Relevant Automotive Applications
TI
©2020 ICPDF网 联系我们和版权申明