TPS65987D_技术文档

TPS65987D

ZHCSI93D –MAY 2018 –REVISED OCTOBER 2022

TPS65987D 具有集成拉电流和灌电流电源路径、支持USB3 和交替模式的USB

Type-C^®和USB PD 控制器

1 特性

2 应用

• 该器件由USB-IF 进行了PD3.0 认证

• 单板计算机

• 电动工具、移动电源、零售自动化和支付

• 无线扬声器、耳机

• 其他个人电子产品和工业应用

• 集线站

– 认证新的USB PD 设计时需使用PD3.0 器件

• TID#: 1067

– 有关PD2.0 与PD3.0 的文章

• TPS65987D 是一款可完全配置的USB PD 器件控

制器：

• 平板监视器

3 说明

– 源端口和接收端口能力可高达20V/5A

– 交替模式支持

TPS65987D 是独立的 USB Type-C 和功率传输 (PD)

控制器，可为单个 USB Type-C 接口提供线缆插头连

接状态和方向检测。进行线缆检测时，TPS65987D 会

使用 USB PD 协议在 CC 线路上进行通信。在线缆检

测和USB PD 协商完成后，TPS65987D 会启用合适的

电源路径并为外部多路复用器配置交替模式设置。

• DisplayPort

– 通过GPIO 或I2C 控制外部直流/直流电源、高

速数据多路复用器及其他外设

• 例如：TPS65987EVM

• 例如：TIDA-050012

– 用于为各种应用轻松配置TPS65987D 的GUI

工具：TPS65988X-CONFIG

– 电源管理

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS65987D

QFN (RSH56)

7.00mm x 7.00mm

• 通过3.3V 或VBUS 电源供电

• 3.3V LDO 输出，在电池电量耗尽时提供支持

– 有关更详尽的选择指南和入门信息，请参阅

www.ti.com/usb-c 和E2E 指南

• 完全管理的集成电源路径：

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

5-20 V

5 A

V_BUS

5-20 V

5 A

– 两个集成的20V、5A、25mΩ拉电流或灌电流

负载开关

– UL 2367 认证编号：20190107-E169910

– IEC 62368-1 认证编号：US-34617-UL

• 集成强大的电源路径保护

3.3 V

CC1/2

CC

V_CONN

Type-C Cable Detection

and

USB PD Controller

2

Host

Interface

Host

USB

Type-C

Connector

TPS65987D

D+/-

2

USB P/N

BC1.2

– 20V/5A 电源路径配置为接收端口时，集成了反

向电流保护、欠压保护、过压保护和压摆率控制

– 20V/5A 电源路径配置为源端口时，集成了欠压

保护、过压保护和提供浪涌电流保护的电流限制

• USB Type-C^®功率传输(PD) 控制器

GND

Alternate Mode Mux Ctrl

GPIO or I2C

SuperSpeed Mux/Retimer

– 13 个可配置GPIO

– 支持BC1.2 充电

简化版原理图

– 符合USB PD 3.0 标准

– 符合USB Type-C 规范

– 线缆连接和方向检测

– 集成式VCONN 开关

– 物理层和策略引擎

– 3.3V LDO 输出，在电池电量耗尽时提供支持

– 通过3.3V 或VBUS 电源供电

– 1 个I2C 主要或次级端口

– 只有1 个I2C 主要端口

– 只有1 个I2C 次级端口

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSES1

TPS65987D

ZHCSI93D –MAY 2018 –REVISED OCTOBER 2022

www.ti.com.cn

Table of Contents

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................42

9 Application and Implementation..................................45

9.1 Application Information............................................. 45

9.2 Typical Application.................................................... 45

10 Power Supply Recommendations..............................55

10.1 3.3-V Power............................................................ 55

10.2 1.8-V Power............................................................ 55

10.3 Recommended Supply Load Capacitance..............55

11 Layout...........................................................................56

11.1 Layout Guidelines................................................... 56

11.2 Layout Example...................................................... 56

11.3 Component Placement............................................57

11.4 Routing PP_HV1/2, VBUS, PP_CABLE,

VIN_3V3, LDO_3V3, LDO_1V8.................................. 58

11.5 Routing CC and GPIO.............................................59

11.6 Thermal Dissipation for FET Drain Pads.................60

11.7 USB2 Recommended Routing For BC1.2

Detection/Advertisement............................................. 62

12 Device and Documentation Support..........................65

12.1 Device Support....................................................... 65

12.2 接收文档更新通知................................................... 65

12.3 支持资源..................................................................65

12.4 Trademarks.............................................................65

12.5 Electrostatic Discharge Caution..............................65

12.6 术语表..................................................................... 65

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 7

6.1 Absolute Maximum Ratings........................................ 7

6.2 ESD Ratings............................................................... 7

6.3 Recommended Operating Conditions.........................7

6.4 Thermal Information....................................................8

6.5 Power Supply Requirements and Characteristics.......8

6.6 Power Consumption Characteristics...........................9

6.7 Power Switch Characteristics..................................... 9

6.8 Cable Detection Characteristics................................11

6.9 USB-PD Baseband Signal Requirements and

Characteristics.............................................................12

6.10 BC1.2 Characteristics............................................. 13

6.11 Thermal Shutdown Characteristics......................... 14

6.12 Oscillator Characteristics........................................ 14

6.13 I/O Characteristics.................................................. 14

6.14 PWM Driver Characteristics....................................15

6.15 I²C Requirements and Characteristics....................15

6.16 SPI Controller Timing Requirements.......................16

6.17 HPD Timing Requirements..................................... 16

6.18 Typical Characteristics............................................17

7 Parameter Measurement Information..........................18

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................20

Information.................................................................... 66

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (August 2021) to Revision D (October 2022)

Page

• Updated pin image to read Pin 36: SPI_POCI (GPIO8) and Pin 37: SPI_PICO (GPIO9)..................................3

Changes from Revision B (January 2019) to Revision C (August 2021)

Page

• 更新了特性列表...................................................................................................................................................1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将提到SPI 的旧术语实例全局更改为控制器和外设............................................................................................1

• 更新了应用部分...................................................................................................................................................1

Changes from Revision A (August 2018) to Revision B (January 2019)

Page

• Changed Pin Description to better clarify that VBUS1 and VBUS2 should be tied together ............................. 3

• Changed 图9-1 and 图11-1 to use the Correct Pin Numbers ........................................................................ 45

Changes from Revision * (May 2018) to Revision A (August 2018)

Page

• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1

2

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5 Pin Configuration and Functions

PP_HV2 -1

PP_HV2 -2

VBUS2 -3

42- GPIO14 (PWM)

41- GPIO13

40- GPIO12

57

DRAIN2

39- SPI_CS (GPIO11)

VBUS2 -4

38- SPI_CLK (GPIO10)

37- SPI_PICO (GPIO9)

36- SPI_POCI (GPIO8)

VIN_3V3 -5

ADCIN1 -6

DRAIN2 -7

DRAIN1 -8

LDO_3V3 -9

59

GND

35- LDO_1V8

34- I2C2_IRQ

ADCIN2 -10

58

33- I2C2_SDA

32- I2C2_SCL

31- HPD2 (GPIO4)

30- HPD1 (GPIO3)

PP_HV1 -11

DRAIN1

PP_HV1 -12

VBUS1 -13

VBUS1 -14

29- I2C1_IRQ

图5-1. RSH Package 56-Pin QFN Top View

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表5-1. Pin Functions

TYPE⁽²⁾

RESET STATE⁽¹⁾

DESCRIPTION

NAME

NO.

Boot configuration Input. Connect to resistor

divider between LDO_3V3 and GND.

ADCIN1

6

I

Input

I2C address configuration Input. Connect to

resistor divider between LDO_3V3 and GND.

ADCIN2

C_CC1

C_CC2

10

24

26

I

Output to Type-C CC or VCONN pin . Filter noise

with capacitor to GND

I/O

High-Z

Output to Type-C CC or VCONN pin . Filter noise

with capacitor to GND

C_USB_N (GPIO19)

C_USB_P (GPIO18)

53

50

I/O

Input (High-Z)

USB D–connection for BC1.2 support

USB D+ connection for BC1.2 support

Drain of internal power path 1. Connect thermal

pad 58 to as big of pad as possible on PCB for

best thermal performance. Short the other pins to

this thermal pad

DRAIN1

8, 15, 19, 58

—

Drain of internal power path 2. Connect thermal

pad 57 to as big of pad as possible on PCB for

best thermal performance. Short the other pins to

this thermal pad

DRAIN2

GND

7, 52, 56, 57

—

20, 45 , 46, 47, 51

Unused pin. Tie to GND.

General Purpose Digital I/O 0. Float pin when

unused. GPIO0 is asserted low during the

TPS65987D boot process. Once device

configuration and patches are loaded GPIO0 is

released

GPIO0

16

I/O

Input (High-Z)

General Purpose Digital I/O 1. Ground pin with a

1-MΩresistor when unused in the application

GPIO1

GPIO2

17

18

I/O

Input (High-Z)

General Purpose Digital I/O 2. Float pin when

unused

General Purpose Digital I/O 3. Configured as Hot

Plug Detect (HPD) TX and RX when DisplayPort

alternate mode is enabled. Float pin when unused

GPIO3 (HPD)

GPIO4

30

31

21

I/O

Input (High-Z)

General Purpose Digital I/O 4. Float pin when

unused

I2C port 3 serial clock. Open-drain output. Tie pin

to I/O voltage through a 10-kΩresistance when

used. Float pin when unused

I2C3_SCL (GPIO5)

I2C port 3 serial data. Open-drain output. Tie pin to

I/O voltage through a 10-kΩresistance when

used. Float pin when unused

I2C3_SDA (GPIO6)

I2C3_IRQ (GPIO7)

22

23

I/O

Input (High-Z)

I2C port 3 interrupt detection (port 3 operates as

an I2C Master Only). Active low detection.

Connect to the I2C slave's interrupt line to detect

when the slave issues an interrupt. Float pin when

unused

General Purpose Digital I/O 12. Float pin when

unused

GPIO12

GPIO13

40

41

42

43

I/O

Input (High-Z)

General Purpose Digital I/O 13. Float pin when

unused

General Purpose Digital I/O 14. May also function

as a PWM output. Float pin when unused

GPIO14 (PWM)

GPIO15 (PWM)

General Purpose Digital I/O 15. May also function

as a PWM output. Float pin when unused

4

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NAME

表5-1. Pin Functions (continued)

TYPE⁽²⁾

RESET STATE⁽¹⁾

DESCRIPTION

NO.

General Purpose Digital I/O 16. May also function

as single wire enable signal for external power

path 1. Pull-down with external resistor when used

for external path control. Float pin when unused

GPIO16 (PP_EXT1)

GPIO17 (PP_EXT2)

48

I/O

Input (High-Z)

General Purpose Digital I/O 17. May also function

as single wire enable signal for external power

path 2. Pull-down with external resistor when used

for external path control. Float pin when unused

49

I/O

Input (High-Z)

General Purpose Digital I/O 20. Float pin when

unused

GPIO20

GPIO21

54

55

I/O

Input (High-Z)

General Purpose Digital I/O 21. Float pin when

unused

Active high hardware reset input. Will reinitialize all

device settings. Ground pin when HRESET

functionality will not be used

HRESET

I2C1_IRQ

I2C1_SCL

I2C1_SDA

I2C2_IRQ

I2C2_SCL

44

29

27

28

34

32

I/O

O

Input

I2C port 1 interrupt. Active low. Implement

externally as an open drain with a pull-up

resistance. Float pin when unused

High-Z

I2C port 1 serial clock. Open-drain output. Tie pin

to I/O voltage through a 10-kΩresistance when

used or unused

I/O

O

I2C port 1 serial data. Open-drain output. Tie pin to

I/O voltage through a 10-kΩresistance when used

or unused

I2C port 2 interrupt. Active low. Implement

externally as an open drain with a pull-up

resistance. Float pin when unused

I2C port 2 serial clock. Open-drain output. Tie pin

to I/O voltage through a 10-kΩresistance when

used or unused

I/O

I2C port 2 serial data. Open-drain output. Tie pin to

I/O voltage through a 10-kΩresistance when used

or unused

I2C2_SDA

LDO_1V8

33

35

I/O

High-Z

Output of the 1.8-V LDO for internal circuitry.

Bypass with capacitor to GND

PWR

—

Output of the VBUS to 3.3-V LDO or connected to

VIN_3V3 by a switch. Main internal supply rail.

Used to power external flash memory. Bypass with

capacitor to GND

LDO_3V3

9

PWR

—

5-V supply input for port 1 C_CC pins. Bypass with

capacitor to GND

PP_CABLE

PP_HV1

25

PWR

—

System side of first VBUS power switch. Bypass

with capacitor to ground. Tie to ground when

unused

11, 12

System side of second VBUS power switch.

Bypass with capacitor to ground. Tie to ground

when unused

PP_HV2

1, 2

PWR

—

SPI_CLK

38

36

I/O

Input

SPI serial clock. Ground pin when unused

SPI serial controller input from peripheral. Ground

pin when unused

SPI_POCI

SPI peripheral serial controller output to slave.

Ground pin when unused

SPI_PICO

SPI_CS

VBUS1

37

39

I/O

Input

—

SPI chip select. Ground pin when unused

Port side of first VBUS power switch. Bypass with

capacitor to ground. Tie to VBUS2

13, 14

PWR

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表5-1. Pin Functions (continued)

TYPE⁽²⁾

RESET STATE⁽¹⁾

DESCRIPTION

NAME

NO.

Port side of second VBUS power switch. Bypass

with capacitor to ground. Tie to VBUS1

VBUS2

3, 4

PWR

—

Supply for core circuitry and I/O. Bypass with

capacitor to GND

VIN_3V3

5

Ground reference for the device as well as thermal

pad used to conduct heat from the device. This

connection serves two purposes. The first purpose

is to provide an electrical ground connection for

the device. The second purpose is to provide a low

thermal-impedance path from the device die to the

PCB. This pad must be connected to a ground

plane

Thermal Pad (PPAD)

59

GND

—

(1) Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.

(2) I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect

6

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.5

–10

–55

MAX

UNIT

PP_CABLE

Input voltage⁽²⁾

6

V

VIN_3V3

3.6

LDO_1V8

2

Output voltage⁽²⁾LDO_3V3

3.6

V

I2Cx _IRQ, SPI_PICO, SPI_CLK, SPI_CS, SWD_CLK

PP_HVx, VBUSx

LDO_3V3 + 0.3 ⁽³⁾

24

I2Cx_SDA, I2Cx_SCL, SPI_POCI, GPIOn, HRESET, ADCINx

LDO_3V3 + 0.3 ⁽³⁾

I/O voltage ⁽²⁾

C_USB_P, C_USB_N

6

C_CC1, C_CC2

Operating junction temperature, T_J

Operating junction temperature PPHV switch, T_J

Storage temperature, T_stg

6

125

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to underside power pad. The underside power pad should be directly connected to the ground plane

of the board.

(3) Not to exceed 3.6V

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±1500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

3.135

2.95

4.5

4

NOM

MAX

UNIT

VIN_3V3

3.45

5.5

(1)

Input voltage, V_I

PP_CABLE

V

PP_HV

22

VBUS

22

C_USB_P, C_USB_N

0

LDO_3V3

5.5

(1)

I/O voltage, V_IO

V

C_CC1, C_CC2

0

GPIOn, I2Cx_SDA, I2Cx_SCL, SPI, ADCIN1, ADCIN2

0

LDO_3V3

75

Operating ambient temperature, T_A

Operating junction temperature, T_J

–10

°C

125

(1) All voltage values are with respect to underside power pad. Underside power pad must be directly connected to ground plane of the

board.

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6.4 Thermal Information

TPS65987

RSH (QFN)

48 PINS

57.7

THERMAL METRIC⁽¹⁾

UNIT

(2)

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

65.4

(2)

R_θJB

30

(2)

Junction-to-top characterization parameter

Junction-to-board characterization parameter

34.1

ψ_JT

(2)

29.9

ψ_JB

R_θ

Junction-to-case (bottom GND pad) thermal resistance

0.7

5.6

°C/W

JC(bot_Controller)

R_{θJC(bot_FET)}Junction-to-case (bottom DRAIN 1/2 pad) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Thermal metrics are not JDEC standard values and are based on the TPS65988 evaluation board.

6.5 Power Supply Requirements and Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

EXTERNAL

V_{IN_3V3}

Input 3.3-V supply

3.135

2.95

3.3

5

3.45

5.5

V

Input to power Vconn output on C_CC

pins

PP_CABLE

PP_HV

VBUS

Source power from PP_HV to VBUS

Sink power from VBUS to PP_HV

4.5

4

5

22

V

C_{VIN_3V3}

Recommended capacitance on the

VIN_3V3 pin

5

10

µF

C_{PP_CABLE}

Recommended capacitance on

PPx_CABLE pins

2.5

4.7

µF

C_{PP_HV_SRC}

Recommended capacitance on

PP_HVx pin when configured as a

source

C_{PP_HV_SNK}

Recommended capacitance on

PP_HVx pin when configured as a

sink

1

47

1

120

12

μF

C_VBUS

Recommended capacitance on

VBUSx pins

0.5

INTERNAL

Output voltage of LDO from VBUS to VIN_3V3 = 0 V, VBUS1 ≥4 V, 0 ≤

V_{LDO_3V3}

3.15

250

3.3

3.45

850

V

LDO_3V3

I

_LOAD≤50mA

Drop out voltage of LDO_3V3 from

VBUS

V_{DO_LDO_3V3}

I_LOAD= 50mA

500

mV

Allowed External Load current on

LDO_3V3 pin

I_{LDO_3V3_EX}

V_{LDO_1V8}

V_{FWD_DROP}

C_{LDO_3V3}

25

1.85

200

25

mA

V

Output voltage of LDO_1V8

1.75

1.8

0 ≤I_LOAD≤20mA

Forward voltage drop across VIN_3V3

to LDO_3V3 switch

I_LOAD= 50 mA

mV

μF

Recommended capacitance on

LDO_3V3 pin

5

10

C_{LDO_1V8}

Recommended capacitance on

LDO_1V8 pin

2.2

4.7

6

μF

8

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6.5 Power Supply Requirements and Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPERVISORY

UV_LDO3V3

UVH_LDO3V3

UV_PCBL

Undervoltage threshold for LDO_3V3.

Locks out 1.8-V LDOs

LDO_3V3 rising

2.2

20

2.325

80

2.45

150

V

mV

V

Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling

Undervoltage threshold for

PP_CABLE rising

PP_CABLE

2.5

2.625

2.75

Undervoltage hysteresis for

PP_CABLE falling

PP_PCABLE

UVH_PCBL

OV_VBUS

20

5

50

80

24

mV

V

Overvoltage threshold for VBUS. This

value is a 6-bit programmable

threshold

VBUS rising

Overvoltage threshold step for VBUS.

This value is the LSB of the

programmable threshold

OVLSB_VBUS

OVH_VBUS

UV_VBUS

VBUS rising

328

mV

%

Overvoltage hysteresis for VBUS

VBUS falling, % of OV_VBUS

VBUS falling

1.4

2.5

1.65

1.9

Undervoltage threshold for VBUS.

This value is a 6-bit programmable

threshold

18.21

V

Undervoltage threshold step for

VBUS. This value is the LSB of the

programmable threshold

UVLSB_VBUS

UVH_VBUS

VBUS falling

249

1.3

mV

%

Undervoltage hysteresis for VBUS

VBUS rising, % of UV_VBUS

0.9

1.7

6.6 Power Consumption Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Sleep (Sink)

VIN_3V3 = 3.3 V, VBUS = 0 V, No

cable connected, T_j= 25C, configured

as sink, BC1.2 disabled

45

µA

(1)

I_{VIN_3V3}

VIN_3V3 = 3.3 V, VBUS = 0 V, No

cable connected, T_j= 25C, configured

as source or DRP, BC1.2 disabled

Sleep (Source/DRP)

Idle (Attached)

Active

55

5

µA

mA

VIN_3V3 = 3.3 V, Cable connected,

No active PD communication, T_j= 25C

(1)

I_{VIN_3V3}

VIN_3V3 = 3.3 V, T_j= 25C

8

(1) Does not include current draw due to GPIO loading

6.7 Power Switch Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

222

269

MAX

325

UNIT

mΩ

4.7 ≤PP_CABLE ≤5.5

2.95 ≤PP_CABLE < 4.7

PP_CABLE to C_CCn power switch

resistance

R_PPCC

414

PP_HVx to VBUSx power switch

resistance

R_PPHV

I_PPHV

Tj = 25C

25

33

5

mΩ

Continuous current capabillity of

power path from PP_HVx to VBUSx

A

Continuous current capabillity of

power path from PP_CABLE to

C_CCn

T_J= 125C

T_J= 85C

320

600

mA

I_PPCC

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6.7 Power Switch Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Active quiescent current from PP_HV Source Configuration, Comparator

I_HVACT

I_HVSD

1

mA

pin, EN_HV = 1

RCP function enabled, I_LOAD= 100mA

Shutdown quiescent current from

PP_HV pin, EN_HV = 0

V_PPHV= 20V

100

µA

1.140

1.380

1.620

1.860

2.100

2.34

1.267

1.533

1.800

2.067

2.333

2.600

2.867

3.133

3.400

3.667

3.933

4.200

4.467

4.733

5.00

1.393

1.687

1.980

2.273

2.567

2.860

3.153

3.447

3.74

A

2.580

2.820

3.060

3.300

3.540

3.780

4.020

4.260

4.500

4.740

4.980

5.220

5.460

5.697

4.033

4.327

4.620

4.913

5.207

5.500

5.793

6.087

6.380

6.673

6.963

Over Current Clamp Firmware

Selectable Settings

I_OCC

5.267

5.533

5.800

6.067

6.330

I_OCP

I_LIMPPCC

I_{HV_ACC 1}

PP_HV Quick Response Current

Limit

10

0.75

6

PP_CABLE current limit

0.6

3.9

0.9

8.1

A

I = 100 mA, Reverse current blocking

disabled

PP_HV current sense accuracy

A/V

I_{HV_ACC 1}

PP_HV current sense accuracy

I = 200 mA

I = 500 mA

I ≥1 A

4.8

5.28

5.4

6

7.2

6.72

6.6

A/V

PP_HV path turn on time from

enable to VBUS = 95% of PP_HV

voltage

Configured as a source or as a sink

with soft start disabled. PP_HV = 20 V,

CVBUS = 10 µF, I_LOAD= 100 mA

t_{ON_HV}

t_{ON_FRS}

t_{ON_CC}

8

150

2

ms

μs

ms

PP_HV path turn on time from

enable to VBUS = 95% of PP_HV

voltage during an FRS enable

Configured as a source. PP_HV = 5 V,

CVBUS = 10 µF, I_LOAD= 100 mA

PP_CABLE path turn on time from

enable to C_CCn = 95% of the

PP_CABLE voltage

PP_CABLE = 5 V, C_CCn = 500 nF,

I_LOAD= 100 mA

I_LOAD= 100mA, setting 0

I_LOAD= 100mA, setting 1

I_LOAD= 100mA, setting 2

I_LOAD= 100mA, setting 3

Diode Mode

0.270

0.6

0.409

0.787

1.567

3.388

6

0.45

1

V/ms

mV

Configurable soft start slew rate for

sink configuration

SS

1.2

1.7

3.6

10

6

2.3

Reverse current blocking voltage

threshold for PP_HV switch

V_REVPHV

Comparator Mode

3

mV

10

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6.7 Power Switch Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.8

UNIT

V

Voltage that is a safe 0 V per USB-

PD specification

V_SAFE0V

t_SAFE0V

SRPOS

0

Voltage transition time to VSAFE0V

650

0.03

ms

Maximum slew rate for positive

voltage transitions

V/µs

Maximum slew rate for negative

voltage transitions

SRNEG

t_STABLE

V/µs

ms

–0.03

EN to stable time for both positive

and negative voltage transitions

275

Supply output tolerance beyond

V_SRCNEWduring time t_STABLE

V_SRCVALID

V_SRCNEW

t_VCONNDIS

0.5

5

V

%

–0.5

–5

Supply output tolerance

Time from cable detach to

VVCONNDIS

250

ms

Voltage at which V_CONNis

considered discharged

V_VCONNDIS

150

mV

6.8 Cable Detection Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Source Current through each C_CC pin when

in a disconnected state and Configured as a

Source advertising Default USB current to a

peripheral device

I_{H_CC_USB}

73.6

80

86.4

µA

Source Current through each C_CC pin when

in a disconnected state when Configured as a

Source advertising 1.5A to a UFP

I_{H_CC_1P5}

165.6

303.6

180

330

194.4

356.4

µA

Source Current through each C_CC pin when

in a disconnected state and Configured as a

Source advertising 3.0A to a UFP.

VIN_3V3 ≥3.135 V, V_CC

2.6 V

<

I_{H_CC_3P0}

Voltage Threshold for detecting a Source

attach when configured as a Sink and the

Source is advertising Default USB current

source capability

V_{D_CCH_USB}

0.15

0.2

0.25

V

Voltage Threshold for detecting a Source

advertising 1.5A source capability when

configured as a Sink

V_{D_CCH_1P5}

0.61

1.16

1.5

0.66

1.23

1.55

2.55

0.2

0.7

1.31

1.65

2.615

0.25

V

Voltage Threshold for detecting a Source

advertising 3A source capability when

configured as a Sink

V_{D_CCH_3P0}

Voltage Threshold for detecting a Sink attach

V_{H_CCD_USB}when configured as a Source and advertising

Default USB current source capability.

IH_CC = IH_CC_USB

IH_CC = IH_CC_1P5

Voltage Threshold for detecting a Sink attach

when configured as a Source and advertising

1.5A source capability

V_{H_CCD_1P5}

1.5

Voltage Threshold for detecting a Sink attach

when configured as a Source and advertising

3.0A source capability.

IH_CC = IH_CC_3P0

VIN_3V3 ≥3.135V

V_{H_CCD_3P0}

2.45

0.15

Voltage Threshold for detecting an active cable

V_{H_CCA_USB}attach when configured as a Source and

advertising Default USB current capability.

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6.8 Cable Detection Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage Threshold for detecting active cables

attach when configured as a Source and

advertising 1.5A capability.

V_{H_CCA_1P5}

0.35

0.4

0.45

V

Voltage Threshold for detecting active cables

attach when configured as a Source and

advertising 3A capability.

V_{H_CCA_3P0}

0.75

4.59

0.8

5.1

0.85

5.61

V

Pulldown resistance through each C_CC pin

when in a disconnect state and configured as a V = 1V, 1.5V

Sink. LDO_3V3 powered.

R_{D_CC}

kΩ

Pulldown resistance through each C_CC pin

when in a disabled state. LDO_3V3 powered.

R_{D_CC_OPEN}

V = 0V to LDO_3V3

V = 1.5V, 2.0V

500

kΩ

Pulldown resistance through each C_CC pin

when LDO_3V3 unpowered

R_{D_DB}

4.08

5.1

6.12

5

R_FRSWAP

V_{TH_FRS}

Fast Role Swap signal pull down

Ω

Fast role swap request detection voltage

threshold

490

520

550

mV

6.9 USB-PD Baseband Signal Requirements and Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

COMMON

PD_BITRATE

UI ⁽²⁾

PD data bit rate

270

300

330

3.7

Kbps

µs

Unit interval (1/PD_BITRATE)

Capacitance for a cable plug (each

3.03

3.33

CCBLPLUG ⁽¹⁾plug on a cable may have up to this

value)

25

65

pF

ZCABLE

Cable characteristic impedance

32

Ω

Receiver capacitance. Capacitance

CRECEIVER ⁽³⁾looking into C_CCn pin when in

receiver mode.

100

pF

TRANSMITTER

TX output impedance. Source

output impedance at the Nyquist

ZDRIVER

frequency of USB2.0 low speed

(750kHz) while the source is driving

the C_CCn line.

33

75

Ω

Rise time. 10 % to 90 % amplitude

points, minimum is under an

unloaded condition. Maximum set

by TX mask.

t_RISE

300

ns

Fall time. 90 % to 10 % amplitude

points, minimum is under an

unloaded condition. Maximum set

by TX mask.

t_FALL

300

ns

V

V_TX

Transmit high voltage

1.05

1.125

1.2

RECEIVER

V_RXTR

V_RXTF

Rx receive rising input threshold

Rx receive falling input threshold

Port configured as Source

Port configured as Sink

Port configured as Source

840

504

240

576

875

525

250

600

910

546

260

624

mV

V_RXTF

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6.9 USB-PD Baseband Signal Requirements and Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Number of transitions for signal

detection (number to count to

detect non-idle bus).

NCOUNT

TTRANWIN

ZBMCRX

3

Time window for detecting non-idle

bus.

12

5

20

µs

Does not include pull-up or pulldown

resistance from cable detect.

Transmitter is Hi-Z.

Receiver input impedance

MΩ

Rx bandwidth limiting filter. Time

TRXFILTER ⁽⁴⁾constant of a single pole filter to

limit broadband noise ingression

100

ns

(1) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.

(2) UI denotes the time to transmit an unencoded data bit not the shortest high or low times on the wire after encoding with BMC. A single

data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the

transition at the start of the cell.

(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External

capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends adding capacitance

to bring the total pin capacitance to 300 pF for improved TX behavior.

(4) Broadband noise ingression is because of coupling in the cable interconnect.

6.10 BC1.2 Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DATA CONTACT

DETECT

ID_{P_SRC}

DCD source current

LDO_3V3 = 3.3 V

7

14.25

10

20

13

24.8

µA

kΩ

R_{DM_DWN}

R_{DP_DWN}

DCD pulldown resistance

C_USB_P ≥VLGC_HI, LDO_3V3 =

3.3 V

V_{LGC_HI}

V_{LGC_LO}

Threshold for no connection

Threshold for connection

2

V

0.8

C_USB_P ≤VLGC_LO

PRIMARY AND SECONDARY

DETECT

V_{DX_SRC}

VDX_ILIM

I_{DX_SNK}

Source voltage

0.55

250

25

0.6

75

0.65

400

125

200

V

VDX_SRC current limit

Sink Current

µA

VC_USB_TN/BN ≥250 mV

R_{DCP_DAT}

Dedicated Charging Port Resistance

Ω

DIVIDER MODE

VCx_USB_P Cx_USB_P Output Voltage

_2.7V

No load on Cx_USB_P

2.57

24

2.7

30

2.79

36

V

VCx_USB_N Cx_USB_N Output Voltage

_2.7V

No load on Cx_USB_N

RCx_USB_P Cx_USB_P Output Impedance

_30k

5µA pulled from Cx_USB_P pin

5µA pulled from Cx_USB_N pin

kΩ

RCx_USB_N Cx_USB_N Output Impedance

_30k

24

30

36

1.2V MODE

RCx_USB_N Cx_USB_N Output Impedance

_102k

5µA pulled from Cx_USB_N pin

No load on Cx_USB_P

80

102

1.2

130

kΩ

VCx_USB_P Cx_USB_P Output Voltage

_1.2V

1.12

1.28

V

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCx_USB_N Cx_USB_N Output Voltage

_1.2V

No load on Cx_USB_N

1.12

1.2

1.28

V

RCx_USB_P Cx_USB_P Output Impedance

_102k

5µA pulled from Cx_USB_P pin

80

102

130

kΩ

6.11 Thermal Shutdown Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Thermal Shutdown Temperature of the

main thermal shutdown

T_{SD_MAIN}

T_{SDH_MAIN}

T_{SD_PWR}

T_{SDH_PWR}

Temperature rising

Temperature falling

Temperature rising

Temperature falling

145

160

175

°C

Thermal Shutdown hysteresis of the

main thermal shutdown

20

160

20

°C

Thermal Shutdown Temperature of the

power path block

145

175

Thermal Shutdown hysteresis of the

power path block

6.12 Oscillator Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

24-MHz oscillator

100-kHz oscillator

TEST CONDITIONS

MIN

22.8

95

TYP

24

MAX

25.2

105

UNIT

MHz

kHz

ƒ_{OSC_24M}

ƒ_{OSC_100K}

100

6.13 I/O Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SPI

SPI_VIH

High-level input voltage

Low input voltage

LDO_1V8 = 1.8V

1.3

V

SPI_VIL

LDO_1V8 = 1.8V

0.63

1

SPI_HYS

SPI_ILKG

SPI_VOH

SPI_VOL

SWDIO

Input hysteresis voltage

Leakage current

LDO_1V8 = 1.8V

0.09

-1

V

Output is Hi-Z, VIN = 0 to LDO_3V3

IO = –2 mA, LDO_3V3 = 3.3 V

IO = 2 mA

µA

V

SPI output high voltage

SPI output low voltage

2.88

0.4

V

SWDCLK

GPIO

GPIO_VIH

GPIO_VIL

GPIO_HYS

GPIO_ILKG

GPIO_RPU

GPIO_RPD

GPIO_DG

GPIO_VOH

GPIO_VOL

I2C_IRQx

OD_VOL

High-level input voltage

Low input voltage

LDO_1V8 = 1.8 V

INPUT = 0 V to VDD

Pullup enabled

1.3

V

0.63

Input hysteresis voltage

I/O leakage current

0.09

–1

50

V

1

150

µA

Pullup resistance

100

20

kΩ

ns

V

Pulldown resistance

Digital input path deglitch

GPIO output high voltage

GPIO output low voltage

Pulldown enabled

50

2.88

IO = –2 mA, LDO_3V3 = 3.3 V

IO = 2 mA, LDO_3V3 = 3.3 V

0.4

V

Low-level output voltage

I_OL= 2 mA

V

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OD_LKG

Leakage current

Output is Hi-Z, VIN = 0 to LDO_3V3

1

µA

–1

6.14 PWM Driver Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

391

94

TYP

MAX

6250

1500

UNIT

Hz

PWM clock = 100kHz

PWM clock = 24MHz

PWM clock = OSC_100K

F_PWM

PWM frequency

kHz

Hz

Frequency step for PWM driver. This

FLSB_PWM value is the LSB of the programmable

frequency

391

94

PWM clock = OSC_24M

kHz

6.15 I²C Requirements and Characteristics

over operating free-air temperature range (unless otherwise noted).

PARAMETER

SDA AND SCL COMMON

CHARACTERISTICS

I_LEAKInput leakage current

V_OL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage on Pin = LDO_3V3

I_OL= 3 mA, LDO_3V3 = 3.3 V

V_OL= 0.4 V

3

µA

V

–3

SDA output low voltage

0.4

3

6

mA

V

I_OL

SDA max output low current

V_OL= 0.6 V

LDO_3V3 = 3.3 V

LDO_1V8 = 1.8 V

LDO_3V3 = 3.3 V

LDO_1V8 = 1.8 V

LDO_3V3 = 3.3 V

LDO_1V8 = 1.8 V

0.99

0.54

V_IL

Input low signal

Input high signal

Input hysteresis

V

2.31

1.3

V

V_IH

V

0.17

0.09

V

V_HYS

V

t_SP

C_I

I²C pulse width suppressed

Pin capacitance

50

10

ns

pF

SDA AND SCL STANDARD

MODE CHARACTERISTICS

I²C clock frequency

0

4

100

kHz

µs

ns

ƒ_SCL

t_HIGH

I²C clock high time

t_LOW

I²C clock low time

4.7

250

0

t_SU;DAT

t_HD;DAT

t_VD;DAT

I²C serial data setup time

I²C serial data hold time

I²C valid data time

ns

SCL low to SDA output valid

3.45

250

µs

ACK signal from SCL low to SDA (out)

low

t_VD;ACK

t_OCF

I²C valid data time of ACK condition

I²C output fall time

µs

ns

µs

10 pF to 400 pF bus

I²C bus free time between stop and

start

t_BUF

4.7

I²C start or repeated Start condition

setup time

t_SU;STA

µs

I²C Start or repeated Start condition

hold time

t_HD;STA

t_SU;STO

4

µs

I²C Stop condition setup time

SDA AND SCL FAST MODE

CHARACTERISTICS

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6.15 I²C Requirements and Characteristics (continued)

over operating free-air temperature range (unless otherwise noted).

PARAMETER

I²C clock frequency

I²C clock high time

I²C clock low time

TEST CONDITIONS

MIN

0

TYP

MAX

400

UNIT

kHz

µs

Configured as Slave

Configured as Master

ƒ_SCL

0

320

400

ƒ_{SCL_MASTER}

t_HIGH

0.6

1.3

100

0

t_LOW

µs

t_SU;DAT

t_HD;DAT

t_VD;DAT

I²C serial data setup time

I²C serial data hold time

I²C Valid data time

ns

SCL low to SDA output valid

0.9

µs

ACK signal from SCL low to SDA (out)

low

t_VD;ACK

I²C Valid data time of ACK condition

I²C output fall time

µs

10 pF to 400 pF bus, V_DD= 3.3 V

10 pF to 400 pF bus, V_DD= 1.8 V

12

250

ns

t_OCF

6.5

I²C bus free time between stop and

start

t_BUF

1.3

0.6

µs

I²C start or repeated Start condition

setup time

t_SU;STA

I²C Start or repeated Start condition

hold time

t_HD;STA

t_SU;STO

0.6

µs

I²C Stop condition setup time

6.16 SPI Controller Timing Requirements

MIN

11.4

79.36

30

NOM

12

MAX

12.6

UNIT

MHz

ns

Frequency of SPI_CLK

ƒ_SPI

t_PER

Period of SPI_CLK (1/F_SPI)

83.33

87.72

t_WHI

SPI_CLK high width

ns

t_WLO

SPI_CLK low width

30

ns

t_DACT

t_DINACT

t_DPICO

t_SUPOCI

t_HDMSIO

t_RIN

SPI_SZZ falling to SPI_CLK rising delay time

SPI_CLK falling to SPI_CSZ rising delay time

SPI_CLK falling to SPI_PICO Valid delay time

SPI_POCI valid to SPI_CLK falling setup time

SPI_CLK falling to SPI_POCI invalid hold time

SPI_POCI input rise time

30

50

180

10

ns

158

–10

33

ns

0

ns

5

ns

10% to 90%, C_L= 5 to 50 pF, LDO_3V3 =

3.3 V

t_RSPI

t_FSPI

SPI_CSZ/CLK/PICO rise time

SPI_CSZ/CLK/PICO fall time

1

25

ns

90% to 10%, C_L= 5 to 50 pF, LDO_3V3 =

3.3 V

25

6.17 HPD Timing Requirements

MIN

NOM

MAX

UNIT

DP SOURCE SIDE (HPD

TX)

t_{IRQ_MIN}

HPD IRQ minimum assert time

HPD assert 2-ms min time

675

3

750

825

µs

t_{2 MS_MIN}

3.33

3.67

ms

DP SINK SIDE (HPD

RX)

HPD_HDB_SEL = 0

HPD_HDB_SEL = 1

300

100

375

111

450

122

µs

t_{HPD_HDB}

HPD high debounce time

ms

16

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MIN

300

NOM

375

1.5

MAX

450

UNIT

µs

t_{HPD_LDB}

t_{HPD_IRQ}

HPD low debounce time

HPD IRQ limit time

1.35

1.65

ms

6.18 Typical Characteristics

32

30

28

26

24

22

-20

0

20

40

60

80

Temperature (°C)

100

120

140

D004

图6-1. PPHVx Rdson vs Junction Temperature

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7 Parameter Measurement Information

t

f

t

r

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

cont.

t

HD;DAT

VD;DAT

t

f

t

HIGH

t

r

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

SCL

t

HD;STA

t

LOW

th

9

clock

1 / f

S

SCL

st

1

clock cycle

t

BUF

SDA

SCL

t

VD;ACK

t

SU;STO

SU;STA

HD;STA

SP

70 %

30 %

Sr

P

S

th

9

clock

002aac938

图7-1. I²C Slave Interface Timing

t

wlow

per

whigh

SPI_CSZ

SPI_CLK

t

dinact

dact

t

dpico

SPI_PICO

SPI_POCI

Valid Data

t

supoci

Valid Data

t

hdpoci

图7-2. SPI Controller Timing

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8 Detailed Description

8.1 Overview

The TPS65987D is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug

and orientation detection for a USB Type-C and PD plug or receptacles. The TPS65987D communicates with the

cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power

switch, controls an external high current port power switch, and negotiates alternate modes . The TPS65987D

may also control an attached super-speed multiplexer via GPIO or I²C to simultaneously support USB3.0/3.1

data rates and DisplayPort video.

The TPS65987D is divided into five main sections: the USB-PD controller, the cable plug and orientation

detection circuitry, the port power switches, the power management circuitry, and the digital core.

The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD

data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible

USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and

more detailed circuitry, see the USB-PD Physical Layer section.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug

insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and

orientation detection, a description of its features and more detailed circuitry, see the Cable Plug and Orientation

Detection section.

The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or

C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a

description of its features and more detailed circuitry, see the Port Power Switches section.

The power management circuitry receives and provides power to the TPS65987D internal circuitry and to the

LDO_3V3 output. For a high-level block diagram of the power management circuitry, a description of its features

and more detailed circuitry, see the Power Management section.

The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as

handling control of all other TPS65987D functionality. A portion of the digital core contains ROM memory which

contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the

ROM, called boot code, is capable of initializing the TPS65987D, loading of device configuration information,

and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the

digital core, a description of its features and more detailed circuitry, see the Digital Core section.

The TPS65987D is an I²C slave to be controlled by a host processor (see the I²Interfaces section), and an SPI

controller to write to and read from an optional external flash memory (see the SPI Controller Interface section).

The TPS65987D also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs off

of accurate clocks provided by the integrated oscillators (see the Oscillators section).

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8.2 Functional Block Diagram

PP_HV1

VBUS1

5 A

PP_HV2

VBUS2

5 A

600 mA

PP_CABLE

LDO_3V3

LDO_1V8

VIN_3V3

HRESET

Power & Supervisor

ADCIN1

Cable Detect &

USB-PD Phy

Cable Power

ADCIN2

C_CC1

C_CC2

5

GPIO0-4

6

GPIO12-17

2

GPIO20-21

Core

&

Other Digital

3

I2C1_SDA/SCL/IRQ

3

I2C2_SDA/SCL/IRQ

3

Charger

Detection &

2

I2C3_SDA/SCL/IRQ

C_USB_P/N

4

SPI_PICO/POCI/CS/CLK

PPAD

8.3 Feature Description

8.3.1 USB-PD Physical Layer

图 8-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and

orientation detection block.

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Fast

current

limit

600 mA

PP_CABLE

C_CC1 Gate Control

and Current Limit

LDO_3V3

C_CC1

C_CC2

Digital

Core

USB-PD

Decode

LDO_3V3

C_CC1 Gate Control

and Current Limit

Fast

current

limit

图8-1. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry

USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output

on the same pin (C_CC1 or C_CC2) that is DC biased due to the DFP (or UFP) cable attach mechanism

discussed in the 节8.3.4 section.

8.3.1.1 USB-PD Encoding and Signaling

图 8-2 illustrates the high-level block diagram of the baseband USB-PD transmitter. 图 8-3 illustrates the high-

level block diagram of the baseband USB-PD receiver.

4b5b

Encoder

BMC

Encoder

Data

to PD_TX

CRC

图8-2. USB-PD Baseband Transmitter Block Diagram

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Data

BMC

Decoder

SOP

Detect

4b5b

Decoder

from PD_RX

CRC

图8-3. USB-PD Baseband Receiver Block Diagram

The USB-PD baseband signal is driven on the C_CCn pins with a tri-state driver. The tri-state driver is slew rate

limited to reduce the high frequency components imparted on the cable and to avoid interference with

frequencies used for communication.

8.3.1.2 USB-PD Bi-Phase Marked Coding

The USBP-PD physical layer implemented in the TPS65987D is compliant to the USB-PD Specifications. The

encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark

Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in

the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity

(limited to 1/2 bit over an arbitrary packet, so a very low DC level). 图8-4 illustrates Biphase Mark Coding.

0

1

0

1

0

1

0

1

0

1

0

1

Data in

BMC

图8-4. Biphase Mark Coding Example

The USB PD baseband signal is driven onto the C_CC1 or C_CC2 pins with a tri-state driver. The tri-state driver

is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When

sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end

tolerates the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver

clocks the final bit of EOP.

8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks

The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal

edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning,

the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The

boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground

offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly,

the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time

masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge

rate that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits

on the rise and fall times. Refer to the USB-PD Specifications for more details.

8.3.1.4 USB-PD BMC Transmitter

The TPS65987D transmits and receives USB-PD data over one of the C_CCn pins for a given CC pin pair (one

pair per USB Type-C port). The C_CCn pins are also used to determine the cable orientation (see the 节 8.3.4

section) and maintain cable/device attach detection. Thus, a DC bias exists on the C_CCn pins. The transmitter

driver overdrives the C_CCn DC bias while transmitting, but returns to a Hi-Z state allowing the DC voltage to

return to the C_CCn pin when not transmitting. 图8-5 shows the USB-PD BMC TX and RX driver block diagram.

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LDO_3V3

Driver

Level

Shifter

PD_TX

PD_RX

C_CC1

C_CC2

Level

Shifter

Digitally

Adjustable

VREF

USB-PD Modem

图8-5. USB-PD BMC TX/Rx Block Diagram

图 8-6 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere

between the minimum threshold for detecting a UFP attach (VD_CCH_USB) and the maximum threshold for

detecting a UFP attach to a DFP (VD_CCH_3P0). This means that the DC bias can be below VOH of the

transmitter driver or above VOH.

VOH

DC Bias

VOL

VOH

DC Bias

VOL

图8-6. TX Driver Transmission with DC Bias

The transmitter drives a digital signal onto the C_CCn lines. The signal peak, VTXP, is set to meet the TX masks

defined in the USB-PD Specifications.

When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by

the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts

the noise ingression in the cable.

图 8-7 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is

bounded.

R_DRIVER

Z_DRIVER

Driver

C_DRIVER

图8-7. ZDRIVER Circuit

8.3.1.5 USB-PD BMC Receiver

The receiver block of the TPS65987D receives a signal that falls within the allowed Rx masks defined in the USB

PD specification. The receive thresholds and hysteresis come from this mask.

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图 8-8 shows an example of a multi-drop USB-PD connection. This connection has the typical UFP (device) to

DFP (host) connection, but also includes cable USB-PD TX/Rx blocks. Only one system can be transmitting at a

time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can

exist on the wire as well as a typical DC bias setting circuit for attach detection.

UFP

DFP

System

Pullup

Cable

for Attach

Detection

Connector

Tx

Rx

Tx

Rx

RD

for Attach

Detection

C_RECEIVER

C_CBLPLUG

图8-8. Example USB-PD Multi-Drop Configuration

8.3.2 Power Management

The TPS65987D power management block receives power and generates voltages to provide power to the

TPS65987D internal circuitry. These generated power rails are LDO_3V3 and LDO_1V8. LDO_3V3 may also be

used as a low power output for external flash memory. The power supply path is shown in 图8-9.

VIN_3V3

VBUS1

VREF

LDO

LDO_3V3

LDO_1V8

VREF

LDO

图8-9. Power Supplies

The TPS65987D is powered from either VIN_3V3, VBUS1, or VBUS2. The normal power supply input is

VIN3V3. In this mode, current flows from VIN_3V3 to LDO3V3 to power the core 3.3-V circuitry and I/Os. A

second LDO steps the voltage down from LDO_3V3 to LDO_1V8 to power the 1.8-V core digital circuitry. When

VIn_3V3 power is unavailable and power is available on VBUS1 or VBUS2 , the TPS65987D is powered from

VBUS. In this mode, the voltage on VBUS1 or VBUS 2 is stepped down through an LDO to LDO_3V3.

8.3.2.1 Power-On And Supervisory Functions

A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a

good supply is present.

8.3.2.2 VBUS LDO

The TPS65987D contains an internal high-voltage LDO which is capable of converting up to 22 V from VBUS to

3.3 V for powering internal device circuitry. The VBUS LDO is only utilized during dead battery operation while

the VIN_3V3 supply is not present. The VBUS LDO may be powered from either VBUS1 or VBUS2. The path

connecting each VBUS to the internal LDO blocks reverse current, preventing power on one VBUS from leaking

to the other. When power is present on both VBUS inputs, the internal LDO draws current from both VBUS pins.

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8.3.2.3 Supply Switch Over

VIN_3V3 takes precedence over VBUS, meaning that when both supply voltages are present the TPS65987D

powers from VIN_3V3. See 图 8-9 for a diagram showing the power supply path block. There are two cases in

which a power supply switch-over occurs. The first is when VBUS is present first and then VIN_3V3 becomes

available. In this case, the supply automatically switches over to VIN_3V3 and brown-out prevention is verified

by design. The other way a supply switch-over occurs is when both supplies are present and VIN_3V3 is

removed and falls below 2.85 V. In this case, a hard reset of the TPS65987D is initiated by device firmware,

prompting a re-boot.

8.3.3 Port Power Switches

图 8-10 shows the TPS65987D internal power paths. The TPS65987D features two internal high-voltage power

paths. Each path contains two back to back common drain N-Fets, current monitor, overvoltage monitor,

undervoltage monitor, and temperature sensing circuitry. Each path may conduct up to 5 A safely. Additional

external paths may be controlled through the TPS65987D GPIOs.

Fast

current

limit

5A

PP_HV2

PP_HV1

VBUS2

VBUS1

Fast

current

limit

5A

PP_EXT1 (GPIO16)

PP_EXT2(GPIO17)

Dead

Battery

Supply

HV Gate Control and

Sense

HV Gate Control and

Sense

C_CC1 Gate

Control

Fast

current

limit

PP_CABLE

C_CC1

600mA

C_CC2 Gate

Control

C_CC2

图8-10. Port Power Switches

8.3.3.1 PP_HV Power Switch

The TPS65987D has two integrated bi-directional high-voltage switches that are rated for up to 5 A of current.

Each switch may be used as either a sink or source path for supporting USB-PD power up to 20 V at 5 A of

current.

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备注

The power paths can sustain up to 5A of continuous current as long as the internal junction

temperature of each path remains below 150C. Care should be taken to follow the layout

recommendations described in Thermal Dissipation for FET Drain Pads

备注

It is recommended to use PPHV1 as a sink path and PPHV2 as a source path.

8.3.3.1.1 PP_HV Over Current Clamp

The internal source PP_HV path has an integrated over-current clamp circuit. The current through the internal

PP_HV paths are current limited to I_OCC. The I_OCCvalue is selected by application firmware and only enabled

while acting as a source. When the current through the switch exceeds I_OCC, the current clamping circuit

activates and the path behaves as a constant current source. If the duration of the over current event exceeds

the deglitch time, the switch is latched off.

8.3.3.1.2 PP_HV Over Current Protection

The TPS65987D continuously monitors the forward voltage drop across the internal power switches. When a

forward drop corresponding to a forward current of I_OCPis detected the internal power switch is latched off to

protect the internal switches as well as upstream power supplies.

8.3.3.1.3 PP_HV OVP and UVP

Both the over voltage and under voltage protection levels are configured by application firmware. When the

voltage on a port's VBUS pin exceeds the set over voltage threshold or falls below the set under voltage

threshold the associated PP_HV path is automatically disabled.

8.3.3.1.4 PP_HV Reverse Current Protection

The TPS65987D reverse current protection has two modes of operation: Comparator mode and Ideal Diode

Mode. Both modes disable the power switch in cases of reverse current. The comparator protection mode is

enabled when the switch is operating as a source, while the ideal diode protection is enabled while operating as

a sink.

In the Comparator mode of reverse current protection, the power switch is allowed to behave resistively until the

current reaches then amount calculated by 方程式 1 and then blocks reverse current from VBUS to PP_HV. 图

8-11 shows the diode behavior of the switch with comparator mode enabled.

IREVHV = VREVHV/RPPHV

(1)

I

1/RPPHV

VREVHV

V

IREVHV

图8-11. Comparator Mode (Source) Internal HV Switch I-V Curve

In the Ideal Diode mode of reverse current protection, the switch behaves as an ideal diode and blocks reverse

current from PP_HV to VBUS. 图8-12 shows the diode behavior of the switch with ideal diode mode enabled.

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I

1/RPPHV

VREVHV/RPPHV

VBUS-PP_HV

VREVHV

图8-12. Ideal Diode Mode (Sink) Internal HV Switch I-V Curve

8.3.3.2 Schottky for Current Surge Protection

To prevent the possibility of large ground currents into the TPS65987D during sudden disconnects due to

inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to ground as shown

in 图8-13.

PP_HV2

PP_HV1

VBUS2

VBUS1

PPAD

图8-13. Schottky for Current Surge Protection

8.3.3.3 PP_EXT Power Path Control

GPIO16 and GPIO17 of the TPS65987D are intended for control of additional external power paths. These

GPIO are active high when configured for external path control and disables in response to an OVP or UVP

event. Over current protection and thermal shutdown are not available for external power paths controlled by

GPIO16 and GPIO17.

备注

GPIO16 and GPIO17 must be pulled to ground through an external pull-down resistor when utilized as

external path control signals.

8.3.3.4 PP_CABLE Power Switch

The TPS65987D has an integrated 5-V unidirectional power mux that is rated for up to 600 mA of current. The

mux may supply power to either of the port CC pins for use as VCONN power.

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8.3.3.4.1 PP_CABLE Over Current Protection

When enabled and providing VCONN power the TPS65987D PP_CABLE power switches have a 600 mA

current limit. When the current through the PP_CABLE switch exceeds 600 mA, the current limiting circuit

activates and the switch behaves as a constant current source. The switches do not have reverse current

blocking when the switch is enabled and current is flowing to either C_CC1 or C_CC2.

8.3.3.4.2 PP_CABLE Input Good Monitor

The TPS65987D monitors the voltage at the PP_CABLE pins prior to enabling the power switch. If the voltage at

PP_CABLE exceeds the input good threshold the switch is allowed to close, otherwise the switch remains open.

Once the switch has been enabled, PP_CABLE is allowed to fall below the input good threshold.

8.3.3.5 VBUS Transition to VSAFE5V

The TPS65987D has an integrated active pull-down on VBUS for transitioning from high voltage to VSAFE5V.

When the high voltage switch is disabled and VBUS > VSAFE5V, an amplifier turns on a current source and

pulls down on VBUS. The amplifier implements active slew rate control by adjusting the pull-down current to

prevent the slew rate from exceeding specification. When VBUS falls to VSAFE5V, the pull-down is turned off.

8.3.3.6 VBUS Transition to VSAFE0V

When VBUS transitions to near 0 V (VSAFE0V), the pull-down circuit in VBUS Transition to VSAFE5V is turned

on until VBUS reaches VSAFE0V. This transition occurs within time TSAFE0V.

8.3.4 Cable Plug and Orientation Detection

图 8-14 shows the plug and orientation detection block at each C_CCn pin (C_CC1, C_CC2). Each pin has

identical detection circuitry.

LDO_3V3

IH_CC_STD

IH_CC_1P5

IH_CC_3P0

VREF1

VREF2

VREF3

C_CCn

RD_CC

图8-14. Plug and Orientation Detection Block

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8.3.4.1 Configured as a DFP

When one of the TPS65987D ports is configured as a DFP, the device detects when a cable or a UFP is

attached using the C_CC1 and C_CC2 pins. When in a disconnected state, the TPS65987D monitors the

voltages on these pins to determine what, if anything, is connected. See USB Type-C Specification for more

information.

表8-1 shows the Cable Detect States for a DFP.

表8-1. Cable Detect States for a DFP

C_CC1 C_CC2

CONNECTION STATE

Open Nothing attached

Open UFP attached

RESULTING ACTION

Continue monitoring both C_CC pins for attach. Power is not applied to VBUS or

VCONN until a UFP connect is detected.

Open

Rd

Monitor C_CC1 for detach. Power is applied to VBUS but not to VCONN (C_CC2).

Monitor C_CC2 for detach. Power is applied to VBUS but not to VCONN (C_CC1).

Open

Rd

UFP attached

Powered Cable-No UFP

attached

Monitor C_CC2 for a UFP attach and C_CC1 for cable detach. Power is not applied to

VBUS or VCONN (C_CC1) until a UFP attach is detected.

Ra

Open

Ra

Open

Powered Cable-No UFP

attached

Monitor C_CC1 for a UFP attach and C_CC2 for cable detach. Power is not applied to

VBUS or VCONN (C_CC1) until a UFP attach is detected.

Ra

Rd

Ra

Rd

Ra

Provide power on VBUS and VCONN (C_CC1) then monitor C_CC2 for a UFP

detach. C_CC1 is not monitored for a detach.

Powered Cable-UFP Attached

Powered Cable-UFP attached

Provide power on VBUS and VCONN (C_CC2) then monitor C_CC1 for a UFP

detach. C_CC2 is not monitored for a detach.

Rd

Debug Accessory Mode

attached

Rd

Sense either C_CC pin for detach.

Audio Adapter Accessory

Mode attached

Ra

When a TPS65987D port is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin is

monitored for different states. When a UFP is attached to the pin a pull-down resistance of Rd to GND exists.

The current IH_CC is then forced across the resistance Rd generating a voltage at the C_CCn pin.

When configured as a DFP advertising Default USB current sourcing capability, the TPS65987D applies

IH_CC_USB to each C_CCn pin. When a UFP with a pull-down resistance Rd is attached, the voltage on the

C_CCn pin pulls below VH_CCD_USB. The TPS65987D can be configured to advertise default (500 mA or 900

mA), 1.5-A and 3-A sourcing capabilities when acting as a DFP.

When the C_CCn pin is connected to an active cable VCONN input, the pull-down resistance is different (Ra). In

this case the voltage on the C_CCn pin will pull below VH_CCA_USB/1P5/3P0 and the system recognizes the

active cable.

The VH_CCD_USB/1P5/3P0 thresholds are monitored to detect a disconnection from each of these cases

respectively. When a connection has been recognized and the voltage on the C_CCn pin rises above the

VH_CCD_USB/1P5/3P0 threshold, the system registers a disconnection.

8.3.4.2 Configured as a UFP

When a TPS65987D port is configured as a UFP, the TPS65987D presents a pull-down resistance RD_CC on

each C_CCn pin and waits for a DFP to attach and pull-up the voltage on the pin. The DFP pulls-up the C_CCn

pin by applying either a resistance or a current. The UFP detects an attachment by the presence of VBUS. The

UFP determines the advertised current from the DFP by the pull-up applied to the C_CCn pin.

8.3.4.3 Configured as a DRP

When a TPS65987D port is configured as a DRP, the TPS65987D alternates the port's C_CCn pins between the

pull-down resistance, Rd, and pull-up current source, Rp.

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8.3.4.4 Fast Role Swap Signaling

The TPS65987D cable plug block contains additional circuitry that may be used to support the Fast Role Swap

(FRS) behavior defined in the USB Power Delivery Specification. The circuitry provided for this functionality is

detailed in 图8-15.

C_CC1

To Cable

Detect and

Orientation

C_CC2

R_FRSWAP

To Digital Core

VREF

图8-15. Fast Role Swap Detection and Signaling

When a TPS65987D port is operating as a sink with FRS enabled, the TPS65987D monitors the CC pin voltage.

If the CC voltage falls below VTH_FRS a fast role swap situation is detected and signaled to the digital core.

When this signal is detected the TPS65987D ceases operating as a sink and begin operating as a source.

When a TPS65987D port is operating as a source with FRS enabled, the TPS65987D digital core can signal to

the connected port partner that a fast role swap is required by enabling the R_FRSWAP pull down on the

connected CC pin. When this signal is sent the TPS65987D ceases operating as the source and begin operating

as a sink.

8.3.5 Dead Battery Operation

8.3.5.1 Dead Battery Advertisement

The TPS65987D supports booting from no-battery or dead-battery conditions by receiving power from VBUS.

Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source provides a voltage on

VBUS. TPS65987D hardware is configured to present this Rd during a dead-battery or no-battery condition.

Additional circuitry provides a mechanism to turn off this Rd once the device no longer requires power from

VBUS. 图 8-16 shows the configuration of the C_CCn pins, and elaborates on the basic cable plug and

orientation detection block shown in 图 8-14. A resistance R_RPD is connected to the gate of the pull-down FET

on each C_CCn pin. During normal operation when configured as a sink, RD is RD_CC; however, while dead-

battery or no-battery conditions exist, the resistance is un-trimmed and is RD_DB. When RD_DB is presented

during dead-battery or no-battery, application code switches to RD_CC.

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C_CCn

R_RPD

RD_DB

RD_DB_EN

RD_CC

RD_CC_EN

图8-16. Dead Battery Pull-Down Resistor

In this case, the gate driver for the pull-down FET is Hi-Z at its output. When an external connection pulls up on

C_CCn (the case when connected to a DFP advertising with a pull-up resistance Rp or pull-up current), the

connection through R_RPD pulls up on the FET gate turning on the pull-down through RD_DB. In this condition,

the C_CCn pin acts as a clamp VTH_DB in series with the resistance RD_DB.

8.3.5.2 BUSPOWER (ADCIN1)

The BUSPOWERz input to the internal ADC controls the behavior of the TPS65987D in response to VBUS being

supplied during a dead battery condition. The pin must be externally tied to the LDO_3V3 output via a resistive

divider. At power-up the ADC converts the BUSPOWER voltage and the digital core uses this value to determine

start-up behavior. It is recommended to tie ADCin1 to LDO_3V3 through a resistor divider as shown in 图 8-17.

For more information about how to use the ADCIN1 pin to configure the TPS65987D, please see 节8.4.1.

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LDO_3V3

ADCIN1

R1

R2

ADC

图8-17. ADCIN1 Resistor Divider

备注

Devices implementing the BP_WaitFor3V3_External configuration must use GPIO16 for external sink

path control.

8.3.6 Battery Charger Detection and Advertisement

The battery charger (BC1.2) block integrates circuitry to detect when the connected entity on the USB D+/D–

pins is a BC1.2 compliant charger, as well as advertise BC1.2 charging capabilities to connected devices. To

enable the required detection and advertisement mechanisms, the block integrates various voltage sources,

currents, and resistances. 图 8-18 shows the connection of these elements to the TPS65987D C_USB_P and

C_USB_N pins.

VLGC_HI

IDP_SRC

RDCP_DAT

C_USB_P

To ADC

C_USB_N

R_DIV

R_1.2V

V_1.2V

IDX_SNK

VDX_SRC

RDM_DWN

RDP_DWN

V_DIV

图8-18. Battery Charger Detection and Advertisement

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备注

The pull-up and pull-down resistors required by the USB2 standard for a USB host or device are not

provided by the TPS65987D and must be provided externally to the device in final applications.

8.3.6.1 BC1.2 Data Contact Detect

Data Contact Detect follows the definition in the USB BC1.2 specification. The detection scheme sources a

current IDP_SRC into the D+ pin of the USB connection. The current is sourced into the C_USB_P D+ pin. A

resistance RDM_DWN is connected between the D– pin and GND. The current source IDP_SRC and the pull-

down resistance RDM_DWN, is activated during data contact detection.

8.3.6.2 BC1.2 Primary and Secondary Detection

The Primary and Secondary Detection follow the USB BC1.2 specification. This detection scheme looks for a

resistance between D+ and D– lines by forcing a known voltage on the first line, forcing a current sink on the

second line and then reading the voltage on the second line using the ADC integrated in the TPS65987D. The

voltage source VDX_SRC and the current source IDX_SNK, are activated during primary and secondary

detection.

8.3.6.3 Charging Downstream Port Advertisement

The Charging Downstream Port (CDP) advertisement follows the USB BC1.2 specification. The advertisement

scheme monitors the D+ line using the ADC. When a voltage of 0.6V is seen on the D+ line, TPS65987D forces

a voltage of 0.6 V on the D– line until the D+ goes low. The voltage source VDX_SRC and the current source

IDX_SNK, are activated during CDP advertisement. CDP advertisement takes place with the USB Host 15kΩ

pull-down resistors on the D+ and D- lines from the USB Host Transceiver, because after CDP negotiation takes

place on the D+/D- lines, USB2.0 data transmission begins.

8.3.6.4 Dedicated Charging Port Advertisement

The Dedicated Charging Port (DCP) advertisement follows the USB BC1.2 specification (Shorted Mode per

BC1.2) and the YD/T 1591-2009 specification. The advertisement scheme shorts the D+ and D– lines through

the RDCP_DAT resistor.

8.3.6.5 2.7V Divider3 Mode Advertisement

2.7 V Divider3 Mode is a proprietary advertisement scheme used to charge popular devices in the market. This

advertisement places V_DIV on D+ with an R_DIV output impedance and V_DIV on D- with an R_DIV output

impedance. With this advertisement scheme present on D+ and D-, specific popular devices are allowed to pull

more than 1.5 A of current from VBUS. If enabling 2.7 V Divider3 Mode advertisement on a port, it is

recommended that VBUS be able to supply at least 2.4 A of current.

8.3.6.6 1.2V Mode Advertisement

1.2 V Mode is a proprietary advertisement scheme used to charge popular devices in the market. This

advertisement places V_1.2 V on D- with an R_1.2 V output impedance and shorts D+ and D- together through

the RDCP_DAT resistor. With this advertisement scheme present on D+ and D-, specific popular devices are

allowed to pull more than 1.5 A of current from VBUS. If enabling 1.2 V Mode advertisement on a port, it is

recommended that VBUS be able to supply at least 2 A of current.

8.3.6.7 DCP Auto Mode Advertisement

DCP Auto Mode Advertisement scheme is a special scheme that automatically advertises the correct charging

scheme depending on the device attached to the USB port. If a device that detects Dedicated Charging Port

Advertisement is connected, the DCP Advertising scheme will automatically be placed on D+/D-. If a device that

detects 2.7 V Divider3 Mode Advertisement is connected, the 2.7 V Divider3 Mode Advertising scheme will

automatically be placed on D+/D-. Likewise, if a device that detects 1.2 V Mode Advertisement is connected, the

1.2 V Mode Advertising scheme will automatically be placed on D+/D-. TPS65987D's DCP Auto Mode

Advertisement circuit is able to place the correct advertisement scheme on D+/D- without needing to discharge

VBUS.

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8.3.7 ADC

The TPS65987D integrated ADC is accessible to internal firmware only. The ADC reads are not available for

external use.

8.3.8 DisplayPort HPD

To enable HPD signaling through PD messaging, a single pin is used as the HPD input and output for each port.

When events occur on these pins during a DisplayPort connection though the Type-C connector (configured by

firmware), hardware timers trigger and interrupt the digital core to indicate needed PD messaging. When one of

the TPS65987D's ports is operating as a DP source, its corresponding HPD pin operates as an output (HPD

TX), and when a port is operating as a DP sink, its corresponding HPD pin operates as an input (HPD RX).

When DisplayPort is not enabled via firmware the HPD pin operates as a generic GPIO (GPIO3).

8.3.9 Digital Interfaces

The TPS65987D contains several different digital interfaces which may be used for communicating with other

devices. The available interfaces include three I²C ports (I²C1 is a Master/Slave, I²C2 is a Slave, and I²C3 is a

Master), one SPI controller, and 12 additional GPIOs.

8.3.9.1 General GPIO

图8-19 shows the GPIO I/O buffer for all GPIOn pins. GPIOn pins can be mapped to USB Type-C, USB PD, and

application-specific events to control other ICs, interrupt a host processor, or receive input from another IC. This

buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When configured as an

input, the signal can be a de-glitched digital input . The push-pull output is a simple CMOS output with

independent pull-down control allowing open-drain connections. The weak push-pull is also a CMOS output, but

with GPIO_RPU resistance in series with the drain. The supply voltage to the output buffer is LDO_3V3 and

LDO_1V8 to the input buffer. When interfacing with non 3.3-V I/O devices the output buffer may be configured as

an open drain output and an external pull-up resistor attached to the GPIO pin. The pull-up and pull-down output

drivers are independently controlled from the input and are enabled or disabled via application code in the digital

core.

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LDO_3V3

GPIO_OD_EN

GPIO_OE

GPIO_DO

GPIO_PU_EN

GPIO_RPU

GPIO_RPD

GPIO_PD_EN

20ns

Deglitch

GPIO

GPIO_DI

GPIO_AI_EN

图8-19. General GPIO Buffer

8.3.9.2 I2C

The TPS65987D features three I²C interfaces. The I²C1 interface is configurable to operate as a master or

slave. The I²C2 interface may only operate as a slave. The I²C3 interface may only operate as a master. The I²C

I/O driver is shown in 图 8-20. This I/O consists of an open-drain output and in input comparator with de-

glitching. The I²C input thresholds are set by LDO_1V8 by default.

50ns

I2C_DI

Deglitch

I2C_SDA/SCL

I2C_DO

图8-20. I²C Buffer

8.3.9.3 SPI

The TPS65987D has a single SPI controller interface for use with external memory devices. 图 8-21 shows the

I/O buffers for the SPI interface.

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SPI_x

SPIin

CMOS

Output

SPIout

SPI_OE

图8-21. SPI buffer

8.3.10 PWM Driver

The TPS65987D includes two integrated PWM drivers which may be multiplexed onto GPIO 14 and GPIO 15.

The PWM driver implements an 8-bit counter driven by either the internal 100-kHz clock or internal 24-MHz

clock. The counter increments by a configurable 4-bit value each clock cycle which determines the output PWM

frequency. The PWM duty cycle is set by a configurable 8-bit value which sets the count threshold for the high to

low edge.

备注

During Sleep power state the 24-MHz clock is unavailable, any PWM drivers running from this clock is

also be disabled when entering the sleep state. If PWM output is needed in Sleep, the output must be

configured to use the 100-kHz clock.

8.3.11 Digital Core

图8-22 shows a simplified block diagram of the digital core.

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HRESET

GPIO 0-4

GPIO 12-17

GPIO 20-21

I2C1_SDA

I2C1_SCL

I2C1_IRQZ

I2C2_SDA

I2C2_SCL

I2C2_IRQZ

I2C3_SDA

I2C3_SCL

I2C3_IRQZ

SPI_CLK

I2C

Port 1

I2C to

System Control

I2C

Port 2

I2C to

Thunderbolt Controller

Digital Core

CBL_DET

Bias CTL

and USB-PD

USB PD Phy

I2C

Port 3

I2C to

I2C Peripherals

SPI_PICO

SPI_POCI

SPI_CSZ

SPI to

Flash

(firmware)

SPI

OSC

Temp

Sense

Thermal

Shutdown

图8-22. Digital Core Block Diagram

8.3.12 I²C Interfaces

The TPS65987D has three I²C interface ports. I²C Port 1 is comprised of the I2C1_SDA, I2C1_SCL, and

I2C1_IRQ1 pins. I²C Port 2 is comprised of the I2C2_SDA, I2C2_SCL, and I2C2_IRQ pins. These interfaces

provide general status information about the TPS65987D, as well as the ability to control the TPS65987D

behavior, as well as providing information about connections detected at the USB-C receptacle and supporting

communications to/from a connected device and/or cable supporting BMC USB-PD. I²C Port 3 is comprised of

the I2C3_SDA, I2C3_SCL, and I2C3_IRQ1 pins. This interface is used as a general I²C master to control

external I²C devices such as a super-speed mux or re-timer.

The first port can be a master or a slave, but the default behavior is to be a slave. The second port operates as a

slave only. Port 1 and Port 2 are interchangeable as slaves. Both Port1 and Port2 operate in the same way and

has the same access in and out of the core. An interrupt mask is set for each that determines what events are

interrupted on that given port. Port 3 operates as a master only.

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8.3.12.1 I²C Interface Description

The TPS65987D support Standard and Fast mode I²C interface. The bidirectional I²C bus consists of the serial

clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor.

Data transfer may be initiated only when the bus is not busy.

A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high

initiates I²C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)

first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/

output during the high of the ACK-related clock pulse. On the I²C bus, only one data bit is transferred during

each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as

changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a

Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a

slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must

generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to

ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this

event, the transmitter must release the data line to enable the master to generate a Stop condition.

图 8-23 shows the start and stop conditions of the transfer. 图 8-24 shows the SDA and SCL signals for

transferring a bit. 图8-25 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

SDA

SCL

S

P

Start Condition

Stop Condition

图8-23. I²C Definition of Start and Stop Conditions

SDA

SCL

Data Line

Change

图8-24. I²C Bit Transfer

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Data Output

by Transmitter

Nack

Data Output

by Receiver

SCL From

Master

Ack

1

2

8

9

S

Clock Pulse for

Acknowledgement

Start

Condition

图8-25. I²C Acknowledgment

8.3.12.2 I²C Clock Stretching

The TPS65987D features clock stretching for the I²C protocol. The TPS65987D slave I²C port may hold the

clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data.

The master communicating with the slave must not finish the transmission of the current bit and must wait until

the clock line actually goes high. When the slave is clock stretching, the clock line remains low.

The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for

standard 100 kbps I²C) before pulling the clock low again.

Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.

8.3.12.3 I²C Address Setting

The boot flow sets the hardware configurable unique I²C address of the TPS65987D before the port is enabled

to respond to I²C transactions. For the I2C1 interface, the unique I²C address is determined by the analog level

set by the analog ADCIN2 pin (three bits) as shown in 表8-2 .

表8-2. I²C Default Unique Address I2C1

DEFAULT I²C UNIQUE ADDRESS

Bit 7

0

Bit 6

1

Bit 5

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

0

I2C_ADDR_DECODE[2:0]

Note 1: Any bit is maskable for each port independently providing firmware override of the I²C address.

For the I2C2 interface, the unique I²C address is a fixed value as shown in 表8-3 .

表8-3. I²C Default Unique Address I2C2

DEFAULT I²C UNIQUE ADDRESS

Bit 7

0

Bit 6

1

Bit 5

1

Bit 4

Bit 3

Bit 2

0

Bit 1

0

Bit 0

R/W

1

0

Note 1: Any bit is maskable for each port independently, providing firmware override of the I²C address.

备注

The TPS65987D I2C address values are set and controlled by device firmware. Certain firmware

configurations may override the presented address settings.

8.3.12.4 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I²C master and a single TPS65987D.

The I²C Slave sub-address is used to receive or respond to Host Interface protocol commands. 图 8-26 and 图

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8-27 show the write and read protocol for the I²C slave interface, and a key is included in 图 8-28 to explain the

terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part.

1

7

1

8

1

8

1

8

1

S

Unique Address

Wr

A

Register Number

A

Byte Count = N

A

Data Byte 1

A

8

1

8

1

Data Byte 2

A

Data Byte N

A

P

图8-26. I²C Unique Address Write Register Protocol

1

S

7

1

8

1

7

1

8

1

Unique Address

Wr

A

Register Number

A

Sr

Unique Address

Rd

A

Byte Count = N

A

8

1

8

1

8

1

Data Byte 1

A

Data Byte 2

A

Data Byte N

A

1

P

图8-27. I²C Unique Address Read Register Protocol

1

7

1

A

x

8

1

A

x

1

S

Slave Address

Wr

Data Byte

P

S

Start Condition

SR

Rd

Wr

x

Repeated Start Condition

Read (bit value of 1)

Write (bit value of 0)

Field is required to have the value x

Acknowledge (this bit position may be 0 for an ACK or

1 for a NACK)

A

P

Stop Condition

Master-to-Slave

Slave-to-Master

Continuation of protocol

图8-28. I²C Read/Write Protocol Key

8.3.12.5 I²C Pin Address Setting (ADCIN2)

To enable the setting of multiple I²C addresses using a single TPS65987D pin, a resistor divider is placed

externally on the ADCIN2 pin. The internal ADC then decodes the address from this divider value. 图8-29 shows

the decoding.

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LDO_3V3

ADCIN2

R1

R2

ADC

图8-29. I²C Address Divider

表8-4 lists the external divider needed to set bits [3:1] of the I²C Unique Address.

表8-4. I²C Address Selection

DIV = R2/(R1+R2)⁽¹⁾

I²C UNIQUE ADDRESS [3:1]

DIV_min

0.00

DIV_max

0.18

I2C_ADDR_DECODE

000b

001b

010b

011b

0.20

0.38

0.40

0.58

0.60

1.00

(1) External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed

MIN and MAX values.

8.3.13 SPI Controller Interface

The TPS65987D loads any ROM patch and-or configuration from flash memory during the boot sequence. The

TPS65987D is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery

conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash

memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 64 kB. The SPI

controller of the TPS65987D supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on

the same cycle as chip select (SPI_CS pin) becomes active. The chip select polarity is active-low. The clock

phase is defined such that data (on the SPI_POCI and SPI_PICO pins) is shifted out on the falling edge of the

clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is

defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum

erasable sector size of the flash must be 4 KB. The W25X05CL or similar is recommended.

8.3.14 Thermal Shutdown

The TPS65987D features a central thermal shutdown as well as independent thermal sensors for each internal

power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions

except for supervisory circuitry when die temperature goes above a rising temperature of TSD_MAIN. The

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temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value,

the device resumes normal operation.

The power path thermal shutdown monitors the temperature of each internal power path and disables the power

path in response to an over temperature event. Once the temperature falls below TSDH_PWR the path can be

configured to resume operation or remain disabled until re-enabled by firmware.

8.3.15 Oscillators

The TPS65987D has two independent oscillators for generating internal clock domains. A 24-MHz oscillator

generates clocks for the core during normal operation. A 100-kHz oscillator generates clocks for various timers

and clocking the core during low power states.

8.4 Device Functional Modes

8.4.1 Boot

At initial power on the device goes through a boot routine. This routine is responsible for initializing device

register values and loading device patch and configuration bundles. The device's functional behavior after boot

can be configured through the use of pin straps on the SPI_POCI and ADCIN1 pins as shown in 表8-5.

表8-5. Boot Mode Pin Strapping

ADCIN1

SPI_POCI

DIV = R2/(R1+R2)⁽¹⁾

Dead Battery Mode

Device Configuration

DIV MIN

0.00

DIV MAX

0.18

0.28

0.38

0.48

0.58

1.00

0.18

0.28

0.38

0.48

0.58

0.68

0.78

0.88

1.00

1

0

BP_NoResponse

BP_WaitFor3V3_Internal

BP_ECWait_Internal

BP_WaitFor3V3_External

BP_ECWait_External

BP_NoWait

Safe Configuration

Infinite Wait

0.20

0.30

0.40

0.50

0.60

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

Safe Configuration

Infinite Wait

Safe Configuration

Configuration 1

Configuration 2

Infinite Wait

BP_NoResponse

BP_NoWait

BP_ECWait_Internal

BP_NoWait

Configuration 3

Infinite Wait

BP_ECWait_External

BP_NoWait

Configuration 4

Reserved

BP_NoWait

BP_NoResponse

BP_NoWait

Reserved

Configuration 5

(1) External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed

MIN and MAX values.

The pin strapping configures two different parameters, Dead battery mode and device configuration. The dead

battery mode selects device behavior when powered from VBUS. The dead battery mode behaviors are detailed

in 表8-6.

表8-6. Dead Battery Configurations

CONFIGURATION

DESCRIPTION

No power switch is enabled and the device does not start-up until VIN_3V3 is

present

BP_NoResponse

The internal power switch from VBUSx to PP_HVx is enabled for the port receiving

power. The device does not continue to start-up or attempt to load device

configurations until VIN_3V3 is present.

BP_WaitFor3V3_Internal

BP_WaitFor3V3_External

The external power switch from VBUSx to PP_HVx is enabled for the port receiving

power. The device does not continue to start-up or attempt to load device

configurations until VIN_3V3 is present.

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表8-6. Dead Battery Configurations (continued)

CONFIGURATION

DESCRIPTION

The internal power switch from VBUSx to PP_HVx is enabled for the port receiving

power. The device infinitely tries to load configuration.

BP_ECWait_Internal

The external power switch from VBUSx to PP_HVx is enabled for the port receiving

power. The device infinitely tries to load configuration.

BP_ECWait_External

BP_NoWait

The device continues to start-up and attempts to load configurations while

receiving power from VBUS. Once configuration is loaded the appropriate power

switch is closed based on the loaded configuration.

备注

Devices implementing the BP_WaitFor3V3_External or BP_ECWait_External configuration must use

GPIO16 for external sink path control, while devices implementing the BP_WaitFor3V3_Internal or

BP_ECWait_Internal must use PPHV1 as the sink path.

When powering up from VIN_3V3 or VBUS the device will attempt to load configuration information from the SPI

or I2C digital interfaces. The device configuration settings select the device behavior should configuration

information not be available during the device boot process. 表 8-7 shows the device behavior for each device

configuration setting.

表8-7. Device Default Configurations

Configuration

Safe

Description

Ports disabled, if powered from VBUS operates a legacy sink

Device infinitely waits in boot state for configuration information

Infinite Wait

DFP only (Internal Switch)

5 V at 3 A Source capability

TBT Alternate Modes not enabled

Configuration 1

Configuration 2

Configuration 3

DisplayPort Alternate Mode not enabled (DFP_D, C/D/E)

UFP only (Internal Switch)

5 V at 0.9 - 3.0 A Sink capability

TBT Alternate Modes not supported

DisplayPort Alternate Modes not supported

UFP only (Internal Switch)

5-20 V at 0.9 - 3.0 A Sink capability

TBT Alternate Modes not supported

DisplayPort Alternate Modes not supported

UFP only (External Switch)

5 V at 0.9-3.0 A Sink capability

Configuration 4

Configuration 5

5 V at 3.0 A Source capability

TBT Alternate Modes not supported

DisplayPort Alternate Modes not supported

UFP only (External Switch))

5-20 V at 0.9-3.0 A Sink capability

5 V at 3.0 A Source capability

TBT Alternate Modes not supported

DisplayPort Alternate Modes not supported

8.4.2 Power States

The TPS65987D may operate in one of three different power states: Active, Idle, or Sleep. The functionality

available in each state is summarized in 表8-8.

表8-8. Power States

ACTIVE

IDLE

SLEEP

Type-C State

Connected or Unconnected

Unconnected

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表8-8. Power States (continued)

ACTIVE

IDLE

SLEEP

Type-C Port 2 State

LDO_3V3⁽¹⁾

Connected or Unconnected

Unconnected

Valid

LDO_1V8

Valid

Oscillator Status

Digital Core Clock Frequency

100kHz Oscillator Status

24MHz Oscillator Status

12 MHz

Enabled

4 MHz - 6 MHz

Enabled

100 kHz

Enabled

Disabled

Enabled

Available Features

Type-C Detection

PD Communication

I2C Communication

SPI Communication

Yes

No

Yes

No

Yes

No

Wake Events

Wake on Attach/Detach

Wake on PD Communication

Wake on I2C Communication

N/A

Yes

Yes⁽²⁾

Yes

No

Yes

(1) LDO_3V3 may be generated from either VIN_3V3 or VBUS. If LDO_3V3 is generated from VBUS, TPS65987D port only operate as

sinks.

(2) Wake up from Idle to Active upon a PD message is supported however the first PD message received is lost.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TPS65987D firmware implements a host interface over I²C to allow for the configuration and control of all

device options. Initial device configuration is configured through a configuration bundle loaded onto the device

during boot. The bundle may be loaded via I²C or SPI. The TPS65987D configuration bundle and host interface

allow the to be customized for each specific application. The configuration bundle can be generated through the

Application Customization Tool and additional information on the device host interface can be found in the Host

Interface Reference Manual.

9.2 Typical Application

U2A

GND

C2

220pF

16

17

18

30

31

21

22

23

36

37

38

39

40

41

42

43

48

49

50

53

54

55

24

26

GPIO0

GPIO1

C1_CC1

C1_CC2

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

SPI_POCI

SPI_PICO

SPI_CLK

SPI_CS

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

C_USB_P

C_USB_N

GPIO_20

GPIO_21

C_CC1

C_CC2

GPIO2

HPD (GPIO3)

GPIO4

C3

220pF

27

28

29

I2C1_SCL

I2C1_SDA

I2C1_IRQ

I2C1_SCL

I2C1_SDA

I2C1_IRQZ

I2C3_SCL (GPIO5)

I2C3_SDA (GPIO6)

I2C3_IRQ (GPIO7)

SPI_POCI (GPIO8)

SPI_PICO (GPIO9)

SPI_CLK (GPIO10)

SPI_CS (GPIO11)

GPIO12

45

47

GND

32

33

34

I2C2_SCL

I2C2_SDA

I2C2_IRQ

I2C2_SCL

I2C2_SDA

I2C2_IRQZ

GPIO13

GPIO14 (PWM)

GPIO15 (PWM)

GPIO16 (PEXT1)

GPIO17 (PEXT2)

C1_USB_P (GPIO18)

C_USB_N (GPIO19)

GPIO20

44

6

HRESET

ADCIN1

ADCIN2

HRESET

ADCIN1

ADCIN2

10

GPIO21

TPS65987DDHRSHR

C11

1µF

U2B

GND

C10

10µF

GND

35

14

13

LDO_1V8

LDO_3V3

LDO_1V8

VBUS1

VBUS

LDO_3V3

PA_PP_CABLE

9

LDO_3V3

3

4

VBUS2

GND

C12

10µF

25

PP1_CABLE

C13

22µF

46

11

12

GND

PP_HV1

PA_PP_HV

GND

8

15

DRAIN1

1

2

PP_HV2

19

58

DRAIN1

GND

DRAIN1

DRAIN2

5

C14

10µF

VIN_3V3

7

52

DRAIN2

56

57

C15

10µF

GND

20

51

GND

59

TPS65987DDHRSHR

GND

图9-1. Example Schematic

9.2.1 Type-C VBUS Design Considerations

USB Type-C and PD allows for voltages up to 20 V with currents up to 5 A. This introduces power levels that

could damage components touching or hanging off of VBUS. Under normal conditions, all high power PD

contracts should start at 5 V and then transition to a higher voltage. However, there some devices that are not

compliant to the USB Type-C and Power Delivery standards and could have 20 V on VBUS. This could cause a

20-V hot plug that can ring above 30 V. Adequate design considerations are recommended below for these non-

compliant devices.

9.2.1.1 Design Requirements

表 9-1 shows VBUS conditions that can be introduced to a USB Type-C and PD Sink. The system should be

able to handle these conditions to ensure that the system is protected from non-compliant and/or damaged USB

PD sources. A USB Sink should be able to protect from the following conditions being applied to its VBUS. The

节9.2.1.2 section explains how to protect from these conditions.

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表9-1. VBUS Conditions

CONDITION

VOLTAGE APPLIED

4 V–21.5 V

Abnormal VBUS Hot Plug

VBUS Transient Spikes

4 V–43 V

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Type-C Connector VBUS Capacitors

C_VBUS

VBUS A4

VBUS B9

10 nF

35V

10 nF

35V

Type-C

Connector

GND

C_VBUS

VBUS A9

VBUS B4

10 nF

35V

10 nF

35V

GND

图9-2. Type-C Connector VBUS Capacitors

The first level of protection starts at the Type-C connector and the VBUS pin capacitors. These capacitors help

filter out high frequency noise but can also help absorb short voltage transients. Each VBUS pin should have a

10-nF capacitor rated at or above 25 V and placed as close to the pin as possible. The GND pin on the

capacitors should have very short path to GND on the connector. The derating factor of ceramic capacitors

should be taken into account as they can lose more than 50% of their effective capacitance when biased. Adding

the VBUS capacitors can help reduce voltage spikes by 2 V to 3 V.

9.2.1.2.2 VBUS Schottky and TVS Diodes

Schottky diodes are used on VBUS to help absorb large GND currents when a Type-C cable is removed while

drawing high current. The inductance in the cable will continue to draw current on VBUS until the energy stored

is dissipated. Higher currents could cause the body diodes on IC devices connected to VBUS to conduct. When

the current is high enough it could damage the body diodes of IC devices. Ideally a VBUS Schottky diode should

have a lower forward voltage so it can turn on before any other body diodes on other IC devices. Schottky

diodes on VBUS also help during hard shorts to GND which can occur with a faulty Type-C cable or damaged

Type-C PD device. VBUS could ring below GND which could damage devices hanging off of VBUS. The

Schottky diode will start to conduct once VBUS goes below the forward voltage. When the TPS65987D is the

only device connected to VBUS place the Schottky Diode close to the VBUS pin of the TPS65987D. The two

figures below show a short condition with and without a Schottky diode on VBUS. In 图 9-4 without the Schottky

diode, VBUS rings 2 V below GND and oscillates after settling to 0 V. In 图 9-5 with the Schottky diode, VBUS

drops 750 mV below GND (Schottky diode Vf) and the oscillations are minimized.

TVS Diodes help suppress and clamp transient voltages. Most TVS diodes can fully clamp around 10 ns and can

keep the VBUS at their clamping voltage for a period of time. Looking at the clamping voltage of TVS diodes

after they settle during a transient will help decide which TVS diode to use. The peak power rating of a TVS

diode must be able to handle the worst case conditions in the system. A TVS diode can also act as a “pseudo

schottky diode”as they will also start to conduct when VBUS goes below GND.

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9.2.1.2.3 VBUS Snubber Circuit

VBUS

4.7 …F

3.48Ω

1 …F

GND

图9-3. VBUS Snubber

Another method of clamping the USB Type-C VBUS is to use a VBUS RC Snubber. An RC Snubber is a great

solution because in general it is much smaller than a TVS diode, and typically more cost effective as well. An RC

Snubber works by modifying the characteristic of the total RLC response in the USB Type-C cable hot-plug from

being under-damped to critically-damped or over-damped. So rather than clamping the over-voltage directly, it

actually changes the hot-plug response from under-damped to critically-damped, so the voltage on VBUS does

not ring at all; so the voltage is limited, but without requiring a clamping element like a TVS diode.

However, the USB Type-C and Power Delivery specifications limit the range of capacitance that can be used on

VBUS for the RC snubber. VBUS capacitance must have a minimum 1 µF and a maximum of 10 µF. The RC

snubber values chosen support up to 4 m USB Type-C cable (maximum length allowed in the USB Type-C

specification) being hot plugged, is to use 4.7-μF capacitor in series with a 3.48-Ω resistor. In parallel with the

RC Snubber a 1μF capacitor is used, which always ensures the minimum USB Type-C VBUS capacitance

specification is met. This circuit can be seen in 图9-3.

9.2.1.3 Application Curves

图9-4. VBUS Short without Schottky Diode

图9-5. VBUS Short with Schottky Diode

9.2.2 Notebook Design Supporting PD Charging

The TPS65987D works very well in single port Notebooks that support PD charging. The two internal power

paths for the TPS65987D source System 5 V on VBUS through the PPHV2 path and sink VBUS up to 20 V on

PPHV1. The TPS65987D integrated reverse current protection allows the designer to connect PPHV1 to another

power source such as a standard barrel jack or proprietary dock connector power to charge the notebook

battery. The System 5-V supplies power to PP_CABLE on the TPS65987D to supply VCONN to Type-C e-

marked cables and Type-C accessories. An embedded controller EC is used for additional control of the

TPS65987D and to relay information back to the operating system. An embedded controller enables features

such as entering and exiting sleep modes, changing source and sink capabilities depending on the state of the

battery, UCSI support, control alternate modes, etc. Refer to the Host Interface and Firmware users guide for

additional information.

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9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging

For systems that support USB and DisplayPort Data, the USB and DisplayPort sources are muxed to the Type-C

connector through the TUSB1046 Super Speed mux. The TPS65987D is capable of controlling the Super Speed

Mux over I²C and will configure it according to the connection at the Type-C connector. The TPS65987D can

also set the configurations for the Super Speed mux equalizer settings for the USB Super Speed and

DisplayPort Lanes through an initializing set of I²C writes. Note that I2C1 is the I²C master controlling the SS

Mux and I2C2 is connected to the embedded controller. I2C1 can operate as an I²C master/slave and I2C2 can

only operate as an I²C slave. Alternatively the Super Speed mux can be controlled through GPIO instead of I²C.

The TPD6S300 provides Type-C protection features such as short to VBUS on the CC and SBU pins and ESD

protection for the USB2 DN/P. See the figure below for the system block diagram.

USB SSTX/RX

I2C/GPIO

USB3.1 Source

SS Mux Control*

DP1.4 Source

SSTX/RX

SBU1/2

TUSB1046

Type C

Receptacle

DP ML

USB2.0 Source

SSTX/RX

SBU1/2

USB2.0

GPIO

SS Mux Control*

BC1.2

TPD6S300

CC1/2

VBUS

C_CC1/2

VIN

BAT

PPHV1

+

BQ Battery

Charger

VIN_3V3

System 3.3V

TPS65987D

I2C

PPHV2

System 5V

PP_CABLE

I2C1 Master

I2C2

SS Mux Control*

EC

I2C MASTER

图9-6. USB and DisplayPort Notebook Supporting PD Charging

9.2.2.1.1 Design Requirements

表9-2 summarizes the Power Design parameters for an USB Type-C PD Notebook.

表9-2. Power Design Parameters

POWER DESIGN PARAMETERS

PPHV2 Input Voltage, Current

PP_CABLE1/2 Input Voltage, Current

PPHV1 Voltage, Current

VALUE

CURRENT PATH

VBUS Source

5 V, 1.5 A

5 V, 500 mA

VCONN Source

VBUS Sink

5 V–20 V, 3 A (5-A Max)

3.3 V, 50 mA

VIN_3V3 Voltage, Current

Internal TPS65987D Circuitry

9.2.2.1.2 Detailed Design Procedure

9.2.2.1.2.1 USB Power Delivery Source Capabilities

Most Type-C dongles (video and data) draw less than 900 mA and supplying 1.5 A on each Type-C port is

sufficient for a notebook supporting USB and DisplayPort. 表9-3 shows the PDO for the Type-C port.

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表9-3. Source PDOs

SOURCE PDO

PDO1

PDO TYPE

VOLTAGE

CURRENT

Fixed

5 V

1.5 A

9.2.2.1.2.2 USB Power Delivery Sink Capabilities

Most notebooks support buck/boost charging which allows them to charge the battery from 5 V to 20 V. USB PD

sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is

recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with

most PD chargers/adapters.

表9-4. Sink PDOs

SINK PDO

PDO1

PDO TYPE

Fixed

VOLTAGE

CURRENT

5 V

3 A

PDO2

Fixed

9 V

PDO3

Fixed

15 V

3 A

PDO4

Fixed

20 V

3 A (5-A Max)

9.2.2.1.2.3 USB and DisplayPort Supported Data Modes

表9-5 summarizes the data capabilities of the notebook supporting USB3 and DisplayPort.

表9-5. Data Capabilities

PROTOCOL

DATA

USB3.1 Gen2

DP1.4

DATA ROLE

USB Data

Host

DisplayPort

Host DFP_D (Pin Assignment C, D, and E)

9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control

The TUSB1046 requires GPIO control in GPIO control mode to determine whether if there is USB or DisplayPort

data connection. 表 9-6 summarizes the TPS65987D GPIO Events and the control pins for the TUSB1046. Note

that the pin strapping on the TUSB1046 will set the GPIO control mode and the required equalizer settings. For

more details refer to the TUSB1046 datasheet.

表9-6. GPIO Events for Super Speed Mux

TPS65987D GPIO EVENT

Port 0 Cable Orientation Event

Port 0 USB3 Event

TUSB1046 CONTROL

FLIP

CTL0

CTL1

Port 0 DP Mode Selection Event

9.2.2.2 Thunderbolt Notebook Supporting PD Charging

A Thunderbolt system is capable of source USB, DisplayPort, and Thunderbolt data. There is an I²C connection

between the TPS65987D and the Thunderbolt controller. The TPS65987D will determine the connection on the

Type-C and will generate an interrupt to the Thunderbolt controller to generate the appropriate data output. An

external mux for SBU may be needed to mux the LSTX/RX and AUX_P/N signal from the Thunderbolt controller

to the Type-C Connector. The TPD6S300 provides additional protection such as short to VBUS on the CC and

SBU pins and ESD for the USB2 DN/P. See 图9-7 for a block diagram of the system.

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PB_TX0/1/RX0/1

SBU Mux Control

PA_LSTX/RX

LSTX/RX

AUXP/N

SBU1/2

TS3DS10224

PA_DPSRC_AUX_P/N

Type C

Receptacle

U1_TBT_I2C_SDA

U2_TBT_I2C_SCL

J4_TBTA_I2C_IRQZ

USB2.0 Source

Thunderbolt

Controller I2C Master

SSTX/RX

SBU1/2

GPIO

SBU Mux Control

TBT RESETN

USB2.0

BC1.2

TPD6S300

TBT RESETN

RESETN

GPIO_0

CC1/2

VBUS

C1_CC1/2

VIN

PPHV1

BAT

Thunderbolt Controller

BQ Battery

Charger

+

VIN_3V3

System 3.3V

System 5V

TPS65987D

PP_CABLE

I2C

PPHV2

Thunderbolt

Controller I2C Master

I2C2

I2C1

EC

I2C MASTER

图9-7. Thunderbolt Notebook Supporting PD Charging

9.2.2.2.1 Design Requirements

表9-7 summarizes the Power Design parameters for an USB Type-C PD Thunderbolt Notebook.

表9-7. Power Design Parameters

POWER DESIGN PARAMETERS

PPHV2 Input Voltage, Current

PP_CABLE1/2 Input Voltage, Current

PPHV1 Voltage, Current

VALUE

CURRENT PATH

5 V, 3 A

VBUS Source

5 V, 500 mA

VCONN Source

VBUS Sink

5 V–20 V, 3 A (5-A Max)

3.3 V, 50 mA

VIN_3V3 Voltage, Current

Internal TPS65987D Circuitry

9.2.2.2.2 Detailed Design Procedure

9.2.2.2.2.1 USB Power Delivery Source Capabilities

All Thunderbolt systems must support sourcing 5 V at 3 A (15 W). See the 表9-8 for the PDO information.

表9-8. Source PDOs

SOURCE PDO

PDO TYPE

VOLTAGE

CURRENT

PDO1

Fixed

5 V

3 A

9.2.2.2.2.2 USB Power Delivery Sink Capabilities

Most notebooks support buck/boost charging which allows them to charge the battery from 5 V to 20 V. USB PD

sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is

recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with

most PD chargers and adapters.

表9-9. Sink PDOs

SINK PDO

PDO TYPE

VOLTAGE

CURRENT

PDO1

Fixed

5 V

3 A

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表9-9. Sink PDOs (continued)

SINK PDO

PDO TYPE

VOLTAGE

CURRENT

3 A

PDO2

PDO3

PDO4

Fixed

9 V

15 V

3 A

20 V

3 A (5-A Max)

9.2.2.2.2.3 Thunderbolt Supported Data Modes

Thunderbolt Controllers are capable of generating USB3, DisplayPort and Thunderbolt Data. The Thunderbolt

controller is also capable of muxing the appropriate super speed signal to the Type-C connector. Thunderbolt

systems do not need a super speed mux for the Type-C connector. 表 9-10 summarizes the data capabilities of

each Type-C port supporting Thunderbolt.

表9-10. Data Capabilities

PROTOCOL

USB Data

DATA

USB3.1 Gen2

DP1.4

DATA ROLE

Host

DisplayPort

Thunderbolt

Host DFP_D (Pin Assignment C, D, and E)

Host/Device

PCIe/DP

9.2.2.2.2.4 RESETN

VCC3P3_SX

RESETN

GPIO_0

GND

图9-8. RESETN Circuit

The TPS65987D and the Thunderbolt controller share the same flash and they must be able to access it at

different times. The TPS65987D will access the flash first to load its configuration and then the Thunderbolt

controller will read the flash for its firmware. The TPS65987D will hold the Thunderbolt controller in reset until it

has read its configuration from the flash. GPIO_0 is reserved to act as the reset signal for the Thunderbolt

controller. The RESET_N (Thunderbolt Controller Master Reset) signal must also be gated by the 3.3-V supply

to the Thunderbolt controller (VCC3P3_SX). When the RESET_N signal is de-asserted before the supply has

come up it may put the Thunderbolt controller in a latched state. The RESET_N signal must be de-asserted at

least 100 µs after the Thunderbolt Controller supply has come up. For dead battery operation the GPIO_0 signal

should be “ANDed” with the 3.3-V supply to avoid de-asserting the RESETN when the Thunderbolt controller

is not powered. The figure below shows the RESET_N control with GPIO_0 and the 3.3-V supply. Alternatively,

the EC could configure GPIO_0 to de-assert RESETN when the system has successfully booted.

9.2.2.2.2.5 I2C Design Requirements

The I²C connection from the TPS65987D and the Thunderbolt control allows the Thunderbolt controller to read

the current data status from the TPS65987D when there is a connection on the Type-C port. The Thunderbolt

controller has an interrupt assigned for TPS65987D and the Thunderbolt controller will read the I²C address

corresponding to the Type-C port. The I2C2 on the TPS65987D is always connected to the Thunderbolt

controller and the I²C channel will respond to the 0x38 address.

9.2.2.2.2.6 TS3DS10224 SBU Mux for AUX and LSTX/RX

The SBU signals must be muxed from the Type-C connector to the Thunderbolt controller. The AUX for

DisplayPort and LSTX/RX for Thunderbolt are connected to the TS3DS10224 and then muxed to the SBU pins.

The SBU mux is controlled through GPIOs from the TPS65987D. 表 9-11 shows the TPS65987D GPIO events

and the control signals from the TS3DS10224.

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表9-11. GPIO Events for SBU Mux

TPS65987D GPIO EVENT

TS3DS10224 CONTROL

Port 0 Cable Orientation Event

SAO, SBO

Port 0 DP Mode Selection Event

ENA

Port 0 TBT Event

ENB

N/A

SAI tied to VCC

SBI tied to GND

表9-12 shows the connections for the AUX, LSTXRX, and SBU pins for the TS3DS10224.

表9-12. TS3DS10224 Pin Connections

TS3DS10224 PIN

SIGNAL

INA+

SBU1

INA-

SBU2

OUTB0+

OUTB0-

OUTB1+

OUTB1-

OUTA0+

OUTA0-

OUTA1+

OUTA1-

LSTX

LSRX

LSTX

AUX_P

AUX_N

AUX_P

9.2.2.2.2.7 Thunderbolt Flash Options

In most Thunderbolt systems the TPS65987D will share the flash with the Thunderbolt controller. The flash

contains the Thunderbolt Controller firmware and the configuration data for the TPS65987D. 表 9-13 shows the

supported SPI flash options for Thunderbolt systems.

表9-13. Flash Supported for Thunderbolt Systems

MANUFACTURER

Winbond

Spansion

AMIC

PART NUMBER

W25Q80JVNIQ

S25FL208K

SIZE

8 Mb

A25L080

Macronix

Micron

MX25L8006EM1I

M25PE80-VMN6TP

M25PX80-VMN6TP

Micron

9.2.2.3 USB and DisplayPort Dock with Bus-Powered and Self-Powered Support

A flexible dock application that can work either on Bus-Power or Self-Power takes advantage of the two

integrated power paths. PPHV1 will sink power into the system when operating off Bus-Power and PPHV2 will

source power on VBUS when powered. When the dock can operate in both modes it allows the end-user to use

the dock in and out of an office.

The regulators that generate the required system voltages are powered from PPHV1 or the external dock supply.

These rails powered from a main 3.3-V rail to ensure that the all the voltages required are valid in Bus-Powered

and Self-Powered operation. This will also help for systems that support USB PD3.0 Fast Role Swap. There is a

variable regulator to provide 5 V, 9 V, 15 V, and 20 V per the Power Delivery Rules.

The Super Speed signals from the Type-C connector are muxed to USB and MST Hubs through the TUSB1064.

The DisplayPort and USB signals from the Super Speed Mux will go to a MST and USB HUB to enable

additional video and USB connectors. The TPS65987D can control the TUSB1064 Super Speed mux through

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I²C or GPIO. The TPD6S300 provides additional protection such as short to VBUS on the CC and SBU pins and

ESD for the USB2 DN/P. See 图9-9 for the system block diagram.

DP ML

MST Hub

SSTX/RX

SBU1/2

I2C/GPIO

SS Mux Control*

TUSB1064

Type C

Receptacle

USB SSTX/RX

TUSB8044

USB Hub

SSTX/RX

SBU1/2

USB2.0

GPIO

SS Mux Control*

BC1.2

TPD6S300

I2C1 Master

CC1/2

VBUS

C_CC1/2

PPHV1

TPS54334

3.3V

PP_CABLE

VIN_3V3

System 5V

System 3.3V

TPS65987D

TPS62097A

1.2V

TPS2500

5V

LM3489

5V/9V/15V/20V

PPHV2

I2C2

EC

I2C MASTER

图9-9. USB and DisplayPort Dock Block Diagram

9.2.2.3.1 Design Requirements

表9-14 summarizes the Power Design parameters for a USB Type-C PD docking system.

表9-14. Power Design Parameters

POWER DESIGN PARAMETERS

PPHV2 Input Voltage, Current

PP_CABLE1/2 Input Voltage, Current

PPHV1 Voltage, Current

VALUE

5 V/9 V/15 V/20 V, 3 A

5 V, 500 mA

CURRENT PATH

VBUS Source

VCONN Source

5 V, 1.5 A

VBUS Sink

VIN_3V3 Voltage, Current

3.3 V, 50 mA

Internal TPS65987D Circuitry

9.2.2.3.2 Detailed Design Procedure

9.2.2.3.2.1 USB Power Delivery Source Capabilities

When operating in Self-Powered mode the dock is recommended to support 60-W Power Delivery Rules to

charge most systems. 表9-15 shows the source PDO for the Type-C port.

表9-15. Source PDOs

SOURCE PDO

PDO1

PDO TYPE

VOLTAGE

CURRENT

3 A

Fixed

5 V

PDO2

Fixed

9 V

3 A

PDO3

Fixed

15 V

3 A

PDO4

Fixed

20 V

3 A

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9.2.2.3.2.2 USB Power Delivery Sink Capabilities

Most Type-C notebooks will support 1.5 A at 5 V on VBUS which should require the dock should be able to

operate at this current level. 表9-16 shows the sink PDO for the Type-C port.

表9-16. Sink PDOs

SINK PDO

PDO TYPE

VOLTAGE

CURRENT

PDO1

Fixed

5 V

1.5 A

9.2.2.3.2.3 USB and DisplayPort Supported Data Modes

表9-17 summarizes the data capabilities of the Type-C port supporting USB3 and DisplayPort.

表9-17. Data Capabilities

PROTOCOL

DATA

USB3.1 Gen2

DP1.4

DATA ROLE

USB Data

Device

DisplayPort

Host UFP_D (Pin Assignment C and D)

9.2.2.3.2.4 TUSB1064 Super Speed Mux GPIO Control

The TUSB1046 requires GPIO control in GPIO control mode to determine whether if there is USB or DisplayPort

data connection. 表 9-18 summarizes the TPS65987D GPIO Events and the control pins for the TUSB1064.

Note that the pin strapping on the TUSB1064 will set the GPIO control mode and the required equalizer settings.

For more details refer to the TUSB1064 datasheet.

表9-18. GPIO Events for Super Speed Mux

TPS65987D GPIO EVENT

Port 0 Cable Orientation Event

Port 0 USB3 Event

TUSB1064 CONTROL

FLIP

CTL0

CTL1

Port 0 DP Mode Selection Event

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10 Power Supply Recommendations

10.1 3.3-V Power

10.1.1 VIN_3V3 Input Switch

The VIN_3V3 input is the main supply to the TPS65987D device. The VIN_3V3 switch (see 图 8-9) is a

unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to

VIN_3V3. This switch is on when 3.3 V is available. See 表 10-1 for the recommended external capacitance on

the VIN_3V3 pin.

10.1.2 VBUS 3.3-V LDO

The 3.3-V LDO from VBUS steps down voltage from VBUS to LDO_3V3 which allows the TPS65987D device to

be powered from VBUS when VIN_3V3 is unavailable. This LDO steps down any recommended voltage on the

VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65987D device

operates without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin can

increase the temperature enough to trigger a thermal shutdown. The VBUS 3.3-V LDO blocks reverse current

from LDO_3V3 back to VBUS allowing VBUS to be unpowered when LDO_3V3 is driven from another source.

See 表10-1 for the recommended external capacitance on the VBUS and LDO_3V3 pins.

10.2 1.8-V Power

The internal circuitry is powered from 1.8 V. The 1.8-V LDO steps the voltage down from LDO_3V3 to 1.8 V. The

1.8-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, memory, and

other digital circuits. The 1.8-V LDO also provides power to all internal low-voltage analog circuits. See 表 10-1

for the recommended external capacitance on the LDO_1V8 pin.

10.3 Recommended Supply Load Capacitance

表 10-1 lists the recommended board capacitances for the various supplies. The typical capacitance is the

nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum

capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum

capacitance allowing for tolerances and voltage derating ensuring proper operation.

表10-1. Recommended Supply Load Capacitance

CAPACITANCE

VOLTAGE

MIN

PARAMETER

DESCRIPTION

TYP

MAX

RATING

(ABSOLUT

E)

(PLACED) (ABSOLUTE)

CVIN_3V3

CLDO_3V3

CLDO_1V8

CVBUS1

Capacitance on VIN_3V3

Capacitance on LDO_3V3

Capacitance on LDO_1V8

Capacitance on VBUS1

Capacitance on VBUS2

6.3 V

4 V

5 µF

10 μF

10 µF

4.7 µF

1 µF

25 µF

12 µF

2.2 µF

0.5 µF

2.5 µF

1 µF

25 V

10 V

25 V

CVBUS2

1 µF

CPP_HV_SRC

CPP_HV_SNK

Capacitance on PP_HV when configured as a 5V source

Capacitance on PP_HV when configured as a 20V sink

4.7 µF

47 µF

120 µF

Capacitance on PP_CABLE. When shorted to PP_HV congifured as a 5V

source, the CPP_HV_SRC capacitance may be shared.

CPP_CABLE

10 V

2.5 µF

4.7 µF

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11 Layout

11.1 Layout Guidelines

Proper routing and placement will maintain signal integrity for high speed signals and improve the heat

dissipation from the TPS65987D power paths. The combination of power and high speed data signals are easily

routed if the following guidelines are followed. It is a best practice to consult with board manufacturing to verify

manufacturing capabilities.

11.1.1 Top TPS65987D Placement and Bottom Component Placement and Layout

When the TPS65987D is placed on top and its components on bottom the solution size will be at its smallest.

11.2 Layout Example

Follow the differential impedances for Super and High Speed signals defined by their specifications (DisplayPort

- AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not all designs

will utilize all of the I/O on the TPS65987D.

U2A

GND

C2

220pF

16

17

18

30

31

21

22

23

36

37

38

39

40

41

42

43

48

49

50

53

54

55

24

26

GPIO0

GPIO1

C1_CC1

C1_CC2

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

SPI_POCI

SPI_PICO

SPI_CLK

SPI_CS

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

C_USB_P

C_USB_N

GPIO_20

GPIO_21

C_CC1

C_CC2

GPIO2

HPD (GPIO3)

GPIO4

C3

220pF

27

28

29

I2C1_SCL

I2C1_SDA

I2C1_IRQ

I2C1_SCL

I2C1_SDA

I2C1_IRQZ

I2C3_SCL (GPIO5)

I2C3_SDA (GPIO6)

I2C3_IRQ (GPIO7)

SPI_POCI (GPIO8)

SPI_PICO (GPIO9)

SPI_CLK (GPIO10)

SPI_CS (GPIO11)

GPIO12

45

47

GND

32

33

34

I2C2_SCL

I2C2_SDA

I2C2_IRQ

I2C2_SCL

I2C2_SDA

I2C2_IRQZ

GPIO13

GPIO14 (PWM)

GPIO15 (PWM)

GPIO16 (PEXT1)

GPIO17 (PEXT2)

C1_USB_P (GPIO18)

C_USB_N (GPIO19)

GPIO20

44

6

HRESET

ADCIN1

ADCIN2

HRESET

ADCIN1

ADCIN2

10

GPIO21

TPS65987DDHRSHR

C11

1µF

U2B

GND

C10

10µF

GND

35

14

13

LDO_1V8

LDO_3V3

LDO_1V8

VBUS1

VBUS

LDO_3V3

PA_PP_CABLE

9

LDO_3V3

3

4

VBUS2

GND

C12

10µF

25

PP1_CABLE

C13

22µF

46

11

12

GND

PP_HV1

PA_PP_HV

GND

8

15

DRAIN1

1

2

PP_HV2

19

58

DRAIN1

GND

DRAIN1

DRAIN2

5

C14

10µF

VIN_3V3

7

52

DRAIN2

56

57

C15

10µF

GND

20

51

GND

59

TPS65987DDHRSHR

GND

图11-1. Example Schematic

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图11-2. Example Schematic2

11.3 Component Placement

Top and bottom placement is used for this example to minimize solution size. The TPS65987D is placed on the

top side of the board and the majority of its components are placed on the bottom side. When placing the

components on the bottom side, it is recommended that they are placed directly under the TPS65987D. When

placing the VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to

face outward from the TPS65987D or to the side since the drain connection pads on the bottom layer should not

be connected to anything and left floating. All other components that are for pins on the GND pad side of the

TPS65987D should be placed where the GND terminal is underneath the GND pad.

The CC capacitors must be placed on the same side as the TPS65987D close to the respective CC1 and CC2

pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC

capacitor is recommended.

The ADCIN1/2 voltage divider resistors can be placed where convenient. In this layout example they are placed

on the opposite layer of the TPS65987D close to the LDO_3V3 pin to simplify routing.

The figures below show the placement in 2-D and 3-D.

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图11-4. Bottom View Layout

图11-3. Top View Layout

图11-5. Top View 3-D

图11-6. Bottom View 3-D

11.4 Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3, LDO_3V3, LDO_1V8

On the top side, create pours for PP_HV1/2 and VBUS1/2 to extend area to place 8-mil hole and 16-mil diameter

vias to connect to the bottom layer. See 图11-7 for the recommended via sizing.

图11-7. Recommended Minimum Via Sizing

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A minimum of four vias should be used to connect between the top and bottom layer power paths. For the

bottom layer, place pours that will connect the PP_HV1/2 and VBUS capacitors to their respective vias. For 5-A

systems, special consideration must be taken for ensuring enough copper is used to handle the higher current.

For 0.5-oz copper, top or bottom pours, with 0.5-oz plating will require about 120-mil pour width for 5-A support.

When routing the 5 A through a 0.5-oz internal layer, more than 200 mil will be required to carry the current.

The figures below show the pours used in this example.

图11-8. Top Polygon Pours

图11-9. Bottom Polygon Pours

For PP_CABLE, it is recommended to connect the capacitor to the pin with two vias. They should be placed side

by side and as close to the pin as possible to allow for routing the CC lines.

Connect the bottom side VIN_3V3 and LDO_3V3 capacitors with traces through a via. The vias should have a

straight connection to the respective pins. LDO_1V8 is connected through a via on the outside of the pin and

connected with a trace on the bottom side capacitor.

11.5 Routing CC and GPIO

Routing the CC lines with a 8-mil trace will ensure the needed current for supporting powered Type-C cables

through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use

a 16-mil trace if possible.

Most of the GPIO signals can be fanned out on the top layer with a 4-mil trace. The PP_EXT1/2 GPIO control go

through a via to be routed on another layer.

图11-10 below shows the CC and GPIO routing.

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图11-10. CC Routing and GPIO Fan-Out

表11-1. Routing Widths

ROUTE

CC1, CC2, PP_CABLE1, PP_CABLE2

VIN_3V3, LDO_3V3, LDO_1V8

Component GND

WIDTH (MIL MINIMUM)

8

6

10

4

GPIO

11.6 Thermal Dissipation for FET Drain Pads

The TPS65987D contains two internal FETs. To assist with thermal dissipation of these FETs, the drains of the

FETs are connected to two metal pads underneath the IC. When completing a board layout for the TPS65987D,

it is important to provide copper pours on the top and bottom layer of the PCB for the thermal pads of each FET.

When looking at the footprint for the TPS65987D, pins 57 and 58 are two smaller pads underneath the device.

These are the drain pads for the two internal FETs. The dimensions are 1.75 mil x 2.6 mil and 1.75 mil x 2.55 mil

for pins 57 and 58 respectively. Each of these FET pads should contain a minimum of six thermal vias through

the PCB. This layout example contains 8 thermal vias through the PCB. On the bottom side of the PCB, the 1.75

mil x 2.6 mil and 1.75 mil x 2.55 mil thermal pads are mirrored to assist with thermal dissipation.

The figures below show the copper fills for the FET Drain pads.

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图11-11. Top Layer FET Pads

图11-12. Bottom Layer FET Pads

As seen in the figures above, it is recommended to connect the Drain pins to their respective Drain pads

underneath the IC. This will help with thermal dissipation by moving some of the heat away from the device. To

further assist with thermal dissipation, it is possible to add copper fins on the top layer for both of the FET Drain

Pads. When calculating the relative thermal dissipation, the first 3 mm of copper away from the device contribute

largely to the thermal performance. Once the copper expands beyond 3 mm from the IC, there are diminishing

returns in thermal performance.

图11-13 highlights an example with copper fins to improve thermal dissipation.

图11-13. Copper Fins on Drain Pad

The thermal vias under each of the FET Drain Pads should be filled. Filling the vias will greatly improve the

thermal dissipation on the FETs as there is significantly more copper that is connecting the top layer pad to the

bottom layer copper. Alternatively, the vias can be epoxy filled but they will have higher thermal resistance. Each

8-/16-mil to 10-/20-mil via could have a thermal resistance ranging from 175°C/W to 200°C/W with board

manufacturing variation. When doing thermal calculations it is recommended to use the worst case 200°C/W

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which will give a set of six vias a thermal resistance of approximately 33°C/W from the top to bottom pad. The

vias in the FET pads should only be connected to copper pads on the top and bottom layers of the PCB. These

should not be connected to GND. Refer to the image below to see which layers should be connected for the

GND vias and FET Pad vias.

图11-14 shows a common stack-up for systems that require Super Speed and high power routing.

GND Vias

FET Pad Vias

Top Layer

GND1

Inner Layer 1

GND2

Inner Layer 2

Inner Layer 3

GND3

Bottom Layer

图11-14. PCB Stack-Up

11.7 USB2 Recommended Routing For BC1.2 Detection/Advertisement

When routing the USB2 signals to the TPS65987D BC1.2 detection pins it is recommended to reduce the

amount of excess trace to get to the TPS65987D pins, as this will cause antennae and degrade signal integrity.

The USB top/bottom signals are shorted together in this example and the same approach can be used if an

external USB mux is used. There are several approaches that can be used to get optimal routing; “tap” the

USB2 signals with vias that connect the TPS65987D pins, via up to the layer where the pins are located and

continue to route on that layer, or a combination of both.

In this layout example, the D+/D- lines are routed to an internal layer from the connector. They are then via’d

up to the TPS65987D directly at the pins. There is a small trace that is connecting the via to the pin on the top

layer. When routing the D+/D- in this manner, the added stub is minimal.

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图11-15. Via Connection for USB2

图 11-16 shows the entire routing from the Type-C connector, ESD Protection, and TPS65987D BC1.2

Detection. This example does not take length matching into consideration but It is recommended to follow

standard USB2 rules for routing and length matching.

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图11-16. Complete USB2 Routing

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.1.2 Firmware Warranty Disclaimer

IN ORDER FOR THE TPS6598X DEVICE TO FUNCTION IN ACCORDANCE WITH THIS SPECIFICATIONS,

YOU WILL NEED TO DOWNLOAD THE LATEST VERSION OF THE FIRMWARE FOR THE DEVICE. IF YOU

DO NOT DOWNLOAD AND INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE,

THEN THE DEVICE IS PROVIDED “AS IS” AND TI MAKES NO WARRANTY OR REPRESENTATION

WHATSOEVER IN RESPECT OF SUCH DEVICE, AND DISCLAIMS ANY AND ALL WARRANTIES AND

REPRESENTATIONS WITH RESPECT TO SUCH DEVICE. FURTHER, IF YOU DO NOT DOWNLOAD AND

INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE, TI WILL NOT BE LIABLE

FOR AND SPECIFICALLY DISCLAIMS ANY DAMAGES, INCLUDING DIRECT DAMAGES, HOWEVER

CAUSED, WHETHER ARISING UNDER CONTRACT, TORT, NEGLIGENCE, OR OTHER THEORY OF

LIABILITY RELATING TO THE DEVICE, EVEN IF TI IS ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

USB Type-C^®is a registered trademark of USB Implementers Forum.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

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TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OUTLINE

RSH0056E

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

A

7.15

6.85

B

PIN 1 INDEX AREA

7.15

6.85

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.4 0.1

1.75 0.1

PKG

(0.2)

15

28

52X 0.4

14

29

2.55 0.1

5.5 0.1

58

57

4X

5.2

SYMM

59

2.6 0.1

1

42

0.25

0.15

0.1

56X

PIN 1 ID

43

56

C A B

C

0.6

0.4

56X

(0.2) TYP

0.05

(0.35)

TYP

4223928/B 09/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RSH0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3X 0.05 MAX

ALL AROUND

(3.4)

(0.65)

2X

48X (0.2)

(1.75)

PKG

48X (0.7)

SEE SOLDER MASK

OPTIONS

4X (0.7)

56

43

(0.2) TYP

1

42

8X (0.2)

1.18

(2.6)

(1.45)

1.32 TYP

SYMM

52X (0.4)

57

58

59

(6.7)

(5.5)

(1.475)

(0.875) TYP

4X SOLDER MASK

DEFINED PAD

(2.55)

29

14

PADS 57,58 & 59

NON SOLDER MASK

DEFINED

(

0.2) TYP

28

15

3X

(0.15)

VIA

3X

(1.2)

(0.475) TYP

SOLDER MASK

OPENING

(1.875)

5X (1.05)

(6.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK OPTIONS

NOT TO SCALE

4223928/A 09/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RSH0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

PKG

4X (0.7)

4X

(1.67)

TYP

(1.47)

48X (0.2)

(0.2) TYP

(0.215)

TYP

48X (0.7)

56

43

8X (0.2)

4X (1.15)

1

42

52X (0.4)

(1.32)

TYP

(1.35)

(0.775)

57

58

(0.66) TYP

59

SYMM

(6.7)

(0.8)

(1.35)

8X (1.12)

29

14

METAL UNDER

SOLDER MASK

TYP

28

15

METAL

TYP

SOLDER MASK

OPENING

TYP

(1.875)

8X (1.47)

(6.7)

SOLDER PASTE EXAMPLE

BASED ON 0.1 MM THICK STENCIL

EXPOSED PAD PRINTED SOLDER COVERAGE BY AREA

PAD 57 & 58: 75%

PAD 59: 70%

SCALE: 12X

4223928/B 09/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TPS65987D
厂家：	TEXAS INSTRUMENTS
描述：	具有集成电源开关的 USB Type-C® 和 USB PD 控制器开关控制器电源开关光电二极管
文件：	总73页 (文件大小：2764K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65987D [TI]

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