TPS65994ADRSLR [TI]
具有集成电源开关的双端口 USB Type-C® 和 USB PD 控制器 | RSL | 48 | -40 to 125;
| 型号： | TPS65994ADRSLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电源开关的双端口 USB Type-C® 和 USB PD 控制器 | RSL | 48 | -40 to 125 开关 控制器 电源开关 光电二极管 |
| 文件： | 总64页 (文件大小：2803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65994AD
ZHCSLY5A –AUGUST 2020 –REVISED JULY 2021
TPS65994AD 双端口、具有集成电源开关、支持USB4 和交替模式的USB Type-
C®和USB PD 控制器
1 特性
2 应用
• 该器件由USB-IF 进行了PD3.0 认证
• PC 和笔记本电脑
• 耐用PC 和笔记本电脑
• 单板计算机
• 集线站
• 平板监视器
– 认证新的USB PD 设计时需使用PD3.0 器件
• TID#：3495
– 有关PD2.0 与PD3.0 的文章
• TPS65994AD 是完全可配置的双端口USB4 和
Thunderbolt 4 (TBT4) PD3.0 控制器
3 说明
– 此器件可用于USB4 主机和器件设计
– 支持工业工作温度范围
– 用于为各种应用轻松配置TPS65994AD 的GUI
工具
– 支持DisplayPort 拉电流、Thunderbolt 和用户
可配置交替模式
TPS65994AD 是一款高度集成的独立式双端口 USB
Type-C 和电力输送 (PD) 控制器，针对 PC 和笔记本
电脑应用进行了优化。TPS65994AD 集成了完全管理
的电源路径与强大的保护功能，可提供完整的 USB-C
PD 解决方案。 TPS65994AD Intel 和 AMD 的 PC 和
笔记本电脑终端设备参考设计使用了此器件，确保 PD
控制器在这类设计中提供适当的系统级交互。此功能显
著降低系统设计的复杂性，并缩短上市时间。
– 有关更详尽的选择指南和入门信息，请参阅
www.ti.com/usb-c 和E2E 指南
• 完全管理的集成电源路径：
– 集成两个5V、3A、38mΩ电源开关
– UL2367 认证编号：E169910
– IEC62368-1 认证编号：US-34737-M3-UL
• 集成强大的电源路径保护
器件信息
器件型号(1)
封装尺寸（标称值）
封装
TPS65994AD
QFN (RSL)
6.0mm × 6.0mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 为拉电流路径集成了过压保护、欠压保护、反向
电流保护和可调节限流功能
– 为灌电流路径集成了过压保护、欠压保护和反向
5A
5A
5-20 V
电流保护
• USB Type-C® 功率传输(PD) 控制器
3.3V
PP_EXT
Control
PP_EXT
Control
LDO
CC1/2
– 10 个可配置GPIO
USB
Type-C
Connector
CC
VCONN
2
– 符合USB PD 3.0 标准
– 符合USB Type-C 规范
– 线缆连接和方向检测
– 集成式VCONN 开关
– 集成式无电电池Rd
TPS65994
3 A
VBUS
5 V
VBUS
3 A
Type-C Rp/Rd & state
CC1/2
CC
VCONN
2
machine,
VCONN switches,
USB PD policy engine,
protocol and physical
layer
EC Host
Interface
EC
USB
Type-C
Connector
– 物理层和策略引擎
TBT
Controller
TBT Host
Interface
– 3.3V LDO 输出，在电池电量耗尽时提供支持
– 通过3.3V 或VBUS 源供电
– 1 个I2C 主端口
GND
I2C
Master
I2C slaves
2 ADCIN pins
(I2C addr &
config)
10 GPIO
– 2 个I2C 次级端口
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFM6
TPS65994AD
ZHCSLY5A –AUGUST 2020 –REVISED JULY 2021
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................40
9 Application and Implementation..................................42
9.1 Application Information............................................. 42
9.2 Typical Application.................................................... 42
10 Power Supply Recommendations..............................49
10.1 3.3-V Power............................................................ 49
10.2 1.5-V Power............................................................ 49
10.3 Recommended Supply Load Capacitance..............49
11 Layout...........................................................................50
11.1 Layout Guidelines................................................... 50
11.2 Layout Example...................................................... 50
11.3 Component Placement............................................50
11.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3,
LDO_1V5.....................................................................52
11.5 Routing CC and GPIO.............................................54
12 Device and Documentation Support..........................56
12.1 Device Support....................................................... 56
12.2 Documentation Support.......................................... 56
12.3 支持资源..................................................................56
12.4 Trademarks.............................................................56
12.5 Electrostatic Discharge Caution..............................56
12.6 术语表..................................................................... 56
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................6
6.4 Recommended Capacitance ......................................6
6.5 Thermal Information ...................................................6
6.6 Power Supply Characteristics ....................................7
6.7 Power Consumption ...................................................7
6.8 PP_5V Power Switch Characteristics ........................ 8
6.9 PP_EXT Power Switch Characteristics ......................9
6.10 Power Path Supervisory ........................................ 10
6.11 CC Cable Detection Parameters ............................10
6.12 CC VCONN Parameters ........................................ 12
6.13 CC PHY Parameters ..............................................12
6.14 Thermal Shutdown Characteristics ........................13
6.15 ADC Characteristics ...............................................13
6.16 Input/Output (I/O) Characteristics .......................... 14
6.17 I2C Requirements and Characteristics .................. 14
6.18 Typical Characteristics ...........................................16
7 Parameter Measurement Information..........................17
8 Detailed Description......................................................18
8.1 Overview...................................................................18
Information.................................................................... 56
13.1 Package Option Addendum....................................57
4 Revision History
Changes from Revision * (August 2020) to Revision A (July 2021)
Page
• 更改了特性列表..................................................................................................................................................1
• 更新了应用部分..................................................................................................................................................1
• 更新了说明部分..................................................................................................................................................1
Copyright © 2022 Texas Instruments Incorporated
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5 Pin Configuration and Functions
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
LDO_1V5
GPIO1
PA_VBUS
PA_VBUS
PA_VBUS
PA_VBUS
PP5V
I2C2s_IRQ
I2C_EC_SDA
I2C2s_SCL
I2C_EC_SCL
I2C_EC_IRQ
I2C2s_SDA
GPIO0
Thermal
Pad
(GND)
PA_GATE_VBUS
PB_GATE_VBUS
PP5V
PB_VBUS
PB_VBUS
PB_VBUS
PB_VBUS
GPIO5
I2C3m_IRQ
I2C3m_SDA
图5-1. RSL Package 48-pin QFN Top View
表5-1. Pin Functions
PIN
TYPE
RESET Description
NAME
ADCIN1
ADCIN2
GND
NO.
33
35
36
I
I
Hi-Z
Hi-Z
—
Configuration input. Connect to a resistor divider to LDO_3V3.
Configuration input. Connect to a resistor divider to LDO_3V3.
Ground. Connect to ground plane.
—
General purpose digital I/O. Tie to PP5V or ground when unused. May be
used as DisplayPort HPD signal for Port B.
GPIO0
GPIO1
45
38
I/O
I/O
Hi-Z
Hi-Z
General purpose digital I/O. Tie to PP5V or ground when unused. May be
used as DisplayPort HPD signal for Port A.
GPIO2
GPIO3
9
I/O
I/O
Hi-Z
Hi-Z
General purpose digital I/O. Tie to PP5V or ground when unused.
General purpose digital I/O. Tie to PP5V or ground when unused.
28
General purpose digital I/O. May be used as an ADC input. Tie to PP5V or
ground when unused.
GPIO4
GPIO5
2
I/O
I/O
Hi-Z
Hi-Z
General purpose digital I/O. May be used as an ADC input. Tie to PP5V or
ground when unused.
46
GPIO6
GPIO7
GPIO8
29
27
10
I/O
I/O
I/O
Hi-Z
Hi-Z
Hi-Z
General purpose digital I/O. Tie to PP5V or ground when unused.
General purpose digital I/O. Tie to PP5V or ground when unused.
General purpose digital I/O. Tie to PP5V or ground when unused.
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表5-1. Pin Functions (continued)
PIN
TYPE
RESET Description
NAME
NO.
GPIO9
8
O
I
Hi-Z
Hi-Z
General purpose digital output. Tie to PP5V or ground when unused.
I2C slave serial clock input. Tie to pullup voltage through a resistor. May be
I2C_EC_SCL
I2C_EC_SDA
42
40
grounded if unused. Connect to Embedded Controller (EC).
I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a
resistor. May be grounded if unused. Connect to Embedded Controller (EC).
I/O
O
Hi-Z
Hi-Z
I2C slave interrupt. Active low. Connect to external voltage through a pull-up
resistor. Connect to Embedded Controller (EC). This can be re-configured to
GPIO10. May be grounded if unused.
I2C_EC_IRQ
43
I2C slave serial clock input. Tie to pull-up voltage through a resistor. May be
grounded if unused.
I2C2s_SCL
I2C2s_SDA
41
44
I
Hi-Z
Hi-Z
I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a
resistor. May be grounded if unused.
I/O
I2C slave interrupt. Active low. Connect to external voltage through a pull-up
resistor. Tie to PP5V or ground when unused. This can be re-configured to
GPIO11.
I2C2s_IRQ
39
O
Hi-Z
I2C master serial clock. Open-drain output. Tie to pullup voltage through a
resistor when used or unused.
I2C3m_SCL
I2C3m_SDA
1
O
Hi-Z
Hi-Z
I2C master serial data. Open-drain input/output. Tie to pullup voltage through
a resistor when used or unused.
48
I/O
I2C master interrupt. Active low. Connect to external voltage through a pull-up
resistor. Tie to PP5V or ground when unused. This can be re-configured to
GPIO12.
I2C3m_IRQ
47
I
Hi-Z
Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This
pin cannot source current to external circuits.
LDO_1V5
LDO_3V3
PA_CC1
PA_CC2
37
34
31
30
O
O
—
—
Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with
capacitance CLDO_3V3 to GND.
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
GND (CPx_CCy).
I/O
I/O
Hi-Z
Hi-Z
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
GND (CPx_CCy).
PA_GATE_VSYS
PA_GATE_VBUS
5
O
O
Hi-Z
Hi-Z
Connect to the PortA N-ch MOSFET that has source tied to VSYS.
Connect to the N-ch MOSFET that has source tied to PA_VBUS.
19
5-V to 20-V input or 5-V output from PP5V. Bypass with capacitance CVBUS to
GND.
PA_VBUS
PB_CC1
PB_CC2
21,22,23,24
I/O
I/O
I/O
—
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
GND (CPx_CCy).
6
7
Hi-Z
Hi-Z
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
GND (CPx_CCy).
PB_GATE_VSYS
PB_GATE_VBUS
4
O
O
Hi-Z
Hi-Z
Connect to the Port B N-ch MOSFET that has source tied to VSYS.
Connect to the N-ch MOSFET that has source tied to PB_VBUS.
18
5-V to 20-V input or 5-V output from PP5V. Bypass with capacitance CVBUS to
GND.
PB_VBUS
PP5V
13,14,15,16
I/O
I
—
—
11,12,17,20,25,
26
5-V System Supply to VBUS, supply for Px_CCy pins as VCONN.
High-voltage sinking node in the system. It is used to implement reverse-
current-protection (RCP) for the external sinking paths controlled by
PA_GATE_VSYS and PB_GATE_VSYS.
VSYS
3
I
I
—
—
VIN_3V3
32
Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.5
MAX
UNIT
PP5V
6
4
VIN_3V3
V
ADCIN1, ADCIN2
VSYS, PA_VBUS, PB_VBUS (4)
4
28
6
Input voltage range (2)
PA_CC1, PA_CC2, PB_CC1, PB_CC2
GPIO0-GPIO9, I2C_EC_IRQ, I2C2s_IRQ,
I2C3m_IRQ
-0.3
6
4
V
V
I2C_EC_SDA, I2C_EC_SCL,I2C2s_SDA,
I2C2s_SCL, I2C3m_SDA, I2C3m_SCL
–0.3
LDO_1V5(3)
Output voltage range (2)
2
4
–0.3
–0.3
LDO_3V3(3)
PA_GATE_VBUS, PA_GATE_VSYS,
Output voltage range (2)
40
V
V
–0.3
–0.5
PB_GATE_VBUS, PB_GATE_VSYS (3)
VGS
VPx_GATE_VBUS - VPx_VBUS, VPx_GATE_SYS - VVSYS
Source or sink current PA_VBUS, PB_VBUS
12
internally limited
Positive source current on PA_CC1, PA_CC2,
PB_CC1, PB_CC2
1
Positive sink current on PA_CC1, PA_CC2,
PB_CC1, PB_CC2 while VCONN switch is
enabled
1
0.005
Source current
A
GPIO0-GPIO9
positive sink current for I2C_EC_SDA,
I2C_EC_SCL, I2C2s_SDA, I2C2s_SCL,
I2C3m_SDA, I2C3m_SCL,
internally limited
positive source current for LDO_3V3, LDO_1V5
internally limited
TJ Operating junction temperature
TSTG Storage temperature
175
150
°C
°C
–40
–55
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(3) Do not apply voltage to these pins.
(4) For Px_VBUS a TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such
as TVS2200. For Px_VBUS a Schottky diode is recommended to ensure the MIN voltage is not violated.
6.2 ESD Ratings
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specificationJESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
3.0
4.9
4
MAX
3.6
5.5
22
UNIT
V
VIN_3V3
VI
VI
Input voltage range (1)
Input voltage range (1)
PP5V (2)
(3)
PA_VBUS, PB_VBUS
VSYS
0
22
V
I2Cx_SDA, I2Cx_SCL, ADCIN1,
ADCIN2
0
0
0
3.6
5.5
GPIOx, I2C_EC_IRQ, I2C2s_IRQ,
I2C3m_IRQ
VIO
I/O voltage range (1)
V
PA_CC1, PA_CC2, PB_CC1,
PB_CC2
5.5
3
PA_VBUS, PB_VBUS
A
IO
Output current (from PP5V)
PA_CC1, PA_CC2, PB_CC1,
PB_CC2
315
1
mA
mA
mA
IO
IO
Output current (from LDO_3V3)
Output current (from VBUS LDO)
GPIOx
sum of current from LDO_3V3 and
GPIO0-9.
5
I
I
PP_5Vx ≤1.5 A, IPP_5Vy ≤3.0 A,
PP_CABLEx ≤315 mA
105
–40
TA
TJ
Ambient operating temperature
Operating junction temperature
°C
°C
I
PP_5Vx ≤3.0 A, IPP_CABLEx ≤315
85
–40
–40
mA
125
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(2) Maximum current sourced from PP5V to PA_VBUS or PB_VBUS. Resistance from Px_VBUS to Type-C connector less than or equal
30 mΩ. Short all PP5V bumps together.
(3) All PA_VBUS bumps should be shorted together. All PB_VBUS bumps should be shorted together.
6.4 Recommended Capacitance
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
VOLTAGE RATING
MIN
NOM
10
MAX
UNIT
µF
CVIN_3V3
CLDO_3V3
CLDO_1V5
CPx_VBUS
CPP5V
Capacitance on VIN_3V3
6.3 V
6.3 V
4 V
5
5
Capacitance on LDO_3V3
Capacitance on LDO_1V5
Capacitance on VBUS(4)
Capacitance on PP5V
10
25
12
10
µF
4.5
µF
25 V
10 V
1
4.7
µF
120(2)
µF
Capacitance on VSYS Sink from
VBUS
CVSYS
25 V
47
100
480
µF
pF
CPx_CCy
Capacitance on Px_CCy pins(3)
6.3 V
200
320
(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by
50% at the required operating voltage, then the required external capacitor value would be 10 µF.
(2) This is a requirement from USB PD (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V.
(3) This includes all capacitance to the Type-C receptacle.
(4) The device can be configured to quickly disable PP_EXT upon certain events. When such a configuration is used, a capacitance on
the higher side of this range is recommended.
6.5 Thermal Information
DEVICE
THERMAL METRIC
QFN (RSL)
48 PINS
26.8
UNIT
RθJA
θJC (top)
Junction-to-ambient thermal resistance
°C/W
°C/W
R
Junction-to-case (top) thermal resistance
15.4
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6.5 Thermal Information (continued)
DEVICE
THERMAL METRIC
QFN (RSL)
48 PINS
8.5
UNIT
RθJB
Junction-to-board thermal resistance
°C/W
°C/W
Junction-to-top characterization parameter
0.2
ψJT
Junction-to-board characterization
parameter
8.5
1.8
°C/W
°C/W
ψJB
Junction-to-case (bottom GND pad)
thermal resistance
RθJC (bottom)
6.6 Power Supply Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIN_3V3, Px_VBUS
rising, VPx_VBUS=0
2.56
2.44
2.66
2.54
0.12
2.76
2.64
voltage required on VIN_3V3 for
power on
VVIN3V3_UVLO
falling, VPx_VBUS=0
hysteresis
rising
3.6
3.5
3.9
3.8
VVBUS_UVLO
UVLO comparator for Px_VBUS falling
hysteresis
V
0.1
3.4
LDO_3V3, LDO_1V5
VVIN_3V3 = 0V, ILDO_3V3 ≤5 mA,
PA_VBUS ≥3.9V or VPB_VBUS
3.9V
VLDO_3V3
voltage on LDO_3V3
2.7
3.6
1.5
V
V
≥
RLDO_3V3
VLDO_1V5
Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3=50mA
up to maximum internal loading
condition.
Ω
Output voltage of LDO_1V5
1.55
V
6.7 Power Consumption
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V, no loading on GPIO pins
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IVIN_3V3,ActSrc
IVIN_3V3,ActSnk
IVSYS
current into VIN_3V3
Active Source mode: VPP5V=5.0V, VVIN_3V3=3.3V
4.5
12 mA
Active Sink mode: 22V ≥VPA_VBUS ≥4.0V, 22V ≥
current into VIN_3V3
current into VSYS
4.8
10
12 mA
µA
V
PB_VBUS ≥4.0V, VVIN_3V3=3.3V
Idle Source mode: VPA_VBUS=5.0V, VPB_VBUS=5.0V,
VVIN_3V3=3.3V
IVIN_3V3,IdlSrc
current into VIN_3V3
1.1
mA
Idle Sink mode: 22V ≥VPA_VBUS ≥4.0V, 22V ≥VPB_VBUS
≥4.0V, VVIN_3V3=3.3V
IVIN_3V3,IdlSnk
current into VIN_3V3
1.1
3.7
mA
Power drawn into PP5V
and VIN_3V3 in Modern
Standby Sink Mode
Modern Standby Sink Mode: VPP5V = 5V, VVIN_3V3=3.3V,
VPA_VBUS=5.0V, VPB_VBUS=0V
PMstbySnk
mW
Power drawn into PP5V
and VIN_3V3 in Modern
Standby Source Mode
Modern Standby Source Mode: VPP5V = 5V, VVIN_3V3=3.3V,
IPx_VBUS=0
PMstbySrc
4.5
67
mW
µA
Sleep mode: VPA_VBUS=0V, VPB_VBUS=0V, VVIN_3V3=3.3V, TJ
≤25 oC
IVIN_3V3,Sleep
current into VIN_3V3
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6.8 PP_5V Power Switch Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6V
PARAMETER
TEST CONDITIONS
ILOAD = 3 A, TJ≤25oC
ILOAD = 3 A, TJ≤125oC
MIN
TYP
37.7
37.7
MAX
41.5
57
UNIT
RPP_5V
Resistance from PP5V to Px_VBUS
mΩ
VPP5V = 0V, VPx_VBUS
=
5.5V, PP_5V disabled,
IPP5V_REV
Px_VBUS to PP5V leakage current
PP5V to Px_VBUS leakage current
0
0
3
µA
µA
TJ≤85oC, measure IPP5V
VPP5V = 5.5V, VPx_VBUS
0V, PP_5V disabled,
TJ≤85oC, measure
IPx_VBUS
=
IPP5V_FWD
15
ILIM5V
ILIM5V
ILIM5V
ILIM5V
ILIM5V
Current limit setting
Current limit setting
Current limit setting
Current limit setting
Current limit setting
Configure to setting 0
configure to setting 1
configure to setting 2
configure to setting 3
configure to setting 4
1.15
1.61
2.3
1.36
1.90
2.70
3.58
3.78
A
A
A
A
A
3.04
3.22
PP5V to Px_VBUS current sense
accuracy
3.0A ≥IPx_VBUS ≥1A,
VVIN_3V3=3.3V
IPx_VBUS
2.8
3.4
15
4.1
A/V
RCP clears and PP_5Vx starts
turning on when VPx_VBUS –VPP5V
<
VPP_5V_RCP
10
20
mV
VPP_5V_RCP. Measure VPx_VBUS
VPP5V
–
Px_VBUS to GND through
10mΩ, CPx_VBUS=0
tiOS_PP_5V
response time to VBUS short circuit
1.15
4.5
µs
µs
Enable PP_5Vx, ramp
VPx_VBUS from 4V to 20V at
100 V/ms
response time to VPx_VBUS
VOVP4RCP
>
tPP_5V_ovp
response time to VPP5V
VPP5V_UVLO, PP_VBUS is deemed off
when VPx_VBUS < 0.8V
<
RL = 100 Ω, no external
capacitance on Px_VBUS
tPP_5V_uvlo
4
µs
µs
VPP5V=5.5V,enable
PP_5Vx, ramp VPx_VBUS
from 4V to 21.5V at 10 V/µs
response time to VPP5V
VPx_VBUS+VPP_5V_RCP
<
tPP_5V_rcp
0.7
Initial VPx_VBUS = 0V, 2µF
≤CPx_VBUS ≤20µF, 0 ≤
Time allowed to enable the pass FET
in PP_5Vx with 3A current limit.
tFRS_on
54
150
µs
I
Px_VBUS ≤0.5 A, FET is
deemed enabled when
VPx_VBUS > 4.75V.
tILIM
tON
Current clamping deglitch time
5
ms
ms
from enable signal to Px_VBUS at
90% of final value
RL = 100Ω, VPP5V = 5V,
CL=0
2.6
0.30
1.2
3.5
4.4
0.6
from disable signal to Px_VBUS at
10% of final value
RL = 100Ω, VPP5V = 5V,
CL=0
tOFF
tRISE
tFALL
0.45
1.7
ms
ms
ms
Px_VBUS from 10% to 90% of final
value
RL = 100Ω, VPP5V = 5V,
CL=0
2.2
Px_VBUS from 90% to 10% of initial
value
RL = 100Ω, VPP5V = 5V,
CL=0
0.06
0.1
0.14
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6.9 PP_EXT Power Switch Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0 ≤VPx_GATE_VSYS-VVSYS
≤6 V, 0 V ≤VVSYS ≤22
V, VPx_VBUS > 4 V, measure
IPx_GATE_VSYS
8.5
10
11.5
µA
IPx_GATE_ON
Gate driver sourcing current
0 ≤VPx_GATE_VBUS
-
V
V
Px_VBUS ≤6 V, 4 V ≤
Px_VBUS ≤22 V, measure
8.5
6
10
11.5
12
µA
V
IPx_GATE_VBUS
0 ≤VVSYS ≤22 V,
IPx_GATE_VSYS < 4 µA,
measure VPx_GATE_VSYS
VVSYS, VPx_VBUS > 4 V.
–
–
VPx_GATE_ON
sourcing voltage (ON)
4 V ≤VPx_VBUS ≤22 V,
IPx_GATE_VBUS < 4 µA,
measure VPx_GATE_VBUS
6
12
V
VPx_VBUS
.
setting 0, 4 V ≤
2
4
6
8
6
8
10
12
14
16
mV
mV
mV
mV
V
V
Px_VBUS ≤22 V,
VIN_3V3 ≤3.63 V
setting 1, 4 V ≤
V
V
Px_VBUS ≤22 V,
VIN_3V3 ≤3.63 V
comparator mode RCP threshold,
VRCP
VVSYS - VPx_VBUS
.
setting 2, 4 V ≤
V
V
10
12
Px_VBUS ≤22 V,
VIN_3V3 ≤3.63 V
setting 3, 4 V ≤
V
V
Px_VBUS ≤22 V,
VIN_3V3 ≤3.63 V
normal turnoff: VVSYS = 5V,
VPx_GATE_VSYS=6V
13
13
µA
µA
Ω
IPx_GATE_OFF
Sinking strength
Sinking strength
normal turnoff: VPx_VBUS
5V, VPx_GATE_VBUS=6V,
VVSYS = 5 V
=
fast turnoff: VVSYS = 5V,
VPx_GATE_VSYS=6V,
85
85
RPx_GATE_FSD
fast turnoff: VPx_VBUS = 5V,
VPx_GATE_VBUS=6V, VVSYS
5 V
=
Ω
VVIN_3V3=0V,
RPx_GATE_OFF_UVLO
Sinking strength in UVLO (safety)
VPx_VBUS=3.0V,
VPx_GATE_VSYS=0.1V
1.5
MΩ
V/ms
µs
soft start slew rate for
Px_GATE_VSYS, setting 0
0.35
0.67
1.33
2.88
0.47
0.91
1.83
3.90
4 V ≤VPx_VBUS ≤22 V,
500pF < CPx_GATE_VSYS
16 nF, measure slope from
10% to 90% of final
Px_GATE_VSYS value,
soft start slew rate for
Px_GATE_VSYS, setting 1
<
SS
soft start slew rate for
Px_GATE_VSYS, setting 2
soft start slew rate for
Px_GATE_VSYS, setting 3
Time allowed to disable the external
FET via Px_GATE_VBUS in normal
shutdown mode.(1)
VPx_VBUS=20V, Gate is off
when VGS < 1 V
tPx_GATE_VBUS_OFF
260
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6.9 PP_EXT Power Switch Characteristics (continued)
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time allowed to disable the external OVP: VOVP4RCP= setting
FET via Px_GATE_VBUS in fast
shutdown mode (VOVP4RCP
exceeded).(1)
57, VPx_VBUS=20V initially,
then raised to 23V in 50ns,
Gate is off when VGS < 1 V
tPx_GATE_VBUS_OVP
3
µs
RCP: VRCP= setting 0,
Time allowed to disable the external VPx_VBUS=5V, VVSYS=5V
tPx_GATE_VBUS_RCP
FET via Px_GATE_VBUS in fast
initially, then raised to 5.5V
1.2
µs
shutdown mode (VRCP exceeded).(1) in 50ns, Gate is off when
VGS < 1 V
Time allowed to disable the external
VVSYS=20V, Gate is off
tPx_GATE_VSYS_OFF
FET via Px_GATE_VSYS in normal
when VGS < 1 V
0.25
ms
shutdown mode(1)
VVSYS=VVBUS=20V initially,
Time allowed to disable the external
then VVBUS raised to 23V in
tPx_GATE_VSYS_FSD
FET via Px_GATE_VSYS in fast
50ns, Gate is off when
0.25
0.25
μs
shutdown mode (OVP or FRS)(1)
VGS< 1 V
measure time from when
time to enable Px_GATE_VBUS (1)
tPx_GATE_VBUS_ON
ms
VGS=0V until VGS>3V
(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when
Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.
6.10 Power Path Supervisory
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
5.25
-5
TYP
MAX
22.9
5
UNIT
VBUS over voltage protection typical
threshold for RCP programmable
range (setting 0 to setting 63).
OVP detected when
VPx_VBUS > VOVP4RCP
VOVP4RCP
V
Tolernance of VOVP4RCP threshold
%
VBUS over voltage protection range
for RCP
VOVPLSB
280
mV
VOVP4RCPH
hysteresis
1.75
1
2
1
2.25
1
%
setting 0
setting 1
setting 2
setting 3
V/V
V/V
V/V
V/V
Configurable ratio of OVP comparator
thresholds. rOVP*VOVP4VSYS
VOVP4RCP
0.925
0.875
0.85
0.95
0.90
0.875
0.975
0.925
0.9
rOVP
=
VBUS over voltage protection range
for VSYS protection
OVP detected when
rOVP*VPx_VBUS > VOVP4RCP
VOVP4VSYS
VOVP4VSYS
5
27.5
V
VBUS falling, % of
VOVP4VSYS
hysteresis
2
%
rising
3.9
3.8
4.1
4.0
0.1
4.3
4.2
VPP5V_UVLO
Voltage required on PP5V
VBUS discharge current (1)
falling
V
hysteresis
VPx_VBUS = 22V, measure
IPx_VBUS
IDSCH
4
13
mA
(1) The discharge is enabled automatically when needed to meet USB specifications. It is not always enabled.
6.11 CC Cable Detection Parameters
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Type-C Source (Rp pull-up)
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6.11 CC Cable Detection Parameters (continued)
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V,
RCC = 47 kΩ
Unattached Px_CCy open circuit
voltage while Rp enabled, no load
VOC_3.3
VOC_5
1.85
V
VPP5V_UVLO < VPP5V < 5.5 V, RCC
=
Attached Px_CCy open circuit
voltage while Rp enabled, no load
2.95
V
47 kΩ
VPx_CCy = 5.5V, VPx_CCx = 0V,
VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V,
VPP5V = 3.8 V , measure current
into Px_CCy
10
10
Unattached reverse current on
Px_CCy
IRev
µA
VPx_CCy = 5.5V, VPx_CCx = 0V,
VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V,
VPP5V = 0, -10oC≤TJ≤85oC,
measure current into Px_CCy
0 < VPx_CCy < 1.0 V, measure
IPx_CCy
IRpDef
IRp1.5
IRp3.0
current source - USB Default
current source - 1.5A
64
166
304
80
180
330
96
194
356
µA
µA
µA
4.75 V < VPP5V < 5.5 V, 0 <
VPx_CCy < 1.5 V, measure IPx_CCy
4.75 V < VPP5V < 5.5 V, 0 <
VPx_CCy < 2.45 V, measure IPx_CCy
current source - 3.0A
Type-C Sink (Rd pull-down)
Open/Default detection threshold
rising
falling
0.2
0.24
0.20
V
V
when Rd applied to Px_CCy
VSNK1
VSNK2
VSNK3
Open/Default detection threshold
when Rd applied to Px_CCy
0.16
hysteresis
0.04
V
V
V
V
Default/1.5A detection threshold
Default/1.5A detection threshold
hysteresis
falling
rising
0.62
0.63
0.68
0.69
0.66
0.01
1.5A/3.0A detection threshold
when Rd applied to Px_CCy
falling
rising
1.17
1.22
1.25
1.3
V
1.5A/3.0A detection threshold
when Rd applied to Px_CCy
V
V
hysteresis
0.05
0.25 V ≤VPx_CCy ≤2.1 V,
measure resistance on Px_CCy
RSNK
Rd pulldown resistance
4.1
4.1
6.1
6.1
kΩ
0V ≤VPx_CCy ≤ 5.5 V, measure
resistance on Px_CCy
RVCONN_DIS
VCONN discharge resistance
Dead battery Rd clamp
kΩ
VVIN_3V3=0V, 64 µA < IPx_CCy<96
µA
0.25
0.65
1.20
1.32
1.32
2.18
VVIN_3V3=0V, 166 µA <
IPx_CCy<194 µA
VCLAMP
V
VVIN_3V3=0V, 304 µA < IPx_CCy
356 µA
<
VPx_VBUS = 0, VVIN_3V3=3.3V,
VPx_CCy=5 V, measure resistance
on Px_CCy
500
500
495
kΩ
kΩ
resistance from Px_CCy to GND
when configured as open.
ROpen
VPx_VBUS = 5V, VVIN_3V3 = 0,
VPx_CCy=5 V, measure resistance
on Px_CCy
Fast Role swap request voltage
detection threshold on Px_CCy
(falling)
VFRS
VFRS
515
535
mV
V
hysteresis
0.01
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6.11 CC Cable Detection Parameters (continued)
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPx_CCy must be below VFRS for at
least this long before the FRS
signal is detected
Fast role swap signal detection
time
tFRS_DET
30
35
µs
response time of the Fast role
swap comparator (rising)
tFRS_Resp
VPx_CCy rises from 0.24V to 0.64V
0.6
µs
Common (Source and Sink)
deglitch time for comparators on
Px_CCy
tCC
3.2
ms
6.12 CC VCONN Parameters
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
Rdson of the VCONN path
TEST CONDITIONS
MIN
TYP MAX
UNIT
VPP5V=5V, IL = 250 mA,
measure resistance from PP5V
to Px_CCy
RPP_CABLE
0.4
0.7
Ω
setting 0, VPP5V=5V,
RL=10mΩ , measure IPx_CCy
ILIMVC
ILIMVC
short circuit current limit
short circuit current limit
350
540
410
605
470
670
mA
mA
setting 1, VPP5V=5V,
RL=10mΩ , measure IPx_CCy
VCONN disabled, TJ ≤85 oC,
VPx_CCy = 5.5 V, VPP5V=0 V,
VPx_VBUS=5V, LDO forced to
draw from VBUS, measure
IPx_CCy
Reverse leakage current
through VCONN FET
ICC2PP5V
0
10
µA
tVCILIM
Current clamp deglitch time
1.28
171
ms
µs
from disable signal to Px_CCy
at 10% of final value
tPP_CABLE_off
IL = 250 mA, VPP5V = 5V, CL=0
100
300
VPP5V=5V, for short circuit RL =
10mΩ.
tiOS_PP_CABLE
response time to short circuit
2
µs
6.13 CC PHY Parameters
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V or VPx_ VBUS ≥3.9 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitter
VTXHI
Transmit high voltage on Px_CCy Standard External load
1.05
-75
1.125
1.2
75
V
VTXLO
Transmit low voltage on Px_CCy
Standard External load
measured at 750 kHz
mV
Transmit output impedance while
driving the CC line using Px_CCy
ZDRIVER
33
75
Ω
Rise time. 10 % to 90 % amplitude
points on Px_CCy, minimum is
under an unloaded condition.
Maximum set by TX mask
tRise
CPx_CCy= 520 pF
300
ns
Fall time. 90 % to 10 % amplitude
points on Px_CCy, minimum is
under an unloaded condition.
Maximum set by TX mask
tFall
CPx_CCy= 520 pF
300
ns
Receiver
Does not include pull-up or
pulldown resistance from cable
detect. Transmitter is Hi-Z.
receiver input impedance on
Px_CCy
ZBMCRX
1
MΩ
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6.13 CC PHY Parameters (continued)
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V or VPx_ VBUS ≥3.9 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver capacitance on
Px_CCy(1)
Capacitance looking into the CC
pin when in receiver mode
CCC
120
pF
Rising threshold on Px_CCy for
receiver comparator
VRX_SNK_R
VRX_SRC_R
VRX_SNK_F
VRX_SRC_F
sink mode (rising)
source mode (rising)
sink mode (falling)
source mode (falling)
499
784
230
523
525
825
250
550
551
866
270
578
mV
mV
mV
mV
Rising threshold on Px_CCy for
receiver comparator
Falling threshold on Px_CCy for
receiver comparator
Falling threshold on Px_CCy for
receiver comparator
(1) CCC includes only the internal capacitance on a Px_CCy pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI
recommends adding CPx_CCy externally.
6.14 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Temperature rising
hysteresis
MIN
TYP
160
15
MAX
UNIT
°C
145
175
TSD_MAIN
Temperature shutdown threshold
°C
Temperature controlled shutdown Temperature rising
threshold. The power paths for
135
150
165
°C
each port sourcing from PP5V
TSD_PP5V
have local sensors that disables
them when this temperature is
exceeded.
hysteresis
5
°C
6.15 ADC Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.6V max scaling, voltage
divider of 3
14
mV
LSB
least significant bit
25.2V max scaling, voltage
divider of 21
98
mV
mA
4.07A max scaling
16.5
0.05V ≤VADCINx
≤
3.6V, VADCINx ≤VLDO_3V3
2.7
–2.7
0.05V ≤VGPIOx ≤3.6V, VGPIOx
≤VLDO_3V3
GAIN_ERR
Gain error
%
2.4
2.1
2.7V ≤VLDO_3V3 ≤3.6V
0.6V ≤VPx_VBUS ≤22V
–2.4
–2.1
0.05V ≤VADCINx
≤
3.6V, VADCINx ≤VLDO_3V3
4.1
–4.1
0.05V ≤VGPIOx ≤3.6V, VGPIOx
≤VLDO_3V3
VOS_ERR
Offset error(1)
mV
-4.1
-4.1
4.1
4.1
2.7V ≤VLDO_3V3 ≤3.6V
0.6V ≤VPx_VBUS ≤22V
(1) The offset error is specified after the voltage divider.
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6.16 Input/Output (I/O) Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO0-8 (Inputs)
GPIO_VIH
GPIOx high-Level input voltage VLDO_3V3 = 3.3V
GPIOx low-level input voltage VLDO_3V3 = 3.3V
GPIOx input hysteresis voltage VLDO_3V3 = 3.3V
1.3
V
V
GPIO_VIL
0.54
GPIO_HYS
0.09
–1
50
V
GPIO_ILKG
GPIO_RPU
GPIOx leakage current
GPIOx internal pull-up
GPIOx internal pull-down
GPIOx input deglitch
VGPIOx = 3.45 V
pull-up enabled
pull-down enabled
1
150
150
µA
100
100
20
kΩ
kΩ
ns
GPIO_RPD
50
GPIO_DG
GPIO0-9 (Outputs)
GPIO_VOH
GPIOx output high voltage
GPIOx output low voltage
VLDO_3V3 = 3.3V, IGPIOx= -2mA
VLDO_3V3 = 3.3V, IGPIOx=2mA
2.9
V
V
GPIO_VOL
0.4
1
ADCIN1, ADCIN2
ADCIN_ILKG
ADCINx leakage current
µA
ms
V
ADCINx ≤VLDO_3V3
–1
time from LDO_3V3 going high
until ADCINx is read for
configuration
tBOOT
10
6.17 I2C Requirements and Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C_EC_IRQ , I2C2s_IRQ
OD_VOL_IRQ
OD_LKG_IRQ
I2C3m_IRQ
IRQ_VIH
Low level output voltage
Leakage Current
IOL = 2 mA
0.4
1
V
Output is Hi-Z, VI2Cx_IRQ = 3.45 V
µA
–1
High-Level input voltage
VLDO_3V3 = 3.3V
1.3
V
V
IRQ_VIH_THRESH
IRQ_VIL
High-Level input voltage threshold VLDO_3V3 = 3.3V
0.72
1.3
0.54
1.08
low-level input voltage
low-level input voltage threshold
input hysteresis voltage
input deglitch
VLDO_3V3 = 3.3V
VLDO_3V3 = 3.3V
VLDO_3V3 = 3.3V
V
IRQ_VIL_THRESH
IRQ_HYS
0.54
0.09
V
V
IRQ_DEG
20
ns
µA
IRQ_ILKG
I2C3m_IRQ leakage current
VI2C3m_IRQ = 3.45 V
1
–1
SDA and SCL Common Characteristics (Master, Slave)
VIL
Input low signal
VLDO_3V3=3.3V,
0.54
V
V
VIH
Input high signal
VLDO_3V3=3.3V,
1.3
VHYS
VOL
ILEAK
IOL
Input hysteresis
VLDO_3V3=3.3V
0.165
V
Output low voltage
Input leakage current
Max output low current
Max output low current
IOL=3 mA
0.36
3
V
Voltage on pin = VLDO_3V3
VOL=0.4 V
µA
mA
mA
ns
ns
ns
pF
–3
15
20
12
12
IOL
VOL=0.6 V
80
150
50
VDD = 1.8V, 10 pF ≤Cb ≤400 pF
VDD = 3.3V, 10 pF ≤Cb ≤400 pF
tf
Fall time from 0.7*VDD to 0.3*VDD
tSP
CI
I2C pulse width surpressed
pin capacitance (internal)
10
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6.17 I2C Requirements and Characteristics (continued)
Operating under these conditions unless otherwise noted: 3.0 V ≤VVIN_3V3 ≤3.6 V (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
pF
Capacitive load for each bus line
(external)
Cb
400
tHD;DAT
Serial data hold time
VDD = 1.8V or 3.3V
0
ns
SDA and SCL Standard Mode Characteristics (Slave)
fSCLS
Clock frequency
Valid data time
VDD = 1.8V or 3.3V
100
kHz
µs
Transmitting Data, VDD = 1.8V or
3.3V, SCL low to SDA output valid
tVD;DAT
3.45
Transmitting Data, VDD = 1.8V or
3.3V, ACK signal from SCL low to
SDA (out) low
tVD;ACK
Valid data time of ACK condition
3.45
µs
SDA and SCL Fast Mode Characteristics (Slave)
fSCLS
Clock frequency
Valid data time
VDD = 1.8V or 3.3V
100
400
0.9
kHz
µs
Transmitting data, VDD = 1.8V,
SCL low to SDA output valid
tVD;DAT
Transmitting data, VDD = 1.8V or
3.3V, ACK signal from SCL low to
SDA (out) low
tVD;ACK
Valid data time of ACK condition
0.9
µs
SDA and SCL Fast Mode Plus Characteristics (Slave)
VDD = 1.8V or 3.3V, master
controls SCL frequency such that:
tLOW > tVD;ACK + tSU;DAT, TJ ≤
65oC
(1)
fSCLS
Clock frequency
400
1000
kHz
Transmitting data, VDD = 1.8V or
3.3V, SCL low to SDA output valid,
TJ ≤65 oC
tVD;DAT
Valid data time
0.55
0.55
µs
µs
Transmitting data, VDD = 1.8V or
3.3V, ACK signal from SCL low to
SDA (out) low, TJ ≤65 oC
tVD;ACK
Valid data time of ACK condition
SDA and SCL Fast Mode Characteristics (Master)
VDD = 3.3V(4)
VDD = 1.8V
400
390
410
400
fSCLM
Clock frequency for master(3)
kHz
µs
Start or repeated start
condition hold time
tHD;STA
VDD = 3.3V
0.6
tLOW
tHIGH
Clock low time
Clock high time
VDD = 3.3V
VDD = 3.3V
1.3
0.6
µs
µs
Start or repeated start
condition setup time
tSU;STA
VDD = 3.3V
0.6
µs
tSU;DAT
tSU;STO
Serial data setup time
Transmitting data, VDD = 3.3V
VDD = 3.3V
100
0.6
ns
µs
Stop condition setup time
Bus free time between stop and
start
tBUF
VDD = 3.3V
1.3
µs
µs
Transmitting data, VDD = 3.3V,
SCL low to SDA output valid
tVD;DAT
Valid data time
0.9
0.9
Transmitting data, VDD = 3.3V,
ACK signal from SCL low to SDA
(out) low
tVD;ACK
Valid data time of ACK condition
µs
(1) Fast Mode Plus is only recommended during boot when the device is in PTCH mode.
(2) The master or slave connected to the device follows I2C specifications.
(3) Actual frequency is dependent upon bus capacitance and pull-up resistance.
(4) Measured at 400kHz with Rp=1kΩ and Cb=145pF
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6.18 Typical Characteristics
50
47.5
45
0.575
0.55
0.525
0.5
42.5
40
0.475
0.45
37.5
35
0.425
0.4
32.5
30
0.375
0.35
0.325
27.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (oC)
TJ (oC)
TypG
TypG
图6-2. PP_CABLEx Rdson vs. Temperature
图6-1. PP_5Vx Rdson vs. Temperature
5.9
5.82
5.815
5.81
5.85
5.8
VPx_VBUS = 4V
VPx_VBUS = 22V
5.75
5.7
5.805
5.8
5.65
5.6
5.55
5.5
5.795
5.79
5.45
5.4
5.785
5.78
5.35
5.3
5.775
5.25
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (oC)
TJ (oC)
TypG
TypG
图6-4. VOVP4RCP (Setting 2) vs. Temperature
图6-3. VRCP vs. Temperature
9
8.8
8.6
8.4
8.2
8
11
10.5
10
Px_GATE_VBUS
Px_GATE_VSYS
Px_GATE_VSYS: VVSYS=0V
Px_GATE_VSYS: VVSYS=22V
Px_GATE_VBUS: 4V < VVBUS < 22V
9.5
9
7.8
7.6
7.4
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (oC)
TJ (oC)
TypG
TypG
图6-6. IPx_GATE_ON vs. Temperature
图6-5. VPx_GATE_ON vs. Temperature
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7 Parameter Measurement Information
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
cont.
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
图7-1. I2C Slave Interface Timing
ILIM5V, ILIMVC
tiOS_PP_5V, tiOS_PP_CABLE
图7-2. Short-Circuit Response Time for Internal Power Paths PP_5Vx and PP_CABLEx
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8 Detailed Description
8.1 Overview
The TPS65994AD is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug
and orientation detection for two USB Type-C and PD receptacles. The TPS65994AD communicates with the
cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power
switch for sourcing, controls a high current port power switch for sinking and negotiates alternate modes for each
port. The TPS65994AD may also control an attached super-speed multiplexer to simultaneously support USB
data and DisplayPort video.
Each Type-C port controlled by the TPS65994AD is functionally identical and supports the full range of the USB
Type-C and PD standards.
The TPS65994AD is divided into several main sections: the USB-PD controller, the cable plug and orientation
detection circuitry, the port power switches, the power management circuitry and the digital core.
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the Px_CC1 pin or the Px_CC2 pin, depending on the orientation of the reversible
USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, see the USB-PD Physical Layer section.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and
orientation detection, a description of its features and more detailed circuitry, see the Cable Plug and Orientation
Detection.
The port power switches provide power to the Px_VBUS pin and also to the Px_CC1 or Px_CC2 pins based on
the detected plug orientation. For a high-level block diagram of the port power switches, a description of its
features and more detailed circuitry, see the Power Paths.
The power management circuitry receives and provides power to the TPS65994AD internal circuitry and to the
LDO_3V3 output. See the Power Management section for more information.
The digital core provides the engine for receiving, processing and sending all USB-PD packets as well as
handling control of all other TPS65994AD functionality. A portion of the digital core contains ROM memory which
contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the
ROM, called boot code, is capable of initializing the TPS65994AD, loading of device configuration information
and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the
digital core, a description of its features and more detailed circuitry, see the Digital Core section.
The digital core of the TPS65994AD also interprets and uses information provided by the analog-to-digital
converter ADC (see the ADC), is configurable to read the status of general purpose inputs and trigger events
accordingly, and controls general outputs which are configurable as push-pull or open-drain types with integrated
pull-up or pull-down resistors. The TPS65994AD has two I2C slave ports to be controlled by host processors ,
and one I2C master to write to and read from external slave devices such as multiplexor, retimer, or an optional
external EEPROM memory (see the I2C Interface).
The TPS65994AD also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by
the integrated oscillator.
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8.2 Functional Block Diagram
PB_VBUS
PA_VBUS
3A
3A
PP5V
LDO_3V3
LDO_1V5
VSYS
Power Supervisor
VIN_3V3
GND
PB_CC1
ADCIN1
ADCIN2
Cable Detect, Cable Power, & USB PD PHY
PB_CC2
I2C_EC_SDA/SCL/IRQ
I2C2s_SDA/SCL/IRQ
I2C3m_SDA/SCL/IRQ
GPIO0-9
3
3
Core & Other Digital
PA_CC1
PA_CC2
3
10
Cable Detect, Cable Power, & USB PD PHY
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8.3 Feature Description
8.3.1 USB-PD Physical Layer
图 8-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block. This block is duplicated for the second TPS65994AD port.
Fast
current
limit
IVCON
PP5V
Px_CC1 Gate Control and
Current Limit
LDO_3V3
IRp
+
œ
RSNK
Px_CC1
Digital
Core
USB-PD PHY
(Rx/Tx)
Px_CC2
LDO_3V3
IRp
RSNK
Px_CC1 Gate Control and
Current Limit
Fast
current
limit
图8-1. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry
USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (Px_CC1 or Px_CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism.
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8.3.1.1 USB-PD Encoding and Signaling
图 8-2 illustrates the high-level block diagram of the baseband USB-PD transmitter. 图 8-3 illustrates the high-
level block diagram of the baseband USB-PD receiver.
4b5b
Encoder
BMC
Encoder
Data
to PD_TX
CRC
图8-2. USB-PD Baseband Transmitter Block Diagram
Data
BMC
Decoder
SOP
Detect
4b5b
Decoder
from PD_RX
CRC
图8-3. USB-PD Baseband Receiver Block Diagram
8.3.1.2 USB-PD Bi-Phase Marked Coding
The USB-PD physical layer implemented in the TPS65994AD is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). 图8-4 illustrates Biphase Mark Coding.
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
Data in
BMC
图8-4. Biphase Mark Coding Example
The USB PD baseband signal is driven onto the Px_CC1 or Px_CC2 pin with a tri-state driver. The tri-state driver
is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When
sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end
tolerates the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver
clocks the final bit of EOP.
8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal
edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning,
the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The
boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground
offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly,
the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time
masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge
rate that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits
on the rise and fall times. Refer to the USB-PD Specifications for more details.
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8.3.1.4 USB-PD BMC Transmitter
The TPS65994AD transmits and receives USB-PD data over one of the Px_CCy pins for a given CC pin pair
(one pair per USB Type-C port). The Px_CCy pins are also used to determine the cable orientation and maintain
the cable/device attach detection. Thus, a DC bias exists on the Px_CCy pins. The transmitter driver overdrives
the Px_CCy DC bias while transmitting, but returns to a Hi-Z state allowing the DC voltage to return to the
Px_CCy pin when not transmitting. While either Px_CC1 or Px_CC2 may be used for transmitting and receiving,
during a given connection only the one that mates with the CC pin of the plug is used; so there is no dynamic
switching between Px_CC1 and Px_CC2. 图8-5 shows the USB-PD BMC TX and RX driver block diagram.
LDO_3V3
Level Shifter
PD_TX
Driver
Px_CC1
Px_CC2
+
Level Shifter
PD_RX
œ
Digitally
Adjustable
VREF (VRXHI, VRXLO
)
USB-PD Modem
图8-5. USB-PD BMC TX/Rx Block Diagram
图 8-6 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere
between the minimum and maximum threshold for detecting a Sink attach. This means that the DC bias can be
above or below the VOH of the transmitter driver.
VOH
DC Bias
DC Bias
VOL
VOH
DC Bias
DC Bias
VOL
图8-6. TX Driver Transmission with DC Bias
The transmitter drives a digital signal onto the Px_CCy lines. The signal peak, VTXHI, is set to meet the TX
masks defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the
driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the
noise ingression in the cable.
图8-7 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is bounded.
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RDRIVER
ZDRIVER
Driver
CDRIVER
图8-7. ZDRIVER Circuit
8.3.1.5 USB-PD BMC Receiver
The receiver block of the TPS65994AD receives a signal that follows the allowed Rx masks defined in the USB
PD specification. The receive thresholds and hysteresis come from this mask.
图8-8 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has the typical
Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one system can
be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the
capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach detection.
Source
System
Sink
System
Pullup for
Attach
Detection
Connector
Connector
Cable
CC wire
Tx
Tx
CRECEIVER
CRECEIVER
Rx
Rx
CCablePlug_CC
CCablePlug_CC
RD for
Attach
Detection
Rx
Rx
Tx
Tx
SOP‘ PD
communication only
(eMarker #1)
SOP‘‘ PD
communication only
(eMarker #2)
图8-8. Example USB-PD Multi-Drop Configuration
8.3.1.6 Squelch Receiver
The TPS65994AD has a squelch receiver to monitor for the bus idle condition as defined by the USB PD
specification.
8.3.2 Power Management
The TPS65994AD power management block receives power and generates voltages to provide power to the
TPS65994AD internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 may also
be used as a low power output for external EEPROM memory. The power supply path is shown in 图8-9.
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PB_VBUS
RLDO_3V3
VIN_3V3
PA_VBUS
VREF
LDO
LDO_3V3
VREF
LDO_1V5
LDO
图8-9. Power Supplies
The TPS65994AD is powered from either VIN_3V3, PA_VBUS, or PB_VBUS. The normal power supply input is
VIN_3V3. When powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V
circuitry and I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core
digital circuitry. When VIN_3V3 power is unavailable and power is available on PA_VBUS, or PB_VBUS it is
referred to as the dead-battery startup condition. In a dead-battery startup condition, the TPS65994AD opens
the VIN_3V3 switch until the host clears the dead-battery flag via I2C. Therefore, the TPS65994AD is powered
from the VBUS input with the higher voltage during the dead-battery startup condition and until the dead-battery
flag is cleared. When powering from a VBUS input, the voltage on PA_VBUS, or PB_VBUS is stepped down
through an LDO to LDO_3V3.
8.3.2.1 Power-On And Supervisory Functions
A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present.
8.3.2.2 VBUS LDO
The TPS65994AD contains an internal high-voltage LDO which is capable of converting Px_VBUS to 3.3 V for
powering internal device circuitry. The VBUS LDO is only used when VIN_3V3 is low (the dead-battery
condition). The VBUS LDO is powered from either PA_VBUS, or PB_VBUS ; the one with the highest voltage.
8.3.3 Power Paths
The TPS65994AD has internal sourcing power paths: PP_5V1, PP_5V2, PP_CABLE1, and PP_CABLE2. It also
has control for external power paths: PP_EXT1, and PP_EXT2. Each power path is described in detail in this
section.
8.3.3.1 Internal Sourcing Power Paths
图 8-10 shows the TPS65994AD internal sourcing power paths. The TPS65994AD features four internal 5-V
sourcing power paths. The path from PP5V to PA_VBUS is called PP_5V1 , and the path from PP5V to
PB_VBUS is called PP_5V2. The path from PP5V to PA_CCx is called PP_CABLE1 , and the path from PP5V to
PB_CCy is called PP_CABLE2. Each path contains current clamping protection, overvoltage protection, UVLO
protection and temperature sensing circuitry. PP_5V1 and PP_5V2 may each conduct up to 3 A continuously,
while PP_CABLE1 and PP_CABLE2 may conduct up to 315 mA continuously. When disabled, the blocking FET
protects the PP5V rail from high-voltage that may appear on Px_VBUS.
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3A
Fast current clamp, ILIM5V
PA_VBUS
Temp
Sensor
PP_VBUS1 Gate Control and Sense
PP_5V1
PP_CABLE1
PA_CC1 Gate Control
TSD_PP5V
Fast current limit, IVCON
PA_CC1
PA_CC2 Gate Control
Temp
Sensor
PP5V
PA_CC2
3A
Fast current clamp, ILIM5V
PB_VBUS
Temp
Sensor
PP_VBUS2 Gate Control and Sense
PP_5V2
TSD_PP5V
PP_CABLE2
PB_CC1 Gate Control
Fast current limit, IVCON
PB_CC1
PB_CC2 Gate Control
Temp
Sensor
PB_CC2
图8-10. Port Power Switches
8.3.3.1.1 PP_5Vx Current Clamping
The current through the internal PP_5Vx paths are current limited to ILIM5V. The ILIM5V value is configured by
application firmware. When the current through the switch exceeds ILIM5V, the current limiting circuit activates
within tiOS_PP_5V and the path behaves as a constant current source. If the duration of the overcurrent event
exceeds tILIM, the PP_5V switch is disabled.
8.3.3.1.2 PP_5Vx Local Overtemperature Shut Down (OTSD)
When PP_5Vx clamps the current, the temperature of the switch will begin to increase. When the local
temperature sensors of PP_5Vx or PP_CABLEx detect that TJ>TSD_PP5V the PP_5Vx switch is disabled and the
affected port enters the USB Type-C ErrorRecovery state.
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8.3.3.1.3 PP_5Vx Current Sense
The current from PP5V to Px_VBUS is sensed through the switch and passed to the internal ADC.
8.3.3.1.4 PP_5Vx OVP
The overvoltage protection level is automatically configured based on the expected maximum VBUS voltage,
which depends upon the USB PD contract. When the voltage on a port's Px_VBUS pin exceeds the configured
value (VOVP4RCP) while PP_5Vx is enabled, then PP_5Vx is disabled within tPP_5V_ovp and the affected port
enters into the Type-C ErrorRecovery state.
8.3.3.1.5 PP_5Vx UVLO
If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO) while PP_5Vx is enabled,
then PP_5Vx is disabled within tPP_5V_uvlo and the port that had PP_5Vx enabled enters into the Type-C
ErrorRecovery state.
8.3.3.1.6 PP_5Vx Reverse Current Protection
If VPx_VBUS - VPP5V > VPP_5V_RCP, then the PP_5Vx path is automatically disabled within tPP_5V_rcp. If the RCP
condition clears, then the PP_5Vx path is automatically enabled within tON
.
8.3.3.1.7 Fast Role Swap
The TPS65994AD supports Fast Role Swap as defined by USB PD. The PP_5Vx path has a fast turn-on mode
that application firmware selectively enables to support Fast Role Swap. When enabled it is engaged when
VPx_VBUS - VPP5V<VPP_5V_RCP, and turns on the switch within tFRS_on
.
8.3.3.1.8 PP_CABLE Current Clamp
When enabled and providing VCONN power the TPS65994AD PP_CABLE power switches clamp the current to
IVCON. When the current through the PP_CABLEx switch exceeds IVCON, the current clamping circuit activates
within tiOS_PP_CABLE and the switch behaves as a constant current source. The switches do not have reverse
current blocking when the switch is enabled and current is flowing to either Px_CC1 or Px_CC2.
8.3.3.1.9 PP_CABLE Local Overtemperature Shut Down (OTSD)
When PP_CABLEx clamps the current, the temperature of the switch will begin to increase. When the local
temperature sensors of PP_5Vx or PP_CABLEx detect that TJ>TSD_PP5V the PP_CABLEx switch is disabled and
latched off within tPP_CABLE_off. The port then enters the USB Type-C ErrorRecovery state.
8.3.3.1.10 PP_CABLE UVLO
If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO), then both PP_CABLE1 and
PP_CABLE2 switches are automatically disabled within tPP_CABLE_off
.
8.3.3.2 Sink Path Control
The sink-path control includes overvoltage protection (OVP), and reverse current protection (RCP).
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3A
PP_EXT1
PP_EXT2
3A
PP_EXT2 Gate Control and
Sense
PP_EXT1 Gate Control and Sense
图8-11. Sink Path Control
The following figure shows the Px_GATE_VSYS gate driver in more detail.
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switch enabled when
gate driver is disabled and
VVIN_3V3 < VVIN_3V3_UVLO
VPx_GATE_ON
RPx_GATE_FSD
Regular enable/
disable
Fast
disable
IPx_GATE_OFF
IPx_GATE_ON
Charge
Pump
Px_VBUS
RPx_GATE_OFF_UVLO
图8-12. Details of the Px_GATE_VSYS gate driver.
8.3.3.2.1 Overvoltage Protection (OVP)
The application firmware enables the OVP and configures it based on the expected Px_VBUS voltage. If the
voltage on Px_VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then Px_GATE_VSYS is
automatically disabled within tPx_GATE_VSYS_FSD to protect the system. If the voltage on Px_VBUS surpasses the
configured threshold VOVP4RCP then Px_GATE_VBUS is automatically disabled within tPx_GATE_VBUS_OVP. When
VPx_VBUS falls below VOVP4RCP - VOVP4RCPHPx_GATE_VBUS is automatically re-enabled within
tPx_GATE_VBUS_ON since the OVP condition has cleared. This allows two sinking power paths to be enabled
simultaneously and Px_GATE_VBUS will be disabled when necessary to ensure that VPx_VBUS remains below
VOVP4RCP
.
While the TPS65994AD is in the BOOT mode in a dead-battery scenario (that is VIN_3V3 is low) it handles an
OVP condition slightly differently. As long as the OVP condition is present Px_GATE_VBUS and
Px_GATE_VSYS are disabled. Once the OVP condition clears, both Px_GATE_VBUS and Px_GATE_VSYS are
re-enabled (unless ADCINx are configured in SafeMode). Since this is a dead-battery condition, the
TPS65994AD will be drawing approximately IVIN_3V3,ActSnk from PA_VBUS or PB_VBUS during this time to help
discharge it.
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Power Path Supervisor
VOVP4RCP
VOVP4VSYS = VOVP4RCP / rOVP
图8-13. Diagram for OVP Comparators
8.3.3.2.2 Reverse-Current Protection (RCP)
The VSYS gate control circuit monitors the VSYS and Px_VBUS voltages and detects reverse current when the
VVSYS surpasses VPx_VBUS by more than VRCP. When the reverse current condition is detected,
Px_GATE_VBUS is disabled within tPx_GATE_VBUS_RCP. When the reverse current condition is cleared,
Px_GATE_VBUS is re-enabled within tPx_GATE_VBUS_ON. This limits the amount of reverse current that may flow
from VSYS to Px_VBUS through the external N-ch MOSFETs.
In reverse current protection mode, the power switch controlled by Px_GATE_VBUS is allowed to behave
resistively until the current reaches VRCP/ RON and then blocks reverse current from VSYS to Px_VBUS , where
RON is the resistance of the external back-to-back N-ch MOSFET. 图8-14 shows the behavior of the switch.
I
1/RON
-VRCP
V=VPx_VBUS - VVSYS
VRCP/RON
图8-14. Switch I-V Curve for RCP on External Switches
8.3.3.2.3 VBUS UVLO
The TPS65994AD monitors Px_VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO
condition is detected, Px_GATE_VBUS is disabled within tPx_GATE_VBUS_RCP. When the UVLO condition is
cleared, Px_GATE_VBUS is re-enabled within tPx_GATE_VBUS_ON
.
8.3.3.2.4 Discharging VBUS to Safe Voltage
The TPS65994AD has an integrated active pull-down (IDSCH) on Px_VBUS for discharging from high voltage to
VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.
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8.3.4 Cable Plug and Orientation Detection
图 8-15 shows the plug and orientation detection block at each Px_CCy pin (PA_CC1, PA_CC2, PB_CC1,
PB_CC2). Each pin has identical detection circuitry.
IRpDef
IRp1.5
IRp3.0
VREF1
VREF2
VREF3
Px_CCy
RSNK
图8-15. Plug and Orientation Detection Block
8.3.4.1 Configured as a Source
When configured as a source, the TPS65994AD detects when a cable or a Sink is attached using the Px_CC1
and Px_CC2 pins. When in a disconnected state, the TPS65994AD monitors the voltages on these pins to
determine what, if anything, is connected. See USB Type-C Specification for more information.
表8-1 shows the Cable Detect States for a Source.
表8-1. Cable Detect States for a Source
Px_CC1 Px_CC2
CONNECTION STATE
Open Nothing attached
Open Sink attached
RESULTING ACTION
Continue monitoring both Px_CCy pins for attach. Power is not applied to Px_VBUS
or VCONN.
Open
Rd
Monitor Px_CC1 for detach. Power is applied to Px_VBUS but not to VCONN
(Px_CC2).
Monitor Px_CC2 for detach. Power is applied to Px_VBUS but not to VCONN
(Px_CC1).
Open
Ra
Rd
Open
Ra
Sink attached
Powered Cable-No UFP
attached
Monitor Px_CC2 for a Sink attach and Px_CC1 for cable detach. Power is not
applied to Px_VBUS or VCONN (Px_CC1).
Powered Cable-No UFP
attached
Monitor Px_CC1 for a Sink attach and Px_CC2 for cable detach. Power is not
applied to Px_VBUS or VCONN (Px_CC1).
Open
Ra
Provide power on Px_VBUS and VCONN (Px_CC1) then monitor Px_CC2 for a Sink
detach. Px_CC1 is not monitored for a detach.
Rd
Powered Cable-UFP Attached
Powered Cable-UFP attached
Provide power on Px_VBUS and VCONN (Px_CC2) then monitor Px_CC1 for a Sink
detach. Px_CC2 is not monitored for a detach.
Rd
Ra
Debug Accessory Mode
attached
Rd
Rd
Sense either Px_CCy pin for detach.
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表8-1. Cable Detect States for a Source (continued)
Px_CC1 Px_CC2
CONNECTION STATE
RESULTING ACTION
Audio Adapter Accessory
Mode attached
Ra
Ra
Sense either Px_CCy pin for detach.
When a TPS65994AD port is configured as a Source, a current IRpDef is driven out each Px_CCy pin and each
pin is monitored for different states. When a Sink is attached to the pin a pull-down resistance of Rd to GND
exists. The current IRpDef is then forced across the resistance Rd generating a voltage at the Px_CCy pin. The
TPS65994AD applies IRpDef until it closes the switch from PP5V to Px_VBUS, at which time application firmware
may change to IRp1.5A or IRp3.0A
.
When the Px_CCy pin is connected to an active cable VCONN input, the pull-down resistance is different (Ra).
In this case the voltage on the Px_CCy pin will be lower and the TPS65994AD recognizes it as an active cable.
The voltage on Px_CCy is monitored to detect a disconnection depending upon which Rp current source is
active. When a connection has been recognized and the voltage on Px_CCy subsequently rises above the
disconnect threshold for tCC, the system registers a disconnection.
8.3.4.2 Configured as a Sink
When a TPS65994AD port is configured as a Sink, the TPS65994AD presents a pull-down resistance RSNK on
each Px_CCy pin and waits for a Source to attach and pull-up the voltage on the pin. The Sink detects an
attachment by the presence of VBUS. The Sink determines the advertised current from the Source based on the
voltage on the Px_CCy pin.
8.3.4.3 Configured as a DRP
When a TPS65994AD port is configured as a DRP, the TPS65994AD alternates the port's Px_CCy pins between
the pull-down resistance, RSNK, and pull-up current source, IRp.
8.3.4.4 Fast Role Swap Signal Detection
The TPS65994AD cable plug block contains additional circuitry that may be used to support the Fast Role Swap
(FRS) behavior defined in the USB Power Delivery Specification. The circuitry provided for this functionality is
detailed in 图8-16.
Px_CC1
To Cable Detect and
Orientation
Px_CC2
To Digital Core
VFRS
图8-16. Fast Role Swap Detection and Signaling
When a TPS65994AD port is operating as a sink with FRS enabled, the TPS65994AD monitors the CC pin
voltage. If the CC voltage falls below VFRS for tFRS_DET a fast role swap signal is detected and indicated to the
digital core. When this signal is detected the TPS65994AD ceases operating as a sink (disables
Px_GATE_VSYS and Px_GATE_VBUS) and begins operating as a source.
8.3.4.5 Dead Battery Advertisement
The TPS65994AD supports booting from no-battery or dead-battery conditions by receiving power from
Px_VBUS. Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source provides
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a voltage on VBUS. TPS65994AD hardware is configured to present this Rd during a dead-battery or no-battery
condition. Additional circuitry provides a mechanism to turn off this Rd once the device no longer requires power
from VBUS.
8.3.5 Default Behavior Configuration (ADCIN1, ADCIN2)
Note
This functionality is firmware controlled and subject to change.
The ADCINx inputs to the internal ADC control the behavior of the TPS65994AD in response to PA_VBUS or
PB_VBUS being supplied when VIN_3V3 is low (that is the dead-battery scenario). The ADCINx pins must be
externally tied to the LDO_3V3 pin via a resistive divider as shown in the following figure. At power-up the ADC
converts the ADCINx voltage and the digital core uses these two values to determine start-up behavior. The
available start-up configurations include options for I2C slave address of I2C_EC_SCL/SDA, sink path control in
dead-battery, and default configuration.
LDO_3V3
Mux and
ADC
Dividers
ADCINx
图8-17. ADCINx Resistor Divider
The device behavior is determined in several ways depending upon the decoded value of the ADCIN1 and
ADCIN2 pins. The following table shows the decoded values for different resistor divider ratios. See Pin
Strapping to Configure Default Behavior for details on how the ADCINx configurations determine default device
behavior. See I2C Address Setting for details on how ADCINx decoded values affects default I2C slave address.
表8-2. Decoding of ADCIN1 and ADCIN2 Pins
(1)
DIV = RDOWN / (RUP + RDOWN
)
Without using RUP
or RDOWN
ADCINx decoded value
MIN
0
Target
0.0114
0.0475
0.1074
0.1899
0.3022
0.5368
0.8062
MAX
0.0228
0.0722
0.1425
0.2372
0.3671
0.7064
0.9060
tie to GND
0
1
2
3
4
5
6
0.0229
0.0723
0.1425
0.2373
0.3672
0.7065
N/A
N/A
N/A
N/A
tie to LDO_1V5
N/A
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表8-2. Decoding of ADCIN1 and ADCIN2 Pins (continued)
(1)
DIV = RDOWN / (RUP + RDOWN
)
Without using RUP
or RDOWN
ADCINx decoded value
MIN
Target
MAX
0.9061
0.9530
1.0
tie to LDO_3V3
7
(1) External resistor tolerance of 1% is recommended. Resistor values must be chosen to yield a DIV value centered nominally between
listed MIN and MAX values. For convenience, the Target column shows this value.
8.3.6 ADC
The TPS65994AD ADC is shown in 图 8-18. The ADC is an 8-bit successive approximation ADC. The input to
the ADC is an analog input mux that supports multiple inputs from various voltages and currents in the device.
The output from the ADC is available to be read and used by application firmware.
Voltage
Px_VBUS
Divider 2
Voltage
Divider 1
LDO_3V3
8 bits
Input
Mux
ADC
GPIO4
Buffers &
Voltage
Divider 1
ADCIN1
ADCIN2
GPIO5
I_Px_VBUS
I-to-V
图8-18. SAR ADC
8.3.7 DisplayPort Hot-Plug Detect (HPD)
The TPS65994AD supports the DisplayPort alternate mode as a DP source . It is recommended to use the
virtual HPD functionality through I2C. However, the TPS65994AD also supports the HPD converter functions on
GPIO pins (See 表8-3). The core will translate PD messaging events onto the HPD pin.
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VBUS
PD Controller
(PD to HPD converter)
CC1
CC2
DisplayPort
Transmitter System
Type-C Connector
HPD
detector
GPIO1 / HPD_Tx
GND
VBUS
PD Controller
(HPD to PD converter)
CC1
CC2
DisplayPort
Receiver System
Type-C Connector
HPD
driver
HPD_Rx
GND
图8-19. Illustration of how a PD-to-HPD Converter Passes the HPD Signal Along in a DisplayPort System
8.3.8 Digital Interfaces
The TPS65994AD contains several different digital interfaces which may be used for communicating with other
devices. The available interfaces include two I2C Slaves and one I2C Master, and additional GPIOs.
8.3.8.1 General GPIO
GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control other ICs,
interrupt a host processor, or receive input from another IC. This buffer is configurable to be a push-pull output, a
weak push-pull, or open drain output. When configured as an input, the signal can be a de-glitched digital input
or an analog input to the ADC (only a subset of the GPIO's are ADC inputs see table below). The push-pull
output is a simple CMOS output with independent pull-down control allowing open-drain connections. The weak
push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain. The supply voltage to
the output buffer is LDO_3V3 and LDO_1V5 to the input buffer. When interfacing with non 3.3-V I/O devices the
output buffer may be configured as an open drain output and an external pull-up resistor attached to the GPIO
pin. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or
disabled via application code in the digital core.
表8-3. GPIO Functionality Table
Pin Name
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Special Functionality
HPD_Tx for Port B
HPD_Tx for Port A
ADC Input,
ADC Input,
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表8-3. GPIO Functionality Table (continued)
Pin Name
Type
Special Functionality
GPIO9
O
O
O
I
PROCHOT#
I2C_EC_IRQ(GPIO10)
I2C2s_IRQ(GPIO11)
I2C3m_IRQ(GPIO12)
IRQ for I2C_EC, or used as a general-purpose output
IRQ for I2C2, or used as a general-purpose output
IRQ for I2C3, or used as a general-purpose input
8.3.8.2 I2C Interface
The TPS65994AD features three I2C interfaces that each use an I2C I/O driver like the one shown in 图 8-20.
This I/O consists of an open-drain output and in input comparator with de-glitching.
50ns
I2C_DI
Deglitch
I2C_SDA/SCL
I2C_DO
图8-20. I2C Buffer
8.3.9 Digital Core
图8-21 shows a simplified block diagram of the digital core.
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GPIO0-9
I2C_EC_SDA
I2C
Port 1
(slave)
I2C to
System Control
I2C_EC_SCL
I2C_EC_IRQ
I2C2s_SDA
I2C
Port 2
(slave)
I2C to
Thunderbolt Controller
I2C2s_SCL
Digital Core
CBL_DET
Bias CTL
and USB-PD
I2C2s_IRQ
USB PD Phy
I2C3m_SDA
I2C to
Thunderbolt Retimer
I2C3m_SCL
I2C
Port 3
(master)
I2C3m_IRQ
OSC
ADC Read
Temp
Sense
Thermal
Shutdown
ADC
图8-21. Digital Core Block Diagram
8.3.10 I2C Interface
The TPS65994AD has two I2C slave interface ports: I2C_EC and I2C2s. I2C port I2C_EC is comprised of the
I2C_EC_SDA, I2C_EC_SCL, and I2C_EC_IRQ pins. I2C I2C2s is comprised of the I2C2s_SDA, I2C2s_SCL,
and I2C2s_IRQ pins. These interfaces provide general status information about the TPS65994AD, as well as the
ability to control the TPS65994AD behavior, supporting communications to/from a connected device and/or
cable supporting BMC USB-PD, and providing information about connections detected at the USB-C receptacle.
When the TPS65994AD is in 'APP ' mode it is recommended to use Standard Mode or Fast Mode (that is a clock
speed no higher than 400 kHz). However, in the 'BOOT' mode when a patch bundle is loaded Fast Mode Plus
may be used (see fSCLS).
The TPS65994AD has one I2C master interface port: I2C3m. I2C3m is comprised of the I2C3m_SDA,
I2C3m_SCL, and I2C3m_IRQ1 pins. This interface can be used to read from or write to external slave devices.
During boot the TPS65994AD attempts to read patch and Application Configuration data from an external
EEPROM with a 7-bit slave address of 0x50. The EEPROM should be at least kilo-bytes.
表8-4. I2C Summary
I2C Bus
I2C_EC
I2C2s
Type
Slave
Slave
Typical Usage
Connect to an Embedded Controller (EC). Used to load the patch and application configuration.
Connect to a TBT controller or second master.
Connect to a TBT retimer, USB Type-C mux, I2C EEPROM, or other slave. Use the LDO_3V3 pin as
the pull-up voltage. Multi-master configuration is not supported.
I2C3m
Master
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8.3.10.1 I2C Interface Description
The TPS65994AD supports Standard and Fast mode I2C interfaces. The bidirectional I2C bus consists of the
serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up
resistor. Data transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input is
high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit
(MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/
output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during
each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as
changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
图 8-22 shows the start and stop conditions of the transfer. 图 8-23 shows the SDA and SCL signals for
transferring a bit. 图8-24 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
SDA
SCL
S
P
Start Condition
Stop Condition
图8-22. I2C Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
图8-23. I2C Bit Transfer
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Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
图8-24. I2C Acknowledgment
8.3.10.2 I2C Clock Stretching
The TPS65994AD features clock stretching for the I2C protocol. The TPS65994AD slave I2C port may hold the
clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data.
The master communicating with the slave must not finish the transmission of the current bit and must wait until
the clock line actually goes high. When the slave is clock stretching, the clock line remains low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
8.3.10.3 I2C Address Setting
The host should only use I2C_EC_SCL/SDA for loading a patch bundle. Once the boot process is complete,
each port has a unique slave address on the I2C_EC_SCL/SDA bus as selected by the ADCINx pins. The slave
address used by each port on the I2C2s bus are determined from the application configuration. The Port A slave
address should be used for pushing the patch bundle since the Port B slave address is not available during the
BOOT mode.
表8-5. I2C Default Slave Address for I2C_EC_SCL/SDA.
I2C address index
(decoded from ADCIN1
and ADCIN2)(1)
Slave Address
Available During
BOOT
Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
#1
#1
#2
#2
#3
#3
#4
#4
A
B
A
B
A
B
A
B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
No
Yes
No
Yes
No
Yes
No
(1) See 表8-2 details about ADCIN1 and ADCIN2 decoding.
8.3.10.4 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65994AD.
The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. 图 8-25 and 图
8-26 show the write and read protocol for the I2C slave interface, and a key is included in 图 8-27 to explain the
terminology used. The TPS65994AD Host interface utilizes a different unique address to identify each of the two
USB Type-C ports controlled by the TPS65994AD. The key to the protocol diagrams is in the SMBus
Specification and is repeated here in part.
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1
7
1
1
8
1
8
1
8
1
S
Unique Address
Wr
A
Register Number
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
Data Byte 2
A
Data Byte N
A
P
图8-25. I2C Unique Address Write Register Protocol
1
S
7
1
1
8
1
1
7
1
1
8
1
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
1
P
图8-26. I2C Unique Address Read Register Protocol
1
7
1
1
A
x
8
1
A
x
1
S
Slave Address
Wr
Data Byte
P
S
Start Condition
SR
Rd
Wr
x
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Field is required to have the value x
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
A
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
图8-27. I2C Read/Write Protocol Key
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8.4 Device Functional Modes
8.4.1 Pin Strapping to Configure Default Behavior
During the boot procedure, the device will read the ADCINx pins and set the configurations based on the table
below. Then it will attempt to load a configuration from an external EEPROM on the I2C3m bus. If no EEPROM
is detected, then the device will wait for an EC to load a configuration.
When an external EEPROM is used, each device is connected to a unique EEPROM, it cannot be shared for
multiple devices. The external EEPROM shall be at 7-bit slave address 0x50.
表8-6. Device Configuration using ADCIN1 and ADCIN2
ADCIN1 decoded
value (2)
ADCIN2 decoded
value (2)
I2C address Index (1)
Dead Battery Configuration
7
5
2
1
7
4
3
2
7
6
6
6
7
3
4
3
5
5
0
7
4
4
0
7
6
6
5
7
3
3
0
7
#1
#2
#3
#4
#1
#2
#3
#4
#1
#2
#3
#4
#1
#2
#3
#4
AlwaysEnableSink: The device always enables the sink path
regardless of the amount of current the attached source is
offering. USB PD is disabled until configuration is loaded.
SinkRequires_3.0A: The device only enables the sink path if the
attached source is offering at least 3.0A. USB PD is disabled
until configuration is loaded.
SinkRequires_1.5A: The device only enables the sink path if the
attached source is offering at least 1.5A. USB PD is disabled
until configuration is loaded.
NegotiateHighVoltage: The device always enables the sink path
during the initial implicit contract regardless of the amount of
current the attached source is offering. The PD controller will
enter the 'APP ' mode, enable USB PD PHY and negotiate a
contract for the highest power contract that is offered up to 20 V.
This cannot be used when a patch is loaded from EEPROM.
7
0
6
5
0
0
0
7
#1
#2
#3
#4
SafeMode: The device does not enable the sink path. USB PD is
disabled until configuration is loaded. Note that the configuration
could put the device into a source-only mode. This is
recommended when the application loads the patch from
EEPROM.
(1) See 表8-5 to see the exact meaning of I2C Address Index.
(2) See 表8-2 for how to configure a given ADCINx decoded value.
8.4.2 Power States
The TPS65994AD may operate in one of three different power states: Active, Idle, or Sleep. The Modern
Standby mode is a special case of the Idle mode. The functionality available in each state is summarized in the
following table. The device will automatically transition between the three power states based on the circuits that
are active and required, see the following figure. In the Sleep State the TPS65994AD will detect a Type-C
connection. Transitioning between the Active mode to the Idle mode requires a period of time (T) without any of
the following activity:
• Incoming USB PD message.
• Change in CC status.
• GPIO input event.
• I2C transactions.
• Voltage alert.
• Fault alert.
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图8-28. Flow Diagram For Power States
表8-7. Power Consumption States
Modern
Standby
Modern
Active Source
Mode(1)
Active Sink
Mode(6)
Idle Source
Mode(2)
Idle Sink
Mode(7)
Standby Sink Sleep Mode(3)
Mode(5)
Source Mode(4)
PP_5V1
enabled
enabled
disabled
disabled
enabled
enabled
disabled
disabled
enabled
enabled
enabled
enabled
enabled
enabled
disabled
disabled
enabled
enabled
disabled
disabled
enabled
enabled
enabled
enabled
enabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
disabled
PP_5V2
PP_EXT 1
PP_EXT2
PP_CABLE1
PP_CABLE2
external
PA_CC1
termination
Rd
open
Rd
Rp 3.0A
open
Rd
open
Rd
Rp 3.0A
open
Rd
Rp 3.0A
open
open
open
open
open
external
PA_CC2
termination
open
open
open
external
PB_CC1
termination
Rp 3.0A
open
Rp 3.0A
open
open
external
PB_CC2
termination
open
open
open
(1) This mode is used for: IVIN_3V3,ActSrc
(2) This mode is used for: IVIN_3V3,IdlSrc
(3) This mode is used for: IVIN_3V3,Sleep
(4) This mode is used for: PMstbySrc
(5) This mode is used for: PMstbySnk
.
(6) This mode is used for: IVIN_3V3,ActSnk
(7) This mode is used for: IVIN_3V3,IdlSnk
8.4.3 Thermal Shutdown
The TPS65994AD features a central thermal shutdown as well as independent thermal sensors for each internal
power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions
except for supervisory circuitry when die temperature goes above a rising temperature of TSD_MAIN. The
temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value, the
device resumes normal operation.
The power path thermal shutdown monitors the temperature of each internal PP5V-to-VBUS power path and
disables both power paths and the VCONN power path when either exceeds TSD_PP5V. Once the temperature
falls by at least TSDH_PP5V the path can be configured to resume operation or remain disabled until re-enabled by
firmware.
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS65994AD firmware implements a host interface over I2C to allow for the configuration and control of all
device options. Initial device configuration is configured through a configuration bundle loaded on to the device
during boot.The bundle may be loaded through the I2C_EC port or it may be loaded over I2C3m from an
external EEPROM.The TPS65994AD configuration bundle and host interface allow the device to be customized
for each specific application. The configuration bundle can be generated through the Application Customization
Tool.
9.2 Typical Application
9.2.1 Type-C VBUS Design Considerations
USB Type-C and PD allows for voltages up to 20 V with currents up to 5 A. This introduces power levels that
could damage components touching or hanging off of VBUS. Under normal conditions, all high power PD
contracts should start at 5 V and then transition to a higher voltage. However, there are some devices that are
not compliant to the USB Type-C and Power Delivery standards and could have 20 V on VBUS. This could
cause a 20-V hot plug that can ring above 30 V. Adequate design considerations are recommended below for
these non-compliant devices.
9.2.1.1 Design Requirements
表 9-1 shows VBUS conditions that can be introduced to a USB Type-C and PD Sink. The system should be
able to handle these conditions to ensure that the system is protected from non-compliant and/or damaged USB
PD sources. A USB Sink should be able to protect from the following conditions being applied to its VBUS. The
Detailed Design Procedure section explains how to protect from these conditions.
表9-1. VBUS Conditions
CONDITION
VOLTAGE APPLIED
4 V - 21.5 V
Abnormal VBUS Hot Plug
VBUS Transient Spikes
4 V - 43 V
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Type-C Connector VBUS Capacitors
The first level of protection starts at the Type-C connector and the VBUS pin capacitors. These capacitors help
filter out high frequency noise but can also help absorb short voltage transients. Each VBUS pin should have a
10-nF capacitor rated at or above 25 V and placed as close to the pin as possible. The GND pin on the
capacitors should have very short path to GND on the connector. The derating factor of ceramic capacitors
should be taken into account as they can lose more than 50% of their effective capacitance when biased. Adding
the VBUS capacitors can help reduce voltage spikes by 2 V to 3 V.
9.2.1.2.2 VBUS Schottky and TVS Diodes
TVS Diodes help suppress and clamp transient voltages. Most TVS diodes can fully clamp around 10 ns and can
keep the VBUS at their clamping voltage for a period of time. Looking at the clamping voltage of TVS diodes
after they settle during a transient will help decide which TVS diode to use. The peak power rating of a TVS
diode must be able to handle the worst case conditions in the system.
To prevent the possibility of large ground currents into the TPS65994AD during sudden disconnects due to
inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to ground.
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The TVS2200 can serve to clamp the VBUS voltage and prevent large ground currents into the PD controller as
shown in 图9-1
PP5V
PA_VBUS
TVS2200
PP5V
PB_VBUS
TVS2200
GND
图9-1. TVS2200 for VBUS clamping and current surge protection
9.2.1.3 Application Curves
图9-2. VBUS Short to Ground (Zoomed In)
图9-3. VBUS Short to Ground (Zoomed Out)
9.2.2 Notebook Design Supporting PD Charging
The TPS65994AD works very well in dual port Notebooks that support PD charging. The internal power paths for
the TPS65994AD source System 5 V from PP5V to the respective VBUS pins. Additionally, the TPS65994AD
can control two external Common Drain N-FET power paths to sink power into the system. The TPS65994AD
offers full reverse-current protection on these external power paths through the N-FET gate driver. The System
5-V connected to the PP5V pin on the TPS65994AD also supplies power to VCONN of Type-C e-marked cables
and Type-C accessories. An embedded controller EC is used for additional control of the TPS65994AD and to
relay information back to the operating system. An embedded controller enables features such as entering and
exiting sleep modes, changing source and sink capabilities depending on the state of the battery, UCSI support,
control alternate modes and so forth.
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9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging
USB SSTX/RX
I2C
USB3.1 Source
SSTX/RX
SBU1/2
SS Mux Control
DP1.4 Source
TUSB1046
DP ML
USB2.0 Source
Port A Type C
Receptacle
SSTX/RX
SBU1/2
USB2.0
PA_HV_GATE
GPIO
PP5V
SS Mux Control*
System 5V
CC1/2
VBUS
PA_CC1/2
VIN
BAT
+
BQ Battery
Charger
VIN_3V3
PP5V
System 3.3V
TPS65994
Port B Type C
Receptacle
I2C
VBUS
CC1/2
PB_CC1/2
I2C3m
I2C_EC
SS Mux Control*
USB2.0
SBU1/2
SSTX/RX
EC
PB_HV_GATE
I2C MASTER
USB2.0 Source
DP ML
I2C
DP1.4 Source
SS Mux Control
USB3.1 Source
SBU1/2
TUSB1046
SSTX/RX
USB SSTX/RX
图9-4. USB and DisplayPort Notebook Supporting PD Charging
9.2.2.1.1 Design Requirements
表9-2 summarizes the Power Design parameters for an USB Type-C PD Notebook.
表9-2. Power Design Parameters
POWER DESIGN PARAMETERS
PP5V Input Voltage, Current
NFET PP_EXT Voltage, Current
VIN_3V3 Voltage, Current
VALUE
CURRENT PATH
5 V, 4 A
VBUS 1 & 2 Source & VCONN 1 & 2 Source
VBUS 1 & 2 Sink
5 V –20 V, 3 A (5-A Maximum)
3.3 V, 50 mA
Internal TPS65994AD Circuitry
9.2.2.1.2 Detailed Design Procedure
9.2.2.1.2.1 USB Power Delivery Source Capabilities
Most Type-C dongles (video and data) draw less than 900 mA and supplying 1.5 A on each Type-C port is
sufficient for a notebook supporting USB and DisplayPort. 表9-3 shows the PDO for the Type-C port.
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表9-3. Source PDOs
SOURCE PDO
PDO1
PDO TYPE
VOLTAGE
CURRENT
Fixed
5 V
1.5 A
9.2.2.1.2.2 USB Power Delivery Sink Capabilities
Most notebooks support buck and boost charging which allows them to charge the battery from 5 V to 20 V. USB
PD sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is
recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with
most PD chargers and adapters.
表9-4. Sink PDOs
SINK PDO
PDO1
PDO TYPE
Fixed
VOLTAGE
CURRENT
5 V
3 A
3 A
PDO2
Fixed
9 V
PDO3
Fixed
15 V
3 A
PDO4
Fixed
20 V
3 A (5 A Max)
9.2.2.1.2.3 USB and DisplayPort Supported Data Modes
表9-5 summarizes the data capabilities of the notebook supporting USB3 and DisplayPort.
表9-5. Data Capabilities
PROTOCOL
DATA
USB3.1 Gen2
DP1.4
DATA ROLE
USB Data
Host
DisplayPort
Host DFP_D (Pin Assignment C, D, and E)
9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control
The TUSB1046 requires GPIO control in GPIO control mode to determine whether if there is USB or DisplayPort
data connection. 表 9-6 summarizes the TPS65994AD GPIO Events and the control pins for the TUSB1046.
Note that the pin strapping on the TUSB1046 will set the GPIO control mode and the required equalizer settings.
For more details refer to the TUSB1046 datasheet.
表9-6. GPIO Events for Super Speed Mux
TPS65994AD GPIO EVENT
Cable_Orientation_Event_Port1
USB3_Event_Port1
TUSB1046 CONTROL
FLIP
CTL0
CTL1
DP_Mode_Selection_Event_Port1
9.2.2.2 Thunderbolt Notebook Supporting PD Charging
A Thunderbolt system is capable of sourcing USB, DisplayPort, and Thunderbolt data. There is an I2C
connection between the TPS65994AD and the Thunderbolt controller. The TPS65994AD will determine the
connection on the Type-C port and will generate an interrupt to the Thunderbolt controller to generate the
appropriate data output. An external mux for SBU may be needed to mux the LSTX/RX and AUX_P/N signal
from the Thunderbolt controller to the Type-C Connector. The TPD6S300 provides additional protection such as
short to VBUS on the CC and SBU pins and ESD for the USB2 DN/P. See 图 9-5 for a block diagram of the
system.
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PB_TX0/1/RX0/1
SBU Mux Control
PA_LSTX/RX
LSTX/RX
AUXP/N
SBU1/2
TS3DS10224
PA_DPSRC_AUX_P/N
USB2.0 Source
U1_TBT_I2C_SDA
U2_TBT_I2C_SCL
Thunderbolt
Controller I2C Master
Port A Type C
Receptacle
J4_TBTA_I2C_IRQZ
E2_TBTB_I2C_IRQZ
SSTX/RX
SBU1/2
GPIO
SBU Mux Control
System 5V
PA_HV_GATE
TBT RESETN
RESETN
USB2.0
TPD6S300
CC1/2
VBUS
PA_CC1/2
PP5V
VIN
BAT
+
BQ Battery
Charger
Thunderbolt Controller
(AR)
VIN_3V3
System 3.3V
TPS65994
Port B Type C
Receptacle
I2C
PP5V
VBUS
CC1/2
PB_CC1/2
Thunderbolt
Controller I2C Master
I2C2s
USB2.0
SBU1/2
SSTX/RX
TPD6S300
EC
I2C_EC
PB_HV_GATE
I2C MASTER
USB2.0 Source
AUXP/N
LSTX/RX
PB_DPSRC_AUX_P/N
PB_LSTX/RX
SBU1/2
TS3DS10224
SBU Mux Control
PB_TX0/1/RX0/1
图9-5. Thunderbolt Notebook Supporting PD Charging
9.2.2.2.1 Design Requirements
表9-7 summarizes the Power Design parameters for an USB Type-C PD Thunderbolt Notebook.
表9-7. Power Design Parameters
POWER DESIGN PARAMETERS
PP5V Input Voltage, Current
NFET PP_EXT Voltage, Current
VIN_3V3 Voltage, Current
VALUE
CURRENT PATH
VBUS 1 & 2 Source & VCONN 1 & 2 Source
VBUS 1 & 2 Sink
5 V, 7 A
5 V –20 V, 3 A (5-A Maximum)
3.3 V, 50 mA
Internal TPS65994AD Circuitry
9.2.2.2.2 Detailed Design Procedure
9.2.2.2.2.1 USB Power Delivery Source Capabilities
All Type-C Ports that support Thunderbolt must support sourcing 5 V at 3 A (15 W). See 表 9-8 for the PDO
information.
表9-8. Source PDOs
SOURCE PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5 V
3 A
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9.2.2.2.2.2 USB Power Delivery Sink Capabilities
Most notebooks support buck and boost charging which allows them to charge the battery from 5 V to 20 V. USB
PD sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is
recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with
most PD chargers and adapters.
表9-9. Sink PDOs
SINK PDO
PDO1
PDO TYPE
Fixed
VOLTAGE
CURRENT
5 V
3 A
PDO2
Fixed
9 V
3 A
3 A
PDO3
Fixed
15 V
PDO4
Fixed
20 V
3 A (5-A Maximum)
9.2.2.2.2.3 Thunderbolt Supported Data Modes
Thunderbolt Controllers are capable of generating USB3, DisplayPort and Thunderbolt Data. The Thunderbolt
controller is also capable of muxing the appropriate super speed signal to the Type-C connector. Thunderbolt
systems do not need a super speed mux for the Type-C connector. 表 9-10 summarizes the data capabilities of
each Type-C port supporting Thunderbolt.
表9-10. Data Capabilities
PROTOCOL
USB Data
DATA
USB3.1 Gen2
DP1.4
DATA ROLE
Host
DisplayPort
Thunderbolt
Host DFP_D (Pin Assignment C, D, and E)
Host/Device
PCIe/DP
9.2.2.2.2.4 I2C Design Requirements
The I2C connection from the TPS65994AD and the Thunderbolt control allows the Thunderbolt controller to read
the current data status from the TPS65994AD when there is a connection on either Type-C port. The
Thunderbolt controller has an interrupt assigned for the TPS65994AD and the Thunderbolt controller will read
the I2C address corresponding to the Type-C port. The I2C2s on the TPS65994AD is always connected to the
Thunderbolt controller.
9.2.2.2.2.5 TS3DS10224 SBU Mux for AUX and LSTX/RX
The SBU signals must be muxed from the Type-C connector to the Thunderbolt controller. The AUX for
DisplayPort and LSTX/RX for Thunderbolt are connected to the TS3DS10224 and then muxed to the SBU pins.
The SBU mux is controlled through GPIOs from the TPS65994AD. 表 9-11 shows the TPS65994AD GPIO
events and the control signals from the TS3DS10224.
表9-11. GPIO Events for SBU Mux
TPS65994AD GPIO EVENT
Cable_Orientation_Event_Port1
DP_Mode_Selection_Event_Port1
TBT_Mode_Selection_Event_Por1
N/A
TS3DS10224 CONTROL
SAO, SBO
ENA
ENB
SAI tied to VCC
SBI tied to GND
N/A
表9-12 shows the connections for the AUX, LSTXRX, and SBU pins for the TS3DS10224.
表9-12. TS3DS10224 Pin Connections
TS3DS10224 PIN
SIGNAL
INA+
INA-
SBU1
SBU2
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表9-12. TS3DS10224 Pin Connections (continued)
TS3DS10224 PIN
OUTB0+
OUTB0-
SIGNAL
LSTX
LSRX
OUTB1+
OUTB1-
LSRX
LSTX
OUTA0+
OUTA0-
AUX_P
AUX_N
AUX_N
AUX_P
OUTA1+
OUTA1-
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10 Power Supply Recommendations
10.1 3.3-V Power
10.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply of the TPS65994AD device. The VIN_3V3 switch (see Power
Management) is a uni-directional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from
LDO_3V3 to VIN_3V3. This switch is on when the 3.3 V supply is availableand the dead-battery flag is cleared.
The recommended capacitance CVIN_3V3 (see the Recommended Capacitance in the Specifications section)
should be connected from the VIN_3V3 pin to the GND pin.
10.1.2 VBUS 3.3-V LDO
The 3.3 V LDO from Px_VBUS to LDO_3V3 steps down voltage from the PA_VBUS pin to LDO_3V3 which
allows the TPS65994AD device to be powered from VBUS when VIN_3V3 is unavailable. This LDO steps down
any recommended voltage on the PA_VBUS pin. When VBUS reaches 20 V, which is allowable by USB PD, the
internal circuitry of the TPS65994AD device operates without triggering thermal shutdown; however, a significant
external load on the LDO_3V3 pin or any GPIOx pin can increase temperature enough to trigger thermal
shutdown. Keep the total load on LDO_3V3 within the limits from the Recommended Operating Conditions in the
Specifications section. Connect the recommended capacitance CPx_VBUS (see Recommended Capacitance in
the Specifications section) from the VBUS pin to the GND pin.
10.2 1.5-V Power
The internal circuitry is powered from 1.5 V. The 1.5-V LDO steps the voltage down from LDO_3V3 to 1.5 V. The
1.5-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, and memory.
The 1.5-V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended
capacitance CLDO_1V5 (see the Recommended Capacitance in the Specifications section) from the LDO_1V5 pin
to the GND pin.
10.3 Recommended Supply Load Capacitance
The Recommended Capacitance in the Specifications section lists the recommended board capacitances for the
various supplies. The typical capacitance is the nominally rated capacitance that must be placed on the board as
close to the pin as possible. The maximum capacitance must not be exceeded on pins for which it is specified.
The minimum capacitance is minimum capacitance allowing for tolerances and voltage derating ensuring proper
operation.
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11 Layout
11.1 Layout Guidelines
Proper routing and placement will maintain signal integrity for high speed signals and improve the heat
dissipation from the power paths. The combination of power and high speed data signals are easily routed if the
following guidelines are followed. It is a best practice to consult with board manufacturing to verify manufacturing
capabilities.
11.1.1 Top TPS65994AD Placement and Bottom Component Placement and Layout
When the TPS65994AD is placed on top and its components on bottom the solution size will be at its smallest.
11.2 Layout Example
Follow the differential impedances for Super and High Speed signals defined by their specifications (DisplayPort
- AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not all designs
will utilize all of the I/O on the TPS65994AD.
Q1
A1
B1
D1
E1
CSD87501L
A2
B2
D2
E2
PPHV
PA_VBUS
PA_GATE_VSYS
PA_GATE_VBUS
PP5V
11
31
30
PA_CC1
PA_CC2
PP5V
PP5V
PP5V
PP5V
PP5V
PP5V
PA_CC1
PA_CC2
12
17
20
25
26
C1
10uF
C2
10uF
C3
220pF
C4
220pF
P3V3
PA_VBUS
21
22
23
24
PA_VBUS
PA_VBUS
PA_VBUS
PA_VBUS
PA_VBUS
GND
32
VIN_3V3
GND
C5
10uF
PA_GATE_VBUS
19
PA_GATE_VBUS
33
35
ADCIN1
ADCIN1
ADCIN2
ADCIN2
GND
PA_GATE_VSYS
PPHV
45
38
9
5
3
4
PB_HPD
PA_HPD
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
PA_GATE_VSYS
VSYS
PA_POL
28
2
PB_USB3
PB_DP_MODE
PA_USB3
GPIO6
PB_GATE_VSYS
PB_GATE_VSYS
46
29
27
10
8
GPIO7
PB_GATE_VBUS
PB_VBUS
18
PA_DP_MODE
PB_POL
PB_GATE_VBUS
13
14
15
16
PB_VBUS
PB_VBUS
PB_VBUS
PB_VBUS
PB_VBUS
42
40
43
I2C1_SCL
I2C1_SDA
I2C1_IRQZ
I2C_EC_SCL
I2C_EC_SDA
I2C_EC_IRQ
PB_CC1
PB_CC2
41
44
39
I2C2_SCL
I2C2_SDA
I2C2_IRQZ
I2C2s_SCL
I2C2s_SDA
I2C2s_IRQ
6
7
PB_CC1
PB_CC2
C8
220pF
C9
220pF
1
48
47
I2C3_SCL
I2C3_SDA
I2C3_IRQZ
I2C3m_SCL
I2C3m_SDA
I2C3m_IRQ
34
37
LDO_3V3
LDO_3V3
LDO_1V5
GND
LDO_1V5
C10
10uF
36
49
GND
GND
C11
10uF
U1
TPS65994ADRSLR
GND
GND
GND
PB_GATE_VSYS
PB_GATE_VBUS
PPHV
E2
D2
B2
A2
E1
D1
B1
A1
PB_VBUS
CSD87501L
Q2
图11-1. Example Schematic
11.3 Component Placement
Top and bottom placement is used for this example to minimize solution size. The TPS65994AD is placed on the
top side of the board and the majority of its components are placed on the bottom side. When placing the
components on the bottom side, it is recommended that they are placed directly under the TPS65994AD. When
placing the VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to
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face outward from the TPS65994AD or to the side since the drain connection pads on the bottom layer should
not be connected to anything and left floating. All other components that are for pins on the GND pad side of the
TPS65994AD should be placed where the GND terminal is underneath the GND pad.
The CC capacitors should be placed on the same side as the TPS65994AD close to the respective CC1 and
CC2 pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.
The ADCIN1/2 voltage divider resistors can be placed where convenient. In this layout example they are placed
on the opposite layer of the TPS65994AD close to the LDO_3V3 pin to simplify routing.
The figures below show the placement in 2-D and 3-D.
图11-3. Bottom View Layout (Flipped)
图11-2. Top View Layout
图11-5. Bottom View 3-D
图11-4. Top View 3-D
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11.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3, LDO_1V5
On the top side, create pours for PP_5V and VBUS1/2. Connect PP5V from the top layer to the bottom layer
using at least 7 8-mil hole and 16-mil diameter vias. See 图 11-6 and 图 11-7 for top and bottom layer via
placement and copper pours respectively.
图11-6. VBUS1 and VBUS2 Copper Pours and Via Placement (Top)
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图11-7. PP5V Copper Pours and Via Placement (Bottom)
Next, VIN_3V3, LDO_3V3, and LDO_1V5 will be routed to their respective decoupling capacitors. This is
highlighted in Figure 8. Connect the bottom side VIN_3V3, LDO_1V5, and LDO_3V3 capacitors with traces
through a via. The vias should have a straight connection to the respective pins.
As shown in 图11-5 (3D view) these decoupling capacitors are in the bottom layer.
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图11-8. VIN_3V3, LDO_3V3, and LDO_1V5 Routing
11.5 Routing CC and GPIO
Routing the CC lines with a 10-mil trace will ensure the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top or bottom layer using either a 6-mil trace or a 8-mil trace.
The following images highlight how the CC lines and GPIOs are routed out.
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图11-9. Top Layer GPIO Routing
表11-1. Routing Widths
ROUTE
WIDTH (mil minimum)
PA_CC1, PA_CC2, PB_CC1, PB_CC2
VIN_3V3, LDO_3V3, LDO_1V5
Component GND
8
6
10
4
GPIO
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Documentation Support
12.2.1 Related Documentation
• USB-PD Specifications
• USB Power Delivery Specification
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
USB Type-C® is a registered trademark of USB Implementers Forum.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
Packaging Information
Orderable
Device
Package
Drawing
Lead/Ball
Finish(3)
MSL Peak
Temp(4)
Device
Status(1)
Package Type
Pins
Package Qty
Eco Plan(2)
Op Temp
Marking(5) (6)
TPS65994
AD
TPS65994ADRSL
R
Green (RoHS& no
Sb/Br)
NiPdAu /
NiPdAuAg
Level-2-260C-1
YEAR
ACTIVE
VQFN
RSL
48
2500
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65994ADRSLR
ACTIVE
VQFN
RSL
48
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TPS65994
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
4.4
13
24
44X 0.4
12
23
SYMM
49
4.5
4.3
4.4
1
36
0.25
0.15
48X
PIN 1 IDENTIFICATION
(OPTIONAL)
37
48
0.1
C A B
C
SYMM
0.5
0.3
0.05
48X
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
(
4.4)
SYMM
48
37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
SYMM
(5.8)
10X (1.12)
49
6X (0.83)
(R0.05) TYP
12
25
13
6X (0.83)
24
(Ø0.2) VIA
10X (1.12)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
SYMM
48
37
48X (0.6)
48X (0.2)
1
49
36
44X (0.4)
16X
(
0.92)
SYMM
8X (0.56)
(5.8)
8X (1.12)
(R0.05) TYP
12
25
13
8X (1.12)
24
METAL TYP
8X (0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS65994AE
具有支持 USB4 和交替模式的集成电源开关的双端口 USB-C® PD 控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS65994AERSLR
具有支持 USB4 和交替模式的集成电源开关的双端口 USB-C® PD 控制器 | RSL | 48 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS66020
具有 3.3V 无电电池 LDO 的 USB-C/PD 20V、灌电流和 5V、拉电流电源开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66020YBGR
具有 3.3V 无电电池 LDO 的 USB-C/PD 20V、灌电流和 5V、拉电流电源开关 | YBG | 28 | -10 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66021
具有 5V 无电电池 LDO 的 USB-C/PD 20V、灌电流和 5V、拉电流电源开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66021YBGR
具有 5V 无电电池 LDO 的 USB-C/PD 20V、灌电流和 5V、拉电流电源开关 | YBG | 28 | -10 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66120
适用于具有 3.3V 无电电池 LDO 灌电流的 USB-C/PD 高压电源开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66120YBGR
适用于具有 3.3V 无电电池 LDO 灌电流的 USB-C/PD 高压电源开关 | YBG | 28 | -10 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66121
适用于具有 5V 无电电池 LDO 灌电流的 USB-C/PD 高压电源开关Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS66121YBGR
适用于具有 5V 无电电池 LDO 灌电流的 USB-C/PD 高压电源开关 | YBG | 28 | -10 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS6734
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS6734I
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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