TPS703 [TI]
具有电源正常指示和使能功能的 1A 双通道超低压降稳压器;
| 型号： | TPS703 |
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TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示和使能功能的 1A 双通道超低压降稳压器 电源电路 光电 线性稳压器IC 半导体 |
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
D
D
Dual Output Voltages for Split-Supply
Applications
D
D
D
D
D
D
D
D
D
D
Open Drain Power Good for Regulator 1
Ultralow 185 µA (typ) Quiescent Current
2 µA Input Current During Standby
Selectable Power Up Sequencing for DSP
Applications (See TPS704xx for
Independent Enabling of Each Output)
Low Noise: 78 µV
Capacitor
Without Bypass
RMS
D
Output Current Range of 1 A on
Regulator 1 and 2 A on Regulator 2
Quick Output Capacitor Discharge Feature
Two Manual Reset Inputs
D
Fast Transient Response
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
24-Pin PowerPAD TSSOP Package
Thermal Shutdown Protection
D
Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V,
3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
Outputs
D
Open Drain Power-On Reset With 120-ms
Delay
PWP PACKAGE
(TOP VIEW)
description
1
24
23
22
21
20
19
18
17
16
15
14
13
GND/HEATSINK
GND/HEATSINK
TPS703xx family of devices are designed to
2
V
V
V
V
V
IN1
IN1
OUT1
provide a complete power management solution
for TI DSP, processor power, ASIC, FPGA, and
digital applications where dual output voltage
regulators are required. Easy programmability of
the sequencing function makes this family ideal
for any TI DSP applications with power
sequencing requirement. Differentiated features,
such as accuracy, fast transient response, SVS
supervisory circuit (power on reset), manual reset
inputs, and enable function, provide a complete
system solution.
3
OUT1
4
NC
MR2
MR1
EN
SEQ
GND
/FB1
SENSE1
5
NC
6
PG1
RESET
NC
7
8
9
V
V
V
/FB2
SENSE2
OUT2
10
11
12
V
V
IN2
IN2
OUT2
GND/HEATSINK
GND/HEATSINK
NC – No internal connection
TPS70351 PWP
DSP
3.3 V
I/O
V
OUT1
5 V
V
IN1
22 µF
250 kΩ
PG1
0.22 µF
V
SENSE1
PG1
MR2
MR2
MR1
>2 V
V
IN2
250 kΩ
<0.7 V
0.22 µF
RESET
RESET
EN
<0.7 V
>2 V
>2 V
MR1
EN
<0.7 V
V
SENSE2
1.8 V
SEQ
V
OUT2
Core
47 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
description (continued)
The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up
sequence control, which is designed primarily for DSP applications. These devices have low noise output
performance without using any added filter bypass capacitors and are designed to have a fast transient
response and be stable with 47 µF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.
Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the
designer to configure the source power.
Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160
mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element
is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal
to EN (enable) shuts down both regulators, reducing the input current to 1 µA at T = 25°C.
J
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the V
and V
pins respectively.
SENSE1
SENSE2
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is
enabledandtheSEQterminalispulledhighorleftopen, V
reaches approximately 83% of its regulated output voltage. At that time V
below 83% (i.e. overload condition) of its regulated voltage, V
turnsonfirstandV
remainsoffuntilV
OUT2
OUT1 OUT2
is turned on. If V
is pulled
OUT1
OUT2
will be turned off. Pulling the SEQ terminal
OUT1
low reverses the power-up order and V
current source.
is turned on first. The SEQ pin is connected to an internal pullup
OUT1
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage conditions at V
reset) for the circuitry supplied by regulator 1.
. The PG1 pin can be used to implement a SVS (power on
OUT1
The TPS703xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output
and requires a pullup resistor for normal operation. When pulled up, RESET goes to a high impedance state
(i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, V
theundervoltagecondition. Second, themanualreset(MR)pinmustbeinahighimpedancestate. Third, V
must be above
IN1
OUT2
must be above approximately 95% of its regulated voltage. To monitor V
, the PG1 output pin can be
OUT1
connected to MR1 or MR2. RESET can be used to drive power on reset or a low-battery indicator. If RESET
is not used, it can be left floating.
Internal bias voltages are powered by V
undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.
and require 2.7 V for full functionality. Each regulator input has an
IN1
AVAILABLE OPTIONS
REGULATOR 1
(V)
REGULATOR 2
(V)
TSSOP
(PWP)
T
J
V
V
O
O
3.3 V
3.3 V
3.3 V
3.3 V
1.2 V
1.5 V
1.8 V
2.5 V
TPS70345PWP
TPS70348PWP
TPS70351PWP
TPS70358PWP
–40°C to 125°C
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70302PWP
NOTE: The TPS70302 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70302PWPR).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
detailed block diagram – fixed voltage version
V
(2 Pins)
V
(2 Pins)
OUT1
IN1
Current
Sense
10 kΩ
UVLO1
V
SENSE1
Shutdown
ENA_1
2.5 V
(see Note A)
ENA_1
FB1
–
+
Reference
V
ref
GND
Thermal
Shutdown
V
ref
UVLO1
FB1
PG1
Rising Edge
Deglitch
0.95 × V
ref
V
IN1
MR2
Shutdown
RESET
FB2
Falling Edge
Delay
Rising Edge
Deglitch
UV Comp
0.95 × V
ref
FB2
Falling Edge
V
IN1
ENA_1
Deglitch
0.83 × V
ref
Power
Sequence
Logic
FB1
ENA_2
V
ref
MR1
Falling Edge
Deglitch
FB2
0.83 × V
ref
UV Comp
2.5 V
–
+
EN
ENA_2
ENA_2
V
IN1
UVLO2
V
SENSE2
(see Note A)
Current
Sense
SEQ
(see Note B)
10 kΩ
V
(2 Pins)
OUT2
V
(2 Pins)
IN2
NOTES: A. For most applications, V
and V
should be externally connected to V
as close as possible to the device.
OUT
SENSE1
For other implementations, refer to SENSE terminal connection discussion in the Application Information section.
B. If the SEQ terminal is floating at the input, V powers up first.
SENSE2
OUT2
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
detailed block diagram – adjustable voltage version
V
(2 Pins)
V
(2 Pins)
OUT1
IN1
Current
Sense
UVLO1
FB1
Shutdown
ENA_1
ENA_1
+
2.5 V
(see Note A)
PG1
–
Reference
V
ref
GND
Thermal
Shutdown
V
ref
UVLO1
FB1
Rising Edge
Deglitch
0.95 × V
ref
V
IN1
MR2
Shutdown
RESET
FB2
Falling Edge
Delay
UV Comp
Rising Edge
Deglitch
0.95 × V
ref
FB2
Falling Edge
V
IN1
Deglitch
ENA_1
Power
Sequence
Logic
0.83 × V
ref
FB1
ENA_2
Falling Edge
Deglitch
MR1
V
ref
0.83 × V
ref
UV Comp
2.5 V
–
+
EN
V
ENA_2
IN1
UVLO2
FB2
(see Note A)
ENA_2
Current
Sense
SEQ
(see Note B)
V
(2 Pins)
OUT2
V
(2 Pins)
IN2
NOTES: A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device.
For other implementations, refer to FB terminals connection discussion in the Application Information section.
B. If the SEQ terminal is floating at the input, V
powers up first.
OUT2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
RESET timing diagram (with V
powered up and MR1 and MR2 at logic high)
IN1
V
IN2
V
V
RES
RES
(see Note A)
t
V
OUT2
V
IT+
(see Note B)
V (see Note B)
IT+
Threshold
Voltage
V
V
IT–
(see Note B)
IT–
(see Note B)
t
RESET
Output
120 ms
Delay
120 ms
Delay
Output
Undefined
Output
Undefined
t
NOTES: A.
B.
V
istheminimuminputvoltageforavalidRESET. ThesymbolV
isnotcurrentlylistedwithinEIAorJEDECstandards
RES
RES
for semiconductor symbology.
V
–Trip voltage is typically 5% lower than the output voltage (95%V ) V
to V
is the hysteresis voltage.
IT+
IT
O
IT–
PG1 timing diagram
V
IN1
V
UVLO
V
UVLO
V
V
PG1
PG1
(see Note A)
t
V
V
IT+
(see Note B)
V
IT+
(see Note B)
V
OUT2
Threshold
Voltage
V
IT–
(see Note B)
IT–
(see Note B)
t
PG1
Output
Output
Undefined
Output
Undefined
t
NOTES: A.
B.
V
is the minimum input voltage for a valid PG. The symbol V is not currently listed within EIA or JEDEC
PG
PG
standards for semiconductor symbology.
V
–Trip voltage is typically 5% lower than the output voltage (95%V ) V
to V
is the hysteresis
IT+
IT
voltage.
O
IT–
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
EN
7
I
Active low enable
Regulator ground
Ground/heatsink
GND
9
GND/HEATSINK
1, 12, 13, 24
MR1
MR2
NC
6
I
I
Manual reset input 1, active low, pulled up internally
Manual reset input 2, active low, pulled up internally
No connection
5
4, 17, 20
PG1
RESET
SEQ
19
18
8
O
O
I
Open drain output, low when V
voltage is less than 95% of the nominal regulated voltage
Open drain output, SVS (power on reset) signal, active low
OUT1
Powerupsequencecontrol:SEQ=High,V
SEQ terminal pulled up internally.
powersupfirst;SEQ=Low, V
powersupfirst,
OUT1
OUT2
V
V
V
V
V
V
2, 3
10, 11
22, 23
14, 15
16
I
I
Input voltage of regulator 1
Input voltage of regulator 2
Output voltage of regulator 1
Output voltage of regulator 2
IN1
IN2
O
O
I
OUT1
OUT2
SENSE2
SENSE1
/FB2
/FB1
Regulator 2 output voltage sense/ regulator 2 feedback for adjustable
Regulator 1 output voltage sense/ regulator 1 feedback for adjustable
21
I
detailed description
The TPS703xx low dropout regulator family provides dual regulated output voltages for DSP applications that
require a high performance power management solution. These devices provide fast transient response and
high accuracy, while drawing low quiescent current. Programmable sequencing provides a power solution for
DSPs without any external component requirements. This reduces the component cost and board space while
increasing total system reliability. TPS703xx family has an enable feature which puts the device in sleep mode
reducing the input current to 1 µA. Other features are the integrated SVS (power on reset, RESET) and power
good(PG1). Thesemonitoroutputvoltagesandprovidelogicoutputtothesystem. Thesedifferentiatedfeatures
provide a complete DSP power solution.
The TPS703xx, unlike many other LDOs, features very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is
directly proportional to the load current through the regulator (I = I /β). The TPS703xx uses a PMOS transistor
B
C
to pass current. Because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
pin functions
enable
The EN terminal is an input which enables or shuts down the device. If EN is at a logic high signal the device
is in shutdown mode. When the EN goes to voltage low, then the device is enabled.
sequence
The SEQ terminal is an input that programs which output voltage (V
or V
) is turned on first. When the
OUT1
OUT2
device is enabled and the SEQ terminal is pulled high or left open, V
turns on first and V
remains off
OUT2
OUT1
until V
reaches approximately 83% of its regulated output voltage. If V
is pulled below 83% (i.e., over
OUT2
OUT2
load condition) V
is turned off. This terminal has a 6-µA pullup current to V
.
OUT1
IN1
PullingtheSEQterminallowreversesthepower-uporderandV
refer to Figures 33 through 39.
isturnedonfirst.Fordetailtimingdiagrams
OUT1
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
detailed description (continued)
power good (PG1)
The PG1 terminal is an open drain, active high output terminal which indicates the status of the V
regulator.
OUT1
When the V
impedance state when V
drain output of the PG1 terminal requires a pullup resistor
reaches 95% of its regulated voltage, PG1 goes to a high impedance state. PG1 goes to a low
OUT1
is pulled below 95% (i.e., over load condition) of its regulated voltage. The open
OUT1
.
manual reset pins (MR1 and MR2)
MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled
to logic low, a POR (RESET) occurs. These terminals have a 6-µA pullup current to V . It is recommended
IN1
that these pins be pulled high to V when they are not used.
IN
sense (V
, V
)
SENSE1 SENSE2
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, the sense terminals connect to high-impedance wide-bandwidth
amplifiers through resistor-divider networks and noise pickup feeds through to the regulator output. It is
essential to route the sense connections in such a way to minimize/avoid noise pickup. Adding RC networks
between the V
regulators to oscillate.
terminals and V
terminals to filter noise is not recommended because it can cause the
SENSE
OUT
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and the V
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
OUT
RESET indicator
RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up,
RESET goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following
conditions are met. First, V
must be in a high impedance state. Third, V
must be above the undervoltage condition. Second, the manual reset (MR) pin
IN1
must be above approximately 95% of its regulated voltage.
OUT2
To monitor V
, the PG1 output pin can be connected to MR1 or MR2.
OUT1
V
and V
IN2
IN1
V
and V
are inputs to the regulators.
IN1
IN2
and V
OUT2
V
OUT1
V
and V
are output terminals of each regulator.
OUT2
OUT1
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
†
absolute maximum ratings over operating junction temperature (unless otherwise noted)
‡
Input voltage range : V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
IN1
IN2
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range (V
Output voltage range (V
, V
)
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
OUT1 SENSE1
, V
OUT2 SENSE2
Maximum RESET, PG1 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum MR1, MR2, and SEQ voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are tied to network ground.
DISSIPATION RATING TABLE
AIR FLOW
PACKAGE
T
A
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T = 85°C
A
(CFM)
0
3.32 W
TBD W
33.2 mW/°C
TBD mW/°C
1.83 W
TBD W
1.33 W
TBD W
§
PWP
250
§
This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 2 oz. copper traces on a
4-in × 4-ingroundlayer. Simultaneousandcontinuousoperationofbothregulatoroutputsatfullloadsmayexceedthepower
dissipation rating of the PWP package. For more information, refer to the power dissipation and thermal information section
at the end of this datasheet, and to TI technical brief SLMA002.
recommended operating conditions
MIN
2.7
0
MAX
6
UNIT
¶
Input voltage, V
V
A
I
Output current, I (regulator 1)
1
O
Output current, I (regulator 2)
O
0
2
A
Output voltage range (for adjustable option)
1.22
–40
5.5
125
V
Operating virtual junction temperature, T
°C
.
J
¶
To calculate the minimum input voltage for maximum output current, use the following equation: V
= V
+ V
O(max) DO(max load)
I(min)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
electrical characteristics over recommended operating junction temperature (T = –40°C to 125°C)
J
V
orV
=V
+1V,I
=1mA,EN=0,C
=22µF, C
=47µF(unlessotherwise
IN1
IN2
OUTX(nom)
OUTX
OUT1
OUT2
noted)
PARAMETER
TEST CONDITIONS
2.7 V < V < 6 V, FB connected to V
MIN
TYP
MAX
UNIT
I
O
Reference
voltage
1.224
T
= 25°C
J
2.7 V < V < 6 V,
FB connected to V
1.196
1.176
1.47
1.248
1.224
1.53
I
O
2.7 V < V < 6 V,
T
T
T
T
T
T
T
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
1.2
1.5
1.2 V Output
I
J
J
J
J
J
J
J
(V
)
OUT2
2.7 V < V < 6 V
I
2.7 V < V < 6 V,
1.5 V Output
(V
I
Output voltage
(see Notes 1 and 3)
)
OUT2
2.7 V < V < 6 V
I
V
V
O
2.8 V < V < 6 V,
1.8
1.8 V Output
I
(V
)
OUT2
2.8 V < V < 6 V
1.764
2.45
1.836
2.55
I
3.5 V < V < 6 V,
2.5
2.5 V Output
(V
I
)
OUT2
3.5 V < V < 6 V
I
4.3 V < V < 6 V,
3.3
3.3 V Output
I
(V
)
OUT2
4.3 V < V < 6 V
I
3.234
3.366
250
See Note 3,
See Note 3
185
Quiescent current (GND current) for regulator 1 and
regulator 2, EN = 0 V, (see Note 1)
µA
V
V
+ 1 V < V ≤ 6 V,
= 25°C, See Note 1
0.01%
Output voltage line regulation (∆V /V )for regulator 1 and
regulator 2 (see Note 2)
O
I
O
O
V
+ 1 V < V ≤ 6 V,
See Note 1
See Note 3
0.1%
O
I
Load regulation for V
and V
T = 25°C,
J
1
79
mV
OUT1
OUT2
Regulator 1
Regulator 2
Regulator 1
Regulator 2
Output noise voltage
(TPS70351)
V
BW = 300 Hz to 100 kHz,
T
= 25°C
µVrms
n
J
J
77
1.75
3.8
150
1
2.2
4.5
Output current limit
Thermal shutdown junction temperature
V
= 0 V
A
O
°C
EN = V ,
T
= 25°C
2
I
I
Standby current
µA
I(standby)
EN = V
10
I
Regulator 1
Regulator 2
f = 1 kHz,
f = 1 kHz,
T
T
= 25°C,
= 25°C,
See Note 1
See Note 1
65
60
PSRR
Power supply ripple rejection
(TPS70351)
J
dB
J
RESET terminal
Minimum input voltage for valid RESET
Trip threshold voltage
I
= 300 µA,
V
≤ 0.8 V
1.0
95%
0.5%
120
1.3
V
(RESET)
decreasing
(RESET)
V
92%
80
98%
V
V
O
O
Hysteresis voltage
Measured at V
O
O
t
t
RESET pulse duration
Rising edge deglitch
160
ms
µs
V
(RESET)
30
r(RESET)
Output low voltage
Leakage current
V = 3.5 V,
I
= 1 mA
0.15
0.4
1
I
(RESET)
V
= 6 V
µA
(RESET)
NOTES: 1. Minimum input operating voltage is 2.7 V or V
current is 1 mA.
+ 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output
O(typ)
2. If V < 1.8 V then V
Imax
= 6 V, V
= 2.7 V:
Imin
O
OǒVImax * 2.7 VǓ
V
ǒ
Ǔ
Line regulation (mV) + %ńV
1000
100
If V > 2.5 V then V
Imax
= 6 V, V
= V + 1 V:
O
Imin
O ǒV
) 1 Ǔ
* ǒVO
Imax
Ǔ
V
O
ǒ
Ǔ
Line regulation (mV) + %ńV
1000
100
3.
I
O
= 1 mA to 1 A for regulator 1 and 1 mA to 2 A for regulator 2.
9
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
electrical characteristics over recommended operating junction temperature (T = –40°C to 125°C)
J
V
orV
=V
+1V,I
=1mA,EN=0,C
=22µF, C
=47µF(unlessotherwise
IN1
IN2
OUTX(nom)
OUTX
OUT1
OUT2
noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PG terminal
Minimum input voltage for valid PG
Trip threshold voltage
I
= 300 µA,
V
) ≤ 0.8 V
1.0
95%
0.5%
30
1.3
V
(PG)
(PG1
V
decreasing
92%
98%
V
O
O
O
Hysteresis voltage
Measured at V
O
V
t
Rising edge deglitch
V = 2.7 V,
µs
V
r(PG1)
Output low voltage
Leakage current
EN terminal
I
= 1 mA
0.15
0.4
1
I
(PG)
V
= 6 V
µA
(PG1)
High-level EN input voltage
Low-level EN input voltage
Input current (EN)
2
V
V
0.7
1
–1
µA
SEQ terminal
High-level SEQ input voltage
Low-level SEQ input voltage
SEQ pullup current source
MR1 / MR2 terminals
2
2
V
V
0.7
0.7
6
6
µA
High-level input voltage
Low-level input voltage
Pullup current source
V
V
µA
V
terminal
OUT2
V
of V
UV comparator – positive-going input threshold voltage
OUT2
80% V
83% V
86% V
O
V
O
O
O
UV comparator
OUT1
V
V
UV comparator – hysteresis
3% V
mV
OUT2
UV comparator – falling edge deglitch
V
decreasing below threshold
140
µs
OUT2
SENSE2
Peak output current
2 ms pulse width
3
A
Discharge transistor current
V
= 1.5 V
7.5
mA
OUT2
V
terminal
OUT1
V
of V
UV comparator – positive-going input threshold voltage
OUT1
80% V
83% V
86% V
O
V
O
O
O
UV comparator
OUT1
V
V
UV comparator – hysteresis
3% V
mV
OUT1
UV comparator – falling edge deglitch
V
decreasing below threshold
140
160
µs
OUT1
SENSE1
I
I
= 1 A,
= 1 A,
V
= 3.2 V,
T = 25°C
J
O
IN1
Dropout voltage (see Note 4)
mV
V
= 3.2 V
250
O
IN1
Peak output current
2 ms pulse width
= 1.5 V
1.2
7.5
A
Discharge transistor current
V
mA
OUT1
V
/ V terminal
IN1 IN2
UVLO threshold
2.3
2.65
V
UVLO hysteresis
110
1
mV
FB1 / FB2 terminals
Input current – TPS70302
NOTE 4: Inputvoltage(V
FB = 1.8 V
µA
orV
)= V (Typ)–100mV.Forthe1.5-V,1.8-Vand2.5-Vregulators,thedropoutvoltageislimitedbyinputvoltage
O
IN1
IN2
range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test.
10
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
vs Junction temperature
vs Junction temperature
vs Frequency
1, 2
3, 4
V
Output voltage
O
Ground current
5
PSRR
Power supply rejection ratio
Output spectral noise density
Output impedance
6 – 9
vs Frequency
10 – 13
14 – 17
18, 19
20, 21
22, 23
24, 25
26, 27
29 – 32
z
vs Frequency
o
vs Temperature
Dropout voltage
vs Input voltage
Load transient response
Line transient response
V
O
Output voltage and enable voltage
Equivalent series resistance
vs Time (start-up)
vs Output current
TPS70351
OUTPUT VOLTAGE
vs
TPS70351
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
3.33
3.32
3.31
3.30
1.815
1.81
V
T
= 2.8V
V
T
= 4.3 V
IN2
= 25°C
IN1
= 25°C
J
J
V
OUT2
V
OUT1
1.805
1.8
1.795
3.29
3.28
3.27
1.79
1.785
0
200
400
600
800
1000
0
500
1000
1500
2000
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 2
Figure 1
11
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
V = 4.3 V
IN1
V
OUT1
3.354
3.334
3.314
I
O
= 1 mA
3.294
I
O
= 1 A
3.274
3.254
3.234
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
J
– Junction Temperature – °C
Figure 3
TPS70351
GROUND CURRENT
vs
TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
210
1.834
1.824
1.814
1.804
1.794
Regulator 1 and Regulator 2
V
V
= 2.8 V
IN2
OUT2
200
190
180
170
I
I
= 1 mA
= 1 mA
OUT1
OUT2
I
O
= 2 A
I
I
= 1 A
= 2 A
OUT1
OUT2
I
= 1 mA
O
1.784
1.774
160
150
1.764
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
J
– Junction Temperature – °C
T
– Junction Temperature – °C
J
Figure 4
Figure 5
12
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TPS70351
TPS70351
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
V
= 4.3 V
= 3.3 V
= 10 mA
= 22 µF
V
= 4.3 V
= 3.3 V
IN1
IN1
V
I
V
I
OUT1
O
OUT1
= 1 A
O
C
C
= 22 µF
o
o
–80
–90
–90
–100
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
f – Frequency – Hz
Figure 6
Figure 7
TPS70351
TPS70351
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
V
= 2.8 V
= 1.8 V
V
= 2.8 V
= 1.8 V
= 10 mA
= 47 µF
IN2
IN2
V
I
V
I
OUT2
= 2 A
OUT2
O
O
C
= 47 µF
C
o
o
–90
–90
–100
–100
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
f – Frequency – Hz
Figure 8
Figure 9
13
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
V
= 4.3 V
= 3.3 V
V
V
= 2.8 V
= 1.8 V
IN1
OUT1
IN2
OUT2
C
I
= 22 µF
= 10 mA
C
I
= 47 µF
= 10 mA
OUT1
OUT2
O
O
T
J
= 25°C
T
J
= 25°C
1
1
0.1
0.1
0.01
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 10
Figure 11
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
V
C
= 4.3 V
= 3.3 V
IN1
OUT1
V
V
C
= 2.8 V
= 1.8 V
IN2
OUT2
= 22 µF
OUT1
= 1 A
= 47 µF
OUT2
= 2 A
I
T
O
J
I
T
O
J
= 25°C
= 25°C
1
1
0.1
0.01
0.1
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 12
Figure 13
14
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
V
= 3.3 V
OUT1
= 1 A
V
= 3.3 V
= 10 mA
= 22 µF
OUT1
I
O
I
O
C
= 22 µF
o
C
o
1
0.1
1
0.1
0.01
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 14
Figure 15
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
V
= 1.8 V
V
I
C
= 1.8 V
= 10 mA
= 47 µF
OUT2
= 2 A
OUT2
O
o
I
O
C
= 47 µF
o
1
0.1
1
0.1
0.01
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 16
Figure 17
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TPS70351
DROPOUT VOLTAGE
vs
TPS70351
DROPOUT VOLTAGE
vs
TEMPERATURE
TEMPERATURE
25
250
200
150
100
50
V
V
V
V
OUT1
= 3.2 V
OUT1
= 3.2 V
IN1
IN1
20
15
I
O
= 1 A
I
O
= 100 mA
10
5
I
O
= 1 mA
I
O
= 10 mA
0
0
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T – Temperature – °C
T – Temperature – °C
Figure 18
Figure 19
TPS70302
DROPOUT VOLTAGE
vs
TPS70302
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
300
300
V
V
OUT1
= 1 A
OUT2
= 2 A
I
O
I
O
250
200
250
200
T
= 125°C
J
T
J
= 125°C
T
J
= 25°C
T
J
= 25°C
150
100
50
150
100
50
T = –40°C
J
T = –40°C
J
0
2.5
0
2.5
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 20
Figure 21
16
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TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
V
I
= 1.8 V
V
V
= 4.3 V
= 3.3 V
OUT2
= 2 A
IN1
OUT1
= 22 µF
2
1
1
O
C
T
= 47 µF
= 25°C
C
T
o
o
= 25°C
J
J
0.5
0
0
50
0
50
0
–50
–100
–50
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t – Time – ms
t – Time – ms
Figure 22
Figure 23
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
V
I
C
= 3.3 V
OUT1
= 1 A
V
I
= 1.8 V
OUT2
= 2 A
5.3
4.3
O
3.8
2.8
O
= 22 µF
o
C = 47 µF
o
50
0
100
0
–50
–100
–200
–100
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
t – Time – µs
t – Time – µs
Figure 24
Figure 25
17
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE AND ENABLE VOLTAGE
OUTPUT VOLTAGE AND ENABLE VOLTAGE
vs
vs
TIME (START-UP)
TIME (START-UP)
4
3
V
= 3.3 V
OUT1
= 1 A
I
C
O
2
1
0
2
1
0
= 22 µF
o
V
IN1
= 4.3 V
SEQ = Low
V
= 1.8 V
OUT2
= 2 A
I
C
O
= 47 µF
o
V
IN2
= 2.8 V
5
0
SEQ = High
5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t – Time (Start-Up) – ms
t – Time (Start-Up) – ms
Figure 26
Figure 27
To Load
IN
V
I
OUT
+
R
L
C
o
EN
GND
ESR
Figure 28. Test Circuit for Typical Regions of Stability
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C .
o
18
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
†
†
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
V
C
= 3.3 V
OUT1
= 22 µF
V
C
= 3.3 V
OUT1
= 220 µF
o
o
REGION OF INSTABILITY
REGION OF INSTABILITY
1
1
0.1
0.1
50 mΩ
15 mΩ
0.01
0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
I
O
– Output Current – A
I
O
– Output Current – A
Figure 29
Figure 30
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
†
†
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
V
C
= 1.8 V
OUT2
= 47 µF
V
C
= 1.8 V
OUT2
= 680 µF
o
1
1
o
0.1
0.1
50 mΩ
15 mΩ
0.01
0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
I
O
– Output Current – A
I
O
– Output Current – A
Figure 31
Figure 32
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C .
o
19
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad )
The thermally enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see
Figure 33(c)] to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down
TO220-typepackageshaveleadsformedasgullwingstomakethemapplicableforsurface-mountapplications.
These packages, however, suffer from several shortcomings: they do not address the very low profile
requirements (<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough
to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages
require power-dissipation derating that severely limits the usable range of many high-performance analog
circuits.
The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal
performance comparable to much larger power packages.
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and
limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction
paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent
pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC.
When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the
ultrathin, fine-pitch, surface-mount package can be reliably achieved.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 33. Views of Thermally Enhanced PWP Package
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal
considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface),
which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference
2
Figure 35(a), 8 cm of copper heat sink and natural convection). Increasing the heat-sink size increases the
power dissipation range for the component. The power dissipation limit can be further improved by adding
2
airflow to a PWB/IC assembly (see Figures 34 and 35). The line drawn at 0.3 cm in Figures 34 and 35 indicates
performance at the minimum recommended heat-sink size, illustrated in Figure 36.
20
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad ) (continued)
The thermal pad is directly connected to the substrate of the IC, which for the TPS703xx series is a secondary
electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane
or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary
electrical connection for a given terminal which is not always ground. The PWP package provides up to 24
independentleadsthatcanbeusedasinputsandoutputs(Note:leads1, 12, 13, and24areinternallyconnected
to the thermal pad and the IC substrate).
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150
125
100
Natural Convection
50 ft/min
100 ft/min
150 ft/min
200 ft/min
75
50
25
250 ft/min
300 ft/min
0 0.3
1
2
3
4
5
6
7
8
2
Copper Heat-Sink Area – cm
Figure 34
21
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad ) (continued)
3.5
3.5
T
A
= 25°C
T
A
= 55°C
300 ft/min
3
2.5
2
3
2.5
2
150 ft/min
300 ft/min
150 ft/min
Natural Convection
1.5
1.5
Natural Convection
1
0.5
0
1
0.5
0
0
2
4
6
8
0
2
4
6
8
0.3
0.3
2
2
Copper Heat-Sink Size – cm
Copper Heat-Sink Size – cm
(a)
(b)
3.5
T
A
= 105°C
3
2.5
2
1.5
1
150 ft/min
300 ft/min
Natural Convection
0.5
0
0
0.3
2
4
6
8
2
Copper Heat-Sink Size – cm
(c)
Figure 35. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
22
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad ) (continued)
Figure 36 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board
configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and
Figure35. Asdiscussedearlier, copperhasbeenaddedonthePWBtoconductheatawayfromthedevice. R
θJA
for this assembly is illustrated in Figure 34 as a function of heat-sink area. A family of curves is included to
illustrate the effect of airflow introduced into the system.
Heat-Sink Area
1 oz Copper
Board thickness
Board size
62 mils
3.2 in. × 3.2 in.
FR4
Board material
Copper trace/heat sink 1 oz
Exposed pad mounting 63/67 tin/lead solder
Figure 36. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package
From Figure 34, R
power-dissipation limit for the component/PWB assembly, with the equation:
for a PWB assembly can be determined and used to calculate the maximum
θJA
T max * T
J
A
P
+
D(max)
R
(1)
qJA(system)
where
T max is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended
J
operating limit) and T is the ambient temperature.
A
P
should then be applied to the internal power dissipated by the TPS703xx regulator. The equation for
D(max)
calculating total internal power dissipation of the TPS703xx is:
I
I
Q
Q
2
+ ǒVIN1
Ǔ
) ǒVIN2
Ǔ
OUT2
P
* V
I
) V
* V
I
) V
(2)
D(total)
OUT1
OUT1
IN1
OUT2
IN2
2
Since the quiescent current of the TPS703xx is very low, the second term is negligible, further simplifying the
equation to:
+ ǒVIN1
Ǔ
ǒ
Ǔ
(3)
P
* V
I
) V
* V
I
D(total)
OUT1
OUT1
IN2
OUT2
OUT2
2
For the case where T = 55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm , the maximum
A
power-dissipation limit can be calculated. First, from Figure 34, we find the system R
the maximum power-dissipation limit is:
is 50°C/W; therefore,
θJA
T max * T
°
°
J
A
125 C * 55 C
P
+
+
+ TBD W
(4)
D(max)
°
R
TBD CńW
qJA(system)
23
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THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad ) (continued)
If the system implements a TPS703xx regulator, where V = 5 V and I = 800 mA, the internal power dissipation
I
O
is:
+ ǒVIN1
Ǔ
) ǒVIN2
Ǔ
OUT2
(5)
P
* V
I
* V
I
D(total)
OUT1
OUT1
OUT2
+ (4.3 * 3.3) 0.8 ) (2.8 * 1.8) 1 + 1.8 W
Comparing P with P reveals that the power dissipation in this example does not exceed the
D(total)
D(max)
calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit
by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by
reducing the input voltage or the load current. In either case, the above calculations should be repeated with
the new system parameters. This parameter is measured with the recommended copper heat sink pattern on
a 4-layer PCB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both
regulator outputs at full load may exceed the power dissipation rating of the PWP package.
mounting information
The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The
thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.
Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The
data included in Figures 34 and 35 is for soldered connections with voiding between 20% and 50%. The thermal
analysis shows no significant difference resulting from the variation in voiding percentage.
Figure 37 shows the solder-mask land pattern for
Minimum Recommended
Heat-Sink Area
Location of Exposed
Thermal Pad on
PWP Package
the PWP package. The minimum recommended
heat-sink area is also illustrated. This is simply a
copper plane under the body extent of the
package, including metal routed under terminals
1, 12, 13, and 24.
Figure 37. PWP Package Land Pattern
24
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
sequencing timing diagrams
The following figures provide a timing diagram of how this device functions in different configurations.
application conditions not shown in block diagram:
TPS703xxPWP
V
and V
are tied to the same fixed input
(Fixed Output Option)
IN1
IN2
V
OUT1
voltage greater than the V
logic low; PG1 is tied to MR2; MR1 is not used and
; SEQ is tied to
V
I
UVLO
V
OUT1
V
IN1
is connected to V .
IN
0.22 µF
22 µF
V
SENSE1
explanation of timing diagrams:
250 kΩ
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic low, when EN is taken to logic low,
PG1
MR2
MR2
V
IN2
V
turns on. V
turns on after V
OUT1
OUT2 OUT1
0.22 µF
RESET
RESET
MR1
reaches 83% of its regulated output voltage.
When V reaches 95% of its regulated output
voltage, PG1 (tied to MR2) goes to logic high.
When both V and V reach 95% of their
OUT1
MR1
V
IN
EN
EN
>2 V
OUT1
OUT2
respective regulated output voltages and both
MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120 ms delay.
When EN is returned to logic high, both devices
power down and both PG1 (tied to MR2) and
RESET return to logic low.
<0.7 V
V
SENSE2
SEQ
V
OUT2
V
OUT2
47 µF
EN
SEQ
V
OUT2
95%
83%
95%
83%
V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 38. Timing When SEQ = Low
25
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APPLICATION INFORMATION
sequencing timing diagrams (continued)
TPS703xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
I
V
OUT1
V
V
OUT1
IN1
IN2
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
logic high; PG1 is tied to MR2; MR1 is not used
; SEQ is tied to
UVLO
0.22 µF
22 µF
V
SENSE1
and is connected to V .
IN
250 kΩ
PG1
MR2
explanation of timing diagrams:
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic high, when EN is taken to logic low,
0.22 µF
RESET
MR1
RESET
MR1
V
turns on. V
turns on after V
OUT2
OUT1 OUT2
reaches 83% of its regulated output voltage.
When V reaches 95% of its regulated output
V
IN
EN
EN
>2 V
OUT1
voltage, PG1 (tied to MR2) goes to logic high.
When both V and V reach 95% of their
V
SENSE2
<0.7 V
OUT1
OUT2
SEQ
respective regulated output voltages and both
MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120 ms delay.
When EN is returned to logic high, both devices
turn off and both PG1 (tied to MR2) and RESET
return to logic low.
V
OUT2
V
OUT2
47 µF
EN
SEQ
V
V
OUT2
95%
83%
95%
83%
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 39. Timing When SEQ = High
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
sequencing timing diagrams (continued)
TPS703xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
I
V
OUT1
V
V
OUT1
IN1
IN2
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
; SEQ is tied to
0.22 µF
UVLO
22 µF
V
logic high; PG1 is tied to MR2; MR1 is initially at
logic high but is eventually toggled.
SENSE1
250 kΩ
PG1
MR2
explanation of timing diagrams:
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
0.22 µF
RESET
RESET
MR1
SEQ at logic high, when EN is taken low, V
OUT2
turnson.V
turnsonafterV
reaches83%
OUT1
OUT2
MR1
of its regulated output voltage. When V
EN
OUT1
EN
2 V
reaches 95% of its regulated output voltage, PG1
(tiedtoMR2)goestologichigh.WhenbothV
>2 V
0.7 V
OUT1
V
<0.7 V
SENSE2
and V
reach 95% of their respective
OUT2
SEQ
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When MR1 is
taken low, RESET returns to logic low but the
V
OUT2
V
OUT2
47 µF
outputs remain in regulation. When MR1 is returned to logic high, since both V
95% of their respective regulated output voltages and MR2 (tied to PG1) remains at logic high, RESET is pulled
and V
remain above
OUT1
OUT2
to logic high after a 120 ms delay.
EN
SEQ
V
V
95%
83%
OUT2
95%
83%
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120 ms
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 40. Timing When MR1 Is Toggled
27
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
sequencing timing diagrams (continued)
TPS703xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
I
V
OUT1
V
V
OUT1
V
and V
are tied to the same fixed input
IN1
IN2
IN1
IN2
voltage greater than the V
logic high; PG1 is tied to MR2; MR1 is not used
; SEQ is tied to
UVLO
0.22 µF
22 µF
V
SENSE1
and is connected to V .
IN
250 kΩ
explanation of timing diagrams:
PG1
MR2
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic high, when EN is taken low, V
0.22 µF
RESET
MR1
RESET
MR1
OUT2
turnson.V
turnsonafterV
reaches83%
OUT1
OUT2
of its regulated output voltage. When V
OUT1
V
IN
EN
EN
reaches 95% of its regulated output voltage, PG1
(tiedtoMR2)goestologichigh.WhenbothV
>2 V
OUT1
V
SENSE2
<0.7 V
and V
reach 95% of their respective
OUT2
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When a fault on
SEQ
V
OUT2
V
OUT2
47 µF
V
causes it to fall below 95% of its regulated
OUT1
output voltage, PG1 (tied to MR2) goes to logic
low.
EN
SEQUENCE
V
OUT2
OUT1
95%
83%
95%
83%
V
Fault on V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
and V
OUT1
Figure 41. Timing When a Fault Occurs on V
OUT1
28
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
TPS703xxPWP
(Fixed Output Option)
sequencing timing diagrams (continued)
V
I
V
OUT1
application conditions not shown in block diagram:
V
V
OUT1
IN1
IN2
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
logic high; PG1 is tied to MR2; MR1 is not used
; SEQ is tied to
0.22 µF
22 µF
UVLO
V
SENSE1
and is connected to V .
IN
250 kΩ
PG1
MR2
explanation of timing diagrams:
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
0.22 µF
RESET
MR1
RESET
MR1
SEQ at logic high, when EN is taken low, V
OUT2
turnson.V
turnsonafterV
reaches83%
OUT1
OUT2
V
IN
of its regulated output voltage. When V
EN
OUT1
EN
reaches 95% of its regulated output voltage, PG1
>2 V
(tiedtoMR2)goestologichigh.WhenbothV
V
OUT1
SENSE2
<0.7 V
and V
reach 95% of their respective
OUT2
SEQ
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When a fault on
V
OUT2
V
OUT2
47 µF
V
causes it to fall below 95% of its regulated
OUT2
outputvoltage,RESETreturnstologiclowandV
beginstopowerdownbecauseSEQishigh.WhenV
OUT1
OUT1
falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to logic low.
ENABLE
SEQUENCE
95%
83%
V
V
OUT2
Fault on V
OUT2
95%
83%
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
(see Note A)
NOTE A: t1 – Time at which both V
and V
OUT1
Figure 42. Timing When a Fault Occurs on V
OUT2
29
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
split voltage DSP application
Figure 43 shows a typical application where the TPS70351 is powering up a DSP. In this application, by grounding
the SEQ pin, V
(I/O) is powered up first, and then V
(core).
OUT1
OUT2
TPS70351 PWP
DSP
I/O
3.3 V
V
OUT1
5 V
V
IN1
IN2
22 µF
0.22 µF
250 kΩ
PG1
V
SENSE1
PG1
MR2
MR2
V
IN
IN
V
250 kΩ
0.22 µF
RESET
RESET
MR1
MR1
EN
>2 V
V
EN
<0.7 V
V
SENSE2
SEQ
1.8 V
V
OUT2
Core
47 µF
EN
SEQ
V
OUT2
95%
(Core)
83%
V
OUT1
(I/O)
95%
83%
PG1
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V
120ms
and V
out2
are greater than the PG1 thresholds and MR1 is logic high.
out1
Figure 43. Application Timing Diagram (SEQ = Low)
30
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APPLICATION INFORMATION
split voltage DSP application (continued)
Figure 44 shows a typical application where the TPS70351 is powering up a DSP. In this application, by pulling
up the SEQ pin, V
(Core) is powered up first, and then V
(I/O).
OUT2
OUT1
TPS70351 PWP
DSP
I/O
5 V
3.3 V
V
OUT1
V
IN1
IN2
22 µF
0.22 µF
250 kΩ
V
SENSE1
PG1
PG1
MR2
MR2
MR1
V
IN
V
250 kΩ
0.22 µF
RESET
RESET
MR1
V
IN
EN
>2 V
EN
<0.7 V
V
SENSE2
SEQ
1.8 V
V
OUT2
Core
47 µF
EN
SEQ
V
OUT2
95%
83%
(Core)
95%
83%
V
OUT1
(I/O)
PG1
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V
120ms
and V
out2
are greater than the PG1 thresholds and MR1 is logic high.
out1
Figure 44. Application Timing Diagram (SEQ = High)
31
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SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
input capacitor
For a typical application, a ceramic input bypass capacitor (0.22 µF – 1 µF) is recommended to ensure device
stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply,
large transient currents causes the input voltage to droop. If this droop causes the input voltage to drop below
the UVLO threshold, the device turns off. Therefore, it is recommended that a larger capacitor be placed in
parallel with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor depends on the
output current, response time of the main power supply, and the main power supply’s distance to the regulator.
At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum
UVLO threshold voltage during normal operating conditions.
output capacitor
As with most LDO regulators, the TPS703xx requires an output capacitor connected between each OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value for V
is 22 µF
OUT1
and the ESR (equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended
capacitance value for V is 47 µF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic,
OUT2
aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements
described above. Larger capacitors provide a wider range of stability and better load transient response. Below
is a partial listing of surface-mount capacitors usable with the TPS703xx for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
VALUE
680 µF
470 µF
150 µF
220 µF
100 µF
68 µF
MFR.
Kemet
Sanyo
Sanyo
Sanyo
Sanyo
Sanyo
Kemet
Kemet
Kemet
Kemet
PART NO.
T510X6871004AS
4TPB470M
4TPC150M
2R5TPC220M
6TPC100M
10TPC68M
68 µF
T495D6861006AS
T495D4761010AS
T495C3361016AS
T495C2261010AS
47 µF
33 µF
22 µF
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
programming the TPS70302 adjustable LDO regulator
The output voltage of the TPS70302 adjustable regulators is programmed using external resistor dividers as
shown in Figure 45.
Resistors R1 and R2 should be chosen for approximately 50 µA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at the sense terminal increase the output voltage error. The recommended design procedure is to
choose R2 = 30.1 kΩ to set the divider current at approximately 50 µA and then calculate R1 using:
V
O
(6)
R1 +
ǒ
* 1
Ǔ
R2
V
ref
where
V
= 1.224 V typ (the internal reference voltage)
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS70302
OUTPUT
VOLTAGE
V
I
R1
R2
UNIT
IN
0.1 µF
2.5 V
3.3 V
3.6 V
31.6
51.1
59.0
30.1
30.1
30.1
kΩ
kΩ
kΩ
>2.0 V
EN
OUT
FB
V
O
<0.7V
+
R1
GND
R2
Figure 45. TPS70302 Adjustable LDO Regulator Programming
regulator protection
Both TPS703xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS703xx also features internal current limiting and thermal protection. During normal operation, the
TPS703xx regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current
to approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator
operation resumes.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70345, TPS70348, TPS70351, TPS70358, TPS70302
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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