TPS70751MPWPREP [TI]
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS; 与上电顺序使用驳电压DSP系统双输出低压差稳压器
| 型号： | TPS70751MPWPREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS |
| 文件： | 总41页 (文件大小：988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
FEATURES
•
Controlled Baseline
•
•
•
Ultralow 190-µA (Typ) Quiescent Current
1-µA Input Current During Standby
–
One Assembly/Test Site, One Fabrication
Site
Low Noise: 65 µVrms Without Bypass
•
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Capacitor
•
•
•
•
•
Quick Output Capacitor Discharge Feature
Two Manual Reset Inputs
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
Dual Output Voltages for Split-Supply
Applications
20-Pin PowerPAD™ Thin Shrink Small-Outline
Package (TSSOP)
•
•
Selectable Power-Up Sequencing for DSP
Applications (See Part Number TPS708xx for
Independently Enabled Outputs)
•
Thermal Shutdown Protection
PWP PACKAGE
(TOP VIEW)
Output Current Range of 250 mA on
Regulator 1 and 125 mA on Regulator 2
•
•
•
Fast Transient Response
NC
VIN1
1
20
19
18
17
16
15
14
13
12
11
NC
2
3.3-V/1.8-V Fixed Voltage Outputs
VOUT1
3
VIN1
VOUT1
Open-Drain Power-On Reset With 120-ms
Delay
4
MR1
MR2
EN
VSENSE1/FB1
PG1
5
•
Open-Drain Power Good for Regulator 1
6
RESET
VSENSE2/FB2
VOUT2
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
7
SEQ
GND
VIN2
8
9
VOUT2
10
VIN2
NC
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
xxxxx
DESCRIPTION
The TPS707xx family devices are designed to provide a complete power-management solution for TI DSP,
processor power, ASIC, FPGA, and digital applications where dual-output voltage regulators are required. Easy
programmability of the sequencing function makes this family ideal for any TI DSP applications with
power-sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS
supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system
solution.
The TPS707xx family of voltage regulators offer very low dropout (LDO) voltage and dual outputs with power-up
sequence control, which is designed primarily for DSP applications. These devices have extremely low noise
output performance without using any added filter bypass capacitors, and are designed to have a fast transient
response and be stable with 10-µF low ESR capacitors.
The TPS70751 has a fixed voltage of 3.3 V/1.8 V. Regulator 1 can support up to 250 mA and regulator 2 can
support up to 125 mA. Separate voltage inputs allow the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV on
regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a
voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA
over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN
(enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
TPS70751 PWP
DSP
I/O
3.3 V
VOUT1
5 V
VIN1
10 mF
0.1 mF
VSENSE1
250 kW
PG1
PG1
MR2
MR2
>2 V
VIN2
250 kW
<0.7 V
0.1 mF
RESET
RESET
MR1
MR1
EN
<0.7 V
>2 V
EN
>2 V
<0.7 V
VSENSE2
SEQ
1.8 V
Core
VOUT2
10 mF
The device is enabled when the enable (EN) pin is connected to a low-level input voltage. The output voltages of
the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.
The input signal at the sequence (SEQ) pin controls the power-up sequence of the two regulators. When the
device is enabled and SEQ is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2
reaches approximately 83% of its regulated output voltage. At that time, VOUT1 is turned on. If VOUT2 is pulled
below 83% (i.e., overload condition), VOUT1 is turned off. Pulling SEQ low reverses the power-up order and VOUT1
is turned on first. SEQ is connected to an internal pullup current source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The power good (PG1) pin reports the voltage conditions at VOUT1. Power good can be used to implement a
SVS for the circuitry supplied by regulator 1.
The TPS70751 features a RESET (SVS, POR, or power-on reset). The RESET output initiates a reset in DSP
systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of
VOUT2 and both manual reset (MR1 and MR2) pins. When VOUT2 reaches 95% of its regulated voltage and MR1
and MR2 are in the logic high state, RESET goes to a high-impedance state after a 120-ms delay. RESET goes
to logic low state when VOUT2 regulated output voltage is pulled below 95% (i.e., overload condition) of its
regulated voltage. To monitor VOUT1, the PG1 output can be connected to MR1 or MR2.
The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until
VIN1 reaches 2.5 V.
AVAILABLE OPTIONS
REGULATOR 1
VO (V)
REGULATOR 2
VO (V)
TSSOP
(PWP)
TJ
–55°C to 125°C
3.3 V
1.8 V
TPS70751MPWPREP
2
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
DETAILED BLOCK DIAGRAM – FIXED-VOLTAGE VERSION
VIN1 (2 Pins)
VOUT1 (2 Pins)
10 kW
Current
Sense
ENA_1
VSENSE1
(see Note A)
UVLO
Shutdown
ENA_1
2.5 V
-
+
Vref
Reference
FB1
GND
Thermal
Shutdown
Vref
PG1
FB1
0.95 ´ Vref
Rising Edge
Deglitch
VIN1
MR2
Shutdown
RESET
FB2
Falling Edge
Delay
Rising Edge
Deglitch
UV Comp
0.95 ´ Vref
FB2
Falling Edge
VIN1
0.83 ´ Vref
Deglitch
ENA_1
Power
Sequence
Logic
FB1
ENA_2
Vref
MR1
Falling Edge
Deglitch
FB2
0.83 ´ Vref
-
UV Comp
+
ENA_2
EN
VIN1
VSENSE2
ENA_2
Current
Sense
(see Note A)
10 kW
SEQ
(see Note B)
VOUT2 (2 Pins)
VIN2 (2 Pins)
NOTES: A. For most applications, V
and V
should be externally connected to V
as close as possible to the device.
SENSE1
SENSE2
OUT
For other implementations, refer to the SENSE terminal connection discussion in the Application Information section.
B. If the SEQ terminal is floating at the input, V powers up first.
OUT2
3
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
RESET TIMING DIAGRAM (WITH VIN1 POWERED UP AND MR1 AND MR2 AT LOGIC HIGH)
VIN2
VRES
VRES
(see Note A)
t
VOUT2
VIT+ (see Note B)
VIT+ (see Note B)
Threshold
Voltage
VIT–
(see Note B)
VIT–
(see Note B)
t
RESET
Output
120-ms
Delay
120-ms
Delay
Output
Undefined
Output
Undefined
t
NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or
JEDEC standards for semiconductor symbology.
B. VIT – Trip voltage is typically 5% lower than the output voltage (95% VO); VIT– to VIT+ is the hysteresis voltage.
PG1 TIMING DIAGRAM
VIN1
VUVLO
VUVLO
VPG1
VPG1
(see Note A)
t
VOUT2
VIT+ (see Note B)
VIT+ (see Note B)
Threshold
Voltage
VIT –
(see Note B)
VIT–
(see Note B)
30 ms
t
PG1
Output
Output
Undefined
Output
Undefined
t
NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or
JEDEC standards for semiconductor symbology.
B. VIT – Trip voltage is typically 5% lower than the output voltage (95% VO); VIT– to VIT+ is the hysteresis voltage.
4
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
NO.
EN
6
I
Active-low enable
Ground
GND
MR1
MR2
NC
8
4
5
I
I
Manual reset 1. Active low, pulled up internally.
Manual reset 2. Active low, pulled up internally.
No connection
1, 11, 20
Power good. Open-drain output, low when VOUT1 voltage is less than 95% of the nominal
regulated voltage.
PG1
16
15
7
O
O
I
RESET
SEQ
Reset. Open-drain output, SVS (power-on reset) signal, active low.
Power up sequence control: SEQ = High, VOUT2 powers up first; SEQ = Low, VOUT1 powers
up first, SEQ terminal pulled up internally.
VIN1
2, 3
9, 10
18, 19
12, 13
17
I
I
Regulator 1 input voltage
VIN2
Regulator 2 input voltage
VOUT1
O
O
I
Regulator 1 output voltage
VOUT2
Regulator 2 output voltage
VSENSE1/FB1
VSENSE2/FB2
Regulator 1 output voltage sense/feedback 1
Regulator 2 output voltage sense/feedback 2
14
I
DETAILED DESCRIPTION
The TPS707xx low-dropout regulator family provides dual regulated output voltages for DSP applications that
require a high-performance power-management solution. These devices provide fast transient response and
high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing
provides a power solution for DSPs, without any external component requirements. This reduces the component
cost and board space while increasing total system reliability. The TPS707xx family has an enable feature that
puts the device in sleep mode, reducing the input currents to less than 3 µA. Other features are integrated SVS
(power-on reset, RESET) and power good (PG1) that monitor output voltages and provide logic output to the
system. These differentiated features provide a complete DSP power solution.
The TPS70751, unlike many other LDOs, features very low quiescent current that remains virtually constant
even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). The TPS70751 uses a PMOS transistor
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the full
load range.
Pin Functions
Enable (EN)
The EN terminal is an input that enables or shuts down the device. If EN is at a voltage high signal, the device is
in shutdown mode. When EN goes to voltage low, the device is enabled.
Sequence (SEQ)
The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2) is turned on first. When the
device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off
until VOUT2 reaches approximately 83% of its regulated output voltage. At that time, the VOUT1 is turned on. If
VOUT2 is pulled below 83% (i.e., overload condition), VOUT1 is turned off. This terminal has a 6-µA pullup current
to VIN1
.
Pulling SEQ low reverses the power-up order and VOUT1 is turned on first. For detailed timing diagrams, see
Figure 33 and Figure 38.
5
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
Power Good (PG1)
The PG1 terminal is an open-drain, active-high output terminal that indicates the status of the VOUT1 regulator.
When the VOUT1 reaches 95% of its regulated voltage, PG1 goes into a high-impedance state. PG1 goes into a
low-impedance state when VOUT1 is pulled below 95% (i.e., overload condition), of its regulated voltage. The
open-drain output of the PG1 terminal requires a pullup resistor.
Manual Reset (MR1 and MR2)
MR1 and MR2 are active-low input terminals used to trigger a reset condition. When either MR1 or MR2 is
pulled to logic low, a POR (RESET) occurs. These terminals have a 6-µA pullup current to VIN1
.
Sense (VSENSE1, VSENSE2
)
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers through
a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route the
sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the VSENSE
terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate.
Feedback (FB1 and FB2)
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and VOUT
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
RESET Indicator
The TPS70751 features a RESET (SVS, POR, or power-on reset). RESET can be used to drive power-on reset
circuitry or a low-battery indicator. RESET is an active-low, open-drain output that indicates the status of the
VOUT2 regulator and both manual reset (MR1 and MR2) pins. When VOUT2 exceeds 95% of its regulated voltage,
and MR1 and MR2 are in the high-impedance state, RESET goes to a high-impedance state after a 120-ms
delay. RESET goes to a low-impedance state when VOUT2 is pulled below 95% (i.e., overload condition) of its
regulated voltage. To monitor VOUT1, the PG1 output can be connected to MR1 or MR2. The open-drain output
of RESET requires a pullup resistor. If RESET is not used, it can be left floating.
Input Voltage (VIN1 and VIN2
)
VIN1 and VIN2 are inputs to the regulators. Internal bias voltages are powered by VIN1
.
Output Voltage (VOUT1 and VOUT2
)
VOUT1 and VOUT2 are output terminals.
6
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
Absolute Maximum Ratings(1)
over operating junction temperature (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
MAX UNIT
VIN1
7
V
7
Input voltage range(2)
VIN2
Voltage range at EN
7
V
VOUT1
VSENSE1
,
5.5
Output voltage
V
VOUT2
,
5.5
VSENSE2
Maximum RESET and PG1 voltage
Maximum MR1, MR2, and SEQ voltage
Peak output current
7
V
V
VIN1
Internally Limited
See Dissipation Rating Tables
Continuous total power dissipation
Operating virtual junction temperature range
Storage temperature range
TJ
–55
–65
150
150
2
°C
°C
kV
Tstg
ESD rating
Human-Body Model (HBM)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are tied to network ground.
Dissipation Ratings
AIR FLOW
(CFM)
DERATING
FACTOR
PACKAGE
TA ≤ 25°C
TA = 70°C
TA = 85°C
0
3.067 W
4.115 W
30.67 mW/°C
41.15 mW/°C
1.687 W
2.265 W
1.227 W
4.646 W
PWP(1)
250
(1) This parameter is measured with the recommended copper heatsink pattern on a four-layer PCB, 1-oz copper on 4-in × 4-in ground
layer. For more information, refer to TI technical brief SLMA002.
Recommended Operating Conditions
MIN
2.7
0
MAX UNIT
VI
IO
TJ
Input voltage(1)
6
250
125
125
V
Regulator 1
Regulator 2
Output current
mA
°C
0
Operating virtual junction temperature
–55
(1) To calculate the minimum input voltage for maximum output current, use VI(min) = VO(max) + VDO(max load)
.
7
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
Electrical Characteristics
over recommended operating junction temperature (TJ = –55°C to 125°C), VIN1 or VIN2 = VO(nom) + 1 V, IO = 1 mA, EN = 0,
CO = 33 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.22
1.8
MAX
UNIT
Reference
voltage
2.7 V < VI < 6 V, FB connected to VO,
TJ = 25°C
2.8 V < VI < 6 V, TJ = 25°C
2.8 V < VI < 6 V
1.8-V output
3.3-V output
VO
Output voltage(1)(2)
V
1.764
3.234
1.836
3.366
230
4.3 V < VI < 6 V, TJ = 25°C
4.3 V < VI < 6 V
3.3
190
TJ = 25°C
Quiescent current (GND current) for regulator 1 and
regulator 2, EN = 0 V(1)(2)
µA
VO + 1 V < VI ≤ 6 V, TJ = 25°C
VO + 1 V < VI ≤ 6 V
TJ = 25°C
0.01%
Output voltage line regulation (∆VO/VO) for regulator
V
1 and regulator 2(3)(2)
0.1%
(1)
Load regulation for VOUT1 and VOUT2
1
65
mV
Regulator 1
BW = 300 Hz to 50 kHz,
CO = 33 µF, TJ = 25°C
Vn
Output noise voltage
µVrms
Regulator 2
Regulator 1
Regulator 2
65
1.6
2.1
1.1
Output current limit
VO = 0 V
A
0.750
150
Thermal shutdown junction temperature
°C
µA
dB
EN = VI, TJ = 25°C
EN = VI
2
6
Regulator 1 and
II(standby) Standby current
Regulator 2
Power-supply ripple rejection
PSRR
f = 1 kHz, CO = 33 µF, TJ = 25°C
60
(1) IO = 1 mA to 250 mA for regulator 1 and 1 mA to 125 mA for regulator 2
(2) Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output current
1 mA.
(3) If VO < 1.8 V, then VI(max) = 6 V, VI(min) = 2.7 V:
VO(VI(max) * 2.7 V)
Line regulation (mV) + (%ńV)
1000
100
If VO > 2.5 V, then VI(max) = 6 V, VI(min) = Vo + 1 V:
VO[VI(max) * (VO ) 1)]
Line regulation (mV) + (%ńV)
1000
100
8
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
Electrical Characteristics (continued)
over recommended operating junction temperature (TJ = –55°C to 125°C), VIN1 or VIN2 = VO(nom) + 1 V, IO = 1 mA, EN = 0,
CO = 33 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET
Minimum input voltage for valid RESET
Trip threshold voltage
Hysteresis voltage
t(RESET)
I(RESET) = 300 µA, V(RESET) ≤ 0.8 V
VO decreasing
1
95%
0.5%
120
1.3
V
92%
80
98%
VO
VO
ms
µs
V
Measured at VO
RESET pulse duration
Rising-edge deglitch
VI = 3.5 V, I(RESET) = 1 mA
V(RESET) = 6 V
160
tr(RESET)
30
Output low voltage
Leakage current
0.15
0.4
1
µA
PG1
Minimum input voltage for valid PG1
Trip threshold voltage
Hysteresis voltage
tf(PG1)
IO(PG1) = 300 µA, V(PG1) ≤ 0.8 V
VO decreasing
1
95%
0.5%
30
1.3
V
92%
98%
VO
VO
µs
V
Measured at VO
Falling-edge deglitch
VI = 2.7 V, I(PG1) = 1 mA
V(PG1) = 6 V
Output low voltage
Leakage current
0.15
0.4
1
µA
EN
High-level EN input voltage
Low-level EN input voltage
Input current (EN)
SEQ
2
–1
2
V
V
0.7
1
µA
High-level SEQ input voltage
Low-level SEQ input voltage
SEQ pullup current source
MR1/MR2
V
V
0.7
6
6
µA
High-level MR1/MR2 input voltage
Low-level MR1/MR2 input voltage
MR1/MR2 pullup current source
VOUT2
2
V
V
0.7
µA
VOUT2 UV comparator – positive-going input
threshold voltage of VOUT1 UV comparator
83%
VO
80% VO
86% VO
V
VOUT2 UV comparator – falling-edge deglitch
Peak output current
VSENSE2 decreasing below threshold
2-ms pulse width
140
375
7.5
µs
mA
mA
Discharge transistor current
VOUT1
VOUT2 = 1.5 V
VOUT1 UV comparator – positive-going input
threshold voltage of VOUT1 UV comparator
83%
VO
80% VO
86% VO
V
0.5%
VO
VOUT1 UV comparator – hysteresis
mV
VOUT1 UV comparator – falling-edge deglitch
VSENSE1 decreasing below threshold
IO = 250 mA, VIN1 = 3.2 V, TJ = 25°C
IO = 250 mA, VIN1 = 3.2 V
2-ms pulse width
140
83
µs
Dropout voltage(4)
mV
140
Peak output current
Discharge transistor current
UVLO threshold
750
7.5
mA
mA
V
VOUT1 = 1.5 V
2.4
2.65
(4) Input voltage (VIN1 or VIN2) = VO(typ) – 100 mV. For 1.8-V regulators, the dropout voltage is limited by the input voltage range. The 3.3-V
regulator input voltage is to 3.2 V to perform this test.
9
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TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
www.ti.com
SLVS718–DECEMBER 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
1, 2
vs Output current
Output voltage
vs Junction temperature
3–6
Ground current
vs Junction temperature
vs Frequency
7
Power-supply rejection ratio
Output spectral noise density
Output impedance
8–11
12–15
16–19
20, 21
22, 23
24, 25
26, 27
vs Frequency
vs Frequency
Dropout voltage
vs Junction temperature
Load transient response
Line transient response
Output voltage
vs Time (start-up)
vs Output current
Equivalent series resistance
(ESR)
29–32
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
1.802
3.303
3.302
3.301
3.3
V
= 2.8 V
V
= 4.3 V
IN2
IN1
T = 25°C
T = 25°C
J
J
1.801
V
OUT2
V
OUT1
1.800
1.799
1.798
1.797
3.299
3.298
3.297
1.796
1.795
3.296
3.295
0
0.025
0.05
0.075
0.1
0.125
0
0.05
0.1
0.15
0.2
0.25
I
O
− Output Current − A
I
O
− Output Current − A
Figure 1.
Figure 2.
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OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
3.35
3.33
3.35
3.33
V
= 4.3 V
= 250 mA
IN1
V
= 4.3 V
= 1 mA
IN1
I
O
I
O
V
OUT1
V
OUT1
3.31
3.29
3.31
3.29
3.27
3.27
3.25
3.23
3.25
3.23
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 3.
Figure 4.
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.800
1.798
1.799
V
= 2.8 V
= 1 mA
IN2
V
= 2.8 V
= 125 mA
IN2
I
O
I
O
1.798
1.797
1.796
1.795
1.794
1.793
V
OUT2
V
OUT2
1.796
1.794
1.792
1.790
1.792
1.791
1.790
1.788
1.786
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 5.
Figure 6.
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GROUND CURRENT
vs
JUNCTION TEMPERATURE
210
Regulator 1 and Regulator 2
200
I
I
= 1 mA
= 1 mA
OUT1
OUT2
190
180
170
I
I
= 250 mA
= 125 mA
OUT1
OUT2
160
150
−40 −25 −10
5
20 35 50 65 80 95 110 125
T − Junction Temperature − °C
J
Figure 7.
POWER-SUPPLY REJECTION RATIO
POWER-SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
−10
I
C
V
= 250 mA
I
C
V
= 10 mA
O
O
0
−10
−20
= 22 µF
= 22 µF
−20
−30
−40
O
O
OUT1
OUT1
−30
−40
−50
−50
−60
−70
−60
−70
−80
−90
−80
−90
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
f − Frequency − Hz
Figure 8.
Figure 9.
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POWER-SUPPLY REJECTION RATIO
POWER-SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
−10
I
I
C
V
= 150 mA
O
= 10 mA
0
−10
−20
O
= 22 µF
O
C
V
= 22 µF
−20
O
OUT2
OUT2
−30
−40
−30
−40
−50
−60
−70
−50
−60
−70
−80
−90
−80
−90
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
f − Frequency − Hz
Figure 10.
Figure 11.
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
V
I
= 4.3 V
= 3.3 V
= 10 mA
V
V
I
= 4.3 V
= 3.3 V
= 250 mA
IN1
OUT1
IN1
OUT1
O
O
1
1
0.1
0.01
0.1
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f − Frequency − Hz
f − Frequency − Hz
Figure 12.
Figure 13.
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OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
V
I
= 2.8 V
= 1.8 V
= 125 mA
V
= 2.8 V
= 1.8 V
= 10 mA
IN2
OUT2
IN2
V
I
OUT2
O
O
1
1
0.1
0.1
0.01
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f − Frequency − Hz
f − Frequency − Hz
Figure 14.
Figure 15.
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
10
100
C
I
= 33 µF
= 250 mA
C
I
= 33 µF
= 10 mA
O
O
O
O
V
OUT1
= 3.3 V
V
OUT1
= 3.3 V
T = 25°C
J
T = 25°C
J
10
1
1
0.1
0.01
0.1
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 16.
Figure 17.
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OUTPUT IMPEDANCE
OUTPUT IMPEDANCE
vs
vs
FREQUENCY
FREQUENCY
10
100
C
O
= 33 µF
C = 33 µF
O
I
O
= 125 mA
I = 10 mA
O
V
OUT2
= 1.8 V
V
OUT2
= 1.8 V
T = 25°C
J
T = 25°C
J
10
1
1
0.1
0.01
0.1
10
10
100
1 k
10 k
100 k
1 M
10 M
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 18.
Figure 19.
DROPOUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
6
5
120
C
= 33 µF
= 3.2 V
C
V
= 33 µF
O
O
V
IN1
= 3.2 V
IN1
100
I
O
= 10 mA
I
O
= 250 mA
80
60
40
4
3
2
20
0
1
0
I
O
= 0 mA
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 20.
Figure 21.
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LOAD TRANSIENT RESPONSE
= 33 µF
LOAD TRANSIENT RESPONSE
= 33 µF
C
O
C
O
T = 25°C
T = 25°C
250
0
J
125
0
J
V
OUT1
= 3.3 V
V
OUT2
= 1.8 V
20
0
20
0
−20
−40
−20
−40
−60
−80
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − ms
t − Time − ms
Figure 22.
Figure 23.
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
3.8
2.8
5.3
4.3
50
0
10
0
I
O
= 125 mA
I
O
= 250 mA
−50
C
= 33 µF
O
C
V
= 33 µF
−10
O
V
OUT2
OUT1
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
t − Time − µs
t − Time − µs
Figure 24.
Figure 25.
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OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME (START-UP)
TIME (START-UP)
V
= 1.8 V
= 33 µF
= 125 mA
V
C
= 3.3 V
= 33 µF
= 250 mA
O
O
3
2
2
1
C
I
O
O
I
O
O
V
OUT2
V
OUT1
SEQ = High
SEQ = Low
1
0
0
−1
5
5
0
0
−5
−5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − ms
t − Time − ms
Figure 26.
Figure 27.
To Load
IN
VI
OUT
+
R
CO
ESR
RL
EN
GND
Figure 28. Test Circuit for Typical Regions of Stability
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TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
†
†
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
V
C
= 3.3 V
= 10 µF
O
V
O
= 3.3 V
O
C
O
= 6.8 µF
T = 25°C
J
T = 25°C
J
1
1
0.1
50 mΩ
250 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
0.1
0.01
0
50
100
150
200
250
0
50
100
150
200
250
I
O
− Output Current − mA
I
O
− Output Current − mA
Figure 29.
Figure 30.
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1)
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
(1)
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
V
C
= 1.8 V
= 6.8 µF
O
V
C
= 1.8 V
= 10 µF
O
O
O
T = 25°C
J
T = 25°C
J
1
1
0.1
50 mΩ
250 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
0.1
0.01
0
25
50
75
100
125
0
25
50
I − Output Current − mA
O
75
100
125
I
O
− Output Current − mA
(1)
(1)
Equivalent series resistance (ESR) refers to the total series
Equivalent series resistance (ESR) refers to the total series
resistance, including the ESR of the capacitor, any series
resistance, including the ESR of the capacitor, any series
resistance added externally, and PWB trace resistance to C .
O
resistance added externally, and PWB trace resistance to C .
O
Figure 31.
Figure 32.
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION
Sequencing Timing Diagrams
The following figures provide timing diagrams showing how this device functions in different configurations.
Application Conditions Not Shown in Block Diagram
VIN1 and VIN2 are tied to the same fixed-input voltage greater than the VUVLO, SEQ is tied to logic low, PG1 is
tied to MR2, and MR1 is left unconnected and is, therefore, at logic high.
TPS70751PWP
(Fixed-Output Option)
VI
VOUT1
VOUT1
VIN1
10 mF
0.1 mF
VSENSE1
250 kW
Pg1
MR2
MR2
VIN2
0.1 mF
RESET
MR1
RESET
MR1
EN
EN
>2 V
<0.7 V
VSENSE2
SEQ
VOUT2
VOUT2
10 mF
Explanation of Timing Diagram
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
low, when EN is taken to logic low, VOUT1 turns on. VOUT2 turns on after VOUT1 reaches 83% of its regulated
output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high.
When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When EN is returned to logic
high, both devices power down and both PG1 (tied to MR2) and RESET return to logic low.
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APPLICATION INFORMATION (continued)
EN
SEQ
VOUT2
95%
83%
95%
83%
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 33. Timing When SEQ = Low
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Application Conditions Not Shown in Block Diagram
VIN1 and VIN2 are tied to the same fixed-input voltage greater than the VUVLO, SEQ is tied to logic high, PG1 is
tied to MR2, and MR1 is left unconnected and is, therefore, at logic high.
TPS70751PWP
(Fixed-Output Option)
VI
VOUT1
VOUT1
VIN1
10 mF
0.1 mF
VSENSE1
250 kW
Pg1
MR2
MR2
VIN2
0.1 mF
RESET
MR1
RESET
MR1
EN
EN
>2 V
<0.7 V
VSENSE2
SEQ
VOUT2
VOUT2
10 mF
Explanation of Timing Diagram
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken to logic low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated
output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high.
When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When EN is returned to logic
high, both devices turn off and both PG1 (tied to MR2) and RESET return to logic low.
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APPLICATION INFORMATION (continued)
EN
SEQ
VOUT2
95%
83%
95%
83%
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120ms
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 34. Timing When SEQ = High
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Application Conditions Not Shown in Block Diagram
VIN1 and VIN2 are tied to the same fixed-input voltage greater than the VUVLO, SEQ is tied to logic high, PG1 is
tied to MR2, and MR1 is initially at logic high but is eventually toggled.
TPS70751PWP
(Fixed Output Option)
VI
VOUT1
VOUT1
VIN1
10 mF
0.1 mF
VSENSE1
250 kW
Pg1
MR2
MR2
VIN2
0.1 mF
RESET
RESET
MR1
MR1
EN
EN
>2 V
<0.7 V
>2 V
<0.7 V
VSENSE2
SEQ
VOUT2
VOUT2
10 mF
Explanation of Timing Diagram
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When MR1 is taken low, RESET
returns to logic low but the outputs remain in regulation. When MR1 is returned to logic high, since both VOUT1
and VOUT2 remain above 95% of their respective regulated output voltages and MR2 (tied to PG1) remains at
logic high, RESET is pulled to logic high after a 120-ms delay.
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
EN
SEQ
VOUT2
95%
83%
95%
83%
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
120 ms
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 35. Timing When MR1 Is Toggled
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Application Conditions Not Shown in Block Diagram
VIN1 and VIN2 are tied to the same fixed-input voltage greater than the VUVLO, SEQ is tied to logic high, PG1 is
tied to MR2, and MR1 is left unconnected and is, therefore, at logic high.
TPS70751PWP
(Fixed-Output Option)
VI
VOUT1
VOUT1
VIN1
10 mF
0.1 mF
VSENSE1
250 kW
Pg1
MR2
MR2
VIN2
0.1 mF
RESET
MR1
RESET
MR1
EN
EN
>2 V
<0.7 V
VSENSE2
SEQ
VOUT2
VOUT2
10 mF
Explanation of Timing Diagram
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When a fault on VOUT1 causes it to
fall below 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic low, causing RESET to return to
logic low. VOUT2 remains on because SEQ is high.
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
EN
SEQUENCE
VOUT2
95%
83%
95%
83%
VOUT1
Fault on VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 36. Timing When VOUT1 Faults Out
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Application Conditions Not Shown in Block Diagram
VIN1 and VIN2 are tied to the same fixed-input voltage greater than the VUVLO, SEQ is tied to logic high, PG1 is
tied to MR2, and MR1 is left unconnected and is, therefore, at logic high.
TPS70751PWP
(Fixed-Output Option)
VI
VOUT1
VOUT1
VIN1
10 mF
0.1 mF
VSENSE1
250 kW
Pg1
MR2
MR2
VIN2
0.1 mF
RESET
MR1
RESET
MR1
EN
EN
>2 V
<0.7 V
VSENSE2
SEQ
VOUT2
VOUT2
10 mF
Explanation of Timing Diagram
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When a fault on VOUT2 causes it to
fall below 95% of its regulated output voltage, RESET returns to logic low and VOUT1 begins to power down
because SEQ is high. When VOUT1 falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to
logic low.
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
ENABLE
SEQUENCE
95%
83%
VOUT2
Fault on VOUT2
95%
83%
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
120 ms
(see Note A)
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 37. Timing When VOUT2 Faults Out
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Split Voltage DSP Application
Figure 38 shows a typical application where the TPS70751 is powering up a DSP. In this application, by
grounding the SEQ pin, VOUT1(I/O) is powered up first, and then VOUT2(core) is powered up.
TPS70751 PWP
DSP
I/O
3.3 V
VOUT1
5 V
VIN1
10 mF
0.1 mF
250 kW
VSENSE1
PG1
PG1
MR2
MR2
>2 V
<0.7 V
VIN2
250 kW
0.1 mF
RESET
RESET
MR1
MR1
EN
>2 V
<0.7 V
>2 V
EN
<0.7 V
VSENSE2
SEQ
1.8 V
VOUT2
Core
10 mF
EN
SEQ
VOUT2
(Core)
95%
83%
VOUT1
(I/O)
95%
83%
PG1
RESET
t1
(see Note A)
120 ms
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 38. Application Timing Diagram (SEQ = Low)
29
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Figure 39 shows a typical application where the TPS70751 is powering up a DSP. In this application, by pulling
up the SEQ pin, VOUT2(core) is powered up first, and then VOUT1(I/O) is powered up.
TPS70751 PWP
DSP
I/O
5 V
3.3 V
VOUT1
VIN1
10 mF
0.1 mF
250 kW
VSENSE1
PG1
PG1
MR2
MR2
>2 V
<0.7 V
VIN2
250 kW
0.1 mF
RESET
RESET
MR1
MR1
>2 V
<0.7 V
EN
>2 V
<0.7 V
EN
VSENSE2
SEQ
1.8 V
VOUT2
Core
10 mF
EN
SEQ
VOUT2
(Core)
95%
83%
95%
83%
VOUT1
(I/O)
PG1
RESET
t1
120 ms
(see Note A)
NOTE : A. t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 39. Application Timing Diagram (SEQ = High)
30
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SLVS718–DECEMBER 2006
APPLICATION INFORMATION (continued)
Input Capacitor
For a typical application, an input bypass capacitor (0.1 µF through 1 µF) is recommended. This capacitor filters
any high-frequency noise generated in the line. For fast transient condition where droop at the input of the LDO
may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size
of this capacitor is dependant on the output current and response time of the main power supply, as well as the
distance to the VI pins of the LDO.
Output Capacitor
As with most LDO regulators, the TPS70751 requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance values are 10-µF ceramic capacitors
with an equivalent series resistance (ESR) between 50 mΩ and 2.5 Ω, or 6.8-µF tantalum capacitors with ESR
between 250 mΩ and 4 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors
with capacitance values greater than 10 µF are all suitable, provided they meet the requirements previously
described. Larger capacitors provide a wider range of stability and better load transient response. The following
is a partial listing of surface-mount capacitors usable with the TPS70751 for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user's application. When it is necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet the previous guidelines.
VALUE
22 µF
33 µF
47 µF
68 µF
MFR.
Kemet
Sanyo
Sanyo
Sanyo
MAX ESR
345 mΩ
100 mΩ
100 mΩ
45 mΩ
PART NO.
7495C226K0010AS
10TPA33M
6TPA47M
10TPC68M
ESR and Transient Response
LDOs typically require an external output capacitor for stability. In fast transient response applications,
capacitors are used to support the load current the while the LDO amplifier is responding. In most applications,
one capacitor is used to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called ESR, and the inductive impedance is called
equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can, therefore, be drawn
as shown in Figure 40.
RESR
LESL
C
Figure 40. ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application
focuses mainly on the parasitic resistance ESR.
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SLVS718–DECEMBER 2006
Figure 41 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
IO
LDO
-
RESR
VESR
+
+
VI
VO
RLOAD
-
CO
Figure 41. LDO Output Stage With Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage [V(CO) = VO]. This means no current is flowing into the CO
branch. If IO suddenly increases (transient condition), the following occurs.
The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 42). Therefore,
capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with an
internal resistance, ESR. Depending on the current demand at the output, a voltage drop occurs at RESR. This
voltage is shown as VESR in Figure 41.
When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the
discharge of CO, the output voltage VO drops continuously until the response time t1 of the LDO is reached and
the LDO resumes supplying the load. From this point, the output voltage starts rising again until it reaches the
regulated voltage. This period is shown as t2 in Figure 42.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs, where number 1 displays the lowest and number 3 displays the highest ESR.
From the previous paragraphs, these conclusions can be drawn:
•
•
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
Conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
32
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SLVS718–DECEMBER 2006
IO
VO
1
2
ESR 1
ESR 2
3
ESR 3
t1
t2
Figure 42. Correlation of Different ESRs and Their Influence to the Regulation of VO
at a Load Step From Low-to-High Output Current
Regulator Protection
Both TPS70751 PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS70751 also features internal current limiting and thermal protection. During normal operation, the
TPS70751 regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current to
approximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C (typ),
regulator operation resumes.
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SLVS718–DECEMBER 2006
Power Dissipation and Junction Temperature
Specified regulator operation is ensured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max)
.
The maximum-power-dissipation limit is determined using the following equation:
T max * T
J
+
A
P
D(max)
R
qJA
Where:
TJmax = Maximum allowable junction temperature
θJA = Thermal resistance junction-to-ambient for the package, i.e., 32.6°C/W for the 20-terminal PWP
R
with no airflow
TA = Ambient temperature
The regulator dissipation is calculated using:
+ ǒVI * V
Ǔ
P
I
D
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
TPS70751MPWPREP
V62/07610-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
20
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
HTSSOP
PWP
20
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS70751-EP :
Catalog: TPS70751
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS70751MPWPREP HTSSOP PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
TPS70751MPWPREP
2000
Pack Materials-Page 2
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