TPS70845PWP [TI]
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS; 具有集成SVS双输出低压差稳压器SPLIT电压系统
| 型号： | TPS70845PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS |
| 文件： | 总29页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
D
D
D
D
Dual Output Voltages for Split-Supply
Applications
D
D
D
D
D
D
D
D
D
D
Fast Transient Response
Ultralow 190 µA (typ) Quiescent Current
1 µA Input Current During Standby
Independent Enable Functions (See Part
Number TPS707xx for Sequenced Outputs)
Low Noise: 65 µV
Capacitor
Without Bypass
RMS
Output Current Range of 250 mA on
Regulator 1 and 125 mA on Regulator 2
Quick Output Capacitor Discharge Feature
One Manual Reset Input
Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V,
3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
Outputs
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
20-Pin PowerPAD TSSOP Package
Thermal Shutdown Protection
D
D
Open Drain Power-On Reset With 120-ms
Delay
Open Drain Power Good for Regulator 1
and Regulator 2
PWP PACKAGE
(TOP VIEW)
description
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V
The TPS708xx is a low-dropout voltage regulator
V
V
IN1
IN1
OUT1
with integrated SVS (RESET, POR, or power on
reset) and power good (PG) functions. These
devices are capable of supplying 250 mA and 125
mA by regulator 1 and regulator 2 respectively.
Quiescent current is typically 190 µA at full load.
Differentiated features, such as accuracy, fast
transient response, SVS supervisory circuit
(power on reset), manual reset input, and
independent enable functions provide a complete
system solution.
V
V
OUT1
MR
EN1
EN2
/FB1
/FB2
SENSE1
PG1
PG2
RESET
GND
V
V
V
SENSE2
OUT2
V
V
IN2
IN2
OUT2
NC
NC – No internal connection
TPS70851 PWP
I/O
3.3 V
V
OUT1
5 V
V
IN1
10 µF
0.1 µF
V
SENSE1
250 kΩ
250 kΩ
PG1
PG1
MR
MR
>2 V
V
IN2
250 kΩ
<0.7 V
0.1 µF
EN1
RESET
RESET
PG2
>2 V
>2 V
PG2
EN1
EN2
<0.7 V
<0.7 V
EN2
V
SENSE2
1.8 V
Core
V
OUT2
10 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
description (continued)
The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices
have extremely low noise output performance without using any added filter bypass capacitors and are
designed to have a fast transient response and be stable with 10 µF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.
Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow
the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV
on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is
a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
230 µA over the full range of output current and full range of temperature). This LDO family also features a sleep
mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When
a high signal is applied to both EN1 and EN2, both regulators are in sleep mode, thereby reducing the input
current to 2 µA at T = 25°C.
J
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage condition at V
. The PG1 pin can be used to implement a SVS (RESET,
OUT1
POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions
at V . The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by
OUT2
regulator 2.
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event
of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the
logic high state, RESET goes to a high-impedance state after 120 ms delay. To monitor V
, the PG1 output
OUT1
pin can be connected to MR. To monitor V
, the PG2 output pin can be connected to MR.
OUT2
ThedevicehasanundervoltagelockoutUVLOcircuitwhichpreventstheinternalregulatorsfromturningonuntil
reaches 2.5V.
V
IN1
AVAILABLE OPTIONS
REGULATOR 1 REGULATOR 2
(V) (V)
TSSOP
(PWP)
T
J
V
O
V
O
3.3 V
3.3 V
3.3 V
3.3 V
1.2 V
1.5 V
1.8 V
2.5 V
TPS70845PWP
TPS70848PWP
TPS70851PWP
TPS70858PWP
–40°C to 125°C
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70802PWP
NOTE: The TPS70802 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70802PWPR).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
detailed block diagram – fixed voltage version
V
(2 Pins)
IN1
V
(2 Pins)
OUT1
Current
Sense
10 kΩ
UVLO
ENA_1
ENA_1
V
Shutdown
SENSE1
(see Note A)
2.5 V
–
+
Reference
V
ref
FB1
GND
Thermal
V
ref
Shutdown
Shutdown
PG1
V
SENSE1
VPGD_1
Rising Edge
Deglitch
V
IN1
MR
RESET
Falling Edge
Delay
UVLO
EN1
ENA_1
Shutdown
PG2
V
SENSE2
VPGD_2
Rising Edge
Deglitch
Shutdown
V
ref
FB2
ENA_2
EN2
–
+
ENA_2
ENA_2
V
SENSE2
Current
Sense
(see Note A)
10 kΩ
V (2 Pins)
OUT2
V
(2 Pins)
IN2
NOTE A: Formostapplications,V
andV
shouldbeexternallyconnectedtoV
OUT1
andV
respectivelyascloseaspossible
OUT2
SENSE1
SENSE2
to the device. For other implementations, refer to SENSE terminal connection discussion in the application information section.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
detailed block diagram – adjustable voltage version
V
(2 Pins)
V
(2 Pins)
OUT1
IN1
Current
Sense
UVLO
ENA_1
ENA_1
+
FB1
Shutdown
2.5 V
(see Note A)
PG1
–
Reference
V
ref
GND
Thermal
Shutdown
V
ref
Shutdown
V
SENSE1
VPGD_1
Rising Edge
Deglitch
V
IN1
MR
RESET
Falling Edge
Delay
UVLO
EN1
ENA_1
Shutdown
PG2
Shutdown
V
SENSE2
VPGD_2
Rising Edge
Deglitch
V
ref
ENA_2
EN2
–
+
ENA_2
FB2
(see Note A)
ENA_2
Current
Sense
V
(2 Pins)
V
(2 Pins)
OUT2
IN2
NOTE A: For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other
implementations, refer to FB terminals connection discussion in the application information section.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
RESET timing diagram
V
IN1
V
UVLO
V
UVLO
V
t
V
RES
RES
MR Input
t
RESET Output
120 ms
Delay
120 ms
Delay
Output
Undefined
Output
Undefined
t
NOTE A: V
RES
is the minimum input voltage for a valid RESET. The symbol V is not currently listed within EIA or JEDEC standards for
RES
semiconductor symbology.
PG1 timing diagram
V
IN1
V
UVLO
V
UVLO
V
PG1
V
PG1
t
V
OUT1
V
IT+
(see Note B)
Threshold
Voltage
V
IT–
(see Note B)
t
PG1 Output
Output
PG1
Output
Undefined
Undefined
t
NOTES: A.
B.
V
is the minimum input voltage for a valid PG1. The symbol V
PG1
is not currently listed within EIA or JEDEC standards
PG1
for semiconductor symbology.
V
– Trip voltage is typically 5% lower than the output voltage (95%V ) V
IT–
to V is the hysteresis voltage.
IT+
IT
O
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
PG2 timing diagram (assuming V
already powered up)
IN1
V
IN2
t
V
OUT2
V
IT+
(see Note A)
Threshold
Voltage
V
IT–
(see Note A)
t
PG2
Output
t
NOTE A: V – Trip voltage is typically 5% lower than the output voltage (95%V ) V
to V
is the hysteresis voltage.
IT+
IT
O
IT–
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5
EN1
EN2
I
I
Active low enable for V
Active low enable for V
Ground
OUT1
6
OUT2
GND
MR
8
4
I
Manual reset input, active low, pulled up internally
No connection
NC
1, 11, 20
16
PG1
PG2
RESET
O
O
I
Open drain output, low when V
Open drain output, low when V
voltage is less than 95% of the nominal regulated voltage
voltage is less than 95% of the nominal regulated voltage
OUT1
15
OUT2
7
Open drain output, SVS (power on reset) signal, active low
Input voltage of regulator 1
V
V
V
V
V
V
2, 3
9, 10
18, 19
12, 13
14
I
IN1
I
Input voltage of regulator 2
IN2
O
O
I
Output voltage of regulator 1
OUT1
OUT2
SENSE2
SENSE1
Output voltage of regulator 2
/FB2
/FB1
Regulator 2 output voltage sense/ regulator 2 feedback for adjustable
Regulator 1 output voltage sense/ regulator 1 feedback for adjustable
17
I
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
detailed description
The TPS708xx low dropout regulator family provides dual regulated output voltages with independent enable
functions. These devices provide fast transient response and high accuracy with small output capacitors, while
drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good
(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features
provide a complete power solution.
The TPS708xx, unlike many other LDOs, features very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is
directly proportional to the load current through the regulator (I = I /β). The TPS708xx uses a PMOS transistor
B
C
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
pin functions
enable (EN1 and EN2)
The EN terminals are inputs which enable or shut down each respective regulator. If EN is at a voltage high
signal the respective regulator is in shutdown mode. WhenEN goes to voltage low, then the respective regulator
is enabled.
power good (PG1 and PG2)
The PG terminals are open drain, active high outputs which indicate the status of each respective regulator.
When the V
reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When the V
OUT1
OUT2
reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance
state when its respective output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage.
The open drain outputs of the PG terminals require a pullup resistor.
manual reset pin (MR)
MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR
(RESET) occurs. The terminal has a 6-µA pullup current to V
.
IN1
sense (V
, V
)
SENSE1 SENSE2
The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection
should be as short as possible. Internally, the sense terminal connects to high-impedance wide-bandwidth
amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is
essential to route the sense connection in such a way as to minimize/avoid noise pickup. Adding RC networks
between sense terminals and V
to oscillate.
to filter noise is not recommended because it can cause the regulators
OUTS
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between FB terminals and V
noise is not recommended because it can cause the regulators to oscillate.
to filter
OUTS
RESET indicator
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on reset
circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the
manual reset pin (MR). When MR is in high impedance state, RESET goes to a high impedance state after a
120msdelay.TomonitorV
,thePG1outputpincanbeconnectedtoMR.TomonitorV
,thePG2output
OUT1
OUT2
pin can be connected to MR. The open drain output of the RESET terminal requires a pullup resistor. If RESET
is not used, it can be left floating.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
detailed description (continued)
V
and V
IN2
IN1
V
and V
are inputs to each regulator. Internal bias voltages are powered by V
.
IN1
IN2
IN1
V
and V
OUT1
OUT2
V
and V
are output terminals of each regulator.
OUT2
OUT1
†
absolute maximum ratings over operating junction temperature (unless otherwise noted)
‡
Input voltage range : V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
IN1
IN2
Voltage range at EN1, EN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range (V
Output voltage range (V
, V
)
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
OUT1 SENSE1
, V
OUT2 SENSE2
Maximum RESET, PG1, PG2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum MR voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are tied to network ground.
DISSIPATION RATING TABLE
AIR FLOW
PACKAGE
T
A
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T = 85°C
A
(CFM)
0
3.067 W
4.115 W
30.67 mW/°C
41.15 mW/°C
1.687 W
2.265 W
1.227 W
1.646 W
§
PWP
250
§
This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on 4-in × 4-in
ground layer. For more information, refer to TI technical brief SLMA002.
recommended operating conditions
MIN
2.7
0
MAX
6
UNIT
V
†
Input voltage, V
I
Output current, I (regulator 1)
250
125
5.5
125
mA
mA
V
O
Output current, I (regulator 2)
O
Output voltage range (for adjustable option)
0
1.22
–40
Operating virtual junction temperature, T
°C
.
J
†
To calculate the minimum input voltage for maximum output current, use the following equation: V
= V
+ V
O(max) DO(max load)
I(min)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
electrical characteristics over recommended operating junction temperature (T = –40°C to 125°C)
J
V
or V
= V
+ 1 V, I = 1 mA, EN = 0, C = 33 µF(unless otherwise noted)
IN1
IN2
O(nom)
O
O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7 V < V < 6 V,
IN
J
FB connected to V
O
O
1.22
T
= 25°C
Reference voltage
2.7 V < V < 6 V,
IN
FB connected to V
1.196
1.176
1.47
1.244
1.224
1.53
2.7 V < V < 6 V,
T
T
T
T
T
T
T
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
1.2
1.5
I
J
J
J
J
J
J
J
1.2 V output
1.5 V output
1.8 V output
2.5 V output
3.3 V output
2.7 V < V < 6 V
I
2.7 V < V < 6 V,
I
V
Output voltage
(see Notes 1 and 3)
2.7 V < V < 6 V
V
I
O
2.8 V < V < 6 V,
1.8
I
2.8 V < V < 6 V
1.764
2.45
1.836
2.55
I
3.5 V < V < 6 V,
2.5
I
3.5 V < V < 6 V
I
4.3 V < V < 6 V,
3.3
I
V
4.3 V < V < 6 V
I
3.234
3.366
230
See Note 3,
See Note 3
190
Quiescent current (GND current) for regulator 1 and
regulator 2, EN1 = EN2 = 0 V, (see Note 1)
µA
V
+ 1 V < V ≤ 6 V,
= 25°C, See Note 1
0.01%
Output voltage line regulation (∆V /V )for
regulator 1 and regulator 2 (see Note 2)
O
O
I
O
O
V
V
+ 1 V < V ≤ 6 V,
See Note 1
0.1%
I
Load regulation for V and V
T = 25°C
J
1
65
mV
OUT1
OUT2
Regulator 1
Regulator 2
Regulator 1
Regulator 2
V
Output noise voltage
BW = 300 Hz to 50 kHz,
C
= 33 µF,
T = 25°C
J
µVrms
n
O
65
1.6
1.9
1
Output current limit
Thermal shutdown junction temperature
V
= 0 V
A
O
0.750
150
°C
2
6
EN1 = V , EN2 = V ,
T
= 25°C
I
I
J
Regulator 1 and
Regulator 2
I
Standby current
µA
I(standby)
EN1 = V , EN2 = V
I
I
f = 1 kHz, C = 33 µF,
T
= 25°C,
= 25°C,
O
J
Regulator 1
Regulator 2
60
50
I
= 250 mA
OUT1
PSRR
Power supply ripple rejection
dB
f = 1 kHz, C = 33 µF,
T
O
J
I
= 125 mA
OUT2
RESET terminal
1.0
120
1.3
160
0.4
1
V
ms
V
Minimum input voltage for valid RESET
I
= 300 µA,
V
≤ 0.8 V
(RESET)
(RESET)
t
80
RESET pulse duration
V = 3.5 V,
(RESET)
Output low voltage
Leakage current
I
= 1 mA
0.15
I
(RESET)
V
= 6 V
µA
(RESET)
NOTES: 1. Minimum input operating voltage is 2.7 V or V
current 1 mA.
+ 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output
O(typ)
2. If V < 1.8 V then V
Imax
= 6 V, V
= 2.7 V:
Imin
O
OǒVImax * 2.7 VǓ
V
ǒ
Ǔ
Line regulation (mV) + %ńV
1000
100
If V > 2.5 V then V
Imax
= 6 V, V
= Vo + 1 V:
Imin
O
* ǒVO
100
Ǔ
OǒVImax
) 1 Ǔ
V
ǒ
Ǔ
Line regulation (mV) + %ńV
1000
3.
I
O
= 1 mA to 250 mA for regulator 1 and 1 mA to 125 mA for regulator 2.
9
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
electrical characteristics over recommended operating junction temperature (T = –40°C to 125°C)
J
V
or V
= V
+ 1 V, I = 1 mA, EN = 0, C = 33 µF(unless otherwise noted) (continued)
IN1
IN2
O(nom)
O
O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO threshold
2.4
2.65
V
FB terminal
Input current – TPS70202
FB = 1.8 V
1
µA
PG1/PG2 terminal
Minimum input voltage for valid PGx
Trip threshold voltage
I
= 300 µA,
V
) ≤ 0.8 V
1.0
95%
0.5%
30
1.3
V
(PGx)
(PGx
V
decreasing
92%
98%
V
V
O
O
Hysteresis voltage
Measured at V
O
O
t
Rising edge deglitch
V = 2.7 V,
µs
V
r(PGx)
Output low voltage
I
= 1 mA
0.15
0.4
1
I
(PGx)
Leakage current
V
= 6 V
µA
(PGx)
EN1/EN2 terminal
High-level ENx input voltage
Low-level ENx input voltage
Input current (ENx)
MR terminal
2
–1
2
V
V
0.7
1
µA
High-level input voltage
Low-level input voltage
Pullup current source
V
V
0.7
6
µA
V
terminal
OUT1
I
I
= 250 mA, V
= 250 mA, V
= 3.2 V, T = 25°C
83
O
IN1
J
Dropout voltage (see Note 4)
mV
= 3.2 V
140
O
IN1
Peak output current
2 ms pulse width
V = 1.5 V
OUT1
750
7.5
mA
mA
Discharge transistor current
V
terminal
OUT2
Peak output current
2 ms pulse width
V = 1.5 V
OUT2
375
7.5
mA
mA
Discharge transistor current
NOTE 4: Inputvoltage(V
orV
)=V (Typ)–100mV. Forthe1.5-V, 1.8-Vand2.5-Vregulators, thedropoutvoltageislimitedbyinputvoltage
O
IN1
IN2
range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test.
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
vs Junction temperature
vs Junction temperature
vs Frequency
1 – 3
4 – 5
V
Output voltage
O
Ground current
6
PSRR
Power supply rejection ratio
Output spectral noise density
Output impedance
7 – 10
11 – 14
15 – 18
19, 20
21, 22
23, 24
25, 26
27, 28
30 – 33
vs Frequency
Z
o
vs Frequency
vs Junction temperature
vs Input voltage
Dropout voltage
Load transient response
Line transient response
Output voltage
V
O
vs Time (start-up)
vs Output current
Equivalent series resistance (ESR)
TPS70851
OUTPUT VOLTAGE
vs
TPS70851
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
1.802
1.801
1.800
3.303
3.302
3.301
3.3
V
= 2.8V
IN2
= 25°C
V
= 4.3 V
IN1
= 25°C
T
V
J
T
V
J
OUT2
OUT1
1.799
1.798
3.299
3.298
3.297
1.797
1.796
1.795
3.296
3.295
0
0.025
0.05
0.075
0.1
0.125
0
0.05
0.1
0.15
0.2
0.25
I
O
– Output Current – A
I
O
– Output Current – A
Figure 1
Figure 2
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TPS70851
OUTPUT VOLTAGE
vs
TPS70845
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
OUTPUT CURRENT
1.201
1.200
3.35
3.33
V
= 2.7 V
V
= 4.3 V
IN1
IN2
= 25°C
T
V
V
OUT1
J
OUT2
I
O
= 250 mA
1.199
1.198
1.197
3.31
3.29
I
O
= 1 mA
3.27
1.196
1.195
3.25
3.23
0
0.025
0.05
0.075
0.1
0.125
–40 –25 –10
5
20 35 50 65 80 95 110 125
I
O
– Output Current – A
T
– Junction Temperature – °C
J
Figure 3
Figure 4
TPS70851
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
GROUND CURRENT
vs
JUNCTION TEMPERATURE
210
1.85
1.83
1.81
1.79
1.77
1.75
1.73
V
IN2
V
OUT2
= 2.8 V
Regulator 1 and Regulator 2
200
190
I
I
= 1 mA
= 1 mA
OUT1
OUT2
I
O
= 1 mA
180
170
I
= 250 mA
O
I
I
= 250 mA
= 125 mA
OUT1
OUT2
160
150
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 5
Figure 6
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TPS70851
TPS70851
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
0
–10
–20
–30
–40
I
C
V
= 250 mA
I
C
V
= 10 mA
O
O
= 22 µF
= 22 µF
O
O
OUT1
OUT1
–10
–20
–30
–40
–50
–50
–60
–70
–60
–70
–80
–90
–80
–90
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
f – Frequency – Hz
Figure 7
Figure 8
TPS70851
TPS70851
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
0
–10
–20
I
C
V
= 10 mA
O
I
C
V
= 150 mA
O
= 22 µF
O
= 22 µF
O
OUT2
OUT2
–10
–20
–30
–40
–30
–40
–50
–50
–60
–70
–60
–70
–80
–90
–80
–90
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
f – Frequency – Hz
Figure 9
Figure 10
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
V
I
= 4.3 V
= 3.3 V
V
V
I
= 4.3 V
= 3.3 V
IN1
OUT1
= 250 mA
IN1
OUT1
= 10 mA
O
O
1
1
0.1
0.01
0.1
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 11
Figure 12
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
= 2.8 V
= 1.8 V
V
= 2.8 V
= 1.8 V
IN2
IN2
V
I
V
I
OUT2
= 10 mA
OUT2
= 125 mA
O
O
1
1
0.1
0.1
0.01
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 13
Figure 14
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TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
10
100
C
I
= 33 µF
= 10 mA
= 3.3 V
= 25°C
C
I
= 33 µF
= 250 mA
O
O
O
O
V
OUT1
T
V
T
= 3.3 V
OUT1
= 25°C
J
J
10
1
1
0.1
0.01
0.1
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 15
Figure 16
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
10
100
C
= 33 µF
= 125 mA
C
= 33 µF
= 10 mA
O
O
I
V
I
V
O
O
= 1.8 V
= 1.8 V
OUT2
= 25°C
OUT2
T = 25°C
J
T
J
10
1
1
0.1
0.1
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 17
Figure 18
15
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TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
6
5
120
100
C
V
= 33 µF
C
V
= 33 µF
O
O
= 3.2 V
= 3.2 V
IN1
IN1
I
O
= 10 mA
I
O
= 250 mA
4
3
2
80
60
40
20
0
1
0
I
O
= 0 mA
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 19
Figure 20
TPS70802
DROPOUT VOLTAGE
vs
TPS70802
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
250
200
140
I
V
= 250 mA
I
V
= 125 mA
O
O
OUT1
OUT2
120
100
80
T
= 125°C
J
T
= 125°C
J
T
J
= 25°C
150
100
T
J
= 25°C
60
T = –40°C
J
40
T
J
= –40°C
50
0
20
0
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 21
Figure 22
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
C
T
= 33 µF
= 25°C
C
T
= 33 µF
O
O
J
= 25°C
250
0
125
0
J
V
OUT1
= 3.3 V
V
OUT2
= 1.8 V
20
0
20
0
–20
–40
–20
–40
–60
–80
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t – Time – ms
t – Time – ms
Figure 23
Figure 24
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
3.8
2.8
5.3
4.3
50
0
10
0
I
C
V
= 125 mA
I
C
V
= 250 mA
O
O
= 33 µF
–50
= 33 µF
–10
O
O
OUT2
OUT1
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
t – Time – µs
t – Time – µs
Figure 25
Figure 26
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
TIME (START-UP)
TIME (START-UP)
V
C
= 3.3 V
= 33 µF
= 250 mA
O
O
V
C
= 1.5 V
= 33 µF
= 125 mA
O
O
3
2
1
0
3
2
1
0
I
V
O
OUT2
I
V
O
OUT1
= Standby
= Standby
5
0
5
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t – Time – ms
t – Time – ms
Figure 28
Figure 27
To Load
IN
V
I
OUT
+
C
O
R
L
EN
GND
ESR
Figure 29. Test Circuit for Typical Regions of Stability
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
†
†
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
= 3.3 V
= 6.8 µF
= 25°C
V
= 3.3 V
= 10 µF
= 25°C
O
O
V
C
C
T
O
O
J
T
J
1
1
0.1
50 mΩ
250 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
0.1
0.01
0
50
100
150
200
250
0
50
100
150
200
250
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 30
Figure 31
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
†
†
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
V
C
= 1.8 V
= 6.8 µF
= 25°C
O
O
V
C
= 1.8 V
= 10 µF
= 25°C
O
O
T
J
T
J
1
1
0.1
50 mΩ
250 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
0.1
0.01
0
25
50
75
100
125
0
25
50
75
100
125
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 32
Figure 33
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
19
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
timing diagrams
The following figures provide a timing diagram of how this device functions in different configurations.
application conditions not shown in block diagram:
and V are tied to the same fixed input
TPS708xxPWP
(Fixed Output Option)
V
IN1
IN2
V
OUT1
V
IN
voltagegreaterthantheV
.PG2istiedtoMR.
UVLO
V
OUT1
V
IN1
explanation of timing diagrams:
0.1 µF
10 µF
250 k
250 k
V
SENSE1
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 (tied to MR)
are at logic low. Since MR is at logic low, RESET
is also at logic low. When EN1 is taken to logic low,
PG1
MR
MR
V
IN2
V
low,V
turns on. Later, when EN2 is taken to logic
OUT1
0.1 µF
turnson.WhenV
reaches95%of
RESET
PG2
RESET
PG2
OUT2
OUT1
its regulated output voltage, PG1 goes to logic
high. When V reaches 95% of its regulated
OUT2
EN1
EN2
output voltage, PG2 (tied to MR) goes to logic
high. When V is greater than V and MR
EN1
>2 V
>2 V
IN1
UVLO
<0.7 V
EN2
V
SENSE2
(tied to PG2) is at logic high, RESET is pulled to
logic high after a 120 ms delay. When EN1 and
EN2 are returned to logic high, both devices
power down and both PG1, PG2 (tied to MR2),
and RESET return to logic low.
V
OUT2
V
OUT2
<0.7 V
10 µF
EN2
EN1
V
OUT2
95%
95%
V
OUT1
PG2
PG1
MR
(PG2 tied to MR)
RESET
t1
120ms
NOTES: A. t1 – Time at which V is greater than V
and MR is logic high.
UVLO
IN
B. The timing diagrams are not drawn to scale.
Figure 34. Timing When V
Is Enabled Before V
OUT2
OUT1
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
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SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
TPS708xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
and V are tied to the same fixed input
V
V
IN
V
OUT1
IN1
IN2
V
V
OUT1
voltage greater than V
high but is eventually toggled.
MR is initially logic
IN1
IN2
UVLO.
0.1 µF
V
SENSE1
explanation of timing diagrams:
250 k
10 µF
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 are at logic
250 k
PG1
V
low. Since V
is greater than V
and MR is
IN1
UVLO
250 k
at logic high, RESET is also at logic high. When
EN2 is taken to logic low, V turns on. Later,
0.1 µF
RESET
RESET
OUT2
when EN1 is taken to logic low, V
turns on.
OUT1
PG2
MR
When V
reaches 95% of its regulated output
OUT2
PG2
MR
EN1
EN2
EN1
voltage, PG2 goes to logic high. When V
OUT1
>2 V
>2 V
2 V
reaches 95% of its regulated output voltage, PG1
goes to logic high. When MR is taken to logic low,
RESET is taken low. When MR returns to logic
high, RESET returns to logic high after a 120 ms
delay.
V
0.7 V
OUT2
10 µF
<0.7 V
EN2
SENSE2
V
V
OUT2
<0.7 V
EN2
EN1
V
V
95%
OUT2
95%
OUT1
PG2
PG1
MR
RESET
t1
120ms
NOTES: A. t1 – Time at which V is greater than V
IN
and MR is logic high.
UVLO
B. The timing diagrams are not drawn to scale.
Figure 35. Timing When MR Is Toggled
21
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
TPS708xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
and V
are tied to same fixed input voltage
V
IN
V
OUT1
IN1
IN2
V
OUT1
V
greater than V
PG1 is tied to MR.
IN1
UVLO.
explanation of timing diagrams:
0.1 µF
10 µF
V
SENSE1
250 k
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 (tied to MR) and PG2
are at logic low. Since MR is at logic low, RESET
is also at logic low. When EN2 is taken to logic low,
PG1
MR
V
IN2
250 k
V
low,V
turns on. Later, when EN1 is taken to logic
OUT2
0.1 µF
RESET
RESET
PG2
turnson.WhenV
reaches95%of
OUT1
OUT2
its regulated output voltage, PG2 goes to logic
high. When V reaches 95% of its regulated
outputvoltage, PG1goestologichigh. WhenV
is greater than V
logic high, RESET is pulled to logic high after a
120 ms delay. When a fault on V causes it to
fallbelow95%ofitsregulatedoutputvoltage, PG1
(tied to MR) goes to logic low. Since MR is logic
low, RESET goes to logic low. V
PG2
OUT1
EN1
EN2
EN1
IN1
>2 V
>2 V
and MR (tied to PG2) is at
UVLO
V
SENSE2
<0.7 V
EN2
OUT1
V
OUT2
V
OUT2
<0.7 V
10 µF
is
OUT2
unaffected.
EN2
EN1
V
V
OUT2
95%
95%
OUT1
PG2
PG1
MR
FAULT ON V
OUT1
(PG1 tied to MR)
RESET
t1
120ms
NOTES: A. t1 – Time at which V is greater than V
IN
and MR is logic high.
UVLO
B. The timing diagrams are not drawn to scale.
Figure 36. Timing When There Is a Fault on V
OUT1
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
input capacitor
For a typical application, an input bypass capacitor (0.1 µF – 1 µF) is recommended. This capacitor will filter
any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO
may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The
size of this capacitor is dependant on the output current and response time of the main power supply, as well
as the distance to the V pins of the LDO.
I
output capacitor
As with most LDO regulators, the TPS708xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance values are 10 µF ceramic
capacitors with an ESR (equivalent series resistance) between 50-mΩ and 2.5-Ω or 6.8-µF tantalum capacitors
with ESR between 250 mΩ and 4 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors with capacitance values greater than 10 µF are all suitable, provided they meet the requirements
described above. Larger capacitors provide a wider range of stability and better load transient response. Below
is a partial listing of surface-mount capacitors usable with the TPS708xx for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high-output current and/or
high-load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
†
VALUE
22 µF
33 µF
47 µF
68 µF
MFR.
Kermet
Sanyo
Sanyo
Sanyo
MAX ESR
345 mΩ
100 mΩ
100 mΩ
45 mΩ
PART NO.
7495C226K0010AS
10TPA33M
6TPA47M
10TPC68M
ESR and transient response
LDOs typically require an external output capacitor for stability. In fast transient response applications,
capacitors are used to support the load current while LDO amplifier is responding. In most applications, one
capacitor is used to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any
capacitor can therefore be drawn as shown in Figure 37.
R
L
ESL
ESR
C
Figure 37. ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application
focuses mainly on the parasitic resistance ESR.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
Figure 38 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
I
O
LDO
–
R
V
ESR
ESR
+
+
V
V
I
O
R
LOAD
–
C
O
Figure 38. LDO Output Stage With Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V(C ) = V ). This means no current is flowing into the C
O
O
O
branch. If I suddenly increases (transient condition), the following occurs:
O
D
The LDO is not able to supply the sudden current need due to its response time. Therefore, capacitor C
O
provides the current for the new load condition (dashed arrow). C now acts like a battery with an internal
O
resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at R
. This
ESR
voltage is shown as V
in Figure 38.
ESR
D
When C is conducting current to the load, initial voltage at the load will be V = V(C ) – V . Due to the
ESR
O
O
O
dischargeofC ,theoutputvoltageV willdropcontinuouslyuntiltheresponsetimet oftheLDOisreached
O
O
1
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it
reaches the regulated voltage. This period is shown as t in Figure 39.
2
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
D
D
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
I
O
V
O
1
2
ESR 1
ESR 2
3
ESR 3
t
t
1
2
Figure 39. Correlation of Different ESRs and Their Influence to the Regulation of V at a
O
Load Step From Low-to-High Output Current
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
programming the TPS70802 adjustable LDO regulator
The output voltage of the TPS70802 adjustable regulators is programmed using an external resistor divider as
shown in Figure 40.
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at the sense terminal increase the output voltage error. The recommended design procedure is to
choose R2 = 30.1 kΩ to set the divider current at approximately 50 µA and then calculate R1 using:
V
O
R1 +
ǒ
* 1
Ǔ
R2
V
ref
where
V
= 1.224 V typ (the internal reference voltage)
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS70802
OUTPUT
VOLTAGE
V
I
R1
R2
UNIT
IN
0.1 µF
2.5 V
3.3 V
3.6 V
31.6
51.1
59.0
30.1
30.1
30.1
kΩ
kΩ
kΩ
>2.0 V
EN
OUT
FB
V
O
<0.7V
+
R1
GND
R2
Figure 40. TPS70802 Adjustable LDO Regulator Programming
regulator protection
Both TPS708xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS708xx also features internal current limiting and thermal protection. During normal operation, the
TPS708xx regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current to
approximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator
operation resumes.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
APPLICATION INFORMATION
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
, and the actual dissipation, P , which must be less than
D(max)
D
or equal to P
.
D(max)
The maximum-power-dissipation limit is determined using the following equation:
T max * T
J
A
P
+
D(max)
R
qJA
where
T max is the maximum allowable junction temperature.
J
R
is the thermal resistance junction-to-ambient for the package, i.e., 32.6°C/W for the 20-terminal
θJA
PWP with no airflow.
T is the ambient temperature.
A
The regulator dissipation is calculated using:
+ ǒVI * V
Ǔ
P
I
D
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the
thermal protection circuit.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
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Mailing Address:
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Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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