TPS71025DRG4 [TI]
Low-Dropout (LDO) Voltage Regulator 8-SOIC 0 to 125;
| 型号： | TPS71025DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Dropout (LDO) Voltage Regulator 8-SOIC 0 to 125 光电二极管 输出元件 调节器 |
| 文件： | 总24页 (文件大小：658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
D OR P PACKAGE
(TOP VIEW)
2.5-V Fixed-Output Regulator
Very Low-Dropout (LDO) Voltage . . . 57 mV
GND
EN
IN
NC
1
2
3
4
8
7
6
5
Typical at I = 100 mA
O
SENSE
OUT
OUT
Very Low Quiescent Current, Independent
of Load . . . 292 µA Typ
IN
Extremely Low Sleep-State Current,
0.5 µA Max
2% Tolerance Over Specified Conditions
Output Current Range . . . 0 mA to 500 mA
PW PACKAGE
(TOP VIEW)
Available in Space Saving 8-Pin SOIC and
20-Pin TSSOP Packages
GND
GND
GND
NC
NC
EN
1
2
3
4
5
6
7
8
9
10
20 NC
19
18
17
16
15
14
13
12
11
NC
0°C to 125°C Operating Junction
Temperature Range
NC
NC
NC
description
SENSE
OUT
OUT
NC
NC
IN
The TPS71025 low-dropout regulator offers an
order of magnitude reduction in both dropout
voltage and quiescent current over conventional
LDO performance. The improvement results from
replacing the typical pnp pass transistor with a
PMOS device.
IN
IN
NC
NC – No internal connection
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 95 mV
at an output current of 100 mA) and is directly proportional to the output current (see Figure 1). Additionally,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains
independent of output loading (typically 292 µA over the full range of output current, 0 mA to 500 mA). These
two key specifications yield a significant improvement in operating life for battery-powered systems. The
TPS71025 also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at T = 25°C.
J
AVAILABLE OPTIONS
OUTPUT VOLTAGE
PACKAGED DEVICES
(V)
CHIP FORM
(Y)
T
J
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
TSSOP
(PW)
MIN
TYP
2.5
MAX
0°C to 125°C
2.45
2.55
TPS71025D
TPS71025P
TPS71025PWLE
TPS71025Y
The D package is availabe taped and reeled. Add R suffix to device type (e.g., TPS71025DR). The PW package is only available left-end taped
and reeled and is indicated by the LE suffix on the device type.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
0.5
T
A
= 25°C
0.4
0.3
0.2
0.1
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
– Output Current – A
I
O
Figure 1. Dropout Voltage Versus Output Current
functional block diagram
IN
†
†
EN
_
+
OUT
V
ref
= 1.182 V
SENSE
260 kΩ
233 kΩ
GND
†
Switch positions are shown with EN low (active).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
Terminal Functions
TERMINAL
NO.
DESCRIPTION
NAME
EN
D or P
PW
6
2
1
Enable input. Logic low enables output
Ground
GND
IN
1–3
8–10
13, 14
15
3, 4
5, 6
7
Input supply voltage
Output voltage
OUT
SENSE
Output voltage sense input
TPS71025Y chip information
These chips, when properly assembled, display characteristics similar to those of the TPS71025. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(3)
(2)
(5)
(4)
IN
SENSE
OUT
(4)
(5)
TPS71025
EN
(1)
GND
CHIP THICKNESS: 15 MILS TYPICAL
80
BONDING PADS: 4 × 4 MILS MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
NOTE A: For most applications, OUT and SENSE should
betiedtogetherascloseaspossibletothedevice;
for other implementations, refer to SENSE-pin
connection discussion in the Application
Information section of this data sheet.
(3)
(2)
(1)
92
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V , EN (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 11 V
I
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND
‡
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE
T
≤ 25°C DERATING FACTOR = 70°C
T
T = 125°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
P
725 mW
5.8 mW/°C
9.4 mW/°C
5.6 mW/°C
464 mW
752 mW
448 mW
145 mW
235 mW
140 mW
1175 mW
PW
700 mW
‡
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE
T
≤ 25°C DERATING FACTOR = 70°C
T
T = 125°C
C
C
C
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
C
D
P
2188 mW
17.5 mW/°C
21.9 mW/°C
32.2 mW/°C
1400 mW
1752 mW
2576 mW
438 mW
548 mW
805 mW
2738 mW
PW
4025 mW
‡
Dissipation rating tables and figures are provided for maintenance of junction temperature at or below
absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within
recommended operating range, see the Thermal Information section.
recommended operating conditions
MIN
2.97
2
MAX
UNIT
V
Input voltage, V
10
I
High-level input voltage at EN, V
V
IH
Low-level input voltage at EN, V
0
0.5
500
125
V
IL
Output current range, I
0
mA
°C
O
Operating virtual junction temperature range, T
0
J
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
electrical characteristics over recommended operating junction temperature range, V
= 3.5 V,
I(IN)
†
I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE shorted to OUT (unless otherwise noted)
O
o
‡
PARAMETER
MIN
TYP
MAX
T
J
UNIT
TEST CONDITIONS
25°C
0°C to 125°C
25°C
2.5
Output voltage
3.5 V ≤ V ≤ 10 V
V
I
2.45
2.55
7.5
10
5.7
57
I
O
I
O
I
O
= 10 mA,
V = 2.45 V
I
0°C to 125°C
25°C
95
Dropout voltage
= 100 mA,
= 500 mA,
V = 2.45 V
I
mV
0°C to 125°C
25°C
105
450
500
0.9
1
330
0.66
V = 2.45 V
I
0°C to 125°C
25°C
Pass-element series resistance
Input regulation
Ω
0°C to 125°C
25°C
7
12.7
18
23
V = 3.5 V to 10 V,
I
mV
mV
mV
50 µA ≤ I ≤ 500 mA
0°C to 125°C
25°C
29
O
38
I
= 5 mA to 500 mA,
O
3.5 V ≤ V ≤ 10 V
0°C to 125°C
25°C
75
I
Output regulation
Ripple rejection
24
53
51
60
I
= 50 µA to 500 mA,
O
3.5 V ≤ V ≤ 10 V
0°C to 125°C
25°C
120
I
43
40
39
36
f = 120 Hz,
I
I
= 50 µA
O
0°C to 125°C
25°C
dB
f = 120 Hz,
f = 120 Hz
= 500 mA
O
0°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
2
274
228
159
292
µV/√Hz
µVrms
25°C
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
10 Hz ≤ f ≤ 100 kHz,
CSR = 1 Ω
25°C
25°C
390
540
475
1900
2
EN ≤ 0.5 V,
Quiescent current (active mode)
Supply current (standby mode)
Output current limit
µA
nA
A
0 mA ≤ I ≤ 500 mA
0°C to 125°C
25°C
O
18
1.07
EN = V ,
2.7 V ≤ V ≤ 10 V
I
I
0°C to 125°C
25°C
V
O
= 0,
V = 10 V
I
0°C to 125°C
25°C
2
0.223
0.5
1
Pass-element leakage current in standby
mode
EN = V ,
2.7 V ≤ V ≤ 10 V
µA
I
I
0°C to 125°C
0°C to 125°C
Output voltage temperature coefficient
Thermal shutdown junction temperature
61
75 ppm/°C
°C
165
2.5 V ≤ V ≤ 6 V
25°C
2
I
Logic high input voltage (standby mode), EN
V
6 V ≤ V ≤ 10 V
0°C to 125°C
25°C
2.7
I
0.5
V
Logic low input voltage (active mode), EN
Hysteresis voltage, EN
2.7 V ≤ V ≤ 10 V
I
0°C to 125°C
0°C to 125°C
25°C
0.5
50
2
mV
–0.5
–0.5
0.5
µA
0.5
Input current, EN
0 V ≤ V ≤ 10 V
I
0°C to 125°C
25°C
2.5
V
Input voltage, minimum for active pass
element
0°C to 125°C
2.5
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C .
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
o
‡
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
†
electrical characteristics at T = 25°C, V
SENSE shorted to OUT (unless otherwise noted)
= 3.5 V, I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω,
J
I(IN)
O
o
TPS71025Y
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
2.5
5.7
57
MAX
Output voltage
Dropout voltage
3.5 V ≤ V ≤ 10 V
V
I
I
I
I
= 10 mA,
= 100 mA,
= 500 mA,
V = 2.45 V
I
O
O
O
V = 2.45 V
I
mV
V = 2.45 V
330
0.66
7
I
Pass-element series resistance
Input regulation
Ω
V = 3.5 V to 10 V
mV
mV
mV
I
I
O
I
O
= 5 mA to 500 mA
18
Output regulation
= 50 µA to 500 mA
24
f = 120 Hz,
f = 120 Hz,
f = 120 Hz
I
I
= 50 µA
53
O
Ripple rejection
dB
= 500 mA
51
O
Output noise-spectral density
2
µV/√Hz
274
228
159
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
10 Hz ≤ f ≤ 100 kHz,
CSR = 1 Ω
Output noise voltage
µVrms
EN = 0 V,
Quiescent current (active mode)
292
µA
0 mA ≤ I ≤ 500 mA
O
Supply current (standby mode)
EN = V ,
2.7 V ≤ V ≤ 10 V
18
1.07
0.223
61
nA
A
I
I
Output current limit
V
O
= 0,
V = 10 V
I
Pass-element leakage current in standby mode
Output voltage temperature coefficient
Thermal shutdown junction temperature
EN = V ,
2.7 V ≤ V ≤ 10 V
µA
I
I
ppm/°C
°C
165
2.5 V ≤ V ≤ 6 V
2
I
V
Logic high input voltage (standby mode), EN
6 V ≤ V ≤ 10 V
2.7
I
Logic low input voltage (active mode), EN
Hysteresis voltage, EN
2.7 V ≤ V ≤ 10 V
0.5
V
mV
µA
V
I
50
0
Input current, EN
0 V ≤ V ≤ 10 V
I
Input voltage, minimum for active pass element
2
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor ,
any series resistance added externally, and PWB trace resistance to C .
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
o
‡
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.55
2.54
2.53
2.52
2.51
2.5
0.4
0.35
0.3
V = 3.5 V
I
V = 2.45 V
I
I
O
= 500 mA
0.25
0.2
I
O
= 10 mA
2.49
2.48
2.47
0.15
I
O
= 500 mA
0.1
I
O
= 100 mA
0.05
0
2.46
2.45
I
= 10 mA
75
O
0
25
T
50
75
100
125
0
25
T
50
100
125
– Free-Air Temperature – °C
– Free-Air Temperature – °C
A
A
Figure 2
Figure 3
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
2.55
2.54
2.53
2.52
2.55
2.54
I
O
= 5 mA
T
= 25°C
= 500 mA
A
I
O
2.53
2.52
2.51
2.5
2.51
2.5
2.49
2.48
2.49
2.48
2.47
2.47
2.46
2.45
2.46
2.45
0
25
T
A
50
75
100
125
3.5
4
4.5 5 5.5
6
6.5
7
7.5
8
8.5 9 9.5 10
– Free-Air Temperature – °C
V – Input Voltage – V
I
Figure 4
Figure 5
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
2.55
2.54
2.53
100
V = 3.5 V
I
No Input Capacitance
C
= 4.7 µF
o
No Added Ceramic Capacitance
= 25°C
T
A
2.52
2.51
2.5
Region of Instability
10
V = 10 V
I
2.49
2.48
2.47
1
V = 3.5 V
I
2.46
2.45
Region of Instability
0.1
0
100
200
300
400
500
0
50 100 150 200 250 300 350 400 450 500
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 7
Figure 6
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
OUTPUT CURRENT
100
100
V = 3.5 V
I
No Input Capacitance
V = 3.5 V
I
No Input Capacitance
I
C
T
= 100 mA
C
= 4.7 µF + 0.5 µF of
O
o
= 4.7 µF
= 25°C
Ceramic Capacitance
= 25°C
o
T
A
A
10
10
Region of Instability
Region of Instability
1
1
Region of Instability
Region of Instability
50 100 150 200 250 300 350 400 450 500
0.1
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Added Ceramic Capacitance – µF
Figure 9
1
0
I
O
– Output Current – mA
Figure 8
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
†
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
OUTPUT CURRENT
100
100
V = 3.5 V
I
Region of Instability
V = 3.5 V
I
No Input Capacitance
No Input Capacitance
C
= 10 µF
o
I
C
= 500 mA
O
No Ceramic Capacitance
= 25°C
= 4.7 µF
= 25°C
o
T
A
T
A
10
10
Region of Instability
1
1
Region of Instability
0.1
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
50 100 150 200 250 300 350 400 450 500
Added Ceramic Capacitance – µF
I
O
– Output Current – mA
Figure 10
Figure 11
†
†
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
COMPENSATION SERIES RESISTANCE
vs
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
100
100
V = 3.5 V
I
No Input Capacitance
V = 3.5 V
I
No Input Capacitance
C
= 10 µF + 0.5 µF of
C
I
O
= 10 µF
= 100 mA
T = 25°C
A
o
o
Added Ceramic Capacitance
= 25°C
T
A
10
10
Region of Instability
Region of Instability
1
1
0.1
0.1
0
50 100 150 200 250 300 350 400 450 500
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Added Ceramic Capacitance – µF
Figure 13
1
I
O
– Output Current – mA
Figure 12
†
CSR values below 0.1 Ω are not recommended.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
†
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
100
V = 3.5 V
I
No Input Capacitance
C
= 10 µF
= 500 mA
= 25°C
o
I
T
O
A
10
Region of Instability
1
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Added Ceramic Capacitance – µF
†
CSR values below 0.1 Ω are not recommended.
Figure 14
To Load
IN
V
I
OUT
+
SENSE
GND
C
o
C
cer
(see Note A)
R
EN
L
CSR
NOTE A: Ceramic capacitor
Figure 15. Test Circuit for Typical Regions of Stability (Figures 7 through 14)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
THERMAL INFORMATION
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch
surface-mount packages. Implementation of many of today’s high-performance devices in these packages
requires special attention to power dissipation. Many system-dependent issues such as thermal coupling,
airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components
affect the power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are illustrated in this discussion:
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
Figure 16 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout
involves adding copper on the PWB to conduct heat away from the device. The R
for this component/board
θJA
system is illustrated in Figure 17. The family of curves illustrates the effect of increasing the size of the
copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch × 0.062 inch);
the board traces and heat sink area are 1-oz (per square foot) copper.
Copper Heat Sink
1 oz Copper
Figure 16. Thermally Enhanced PWB Layout (Not to Scale) for the 20-Pin TSSOP
Figure 18 shows the thermal resistance for the same system with the addition of a thermally conductive
compound between the body of the TSSOP package and the PWB copper routed directly beneath the device.
The thermal conductivity for the compound used in this analysis is 0.815 W/m × °C.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
THERMAL INFORMATION
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
vs
AIR FLOW
AIR FLOW
190
190
Component/Board System
Component/Board System
20-Lead TSSOP
Includes Thermally Conductive
Compound Between Body and Board
20-Lead TSSOP
170
170
2
0 cm
2
1 cm
150
150
130
110
90
2
2 cm
2
0 cm
130
110
90
2
8 cm
2
4 cm
2
2 cm
2
1 cm
2
4 cm
2
8 cm
70
70
50
50
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Air Flow – ft/min
Air Flow – ft/min
Figure 17
Figure 18
Using these figures to determine the system R
calculated with the equation:
allows the maximum power-dissipation P
limit to be
θJA
D(max)
T
T
J(max)
A
P
D(max)
R
JA(system)
Where
T
is the maximum allowable junction temperature (i.e., 150°C absolute maximum or
J(max)
125°C maximum recommended operating temperature for specified operation).
This limit should then be applied to the internal power dissipated by the TPS71025 regulator. The equation for
calculating total internal power dissipation of the device is:
P
V
V
I
V
I
D(total)
I
O
O
I
Q
Because the quiescent current is very low, the second term is negligible, further simplifying the equation to:
P
V
V
I
D(total)
I
O
O
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
THERMAL INFORMATION
For a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the
2
device body, where T = 55°C, airflow = 100 ft/min, and copper heat sink area = 1 cm , the maximum
A
power-dissipation limit can be calculated. As indicated in Figure 18, the system R
maximum power-dissipation limit is:
is 94°C/W; therefore, the
θJA
T
T
J(max)
A
°
°
125 C 55 C
P
745 mW
D(max)
°
R
94 C W
JA(system)
IfthesystemimplementsaTPS71025regulatorwhereV =3.3VandI =385mA, theinternalpowerdissipation
I
O
is:
P
V
V
I
(3.3 2.5)
0.385
308 mW
D(total)
I
O
O
Comparing P
with P
reveals that the power dissipation in this example does not exceed the
D(total)
D(max)
maximum limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be
raisedbyincreasingtheairflowortheheat-sinkarea. Alternatively, theinternalpowerdissipationoftheregulator
can be lowered by reducing the input voltage or the load current. In either case, the above calculations should
be repeated with the new system parameters.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
APPLICATION INFORMATION
†
TPS71025
8
V
IN
IN
IN
EN
I
15
14
13
9
SENSE
OUT
10
V
O
C1
0.1 µF
50 V
6
OUT
+
C
o
10 µF
GND
CSR
1
2
3
†
Capacitor selection is nontrivial. See external capacitor requirements section.
Figure 19. Typical Application Circuit
The TPS71025 low-dropout (LDO) regulator overcomes many of the shortcomings of earlier-generation LDOs,
while adding features such as a power-saving shutdown mode.
device operation
The TPS71025, unlike many other LDOs, features very low quiescent current that remains virtually constant
even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is
directly proportional to the load current through the regulator (I = I /β). Examination of the data sheets reveals
B
C
that those devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves. The TPS71025 uses a PMOS
transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low
and stable over the full load range. The TPS71025 specifications reflect actual performance under load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates
B
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS71025 quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS71025 also features a shutdown mode that places the output in the high-impedance state (essentially
equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the shutdown feature
is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage
is reestablished in typically 120 µs.
minimum load requirements
The TPS71025 family is stable even at zero load; no minimum load is required for operation.
SENSE-pin connection
The SENSE pin must be connected to the regulator output for proper functioning of the regulator. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit (remote
sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth
amplifier through a resistor-divider network, and noise pickup feeds through to the regulator output. Routing the
SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and
OUT to filter noise is not recommended because it can cause the regulator to oscillate.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
APPLICATION INFORMATION
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transientresponseandnoiserejectioniftheTPS71025islocatedmorethanafewinchesfromthepowersupply.
A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients
with fast rise times are anticipated.
As with most LDO regulators, the TPS71025 requires an output capacitor for stability. A low-ESR 10-µF
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 11). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the
AVX TPSD106K035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at
25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem,
physically smaller, 10-µF devices can be screened for ESR. Figure 7 through Figure 14 show the stable regions
of operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be
reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because minimum capacitor ESR is
seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit
ESR to 1.5 Ω maximum. As shown in the ESR graphs (Figure 7 through Figure 14), minimum ESR is not a
problem when using 10-µF or larger output capacitors.
Below is a partial listing of surface-mount capacitors usable with the TPS71025. This information (along with
the ESR graphs, Figure 7 through Figure 14) is included to assist in selection of suitable capacitance for the
application. When necessary to achieve low height requirements along with high output current and/or high
ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
APPLICATION INFORMATION
external capacitor requirements (continued)
All load and temperature conditions with up to 1 µF of added ceramic load capacitance:
†
†
†
†
PART NO.
MFR.
VALUE
MAX ESR
0.5
SIZE (H × L × W)
2.8 × 6 × 3.2
T421C226M010AS
593D156X0025D2W
593D106X0035D2W
Kemet
22 µF, 10 V
Sprague 15 µF, 25 V
Sprague 10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
2.8 × 7.3 × 4.3
2.8 × 7.3 × 4.3
0.3
TPSD106M035R0300 AVX
10 µF, 35 V
0.3
Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:
†
PART NO.
MFR.
VALUE
MAX ESR
SIZE (H × L × W)
1.2 × 7.2 × 6
592D156X0020R2T
595D156X0025C2T
595D106X0025C2T
293D226X0016D2W
Sprague 15 µF, 20 V
Sprague 15 µF, 25 V
Sprague 10 µF, 25 V
Sprague 22 µF, 16 V
1.1
1
2.5 × 7.1 × 3.2
2.5 × 7.1 × 3.2
2.8 × 7.3 × 4.3
1.2
1.1
Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:
†
PART NO.
MFR.
VALUE
MAX ESR
1.5
SIZE (H × L × W)
1.3 × 3.5 × 2.7
1.3 × 7 × 2.7
195D106X06R3V2T
195D106X0016X2T
595D156X0016B2T
695D226X0015F2T
695D156X0020F2T
695D106X0035G2T
Sprague 10 µF, 6.3 V
Sprague 10 µF, 16 V
Sprague 15 µF, 16 V
Sprague 22 µF, 15 V
Sprague 15 µF, 20 V
Sprague 10 µF, 35 V
1.5
1.8
1.6 × 3.8 × 2.6
1.8 × 6.5 × 3.4
1.8 × 6.5 × 3.4
2.5 × 7.6 × 2.5
1.4
1.5
1.3
†
Size is in mm. ESR is maximum resistance at 100 kHz and T = 25°C. Listings are sorted by height.
A
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
TPS71025D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
71025
71025
71025
71025
TPS71025DG4
TPS71025DR
TPS71025DRG4
TPS71025P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
P
P
75
2500
2500
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
TPS71025P
TPS71025P
TPS71025PE4
50
Pb-Free
(RoHS)
N / A for Pkg Type
TPS71025PWLE
TPS71025PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PT71025
TPS71025PWRG4
ACTIVE
TSSOP
PW
20
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS71025DR
SOIC
D
8
2500
2000
330.0
330.0
12.4
16.4
6.4
5.2
7.1
2.1
1.6
8.0
8.0
12.0
16.0
Q1
Q1
TPS71025PWR
TSSOP
PW
20
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71025DR
SOIC
D
8
2500
2000
367.0
367.0
367.0
367.0
35.0
38.0
TPS71025PWR
TSSOP
PW
20
Pack Materials-Page 2
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相关型号：
TPS71157YZR
IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PBGA8, CSP-8, Fixed Positive Multiple Output LDO Regulator
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