TPS71229DRCT [TI]
Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator;
| 型号： | TPS71229DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator 光电二极管 输出元件 调节器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS71202, TPS71219
TPS71229, TPS71247
A ctu al S ize
(3 m m x 3 m m)
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
Dual 250 mA Output, UltraLow Noise, High PSRR,
Low-Dropout Linear Regulator
Check for Samples: TPS71202, TPS71219, TPS71229, TPS71247, TPS71256, TPS71257
1
FEATURES
DESCRIPTION
•
Dual 250 mA High-Performance RF LDOs
The TPS712xx family of low-dropout (LDO) voltage
regulators is tailored to noise-sensitive and RF
applications. These products feature dual 250 mA
LDOs with ultralow noise, high power-supply rejection
ratio (PSRR), and fast transient and start-up
response. Each regulator output is stable with
low-cost 2.2 mF ceramic output capacitors and
features very low dropout voltages (125 mV typical at
250 mA). Each regulator achieves fast start-up times
(approximately 60 ms with a 0.001 mF bypass
capacitor) while consuming very low quiescent
current (300 mA typical with both outputs enabled).
When the device is placed in standby mode, the
supply current is reduced to less than 0.3 mA typical.
Each regulator exhibits approximately 32 mVrms of
output voltage noise with VOUT = 2.8 V and a 0.01 mF
noise reduction (NR) capacitor. Applications with
analog components that are noise-sensitive, such as
portable RF electronics, will benefit from high PSRR,
low noise, and fast line and load transient features.
The TPS712 family is offered in a thin 3mm x 3mm
SON package and is fully specified from -40°C to
+125°C (TJ).
•
Available in Fixed and Adjustable
Voltage Options (1.2 V to 5.5 V)
•
•
•
•
•
•
•
•
High PSRR: 65 dB at 10 kHz
UltraLow Noise: 32 mVrms
Fast Start-Up Time: 60 ms
Stable with 2.2 mF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage: 125 mV at 250 mA
Independent Enable Pins
Thermal Shutdown and Independent Current
Limit
•
Available in Thermally-Enhanced SON
Package: 3mm x 3mm x 1mm
APPLICATIONS
•
•
•
•
•
Cellular and Cordless Phones
Wireless PDA/Handheld Products
PCMCIA/Wireless LAN Applications
Digital Camera/Camcorder/Internet Audio
DSP/FPGA/ASIC/Controllers and Processors
PSRR (RIPPLE REJECTION) vs FREQUENCY
80
70
60
50
40
30
20
10
0
IOUT = 250 mA
DRC PACKAGE
3mm x 3mm SON
(TOP VIEW)
IN
NC
1
2
3
4
5
10 EN1
IOUT = 1 mA
9
8
7
6
FB1/NC
OUT1
OUT2
GND
EN2
FB2/NC
NR
VOUT = 2.8 V
µ
COUT = 2.2
CNR = 0.01
F
F
µ
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
VOLTAGE (V)
VOUT1 VOUT2
Adjustable Adjustable
PACKAGE-
LEAD
(DESIGNATOR)
SPECIFIED
TEMPERATURE
RANGE (TJ)
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
TPS71202DRCT
TPS71202DRCR
TPS71219DRCT
TPS71219DRCR
TPS71229DRCT
TPS71229DRCR
TPS71247DRCT
TPS71247DRCR
TPS71256DRCT
TPS71256DRCR
TPS71257DRCT
TPS71257DRCR
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
TPS71202
SON-10 (DRC)
SON-10 (DRC)
SON-10 (DRC)
SON-10 (DRC)
SON-10 (DRC)
SON-10 (DRC)
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
ARQ
ARW
ARU
ARS
ARV
ART
TPS71219
TPS71229
TPS71247
TPS71256
TPS71257
1.8 V
2.8 V
1.8 V
2.8 V
2.85 V
Adjustable
Adjustable
2.85 V
2.8 V
2.85 V
(1) For the most current package and ordering information, see the Package Ordering Addendum located at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
TPS712xx
-0.3 to 6.0
UNIT
VIN range
V
V
V
VEN1, VEN2 range
-0.3 to VIN + 0.3
-0.3 to 6.0
VOUT range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
Internally limited
Indefinite
See Dissipation Ratings Table
-40 to +150
-65 to +150
2
°C
°C
kV
V
ESD rating, CDM
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS712xx
THERMAL METRIC(1)(2)
UNITS
DRC (10 PINS)
qJA
Junction-to-ambient thermal resistance
49.6
70.0
17.8
0.6
qJCtop
qJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
yJB
15.2
5.2
qJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
2
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = -40°C to +125°C), VIN = highest VOUT(nom) + 1.0 V or 2.7 V (whichever is greater),
IOUT = 1 mA, VEN1, 2 = 1.2 V, COUT = 10 mF, CNR = 0.01 mF, and adjustable LDOs are tested at VOUT = 3.0 V, unless otherwise
noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Input voltage range(1)
2.7
5.5
V
V
VFB
Internal reference (adjustable LDOs)
1.200
1.225 1.250
5.5 - VDO
+1.5
Output voltage range
(adjustable LDOs)
VFB
-1.5
-3
V
VOUT
Nominal
TJ = +25°C, IOUT = 0 mA
VOUT + 1.0 V ≤ VIN ≤ 5.5 V,
Accuracy(1)
%
Over VIN
,
±1
0.05
0.8
+3
IOUT, and T 0 mA ≤ IOUT ≤ 250 mA
ΔVOUT%/ΔVIN Line regulation(1)
VOUT + 1.0 V ≤ VIN ≤ 5.5 V
%/V
ΔVOUT%/ΔIOU
T
Load regulation
0 mA ≤ IOUT ≤ 250 mA
%/mA
2.8 V,
2.85 V
Adjustable
Dropout voltage(2)
VDO
IOUT1 = IOUT2 = 250 mA
125
230
mV
mA
(VIN = VOUT(nom) - 0.1V)
ICL
Output current limit
Ground pin current
Shutdown current(3)
VOUT = 0.9 × VOUT(nom)
400
600
190
800
250
One LDO
enabled
IOUT = 1 mA (enabled channel)
IGND
mA
Both LDOs
enabled
IOUT1 = IOUT2 = 1 mA to 250 mA
300
600
ISHDN
IFB
VEN ≤ 0.4 V, 0 V ≤ VIN ≤ 5.5 V
0.3
0.1
2.0
1
mA
mA
FB pin current (adjustable LDOs)
No CNR, IOUT = 250 mA
80.0 × VOUT
Output noise voltage,
BW = 10 Hz - 100 kHz
Vn
mVrms
CNR = 0.01 mF, IOUT = 250 mA
f = 100 Hz, IOUT = 250 mA
11.8 × VOUT
65
65
60
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
f = 10 kHz, IOUT = 250 mA
tSTR
VIH
VIL
Startup time
VOUT = 2.85 V, RL = 30Ω, CNR = 0.001 mF
ms
V
Enable threshold high (EN1, EN2)
Enable threshold low (EN1, EN2)
Enable pin current (EN1, EN2)
1.2
VIN
0.4
1
0
V
IEN
VIN = VEN = 5.5 V
-1
mA
Shutdown
Reset
Temp increasing
Temp decreasing
+160
+140
TSD
Thermal shutdown temperature
°C
Undervoltage lockout threshold
Undervoltage lockout hysteresis
VIN rising
VIN falling
2.25
2.65
V
UVLO
100
mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
(2) VDO is not measured for 1.8 V regulators since minimum VIN = 2.7 V.
(3) For the adjustable version, this applies only after VIN is applied; then VEN transitions from high to low.
Copyright © 2004–2010, Texas Instruments Incorporated
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TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM —
FIXED VERSION
FUNCTIONAL BLOCK DIAGRAM —
ADJUSTABLE VERSION
IN
OUT1
IN
OUT1
Current
Limit
Current
Limit
µ
30
A
90 kΩ
FB1
EN1
EN1
Thermal
Shutdown
Thermal
Shutdown
OUT2
OUT2
µ
30
A
Current
Limit
Current
Limit
UVLO
UVLO
90 kΩ
FB2
NR
EN2
EN2
Ω
250 k
Ω
250 k
NR
VREF
VREF
5 pF
5 pF
TPS712xx
Fixed/Fixed
1.225 V
1.225 V
TPS712xx
Adj/Adj
Quickstart
Quickstart
Table 1. TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
DRC
IN
1
Unregulated input supply. A small 0.1 mF capacitor should be connected from IN to GND.
GND
5, Pad
Ground
Output of the regulator. A small 2.2 mF ceramic capacitor is required from this pin to ground to assure
stability.
OUT1
OUT2
EN1
3
4
Same as OUT1 but for LDO2.
Driving the enable pin (EN) high turns on LDO1. Driving this pin low puts LDO1 into shutdown mode,
reducing operating current. The enable pin should be connected to IN if not used.
10
EN2
FB1/NC
FB2/NC
NR
8
9
7
6
2
Same as EN1 but controls LDO2.
Feedback for CH1 adjustable version; no connection for non-adjustable CH1.
Feedback for CH2 adjustable version; no connection for non-adjustable CH2.
Noise reduction pin; connect an external bypass capacitor to reduce LDO output noise.
No connection.
NC
4
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
OUTPUT VOLTAGE vs INPUT VOLTAGE
OUTPUT VOLTAGE vs OUTPUT CURRENT
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
+25
+25 C
C
−
_
40
C
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
_
+125
C
−
_
40
C
_
+125
C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
50
100
150
200
250
VIN (V)
IOUT (mA)
Figure 1.
Figure 2.
DROPOUT VOLTAGE vs INPUT VOLTAGE
(ADJUSTABLE VERSION)
OUTPUT VOLTAGE vs TEMPERATURE
200
180
160
140
120
100
80
1.0
0.5
0
_
TJ = +125
C
IOUT = 10 mA
_
TJ = +25 C
IOUT = 125 mA
−
−
−
0.5
1.0
1.5
60
IOUT = 250 mA
−
_
TJ
= 40 C
40
20
0
−
−
−
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
VIN (V)
40 25 10
5
20 35 50 65 80 95 110 125
_
Junction Temperature ( C)
Figure 3.
Figure 4.
TPS71256
TPS71256
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
200
150
100
50
250
_
TJ = +125
C
200
150
100
50
IOUT = 250 mA
−
_
TJ
= 40 C
_
TJ = +25 C
0
0
0
50
100
150
200
250
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
IOUT (mA)
Junction Temperature (°C)
Figure 5.
Figure 6.
Copyright © 2004–2010, Texas Instruments Incorporated
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TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE
GROUND PIN CURRENT vs IOUT
400
375
350
325
300
275
250
225
200
400
375
350
325
300
275
250
225
200
_
+125
C
_
+125
C
_
+25
C
−
_
40
C
_
+25
C
−
_
40 C
2.7
3.2
3.7
4.2
4.7
5.2
5.7
0
50
100
150
200
250
VIN (V)
IOUT (mA)
Figure 7.
Figure 8.
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
(DISABLED)
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
500
400
VEN1 = VEN2 = 0.4V
VEN1 = VEN2 = 1.2V
450
375
VIN = 3.8 V
VIN = 3.8 V
400
350
300
250
200
150
100
50
350
325
300
275
250
225
200
0
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
_
Junction Temperature ( C)
_
Junction Temperature ( C)
Figure 9.
Figure 10.
TPS71256
CURRENT LIMIT vs JUNCTION TEMPERATURE
LINE TRANSIENT RESPONSE
800
µ
COUT1 = COUT2 = 10
F
VIN = 3.8 V
750
700
650
600
550
500
450
400
3.8 V
3.2 V
VIN
IOUT = 250 mA
IOUT = 1 mA
VOUT1
10 mV/div
10 mV/div
VOUT2
µ
100 s/div
−
−
−
40 25 10
5
20 35 50 65 80 95 110 125
_
Junction Temperature ( C)
Figure 11.
Figure 12.
6
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Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
TPS71256
LOAD TRANSIENT RESPONSE
AND VOUT2 CROSSTALK
TPS71256
CHANNEL-TO-CHANNEL ISOLATION vs FREQUENCY
60
50
40
30
20
µ
COUT2 = 10
F
2 mV/div
VOUT2
µ
COUT1 = 10
F
100 mV/div
VOUT1
250 mA
µ
COUT1 = COUT2 = 10
F
10 mA
200 mA/div
IOUT1
10
0
IOUT1 = 0 mA to 500 mA Sinusoidal Load
IOUT2 = 25 mA
µ
20 s/div
0.1
1
10
100
1k
Frequency (Hz)
Figure 13.
TPS71256
Figure 14.
TURN-ON/OFF RESPONSE
AND VOUT2 CROSSTALK
TPS71229
POWER-UP/POWER-DOWN
IOUT1 = IOUT2 = 250 mA
µ
CNR = 0.01
F
IOUT1 = IOUT2 = 250 mA
µ
COUT1 = COUT 2 = 10
F
20 mV/div
VOUT2
VIN
µ
CNR = 0.001
F
VOUT1
VOUT2
VOUT1
VEN1
1 V/div
µ
50 s/div
50 ms/div
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
TOTAL NOISE vs CNR
COUT = 2.2 mF
250
200
150
100
50
350
300
250
200
150
100
50
µ
COUT = 2.2
F
µ
F
VOUT = 2.8 V
CNR = 0.1
IOUT = 250 mA
VOUT = 2.8 V
IOUT = 250 mA
µ
COUT = 2.2
F
IOUT = 0 mA
µ
COUT = 10
F
IOUT = 250 mA
IOUT = 1 mA
µ
COUT = 10
F
IOUT = 0 mA
0
0
1
10
100
1k
10k
100k
100
1k
10k
100k
CNR (pF)
Frequency (Hz)
Figure 17.
Figure 18.
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TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
NOISE SPECTRAL DENSITY
COUT = 10 mF
NOISE SPECTRAL DENSITY vs CNR
350
300
250
200
150
100
50
2.0
1.75
1.5
µ
CNR = 0.1
F
µ
COUT = 10
F
VOUT = 2.8 V
IOUT = 250 mA
VOUT = 2.8 V
1.25
1.0
µ
0.001
F
IOUT = 10 mA
µ
F
0.047
IOUT = 250 mA
µ
F
0.75
0.5
0.01
µ
0.1
F
0.25
0
100
0
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs FREQUENCY
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
IOUT = 1 mA
IOUT = 250 mA
IOUT = 1 mA
IOUT = 250 mA
VOUT = 2.8 V
VOUT = 2.8 V
µ
COUT = 10 F
µ
COUT = 2.2
CNR = 0.01
F
F
µ
µ
F
CNR = 0.01
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 21.
Figure 22.
PSRR (RIPPLE REJECTION) vs VIN - VOUT
80
70
60
50
40
30
20
10
0
f = 1 kHz
f = 10 kHz
f = 100 kHz
VOUT = 2.8 V
IOUT = 250 mA
µ
µ
COUT = 10
CNR = 0.01
F
F
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
−
VIN VOUT (V)
Figure 23.
8
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TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
APPLICATION INFORMATION
1.8 V or less is chosen, the minimum recommended
output capacitor is 4.7 mF. Any ceramic capacitor that
meets the minimum output capacitor requirements is
suitable. Capacitors with higher ESR may be used,
provided the ESR is less than 1Ω.
The TPS712xx family of dual low-dropout (LDO)
regulators has been optimized for use in
noise-sensitive battery-operated equipment. The
device features extremely low dropout, high PSRR,
ultralow output noise, and low quiescent current
(190 mA typical per channel). When both outputs are
disabled, the supply currents are reduced to less than
2 mA. A typical application circuit is shown in
Figure 24.
OUTPUT NOISE
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS712xx has an NR
pin that is connected to the voltage reference through
a 250 kΩ internal resistor. The 250 kΩ internal
resistor, in conjunction with an external ceramic
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. To
achieve a fast startup, the 250 kΩ internal resistor is
shorted for 400 ms after the device is enabled.
TPS712xx
VIN
VOUT1
IN
OUT1
µ
µ
2.2
2.2
F
VOUT2
EN1
EN2
OUT2
NR
µ
0.1
F
F
GND
µ
0.01
F
Because the primary noise source is the internal
voltage reference, the output noise will be greater for
higher output voltage versions. For the case where
no noise reduction capacitor is used, the typical noise
(mVrms) over 10 Hz to 100 kHz is 80 times the output
voltage. If a 0.01 mF capacitor is used from the NR
pin to ground, the noise (mVrms) drops to 11.8 times
the output voltage. For example, the TPS71256
exhibits only 33 mVrms of output voltage noise using
a 0.01 mF ceramic bypass capacitor and a 2.2 mF
ceramic output capacitor.
Figure 24. Typical Application Circuit
(fixed-voltage versions)
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
A 0.1 mF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS712xx, is required for stability. It improves
transient response, noise rejection, and ripple
rejection. A higher-value input capacitor may be
necessary if large, fast-rise-time load transients are
anticipated and the device is located several inches
from the power source.
STARTUP CHARACTERISITCS
To minimize startup overshoot, the TPS712xx will
initially target an output voltage that is approximately
80% of the final value. To avoid a delayed startup
time, noise reduction capacitors of 0.01 mF or less
are recommended. Larger noise reduction capacitors
will cause the output to hold at 80% until the voltage
on the noise reduction capacitor exceeds 80% of the
bandgap voltage. The typical startup time with a
0.001 mF noise reduction capacitor is 60 ms. Once
one of the output voltages is present, the startup time
of the other output will not be affected by the noise
reduction capacitor.
The TPS712xx requires an output capacitor
connected between the outputs and GND to stabilize
the
internal
control
loops.
The
minimum
recommended output capacitor is 2.2 mF. If an output
voltage
of
Copyright © 2004–2010, Texas Instruments Incorporated
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9
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
5
(
)
(
)
3 10 R1 ) R2
PROGRAMMING THE TPS71202
ADJUSTABLE LDO REGULATOR
(
)
pF
C1 +
(
)
R1 R2
(3)
The output voltage of the TPS71202 dual adjustable
regulator is programmed using an external resistor
divider, as shown in Figure 25. The output voltage is
calculated using Equation 1:
blank
The suggested value of this capacitor for several
resistor ratios is shown in Figure 25. If this capacitor
is not used (such as in a unity-gain configuration) or if
an output voltage ≤ 1.8 V is chosen, then the
minimum recommended output capacitor is 4.7 mF
instead of 2.2 mF.
R1
R2
ǒ Ǔ
VOUT + VREF 1 )
(1)
where VREF
voltage).
=
1.225
V
(the internal reference
DROPOUT VOLTAGE
Resistors R2 and R4 should be chosen for
approximately a 40 mA divider current. Lower value
resistors can be used for improved noise
performance, but will consume more power. Higher
values should be avoided because leakage current at
FB increases the output voltage error. The
recommended design procedure is to choose R2 =
30.1 kΩ to set the divider current at 40 mA, and then
calculate R1 using Equation 2:
The TPS712xx uses a PMOS pass transistor to
achieve extremely low dropout. When (VIN - VOUT) is
less than the dropout voltage (VDO), the PMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the PMOS
pass element. Dropout voltages at lower currents can
be approximated by calculating the effective RDS, ON
of the pass element and multiplying that resistance by
the load current. RDS, ON of the pass element can be
obtained by dividing the dropout voltage by the rated
output current. For the TPS71256, the RDS, ON of the
pass element is 84 mΩ. The dropout voltage of the
TPS712xx will be less for higher output voltage
versions. This is because the PMOS pass element
will have lower on-resistance due to increased gate
drive.
R1 + ǒVOUT Ǔ
* 1 R2
VREF
(2)
To improve the stability and noise performance of the
adjustable version, a small compensation capacitor
can be placed between OUT and FB.
For voltages ≤ 1.8 V, the value of this capacitor
should be 100 pF. For voltages > 1.8 V, the
approximate value of this capacitor can be calculated
as Equation 3:
TPS71202
VIN
VOUT1
IN
OUT1
FB1
Output Voltage Programming Guide
µ
µ
2.2
F
F
R1
R2
C1
V
OUT
R1/R3
R2/R4
C1/C2
EN1
EN2
1.225 V
1.5 V
Short
Open
Open
100 pF
22 pF
15 pF
15 pF
15 pF
7.15 kΩ
31.6 kΩ
43.2 kΩ
49.9 kΩ
86.6 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
µ
0.1
F
VOUT2
2.5 V
OUT2
FB2
2.2
R3
R4
3.0 V
C2
NR
GND
3.3 V
µ
0.01
F
4.75 V
Figure 25. TPS71202 Adjustable LDO Regulator Programming
10
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
TRANSIENT RESPONSE
enabled. Depending on power dissipation, thermal
resistance, and ambient temperature, the thermal
protection circuit may cycle on and off. This limits the
dissipation of the regulator, protecting it from damage
due to overheating.
As with any regulator, increasing the size of the
output capacitor will reduce over/undershoot
magnitude but increase duration of the transient
response. In the adjustable version, the addition of a
capacitor, CFB, from the output to the feedback pin
will also improve stability and transient response. The
transient response of the TPS712xx is enhanced with
an active pull-down that engages when the output is
over-voltaged. The active pull-down decreases the
output recovery time when the load is removed.
Figure 13 in the Typical Characteristics section shows
the output transient response.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
SHUTDOWN
condition of your application. This produces
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
a
Both enable pins are active high and are compatible
with standard TTL-CMOS levels. The device is only
completely disabled when both EN1 and EN2 are
logic low. In this state, the LDO is completely off and
the ground pin current drops to approximately 100
nA. With one output disabled, the ground pin current
is slightly greater than half the nominal value. When
shutdown capability is not required, the enable pins
should be connected to the input supply.
The internal protection circuitry of the TPS712xx was
designed to protect against overload conditions. It
was not intended to replace proper heatsinking.
Continuously running the TPS712xx into thermal
shutdown will degrade device reliability.
POWER DISSIPATION
INTERNAL CURRENT LIMIT
The ability to remove heat from the die is different for
The TPS712xx internal current limit helps protect the
regulator during fault conditions. During current limit,
the output will source a fixed amount of current that is
largely independent of the output voltage.
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for a JEDEC high-K board is
shown in the Dissipation Ratings table. Using heavier
copper will increase the effectiveness in removing
heat from the device. The addition of plated
through-holes to heat-dissipating layers will also
improve the heat-sink effectiveness.
The TPS712xx PMOS-pass transistors have a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (that is,
during power-down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting may be appropriate.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
THERMAL PROTECTION
Thermal protection disables both outputs when the
junction temperature of either channel rises to
approximately +160°C, allowing the device to cool.
PD + (VIN * VOUT) IOUT
(4)
When
the
junction
temperature
cools
to
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
approximately +140°C, the output circuitry is again
Copyright © 2004–2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July, 2005) to Revision D
Page
•
Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3
12
Submit Documentation Feedback
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
PACKAGING INFORMATION
Orderable Device
TPS71202DRCR
TPS71202DRCRG4
TPS71202DRCT
TPS71202DRCTG4
TPS71219DRCR
TPS71219DRCRG4
TPS71219DRCT
TPS71219DRCTG4
TPS71229DRCR
TPS71229DRCRG4
TPS71229DRCT
TPS71229DRCTG4
TPS71247DRCR
TPS71247DRCRG4
TPS71247DRCT
TPS71247DRCTG4
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125 ARQ
-40 to 125 ARQ
-40 to 125 ARQ
-40 to 125 ARQ
-40 to 125 ARW
-40 to 125 ARW
-40 to 125 ARW
-40 to 125 ARW
-40 to 125 ARU
-40 to 125 ARU
-40 to 125 ARU
-40 to 125 ARU
-40 to 125 ARS
-40 to 125 ARS
-40 to 125 ARS
-40 to 125 ARS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
TPS71256DRCR
OBSOLETE
OBSOLETE
SON
SON
DRC
DRC
10
10
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125 ARV
-40 to 125
TPS71256DRCRG4
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
TPS71256DRCT
TPS71256DRCTG4
TPS71257DRCR
TPS71257DRCRG4
TPS71257DRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
SON
SON
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125 ARV
-40 to 125 ARV
-40 to 125 ART
-40 to 125 ART
-40 to 125 ART
-40 to 125 ART
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS71257DRCTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS71202 :
Enhanced Product: TPS71202-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS71202DRCR
TPS71202DRCT
TPS71219DRCR
TPS71219DRCT
TPS71229DRCR
TPS71229DRCT
TPS71247DRCR
TPS71247DRCT
TPS71256DRCT
TPS71257DRCR
TPS71257DRCT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71202DRCR
TPS71202DRCT
TPS71219DRCR
TPS71219DRCT
TPS71229DRCR
TPS71229DRCT
TPS71247DRCR
TPS71247DRCT
TPS71256DRCT
TPS71257DRCR
TPS71257DRCT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
250
3000
250
Pack Materials-Page 2
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相关型号：
TPS71256DRCR
Dual 250 mA Output, UltraLow Noise, High PSRR Low Dropout Linear Regulator 10-VSON -40 to 125
TI
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