TPS7148QDRG4_技术文档

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

D OR P PACKAGE

(TOP VIEW)

Available in 5-V, 4.85-V, and 3.3-V

Fixed-Output and Adjustable Versions

Very Low-Dropout Voltage . . . Maximum of

GND

EN

IN

PG

1

2

3

4

8

7

6

5

32 mV at I = 100 mA (TPS7150)

†

‡

O

SENSE /FB

OUT

Very Low Quiescent Current – Independent

of Load . . . 285 µA Typ

IN

OUT

Extremely Low Sleep-State Current

0.5 µA Max

PW PACKAGE

(TOP VIEW)

2% Tolerance Over Specified Conditions

For Fixed-Output Versions

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

NC

EN

PG

NC

Output Current Range of 0 mA to 500 mA

TSSOP Package Option Offers Reduced

Component Height for Space-Critical

Applications

‡

FB

NC

Power-Good (PG) Status Output

†

SENSE

NC

IN

OUT

NC

description

IN

The TPS71xx integrated circuits are a family

of micropower low-dropout (LDO) voltage

regulators. An order of magnitude reduction in

dropout voltage and quiescent current over

conventional LDO performance is achieved by

replacing the typical pnp pass transistor with a

PMOS device.

IN

NC

NC – No internal connection

SENSE – Fixed voltage options only

(TPS7133, TPS7148, and TPS7150)

FB – Adjustable version only (TPS7101)

†

‡

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32

mV at an output current of 100 mA for the TPS7150) and is directly proportional to the output current (see

Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very

low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to

500 mA). These two key specifications yield a significant improvement in operating life for battery-powered

systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down

the regulator, reducing the quiescent current to 0.5 µA maximum at T = 25°C.

J

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

description (continued)

0.25

T

A

= 25°C

0.2

0.15

0.1

TPS7133

TPS7148

TPS7150

0.05

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

– Output Current – A

I

O

Figure 1. Dropout Voltage Versus Output Current

Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery

indicator.

The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version

(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%

over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in PDIP

(8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of 1,2 mm.

AVAILABLE OPTIONS

OUTPUT VOLTAGE

PACKAGED DEVICES

(V)

CHIP FORM

T

J

(Y)

SMALL OUTLINE

(D)

PLASTIC DIP

(P)

TSSOP

(PW)

MIN

TYP

MAX

4.9

4.75

3.23

5

4.85

3.3

5.1

4.95

3.37

TPS7150QD

TPS7148QD

TPS7133QD

TPS7150QP

TPS7148QP

TPS7133QP

TPS7150QPW

TPS7148QPW

TPS7133QPW

TPS7150Y

TPS7148Y

TPS7133Y

–40°C to 125°C

†

Adjustable

1.2 V to 9.75 V

TPS7101QD

TPS7101QP

TPS7101QPW

TPS7101Y

†

The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS7150QDR). The TPS7101Q is

programmable using an external resistor divider (see application information). The chip form is tested at 25°C.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

TPS71xx

8

20

15

14

13

V

IN

PG

I

9

IN

SENSE

OUT

10

V

O

6

0.1 µF

EN

OUT

‡

C

O

+

10 µF

GND

1

2

3

CSR

†

‡

TPS7133, TPS7148, TPS7150 (fixed-voltage options)

Capacitor selection is nontrivial. See application information section

for details.

Figure 2. Typical Application Configuration

TPS71xx chip information

These chips, when properly assembled, display characteristics similar to the TPS71xxQ. Thermal compression

or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with

conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(5)

(6)

§

SENSE

(3)

(2)

IN

¶

FB

(4)

(5)

(6)

TPS71xx

(4)

(7)

OUT

PG

EN

(1)

(7)

GND

CHIP THICKNESS: 15 MILS TYPICAL

80

BONDING PADS: 4 × 4 MILS MINIMUM

T max = 150°C

J

TOLERANCES ARE ±10%.

ALL DIMENSIONS ARE IN MILS.

§

¶

SENSE – Fixed voltage options only (TPS7133, TPS7148,

and TPS7150)

FB – Adjustable version only (TPS7101)

(3)

(2)

(1)

NOTE A: For most applications, OUT and SENSE should

betiedtogetherascloseaspossibletothedevice;

for other implementations, refer to SENSE-pin

connection discussion in the Applications

Information section of this data sheet.

92

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

functional block diagram

IN

RESISTOR DIVIDER OPTIONS

†

DEVICE

R1

R2

UNIT

†

EN

TPS7101

TPS7133

TPS7148

TPS7150

0

∞

Ω

420

726

756

233

kΩ

PG

_

+

NOTE A: Resistors are nominal values only.

OUT

COMPONENT COUNT

‡

1.12 V

SENSE /FB

MOS transistors

Bilpolar transistors

Diodes

Capacitors

Resistors

464

41

4

17

76

+

_

R1

R2

V

ref

= 1.178 V

GND

Switch positions are shown with EN low (active).

For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to

SENSE-pin connection discussion in Applications Information section.

†

‡

§

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

¶

Input voltage range , V , PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 11 V

I

Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A

O

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

§

¶

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to network terminal ground.

#

DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Figure 3)

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 125°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

D

P

PW

725 mW

1175 mW

700 mW

5.8 mW/°C

9.4 mW/°C

5.6 mW/°C

464 mW

752 mW

448 mW

145 mW

235 mW

140 mW

||

#

DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Figure 4)

≤ 25°C DERATING FACTOR = 70°C

T

C

T

C

T

= 125°C

C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

C

D

P

PW

2188 mW

2738 mW

4025 mW

17.5 mW/°C

21.9 mW/°C

32.2 mW/°C

1400 mW

1752 mW

2576 mW

438 mW

548 mW

805 mW

||

#

||

Dissipation rating tables and figures are provided for maintenance of junction temperature at or below

absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within

recommended operating range, see the Thermal Information section.

Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

DISSIPATION DERATING CURVE

vs

†

DISSIPATION DERATING CURVE

vs

FREE-AIR TEMPERATURE

CASE TEMPERATURE

1400

1200

4800

4400

PW Package

4000

3600

3200

2800

2400

2000

1600

1200

800

R

= 31°C/W

θJC

P Package

R

= 106°C/W

1000

800

θJA

P Package

R

= 46°C/W

θJC

D Package

R

= 172°C/W

θJA

600

400

200

0

PW and PWP

Package

= 178°C/W

D Package

= 57°C/W

R

θJA

400

R

θJC

0

25

50

75

100

125

150

25

50

75

100

125

150

T

A

– Free-Air Temperature – °C

T – Case Temperature – °C

C

Figure 3

Figure 4

†

Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.

For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.

recommended operating conditions

MIN

2.5

3.77

5.2

5.33

2

MAX

10

UNIT

TPS7101Q

TPS7133Q

TPS7148Q

TPS7150Q

10

‡

Input voltage, V

V

I

10

High-level input voltage at EN, V

V

IH

Low-level input voltage at EN, V

0.5

500

125

IL

Output current range, I

0

mA

°C

O

Operating virtual junction temperature range, T

–40

J

‡

Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the

maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To

calculate the minimum input voltage for your maximum output current, use the following equation: V

= V

+ V

I(min)

O(max)

beforeapplyingtheaboveequation.Theequationforcalculating

DO(max load)

BecausetheTPS7101isprogrammable,r

DS(on)

shouldbeusedtocalculateV

DO

V

from r

is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the

DO

DS(on)

recommended input voltage range for the TPS7101.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE/FB shorted to OUT

O

(unless otherwise noted)

TPS7101Q, TPS7133Q

TPS7148Q, TPS7150Q

‡

PARAMETER

T

J

UNIT

TEST CONDITIONS

MIN

TYP

MAX

350

460

0.5

2

25°C

–40°C to 125°C

25°C

285

EN ≤ 0.5 V,

V = V + 1 V,

I O

Ground current (active mode)

Input current (standby mode)

Output current limit

µA

A

0 mA ≤ I ≤ 500 mA

O

EN = V ,

2.7 V ≤ V ≤ 10 V

I

–40°C to 125°C

25°C

1.2

2

V

O

= 0,

V = 10 V

I

–40°C to 125°C

25°C

2

0.5

1

Pass-element leakage current in standby

mode

µA

EN = V ,

I

2.7 V ≤ V ≤ 10 V

I

–40°C to 125°C

25°C

0.02

0.5

Normal operation,

V

PG

= 10 V

PG leakage current

–40°C to 125°C

Output voltage temperature coefficient

Thermal shutdown junction temperature

61

75 ppm/°C

°C

165

2.5 V ≤ V ≤ 6 V

2

I

–40°C to 125°C

V

EN logic high (standby mode)

6 V ≤ V ≤ 10 V

2.7

I

25°C

–40°C to 125°C

25°C

0.5

V

2.7 V ≤ V ≤ 10 V

EN logic low (active mode)

EN hysteresis voltage

I

0.5

50

mV

25°C

–0.5

0.5

µA

0.5

0 V ≤ V ≤ 10 V

I

EN input current

I

–40°C to 125°C

25°C

2.05

1.06

2.5

V

Minimum V for active pass element

I

–40°C to 125°C

25°C

2.5

1.5

V

Minimum V for valid PG

I

= 300 µA

I

= 300 µA

I

PG

–40°C to 125°C

1.9

†

‡

CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any

series resistance added externally, and PWB trace resistance to C .

O

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

TPS7101 electrical characteristics at I = 10 mA, V = 3.5 V, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, FB

shorted to OUT at device leads (unless otherwise noted)

O

I

O

TPS7101Q

‡

T

PARAMETER

UNIT

V

TEST CONDITIONS

J

MIN

TYP

MAX

V = 3.5 V,

I

O

= 10 mA

25°C

1.178

I

Reference voltage (measured at FB

with OUT connected to FB)

2.5 V ≤ V ≤ 10 V,

5 mA ≤ I ≤ 500 mA,

O

I

–40°C to 125°C 1.143

–40°C to 125°C

1.213

V

See Note 1

Reference voltage temperature

coefficient

61

75 ppm/°C

25°C

–40°C to 125°C

25°C

0.7

1

V = 2.4 V,

50 µA ≤ I ≤ 150 mA

O

I

0.83

0.52

1.3

150 mA ≤ I ≤ 500

O

V = 2.4 V,

I

mA

–40°C to 125°C

25°C

1.3

Pass-element series resistance

(see Note 2)

Ω

0.85

V = 2.9 V,

I

50 µA ≤ I ≤ 500 mA

O

–40°C to 125°C

25°C

0.85

V = 3.9 V,

I

50 µA ≤ I ≤ 500 mA

0.32

0.23

O

V = 5.9 V,

I

50 µA ≤ I ≤ 500 mA

25°C

O

25°C

18

25

14

25

22

54

V = 2.5 V to 10 V,

I

50 µA ≤ I ≤ 500 mA,

O

Input regulation

mV

See Note 1

–40°C to 125°C

25°C

I

= 5 mA to 500 mA, 2.5 V ≤ V ≤ 10 V,

I

O

See Note 1

–40°C to 125°C

25°C

Output regulation

I

O

= 50 µA to 500 mA, 2.5 V ≤ V ≤ 10 V,

I

See Note 1

f = 120 Hz

–40°C to 125°C

25°C

–40°C to 125°C

25°C

48

44

45

44

59

54

I

= 50 µA

O

Ripple rejection

dB

= 500 mA,

O

See Note 1

–40°C to 125°C

25°C

Output noise-spectral density

Output noise voltage

f = 120 Hz

2

95

89

74

µV/√Hz

µVrms

C

= 4.7 µF

= 10 µF

= 100 µF

25°C

O

10 Hz ≤ f ≤ 100 kHz,

25°C

†

CSR = 1 Ω

25°C

§

V

FB

voltage decreasing from above V

PG

–40°C to 125°C 1.101

1.145

V

PG trip-threshold voltage

§

25°C

12

mV

Measured at V

PG hysteresis voltage

FB

0.1

0.4

10

§

I

= 400 µA,

V = 2.13 V

I

V

PG output low voltage

PG

–40°C to 125°C

25°C

–10

–20

0.1

FB input current

nA

–40°C to 125°C

20

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

‡

§

Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When V < 2.9 V and I > 150 mA simultaneously, pass element r

increases (see Figure 27) to a point such that the resulting

I

O

DS(on)

dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation:

V

DO

= I

r

O

DS(on)

r

is a function of both output current and input voltage. The parametric table lists r

for V = 2.4 V, 2.9 V, 3.9 V, and

I

DS(on)

5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other

programmed values, refer to Figure 26.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

TPS7133 electrical characteristics at I = 10 mA, V = 4.3 V, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE

shorted to OUT (unless otherwise noted)

O

I

O

TPS7133Q

‡

T

J

PARAMETER

UNIT

TEST CONDITIONS

MIN

TYP

MAX

V = 4.3 V,

I

= 10 mA

25°C

3.3

I

O

Output voltage

V

4.3 V ≤ V ≤ 10 V,

5 mA ≤ I ≤ 500 mA –40°C to 125°C

3.23

3.37

7

I

O

25°C

4.5

47

I

O

I

O

I

O

= 10 mA,

= 100 mA,

= 500 mA,

V = 3.23 V

I

–40°C to 125°C

25°C

8

60

V = 3.23 V

I

mV

Dropout voltage

–40°C to 125°C

25°C

80

235

0.47

300

400

0.6

0.8

20

V = 3.23 V

I

–40°C to 125°C

25°C

(3.23 V – V )/I ,

V = 3.23 V,

I

O

Pass-element series resistance

Input regulation

Ω

I

O

= 500 mA

–40°C to 125°C

25°C

V = 4.3 V to 10 V,

I

50 µA ≤ I ≤ 500 mA

mV

O

–40°C to 125°C

25°C

27

21

30

54

49

38

I

= 5 mA to 500 mA, 4.3 V ≤ V ≤ 10 V

I

O

–40°C to 125°C

25°C

75

Output regulation

Ripple rejection

60

I

= 50 µA to 500 mA, 4.3 V ≤ V ≤ 10 V

I

–40°C to 125°C

25°C

120

43

40

39

36

I

= 50 µA

O

–40°C to 125°C

25°C

f = 120 Hz

dB

I

= 500 mA

–40°C to 125°C

25°C

Output noise-spectral density

Output noise voltage

f = 120 Hz

2

274

228

159

µV/√Hz

µVrms

25°C

C

= 4.7 µF

= 10 µF

= 100 µF

O

10 Hz ≤ f ≤ 100 kHz,

25°C

†

CSR = 1 Ω

25°C

V

O

voltage decreasing from above V

PG

–40°C to 125°C 2.868

25°C

3

V

PG trip-threshold voltage

PG hysteresis voltage

35

mV

25°C

0.22

0.4

PG output low voltage

I

= 1 mA,

V = 2.8 V

I

V

PG

–40°C to 125°C

†

‡

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

TPS7148 electrical characteristics at I =10mA, V =5.85V, EN=0V, C =4.7µF/CSR =1Ω,SENSE

shorted to OUT (unless otherwise noted)

O

I

O

TPS7148Q

‡

T

J

PARAMETER

UNIT

TEST CONDITIONS

MIN

TYP

MAX

V = 5.85 V,

I

= 10 mA

25°C

4.85

I

O

Output voltage

V

5.85 V ≤ V ≤ 10 V,

5 mA ≤ I ≤ 500 mA –40°C to 125°C

4.75

4.95

6

I

O

25°C

2.9

30

I

O

I

O

I

O

= 10 mA,

= 100 mA,

= 500 mA,

V = 4.75 V

I

–40°C to 125°C

25°C

8

37

V = 4.75 V

I

mV

Dropout voltage

–40°C to 125°C

25°C

54

150

0.32

180

250

0.35

0.52

27

V = 4.75 V

I

–40°C to 125°C

25°C

(4.75 V – V )/I ,

V = 4.75 V,

I

O

Pass-element series resistance

Input regulation

Ω

I

O

= 500 mA

–40°C to 125°C

25°C

V = 5.85 V to 10 V,

I

50 µA ≤ I ≤ 500 mA

mV

O

–40°C to 125°C

25°C

37

12

42

53

50

42

I

= 5 mA to 500 mA, 5.85 V ≤ V ≤ 10 V

I

O

–40°C to 125°C

25°C

80

Output regulation

Ripple rejection

60

I

= 50 µA to 500 mA, 5.85 V ≤ V ≤ 10 V

I

–40°C to 125°C

25°C

130

42

39

35

I

= 50 µA

O

–40°C to 125°C

25°C

f = 120 Hz

dB

I

= 500 mA

–40°C to 125°C

25°C

Output noise-spectral density

Output noise voltage

f = 120 Hz

2

410

328

212

µV/√Hz

µVrms

25°C

C

= 4.7 µF

= 10 µF

= 100 µF

O

10 Hz ≤ f ≤ 100 kHz,

25°C

†

CSR = 1 Ω

25°C

V

O

voltage decreasing from above V

PG

–40°C to 125°C

25°C

4.5

4.7

V

PG trip-threshold voltage

PG hysteresis voltage

50

mV

25°C

0.2

0.4

I

= 1.2 mA,

V = 4.12 V

I

V

PG output low voltage

PG

–40°C to 125°C

†

‡

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

TPS7150 electrical characteristics at I = 10 mA, V = 6 V, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, SENSE

shorted to OUT (unless otherwise noted)

O

I

O

TPS7150Q

‡

T

J

PARAMETER

UNIT

TEST CONDITIONS

MIN

TYP

MAX

V = 6 V,

I

= 10 mA

25°C

5

I

O

Output voltage

V

6 V ≤ V ≤ 10 V,

5 mA ≤ I ≤ 500 mA –40°C to 125°C

4.9

5.1

6

I

O

25°C

2.9

27

I

O

I

O

I

O

= 10 mA,

= 100 mA,

= 500 mA,

V = 4.88 V

I

–40°C to 125°C

25°C

8

32

V = 4.88 V

I

mV

Dropout voltage

–40°C to 125°C

25°C

47

146

0.29

170

230

0.32

0.47

25

V = 4.88 V

I

–40°C to 125°C

25°C

(4.88 V – V )/I ,

V = 4.88 V,

I

O

Pass-element series resistance

Input regulation

Ω

I

O

= 500 mA

–40°C to 125°C

25°C

V = 6 V to 10 V,

I

50 µA ≤ I ≤ 500 mA

mV

O

–40°C to 125°C

25°C

32

30

45

55

52

45

I

= 5 mA to 500 mA, 6 V ≤ V ≤ 10 V

I

O

–40°C to 125°C

25°C

86

Output regulation

Ripple rejection

65

I

= 50 µA to 500 mA, 6 V ≤ V ≤ 10 V

I

–40°C to 125°C

25°C

140

45

40

42

36

I

= 50 µA

O

–40°C to 125°C

25°C

f = 120 Hz

dB

I

= 500 mA

–40°C to 125°C

25°C

Output noise-spectral density

Output noise voltage

f = 120 Hz

2

430

345

220

µV/√Hz

µVrms

25°C

C

= 4.7 µF

= 10 µF

= 100 µF

O

10 Hz ≤ f ≤ 100 kHz,

25°C

†

CSR = 1 Ω

25°C

V

O

voltage decreasing from above V

PG

–40°C to 125°C

25°C

4.55

4.75

V

PG trip-threshold voltage

PG hysteresis voltage

53

mV

25°C

0.2

0.4

PG output low voltage

I

= 1.2 mA,

V = 4.25 V

I

V

PG

–40°C to 125°C

†

‡

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, T = 25°C, SENSE/FB

O

J

shorted to OUT (unless otherwise noted)

TPS7101Y, TPS7133Y

TPS7148Y, TPS7150Y

‡

PARAMETER

UNIT

TEST CONDITIONS

MIN

TYP

MAX

EN ≤ 0.5 V,

0 mA ≤ I ≤ 500 mA

V = V + 1 V,

I O

Ground current (active mode)

285

µA

O

Output current limit

V

= 0,

V = 10 V

1.2

0.02

165

50

A

µA

°C

mV

V

O

I

Normal operation,

V

PG

= 10 V

PG leakage current

Thermal shutdown junction temperature

EN hysteresis voltage

Minimum V for active pass element

2.05

1.06

I

Minimum V for valid PG

I

= 300 µA

V

I

PG

TPS7101Y

TYP

‡

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

Reference voltage (measured at FB with OUT

connected to FB)

V = 3.5 V,

I

O

= 10 mA

1.178

V

V = 2.4 V,

50 µA ≤ I ≤ 150 mA

0.7

0.83

0.52

0.32

0.23

I

O

V = 2.4 V,

I

150 mA ≤ I ≤ 500 mA

O

V = 2.9 V,

I

50 µA ≤ I ≤ 500 mA

Ω

Pass-element series resistance (see Note 2)

O

V = 3.9 V,

I

50 µA ≤ I ≤ 500 mA

O

V = 5.9 V,

I

50 µA ≤ I ≤ 500 mA

O

V = 2.5 V to 10 V,

I

50 µA ≤ I ≤ 500 mA,

O

Input regulation

18

14

22

mV

See Note 1

2.5 V ≤ V ≤ 10 V,

I

= 5 mA to 500 mA,

I

O

See Note 1

Output regulation

2.5 V ≤ V ≤ 10 V,

I

= 50 µA to 500 mA,

I

See Note 1

V = 3.5 V,

f = 120 Hz,

I

Ripple rejection

59

dB

I

O

= 50 µA

Output noise-spectral density

V = 3.5 V,

f = 120 Hz

2

95

89

74

12

µV/√Hz

I

C

= 4.7 µF

= 10 µF

= 100 µF

O

V = 3.5 V,

I

Output noise voltage

µVrms

10 Hz ≤ f ≤ 100 kHz,

†

CSR = 1 Ω

§

mV

V

V = 3.5 V,

I

Measured at V

FB

PG hysteresis voltage

§

V = 2.13 V,

I

= 400 µA

0.1

PG output low voltage

PG

FB input current

nA

V = 3.5 V

I

V = 3.5 V

I

†

‡

§

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When V < 2.9 V and I > 150 mA simultaneously, pass element r

increases (see Figure 27) to a point such that the resulting

I

O

DS(on)

dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation:

V

DO

= I

r

O

DS(on)

r

is a function of both output current and input voltage. The parametric table lists r

for V = 2.4 V, 2.9 V, 3.9 V, and

I

DS(on)

5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other

programmed values, refer to Figure 26.

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, T = 25°C, SENSE shorted

O

J

to OUT (unless otherwise noted) (continued)

TPS7133Y

TYP

‡

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

Output voltage

Dropout voltage

V = 4.3 V,

I

O

I

O

I

O

I

O

= 10 mA

= 100 mA

= 500 mA

3.3

V

I

V = 3.23 V,

I

0.02

V = 3.23 V,

I

47

mV

V = 3.23 V,

I

235

(3.23 V – V )/I ,

V = 3.23 V,

I

O

Pass-element series resistance

Output regulation

0.47

Ω

I

O

= 500 mA

4.3 V ≤ V ≤ 10 V,

I

O

I

O

I

O

I

O

= 5 mA to 500 mA

= 50 µA to 500 mA

= 50 µA

21

30

mV

I

4.3 V ≤ V ≤ 10 V,

I

54

V = 4.3 V,

I

f = 120 Hz

Ripple rejection

dB

= 500 mA

49

Output noise-spectral density

V = 4.3 V,

I

f = 120 Hz

2

µV/√Hz

274

228

159

35

C

= 4.7 µF

= 10 µF

= 100 µF

O

V = 4.3 V,

I

10 Hz ≤ f ≤ 100 kHz,

Output noise voltage

µVrms

†

CSR = 1 Ω

mV

V

PG hysteresis voltage

PG output low voltage

V = 4.3 V

I

V = 2.8 V,

I

= 1 mA

0.22

PG

TPS7148Y

TYP

‡

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

Output voltage

V = 5.85 V,

I

O

I

O

I

O

I

O

= 10 mA

= 100 mA

= 500 mA

4.85

V

I

V = 4.75 V,

I

0.08

V = 4.75 V,

I

30

mV

Dropout voltage

V = 4.75 V,

I

150

(4.75 V – V )/I ,

V = 4.75 V,

I

O

Pass-element series resistance

Output regulation

0.32

Ω

I

O

= 500 mA

5.85 V ≤ V ≤ 10 V,

I

O

I

O

I

O

I

O

= 5 mA to 500 mA

= 50 µA to 500 mA

= 50 µA

12

42

mV

I

5.85 V ≤ V ≤ 10 V,

I

53

V = 5.85 V,

I

f = 120 Hz

Ripple rejection

dB

= 500 mA

50

Output noise-spectral density

V = 5.85 V,

I

f = 120 Hz

2

µV/√Hz

410

328

212

50

C

= 4.7 µF

= 10 µF

= 100 µF

O

V = 5.85 V,

I

10 Hz ≤ f ≤ 100 kHz,

Output noise voltage

µVrms

†

CSR = 1 Ω

mV

V

PG hysteresis voltage

PG output low voltage

V = 5.85 V

I

V = 4.12 V,

I

= 1.2 mA

0.2

0.4

PG

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

‡

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

†

electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR = 1 Ω, T = 25°C, SENSE shorted

O

J

to OUT (unless otherwise noted) (continued)

TPS7150Y

‡

PARAMETER

UNIT

TEST CONDITIONS

MIN

TYP

5

MAX

Output voltage

Dropout voltage

V = 6 V,

I

O

I

O

I

O

I

O

= 10 mA

V

I

V = 4.88 V,

I

= 10 mA

= 100 mA

= 500 µA

0.13

27

V = 4.88 V,

I

mV

V = 4.88 V,

I

146

(4.88 V – V )/I ,

V = 4.88 V,

I

O

Pass-element series resistance

Output regulation

0.29

Ω

I

O

= 500 mA

6 V ≤ V ≤ 10 V,

I

O

I

O

I

O

I

O

= 5 mA to 500 mA

= 50 µA to 500 mA

= 50 µA

30

45

mV

I

6 V ≤ V ≤ 10 V,

I

55

V = 6 V,

I

f = 120 Hz

Ripple rejection

dB

= 500 mA

52

Output noise-spectral density

V = 6 V,

I

f = 120 Hz

2

µV/√Hz

430

345

220

53

C

= 4.7 µF

= 10 µF

= 100 µF

O

V = 6 V,

I

10 Hz ≤ f ≤ 100 kHz,

Output noise voltage

µVrms

†

CSR = 1 Ω

mV

V

PG hysteresis voltage

PG output low voltage

V = 6 V

I

V = 4.25 V,

I

= 1.2 mA

0.2

PG

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance

to C

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must

be taken into account separately.

.

O

‡

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

5

vs Output current

I

Q

Quiescent current

vs Input voltage

6

vs Free-air temperature

vs Output current

7

V

DO

Dropout voltage

8

∆V

Change in dropout voltage

Change in output voltage

Output voltage

vs Free-air temperature

vs Input voltage

9

DO

O

∆V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

V

O

∆V

Change in output voltage

vs Input voltage

O

V

O

Output voltage

Ripple rejection

vs Output current

vs Frequency

Output spectral noise density

r

Pass-element resistance

vs Input voltage

DS(on)

R

Divider resistance

vs Free-air temperature

I

SENSE pin current

I(SENSE)

FB leakage current

Minimum input voltage for active-pass element

Minimum input voltage for valid PG

Input current (EN)

V

I

I(EN)

Output voltage response from Enable (EN)

Power-good (PG) voltage

V

PG

vs Output voltage

vs Output current

34

35

36

37

38

39

40

41

CSR

Compensation series resistance

vs Added ceramic capacitance

vs Output current

vs Added ceramic capacitance

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT

vs

QUIESCENT CURRENT

vs

OUTPUT CURRENT

INPUT VOLTAGE

355

345

335

400

350

300

250

200

150

100

T

R

= 25°C

= 10 Ω

A

L

T

= 25°C

A

TPS71xx, V = 10 V

I

TPS7133

TPS7148

325

315

305

295

TPS7150

TPS7101 With V

Programmed to 2.5 V

O

TPS7150, V = 6 V

I

285

275

265

TPS7148, V = 5.85 V

I

50

0

TPS7133, V = 4.3 V

I

0

50 100 150 200 250 300 350 400 450 500

0

1

2

3

4

5

6

7

8

9

10

I

O

– Output Current – mA

V – Input Voltage – V

I

Figure 5

Figure 6

TPS7148Q

QUIESCENT CURRENT

vs

FREE-AIR TEMPERATURE

DROPOUT VOLTAGE

vs

OUTPUT CURRENT

400

0.3

V = V

+ 1 V

I

O(nom)

= 10 mA

T

A

= 25°C

I

O

0.25

350

300

250

TPS7133

0.2

0.15

TPS7148

TPS7150

0.1

0.05

0

200

150

0

50 100 150 200 250 300 350 400 450 500

–50

–25

0

25

50

75

100

125

T

A

– Free-Air Temperature – °C

I

O

– Output Current – mA

Figure 8

Figure 7

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

CHANGE IN DROPOUT VOLTAGE

vs

CHANGE IN OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

10

8

20

15

10

5

I

O

= 100 mA

V = V

+ 1 V

I

O(nom)

I

O

= 10 mA

6

4

2

0

–2

–4

–5

–10

–15

–20

–6

–8

–10

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 9

Figure 10

OUTPUT VOLTAGE

vs

INPUT VOLTAGE

CHANGE IN OUTPUT VOLTAGE

vs

INPUT VOLTAGE

6

5

4

3

2

1

20

T

R

= 25°C

= 10 Ω

T

R

= 25°C

= 10 Ω

A

L

A

L

TPS7150

15

10

5

TPS7148

TPS7150

TPS7148

0

–5

TPS7133

TPS7101 With V

O

Programmed to 2.5 V

–10

–15

–20

0

1

2

3

4

5

6

7

8

9

10

4

5

6

7

8

9

10

V – Input Voltage – V

I

V – Input Voltage – V

I

Figure 11

Figure 12

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

TPS7101Q

OUTPUT VOLTAGE

vs

TPS7133Q

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

2.52

2.515

2.51

3.34

3.33

3.32

3.31

3.3

T

V

= 25°C

Programmed to 2.5 V

A

O

T

A

= 25°C

2.505

2.5

V = 10 V

I

V = 3.5 V

I

V = 4.3 V

I

2.495

2.49

3.29

3.28

V = 10 V

I

2.485

2.48

3.27

3.26

0

100

200

300

400

500

0

100

200

300

400

500

I

O

– Output Current – mA

I

O

– Output Current – mA

Figure 13

Figure 14

TPS7148Q

TPS7150Q

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

4.92

4.91

4.9

5.06

5.05

5.04

5.03

5.02

5.01

5

T

A

= 25°C

T

A

= 25°C

4.89

4.88

4.87

4.86

4.85

4.84

V = 6 V

I

V = 5.85 V

I

4.99

4.98

V = 10 V

I

V = 10 V

I

4.83

4.82

4.81

4.8

4.97

4.96

4.95

4.94

0

100

200

300

400

500

0

100

200

300

400

500

I

O

– Output Current – mA

I

O

– Output Current – mA

Figure 15

Figure 16

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

TPS7133Q

RIPPLE REJECTION

vs

TPS7101Q

RIPPLE REJECTION

vs

FREQUENCY

70

60

50

70

60

50

R

= 100 kΩ

L

R

= 100 kΩ

L

40

30

40

R

= 500 Ω

L

30

20

10

0

R

= 500 Ω

L

T

= 25°C

20

A

I

V = 3.5 V

R

L

= 10 Ω

C

= 4.7 µF (CSR = 1 Ω)

T

= 25°C

O

10

A

I

No Input Capacitance

Programmed to 2.5 V

V = 3.5 V

V

O

C

= 4.7 µF (CSR = 1 Ω)

O

0

No Input Capacitance

R

= 10 Ω

L

–10

10

100

1K

10K

100K

1M

10M

10

100

1 k

10 k

100 k

1 M

10 M

f – Frequency – Hz

Figure 17

Figure 18

TPS7148Q

RIPPLE REJECTION

vs

TPS7150Q

RIPPLE REJECTION

vs

FREQUENCY

70

60

50

70

60

50

40

30

20

10

0

R

= 100 kΩ

L

R

L

= 100 kΩ

L

40

30

R

= 10 Ω

L

R

= 10 Ω

L

R

= 500 Ω

20

R

= 500 Ω

L

10

T

= 25°C

V = 3.5 V

A

I

T

= 25°C

A

V = 3.5 V

I

0

C

= 4.7 µF (CSR = 1 Ω)

No Input Capacitance

O

C

= 4.7 µF (CSR = 1 Ω)

O

No Input Capacitance

–10

10

100 1 k

10 k

100 k

1 M

10 M

10

100 1 k

10 k

100 k

1 M

10 M

f – Frequency – Hz

Figure 19

Figure 20

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

TPS7101Q

TPS7133Q

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

T

= 25°C

T = 25°C

A

No Input Capacitance

V = 3.5 V

V

No Input Capacitance

V = 4.3 V

I

O

Programmed to 2.5 V

C

= 10 µF (CSR = 1 Ω)

C

= 4.7 µF (CSR = 1 Ω)

O

1

C

= 4.7 µF (CSR = 1 Ω)

O

C

= 10 µF (CSR = 1 Ω)

O

C

= 100 µF (CSR = 1 Ω)

O

0.1

0.01

0.1

C

= 100 µF (CSR = 1 Ω)

O

0.01

2

10

3

10

4

10

5

10

2

10

3

10

4

10

5

10

f – Frequency – Hz

Figure 21

Figure 22

TPS7148Q

TPS7150Q

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

T

= 25°C

A

C

= 10 µF (CSR = 1 Ω)

O

No Input Capacitance

V = 5.85 V

I

C

= 4.7 µF (CSR = 1 Ω)

O

C

= 10 µF (CSR = 1 Ω)

O

1

C

= 4.7 µF (CSR = 1 Ω)

O

T

A

= 25°C

No Input Capacitance

V = 6 V

I

0.1

0.01

0.1

C

= 100 µF (CSR = 1 Ω)

O

C

= 100 µF (CSR = 1 Ω)

O

0.01

10

100

1 k

10 k

100 k

10

100

1 k

10 k

100 k

f – Frequency – Hz

Figure 23

Figure 24

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

PASS-ELEMENT RESISTANCE

DIVIDER RESISTANCE

vs

FREE-AIR TEMPERATURE

vs

INPUT VOLTAGE

1.1

1

1.2

1.1

1

T

V

= 25°C

V = V

I

I(sense)

+ 1 V

A

O(nom)

= V

= 1.12 V

V

I(FB)

O(nom)

TPS7150

0.9

0.8

0.7

TPS7148

I

O

= 500 mA

0.9

0.6

0.5

0.4

0.8

0.7

I

O

= 100 mA

TPS7133

0.6

0.5

0.4

0.3

0.2

0.1

2

3

4

5

6

7

8

9

10

–50

–25

0

25

50

75

100

125

V – Input Voltage – V

I

T

A

– Free-Air Temperature – °C

Figure 25

Figure 26

FIXED-OUTPUT VERSIONS

SENSE PIN CURRENT

vs

ADJUSTABLE VERSION

FB LEAKAGE CURRENT

vs

FREE-AIR TEMPERATURE

6

5.8

5.6

5.4

0.6

V = V

+ 1 V

O(nom)

I

V

FB

= 2.5 V

V

= V

I(sense)

O(nom)

0.5

0.4

0.3

5.2

5

0.2

0.1

0

4.8

4.6

4.4

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 27

Figure 28

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

MINIMUM INPUT VOLTAGE FOR ACTIVE

MINIMUM INPUT VOLTAGE FOR VALID

POWER GOOD (PG)

vs

PASS ELEMENT

vs

FREE-AIR TEMPERATURE

1.1

2.1

2.09

2.08

2.07

R

= 500 Ω

L

1.09

1.08

1.07

2.06

2.05

2.04

2.03

2.02

1.06

1.05

2.01

2

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 29

Figure 30

EN INPUT CURRENT

vs

FREE-AIR TEMPERATURE

100

V = V

I

= 10 V

I(EN)

90

80

70

60

50

40

30

20

10

0

–40 –20

0

20 40 60

80 100 120 140

T

A

– Free-Air Temperature – °C

Figure 31

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE RESPONSE FROM

ENABLE (EN)

V

O(nom)

T

R

C

= 25°C

= 500 Ω

= 4.7 µF (ESR = 1Ω)

A

L

O

6

4

No Input Capacitance

2

0

–2

0

20 40 60 80 100 120 140

Time – µs

Figure 32

POWER-GOOD (PG) VOLTAGE

vs

OUTPUT VOLTAGE

6

5

4

3

2

1

T

= 25°C

A

PG Pulled Up to 5 V With 5 kΩ

0

93

94

95

96

97

98

) – %

V

O

– Output Voltage (V as a percent of V

O

O(nom)

Figure 33

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

vs

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

vs

OUTPUT CURRENT

100

V = V

+ 1 V

I

O(nom)

No Input Capacitance

= 4.7 µF

V = V

+ 1 V

I

O(nom)

No Input Capacitance

= 4.7 µF + 0.5 µF of

C

O

C

O

No Added Ceramic Capacitance

= 25°C

Ceramic Capacitance

= 25°C

T

A

T

A

Region of Instability

10

Region of Instability

1

Region of Instability

50 100 150 200 250 300 350 400 450 500

Region of Instability

0.1

0

50 100 150 200 250 300 350 400 450 500

I – Output Current – mA

O

I

O

– Output Current – mA

Figure 34

Figure 35

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

vs

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

vs

ADDED CERAMIC CAPACITANCE

100

V = V

+ 1 V

V = V

+ 1 V

I

O(nom)

No Input Capacitance

= 100 mA

I

O(nom)

No Input Capacitance

I = 500 mA

O

I

C

T

O

A

= 4.7 µF

= 25°C

C

= 4.7 µF

T = 25°C

A

O

10

Region of Instability

1

Region of Instability

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

Ceramic Capacitance – µF

Figure 36

Figure 37

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

†

TYPICAL REGIONS OF STABILITY

†

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

vs

OUTPUT CURRENT

100

V = V

+ 1 V

I

O(nom)

No Input Capacitance

= 10 µF

V = V

+ 1 V

Region of Instability

I

O(nom)

No Input Capacitance

C = 10 µF + 0.5 µF of

O

C

O

No Ceramic Capacitance

= 25°C

Added Ceramic Capacitance

T = 25°C

A

T

A

10

Region of Instability

1

0.2

0.1

0.2

0.1

0

50 100 150 200 250 300 350 400 450 500

0

50 100 150 200 250 300 350 400 450 500

I

O

– Output Current – mA

I

O

– Output Current – mA

Figure 38

Figure 39

†

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE

vs

COMPENSATION SERIES RESISTANCE

vs

ADDED CERAMIC CAPACITANCE

100

V = V

+ 1 V

V = V

+ 1 V

I

O(nom)

No Input Capacitance

= 10 µF

I

O(nom)

No Input Capacitance

C = 10 µF

O

C

O

I

T

= 100 mA

I

T

= 500 mA

= 25°C

O

= 25°C

A

10

Region of Instability

1

0.2

0.1

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

Ceramic Capacitance – µF

Figure 40

Figure 41

†CSR values below 0.1 Ω are not recommended.

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

TYPICAL CHARACTERISTICS

To Load

IN

V

I

OUT

+

SENSE

C

†

O

C

cer

R

EN

L

GND

CSR

†

Ceramic capacitor

Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 41)

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

APPLICATION INFORMATION

The TPS71xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of

earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good

indicator. The TPS71xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the

TPS7148(4.85V), andtheTPS7150(5V). Thefamilyalsooffersanadjustabledevice, theTPS7101(adjustable

from 1.2 V to 9.75 V).

device operation

The TPS71xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even

with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly

proportional to the load current through the regulator (I = I /β). Close examination of the data sheets reveals

B

C

that those devices are typically specified under near no-load conditions; actual operating currents are much

higher as evidenced by typical quiescent current versus load current curves. The TPS71xx uses a PMOS

transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low

and invariable over the full load range. The TPS71xx specifications reflect actual performance under load.

Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into

dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates

B

to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,

it means rapid battery discharge when the voltage decays below the minimum required for regulation. The

TPS71xx quiescent current remains low even when the regulator drops out, eliminating both problems.

Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular

systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems

specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack

before the device drops out, adding crucial talk minutes between charges.

The TPS71xx family also features a shutdown mode that places the output in the high-impedance state

(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the

shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated

output voltage is reestablished in typically 120 µs.

minimum load requirements

The TPS71xx family is stable even at zero load; no minimum load is required for operation.

SENSE-pin connection

The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the

regulator. Normally, this connection should be as short as possible; however, the connection can be made near

a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a

high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through

to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an

RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator

to oscillate.

external capacitor requirements

An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load

transient response and noise rejection if the TPS71xx is located more than a few inches from the power supply.

A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients

with fast rise times are anticipated.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

APPLICATION INFORMATION

external capacitor requirements (continued)

As with most LDO regulators, the TPS71xx family requires an output capacitor for stability. A 10-µF

solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the

full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass

capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum

capacitor is less than 1.2 Ω over temperature. Where component height and/or mounting area is a problem,

physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of

operation using different values of output capacitance with various values of ceramic load capacitance.

In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be

reduced to 4.7 µF, provided ESR is maintained between the values shown in figures 34 through 41. Because

minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series

with the capacitor and limit ESR to 1.5 Ω maximum.

†

TPS71xx

8

20

15

14

13

V

IN

PG

I

9

250 kΩ

IN SENSE

10

V

O

IN

OUT

C1

0.1 µF

50 V

6

EN

C

+

O

10 µF

GND

ESR

1

2

3

†

TPS7133, TPS7148, TPS7150 (fixed-voltage options)

Figure 43. Typical Application Circuit

programming the TPS7101 adjustable LDO regulator

Programming the adjustable regulators is accomplished using an external resistor divider as shown in

Figure 44. The equation governing the output voltage is:

R1

R2

V

1

O

ref

where

V

= reference voltage, 1.178 V typ

ref

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

APPLICATION INFORMATION

programming the TPS7101 adjustable LDO regulator (continued)

Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2

is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent

advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at

FB introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate

resistance:

V

O

R1

1

R2

V

ref

OUTPUT VOLTAGE

PROGRAMMING GUIDE

TPS7101

OUTPUT

VOLTAGE

R1

R2

UNIT

Power-Good

Indicator

250 kΩ

V

I

IN

PG

OUT

FB

0.1 µF

2.5 V

3.3 V

3.6 V

4 V

191

309

348

402

549

750

169

kΩ

>2.7 V

EN

V

O

<0.5V

+

R1

5 V

GND

6.4 V

R2

Figure 44. TPS7101 Adjustable LDO Regulator Programming

power-good indicator

The TPS71xx features a power-good (PG) output that can be used to monitor the status of the regulator. The

internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal

regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup

resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery

indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance,

but instead reports an output voltage low, relative to its nominal regulated value.

regulator protection

The TPS71xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the

input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output

to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be

appropriate.

The TPS71xx also features internal current limiting and thermal protection. During normal operation, the

TPS71xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales

back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device

failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of

the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator

operation resumes.

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

PINS **

0.050 (1,27)

8

14

16

DIM

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

M

A MAX

14

8

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

0.244 (6,20)

0.228 (5,80)

0.008 (0,20) NOM

0.157 (4,00)

0.150 (3,81)

Gage Plane

1

7

A

0.010 (0,25)

0°–8°

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.004 (0,10)

0.069 (1,75) MAX

4040047/B 03/95

NOTES: B. All linear dimensions are in inches (millimeters).

C. This drawing is subject to change without notice.

D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

E. Four center pins are connected to die mount pad.

F. Falls within JEDEC MS-012

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

MECHANICAL DATA

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.310 (7,87)

0.290 (7,37)

0.020 (0,51) MIN

0.200 (5,08) MAX

Seating Plane

0.125 (3,18) MIN

0.100 (2,54)

0°–15°

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

M

0.010 (0,25) NOM

4040082/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q

TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y

LOW-DROPOUT VOLTAGE REGULATORS

SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,32

0,17

0,65

M

0,13

14

8

0,15 NOM

4,50

4,30

6,70

6,10

Gage Plane

0,25

1

7

0°–8°

0,75

A

0,50

Seating Plane

0,10

1,20 MAX

0,10 MIN

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/D 10/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

19-Jun-2007

PACKAGING INFORMATION

Orderable Device

TPS7101QD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7101QDG4

TPS7101QDR

TPS7101QDRG4

TPS7101QP

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PDIP

P

8

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TPS7101QPE4

TPS7101QPW

TPS7101QPWG4

PDIP

P

8

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TSSOP

PW

20

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7101QPWLE

TPS7101QPWR

OBSOLETE TSSOP

PW

20

TBD

Call TI

ACTIVE

TSSOP

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7101QPWRG4

TPS7133QD

PW

D

20

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7133QDG4

TPS7133QDR

TPS7133QDRG4

TPS7133QP

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PDIP

P

8

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TPS7133QPE4

TPS7133QPW

TPS7133QPWG4

PDIP

P

8

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TSSOP

PW

20

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7133QPWLE

TPS7133QPWPLE

TPS7133QPWR

OBSOLETE TSSOP

PW

20

TBD

Call TI

ACTIVE

TSSOP

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7133QPWRG4

TPS7148QD

PW

D

20

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7148QDG4

TPS7148QDR

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Jun-2007

Orderable Device

TPS7148QDRG4

TPS7148QP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PDIP

P

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TPS7148QPE4

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TPS7148QPWLE

TPS7148QPWRG4

TPS7150QD

OBSOLETE TSSOP

PW

D

20

8

TBD

Call TI

ACTIVE

TSSOP

SOIC

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7150QDG4

TPS7150QDR

TPS7150QDRG4

TPS7150QP

ACTIVE

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PDIP

P

8

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TPS7150QPE4

TPS7150QPW

TPS7150QPWG4

PDIP

P

8

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TSSOP

PW

20

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7150QPWLE

TPS7150QPWR

OBSOLETE TSSOP

PW

20

TBD

Call TI

ACTIVE

TSSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7150QPWRG4

ACTIVE

TSSOP

PW

20

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

19-Jun-2007

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

12

TPS7101QDR

TPS7101QPWR

TPS7133QDR

TPS7133QPWR

TPS7148QDR

TPS7150QDR

TPS7150QPWR

D

PW

D

8

20

8

SITE 60

SITE 41

SITE 60

SITE 41

SITE 60

SITE 41

6.4

6.95

6.4

5.2

7.1

5.2

7.1

5.2

7.1

2.1

1.6

2.1

1.6

2.1

1.6

8

12

16

12

16

12

16

Q1

16

12

PW

D

20

8

16

6.95

6.4

12

D

8

12

6.4

PW

20

16

6.95

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TPS7101QDR

TPS7101QPWR

TPS7133QDR

TPS7133QPWR

TPS7148QDR

TPS7150QDR

TPS7150QPWR

D

PW

D

8

20

8

SITE 60

SITE 41

SITE 60

SITE 41

SITE 60

SITE 41

346.0

29.0

33.0

29.0

33.0

29.0

33.0

PW

D

20

8

D

8

PW

20

Pack Materials-Page 2

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this

warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily

performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should

provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask

work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services

are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such

products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under

the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an

unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties

may be subject to additional restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service

voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business

practice. TI is not responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would

reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement

specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications

of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related

requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any

applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its

representatives against any damages arising out of the use of TI products in such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is

solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in

connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products

are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any

non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS7148QDRG4
厂家：	TEXAS INSTRUMENTS
描述：	LOW-DROPOUT VOLTAGE REGULATORS 低压差稳压器线性稳压器IC 调节器电源电路光电二极管输出元件
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