TPS72750YFFT [TI]
250mA, Ultralow IQ, Fast Transient Response, RF LOW-DROPOUT LINEAR REGULATOR; 250毫安，超低IQ ，快速瞬态响应，射频低压差线性稳压器
| 型号： | TPS72750YFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 250mA, Ultralow IQ, Fast Transient Response, RF LOW-DROPOUT LINEAR REGULATOR |
| 文件： | 总21页 (文件大小：841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS727xx
www.ti.com
SBVS128C –JUNE 2009–REVISED JANUARY 2011
250mA, Ultralow IQ, Fast Transient Response,
RF LOW-DROPOUT LINEAR REGULATOR
1
FEATURES
DESCRIPTION
234
•
Very Low Dropout:
The TPS727xx family of low-dropout (LDO) linear
regulators are ultralow quiescent current LDOs with
excellent line and ultra-fast load transient
performance and are designed for power-sensitive
applications. The LDO output voltage level is preset
by the use of innovative factory EEPROM
–
–
–
65mV Typical at 100mA
130mV Typical at 200mA
163mV Typical at 250mA
•
2% Accuracy Over Load/Line/Temperature
programming.
amplifier provides overall 2% accuracy over load, line,
and temperature extremes. The TPS727xx family is
A
precision bandgap and error
•
•
Ultralow IQ: 7.9mA
Excellent Load Transient Performance:±50mV
for 200mA Loading/Unloading Transient
available in 1,5mm
x 1,5mm SON and wafer
chip-scale (WCSP) packages that make it ideal for
handheld applications. This family of devices is fully
specified over a temperature range of TJ = –40°C to
+125°C.
•
Available in Fixed-Output Voltages From 0.9V
to 5V Using Innovative Factory EEPROM
Programming
•
•
•
•
High PSRR: 70dB at 1kHz
YFF PACKAGE
WCSP-4
(Top View)
DSE PACKAGE
1,5mm ´ 1,5mm SON-6
(Top View)
Stable with a 1.0mF Ceramic Capacitor
Thermal Shutdown and Overcurrent Protection
OUT
B2
GND
B1
Available in 4-Ball, 0,4mm Pitch Wafer-Level
Chip Scale and 1,5mm x 1,5mm SON Packages
OUT
NC
1
2
3
6
5
4
IN
NC
EN
A2
IN
A1
GND
APPLICATIONS
EN
•
•
•
•
•
Wireless Handsets, Smart Phones, PDAs
MP3 Players and Other Handheld Products
Wireless LAN, Bluetooth®, Zigbee®
Remote Controls
Portable Consumer Products
space
TYPICAL APPLICATION CIRCUIT
VIN
VOUT
IN
OUT
1mF
Ceramic
CIN
COUT
TPS727xx
On
Off
EN
GND
PSRR vs FREQUENCY
GROUND PIN CURRENT vs TEMPERATURE
15
12
9
100
VIN = 2.1V
IOUT = 0mA
90
80
70
IOUT = 10mA
60
50
40
30
20
10
0
6
3
IOUT = 200mA
0
10
100
1k
10k
100k
1M
10M
-40 -25 -10
5
20 35 50 65 80 95 110 125
Frequency (Hz)
Temperature (°C)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
Bluetooth is a registered trademark of Bluetooth SIG.
Zigbee is a registered trademark of Zigbee Alliance.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
TPS727xx
SBVS128C –JUNE 2009–REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS727xxx yyy z
XXX is the nominal output voltage.
YYY is package designator.
Z is package tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Output voltages from 0.9V to 5.0V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS(1)
At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
TPS727xx
–0.3 to +6.0
–0.3 to +6.0(2)
–0.3 to +6.0
UNIT
Input voltage range, VIN
V
V
V
Enable voltage range, VEN
Output voltage range, VOUT
Maximum output current, IOUT
Output short-circuit duration
Total continuous power dissipation, PDISS
Internally limited
Indefinite
See Dissipation Ratings Table
Human body model (HBM)
Charged device model (CDM)
2
kV
V
ESD rating
500
Operating junction temperature range, TJ
Storage temperature range, TSTG
–55 to +150
–55 to +150
°C
°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) VEN absolute maximum rating is VIN or 6.0V, whichever is less.
DISSIPATION RATINGS
DERATING FACTOR
BOARD
High-K(1)
High-K(1)
PACKAGE
DSE
RqJC
—
RqJA
ABOVE TA = +25°C
TA < +25°C
485mW
TA = +70°C
269mW
TA = +85°C
194mW
206°C/W
268°C/W
4.85mW/°C
YFF
85°C/W
3.7mW/°C
370mW
205mW
150mW
(1) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2
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TPS727xx
www.ti.com
SBVS128C –JUNE 2009–REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater;
IOUT = 10mA, VEN = 0.9V, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C.
TPS727xx
PARAMETER
Input voltage range
Output voltage range
TEST CONDITIONS
MIN
2.0
TYP
MAX
5.5
UNIT
V
VIN
VO
0.9
5.0
V
TJ = +25°C
–2.5
+2.5
mV
VOUT + 0.3V ≤ VIN ≤ 5.5V,
0mA ≤ IOUT ≤ 200mA
–2.0
±1.0
±1.0
±50.0
±65
+2.0
%
%
(1)
VOUT
DC output accuracy
Load transient
VOUT + 0.3V ≤ VIN ≤ 5.5V,
0mA ≤ IOUT ≤ 250mA
1mA to 200mA or
200mA to 1mA in 1ms, COUT = 1mF
mV
mV
mV/V
ΔVOUT
1mA to 250mA or
250mA to 1mA in 1ms, COUT = 1mF
VOUT(NOM) + 0.3V ≤ VIN ≤ 5.5V,
IOUT = 10mA
ΔVO/ΔVIN Line regulation
ΔVO/ΔIOUT Load regulation
8
0mA ≤ IOUT ≤ 250mA
20
6.5
mV/mA
mV
mV
mV
mV
mV
mA
mA
VIN = 0.98 × VOUT(NOM), IOUT = 10mA
VIN = 0.98 × VOUT(NOM), IOUT = 50mA
VIN = 0.98 × VOUT(NOM), IOUT = 100mA
VIN = 0.98 × VOUT(NOM), IOUT = 200mA
VIN = 0.98 × VOUT(NOM), IOUT = 250mA
VOUT = 0.9 × VOUT(NOM)
32.5
65
VDO
Dropout voltage(2)
130
162.5
400
7.9
200
ICL
Output current limit
Ground pin current
300
550
12
IOUT = 0mA, TJ = –40°C to +125°C
IOUT = 200mA
IGND
110
130
0.12
mA
IOUT = 250mA
mA
V
EN ≤ 0.4V, VIN = 2V, TJ = +25°C
EN ≤ 0.4V, 2.0V < VIN ≤ 4.5V,
mA
ISHDN
Shutdown current (IGND)
V
0.55
2
mA
TJ = –40°C to +85°C
f = 10Hz
85
75
70
55
40
45
dB
dB
dB
dB
dB
dB
f = 100Hz
f = 1kHz
VIN = 2.3V,
PSRR
Power-supply rejection ratio
Output noise voltage
VOUT = 1.8V,
IOUT = 10mA
f = 10kHz
f = 100kHz
f = 1MHz
BW = 100Hz to 100kHz, VIN = 2.1V,
VOUT = 1.8V, IOUT = 10mA
VN
33.5
100
mVRMS
tSTR
VHI
Startup time(3)
COUT = 1.0mF, 0 ≤ IOUT ≤ 250mA
ms
V
Enable pin high (enabled)
Enable pin low (disabled)
Enable pin current
0.9
0
VIN
0.4
VLO
V
IEN
EN = 5.5V
40
1.90
500
1.95
nA
V
UVLO
Undervoltage lock-out
VIN rising
1.85
–40
Shutdown, temperature increasing
Reset, temperature decreasing
+160
+140
°C
°C
°C
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
+125
(1) The output voltage is programmed at the factory.
(2) VDO is measured for devices with VOUT(NOM) ≥ 2.35V so that VIN ≥ 2.3V.
(3) Startup time: Time from EN assertion to 0.98 × VOUT(NOM)
.
Copyright © 2009–2011, Texas Instruments Incorporated
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TPS727xx
SBVS128C –JUNE 2009–REVISED JANUARY 2011
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DEVICE INFORMATION
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EEPROM
Bandgap
EN
LOGIC
Figure 1. Functional Block Diagram
4
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TPS727xx
www.ti.com
SBVS128C –JUNE 2009–REVISED JANUARY 2011
PIN CONFIGURATIONS
space
TPS72715, TPS72718, TPS72728
ALL OTHER TPS727xx DEVICES
YFF PACKAGE
YFF PACKAGE
WCSP-4
(TOP VIEW)
WCSP-4
(TOP VIEW)
OUT
GND
OUT
GND
B2
B1
B2
B1
A2
IN
A1
A2
IN
A1
EN
EN
See note.
See note.
DSE PACKAGE
1,5mm × 1,5mm SON-6
(TOP VIEW)
OUT
NC
1
2
3
6
5
4
IN
NC
EN
GND
Tape and Reel
Sprocket Holes
Tape and Reel
Sprocket Holes
Tape and Reel
Sprocket Holes
Top Dot
Mark
Top Dot
Mark
Top Dot
Mark
TPS72715YFF
TPS72718YFF
TPS72728YFF
TPS727xxDSE
(All Voltage Versions)
TPS72711YFF
(Example)
See Note
See Note
See Note
NOTE
EN pin marked with dot for 1.5V, 1.8V, and 2.8V versions of YFF package. GND pin
marked with dot for all other voltage versions of YFF package.
PIN DESCRIPTIONS
TPS727xx
YFF
NAME
DSE
DESCRIPTION
Regulated output voltage pin. A small 1mF ceramic capacitor is needed from this pin to ground to assure stability. See Input
and Output Capacitor Requirements in the Application Information section for more details.
OUT
B2
1
NC
—
2
3
No connection. This pin can be tied to to ground to improve thermal dissipation.
Ground pin.
GND
B1
Enable pin. Driving EN over 0.9V turns on the regulator. Driving EN below 0.4V puts the regulator into shutdown mode, thus
reducing the operating current to 120nA, nominal.
EN
NC
IN
A1
—
4
5
6
No connection. This pin can be tied to to ground to improve thermal dissipation.
Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor
Requirements in the Application Information section for more details.
A2
Copyright © 2009–2011, Texas Instruments Incorporated
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TPS727xx
SBVS128C –JUNE 2009–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA,
VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C.
LINE REGULATION
(TPS72718)
LINE REGULATION
(TPS72718)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
IOUT = 10mA
IOUT = 200mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN (V)
VIN (V)
Figure 2.
Figure 3.
LOAD REGULATION UNDER LIGHT LOADS
(TPS72718)
LOAD REGULATION
(TPS72718)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
0mA £ IOUT £ 10mA
0mA £ IOUT £ 250mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
1
2
3
4
5
6
7
8
9
10
0
25
50
75 100 125 150 175 200 225 250
IOUT (mA)
IOUT (mA)
Figure 4.
Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT
(TPS72750)
DROPOUT VOLTAGE vs INPUT VOLTAGE
160
140
120
100
80
160
140
120
100
80
IOUT = 200mA
60
60
40
+125°C
+85°C
+25°C
-40°C
40
+125°C
+85°C
+25°C
-40°C
20
20
0
0
0
50
100
150
200
250
2.25
2.75
3.25
3.75
4.25
4.75
IOUT (mA)
VIN (V)
Figure 6.
Figure 7.
6
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TPS727xx
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SBVS128C –JUNE 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA,
VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C.
OUTPUT VOLTAGE vs TEMPERATURE
(TPS72718)
GROUND PIN CURRENT vs INPUT VOLTAGE
(TPS72718)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
12.0
11.5
11.0
10.5
10.0
9.5
IOUT = 0mA
+125°C
+85°C
+25°C
-40°C
IOUT = 10mA
9.0
IOUT = 200mA
8.5
8.0
7.5
7.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
Temperature (°C)
VIN (V)
Figure 8.
Figure 9.
GROUND PIN CURRENT vs LOAD
(TPS72718)
GROUND PIN CURRENT vs TEMPERATURE
(TPS72718)
140
120
100
80
15
12
9
VIN = 2.1V
IOUT = 0mA
0mA £ IOUT £ 250mA
60
6
+125°C
40
+85°C
+25°C
-40°C
3
20
0
0
0
25
50
75 100 125 150 175 200 225 250
IOUT (mA)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 10.
Figure 11.
SHUTDOWN CURRENT vs INPUT VOLTAGE
(TPS72718)
CURRENT LIMIT vs INPUT VOLTAGE
(TPS72718)
550
500
450
400
350
2.0
1.6
1.2
0.8
0.4
0
+125°C
+85°C
+25°C
-40°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
VIN (V)
Figure 12.
Figure 13.
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SBVS128C –JUNE 2009–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA,
VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C.
PSRR vs FREQUENCY
PSRR vs FREQUENCY
(VIN – VOUT = 0.5V, TPS72718)
(VIN – VOUT = 0.3V, TPS72718)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
IOUT = 10mA
IOUT = 10mA
IOUT = 200mA
IOUT = 200mA
1M 10M
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 14.
Figure 15.
OUTPUT SPECTRAL NOISE DENSITY
vs OUTPUT VOLTAGE
(TPS72718)
PSRR vs INPUT VOLTAGE
(TPS72718)
80
70
60
50
40
30
20
10
0
10.00
1.00
0.10
0.01
0
1kHz
10kHz
100kHz
IOUT = 10mA
CIN = COUT = 1mF
10
100
1k
10k
100k
1M
10M
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
VIN (V)
Frequency (Hz)
Figure 16.
Figure 17.
LOAD TRANSIENT RESPONSE: 0.1mA TO 200mA
(TPS72718)
LOAD TRANSIENT RESPONSE: 1mA TO 200mA
(TPS72718)
VIN = 2.3V
VIN = 2.3V
tR = tF = 1ms
tR = tF = 1ms
200mA
200mA
IOUT
IOUT
1mA
0.1mA
VOUT
VOUT
100ms/div
50ms/div
Figure 18.
Figure 19.
8
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SBVS128C –JUNE 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.0V, whichever is greater; IOUT = 10mA,
VEN = VIN, and COUT = 1.0mF, unless otherwise noted. Typical values are at TJ = +25°C.
LOAD TRANSIENT RESPONSE: 10mA TO 200mA
(TPS72718)
LINE TRANSIENT RESPONSE
(TPS72718)
VIN = 2.3V
tR = tF = 1ms
200mA
VOUT
IOUT
10mA
2.7V
VOUT
VIN
Slew Rate = 1V/ms
IOUT =100mA
2.1V
1ms/div
50ms/div
Figure 20.
Figure 21.
LINE TRANSIENT RESPONSE
(TPS72718)
VIN INRUSH CURRENT
(TPS72718)
EN
VOUT
VOUT
VIN = 2.1V
2.7V
VIN
VOUT = 1.8V
IOUT = 100mA
IIN
Slew Rate = 1V/ms
2.1V
IOUT = 200mA
100ms/div
20ms/div
Figure 22.
Figure 23.
VIN INRUSH CURRENT
(TPS72718)
VIN RAMP UP,
RAMP DOWN RESPONSE (TPS72718)
IOUT = 200mA
EN
VIN
VOUT
VOUT
VIN = 2.1V
IIN
VOUT = 1.8V
IOUT = 200mA
200ms/div
20ms/div
Figure 24.
Figure 25.
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APPLICATION INFORMATION
ILIMIT × RLOAD. The PMOS pass transistor dissipates
(VIN – VOUT) × ILIMIT until thermal shutdown is
triggered and the device is turned off. As the device
cools down, it is turned on by the internal thermal
shutdown circuit. If the fault condition continues, the
device cycles between current limit and thermal
shutdown. See the Thermal Information section for
more details.
The TPS727xx family belongs to a family of new
generation LDO regulators that consume extremely
low quiescent current while simulatenously delivering
excellent PSRR with very little headroom (VIN – VOUT
differential voltage), and very good transient
response. These features, combined with low noise
without
a noise reduction pin in an ultrasmall
package, make this device ideal for portable
applications. This family of regulators offers
sub-bandgap output voltages, current limit and
thermal protection, and is fully specified from –40°C
to +125°C.
The PMOS pass element in the TPS727xx has a
built-in body diode that conducts current when the
voltage at the OUT pin exceeds the voltage at the IN
pin. This current is not limited, so if extended reverse
voltage operation is anticipated, external limiting to
5% of rated output current is recommended.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
SOFT START
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1mF to 1.0mF low equivalent series resistance
(ESR) capacitor across the IN pin and GND input of
the regulator. This capacitor counteracts reactive
input sources and improves transient response, noise
The startup current is given by Equation 1:
ISOFT START (mA) = COUT(mF) ´ 0.07(V/ms) + ILOAD(mA)
(1)
This equation shows that soft-start current is directly
proportional to COUT
.
rejection, and ripple rejection.
A
higher-value
The output voltage ramp rate is independent of COUT
and load current, and has a typical value of 0.07V/ms.
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not
located close to the power source. If source
impedance is not sufficiently low, a 0.1mF input
capacitor may be necessary to ensure stability.
The TPS727xx automatically adjusts the soft-start
current to supply both the load current and the COUT
charge current. For example, if ILOAD = 0mA upon
enabling the LDO, ISOFT
0mA = 70mA, the current that charges the output
capacitor.
= 1mF × 0.07 V/ms +
START
The TPS727xx is designed to be stable with standard
ceramic capacitors with values of 1.0mF or larger at
the output. X5R- and X7R-type capacitors are best
because they have minimal variation in value and
ESR over temperature. Maximum ESR should be less
than 200mΩ.
If ILOAD = 200mA, ISOFT
200mA = 270mA, the current required for charging
output capacitor and supplying the load current.
= 1mF × 0.07V/ms +
START
If the output capacitor and load are increased such
that the soft-start current exceeds the output current
limit, it is clamped at the typical current limit of
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with the ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should
connect directly to the GND pin of the device. High
ESR capacitors may degrade PSRR.
400mA. For example, if COUT = 10mF and IOUT
=
200mA, 10mF × 0.07V/ms + 200mA = 900mA is not
supplied. Instead, it is clamped at 400mA.
SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to the IN pin.
INTERNAL CURRENT LIMIT
The TPS727xx internal current limit helps protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. In such a case,
the output voltage is not regulated, and is VOUT
=
10
Submit Documentation Feedback
Copyright © 2009–2011, Texas Instruments Incorporated
TPS727xx
www.ti.com
SBVS128C –JUNE 2009–REVISED JANUARY 2011
DROPOUT VOLTAGE
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The TPS727xx uses a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
in the linear region of operation and the
input-to-output resistance is the RDS(ON) of the PMOS
pass element. VDO approximately scales with output
current because the PMOS device behaves like a
resistor in dropout.
a
worst-case junction
The internal protection circuitry of the TPS727xx has
been designed to protect against overload conditions.
It is not intended to replace proper heatsinking.
Continuously running the TPS727xx into thermal
shutdown degrades device reliability.
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 16 in the
Typical Characteristics section.
TRANSIENT RESPONSE
Power Dissipation
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air. Performance data for JEDEC low-
and high-K boards are given in the Dissipation
Ratings table. Using heavier copper increases the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heatsink effectiveness.
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS727xx uses an undervoltage lock-out circuit
that keeps the output shut off until the input voltage
reaches the UVLO threshold voltage.
THERMAL INFORMATION
Thermal Protection
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 2:
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
PD = (VIN - VOUT) ´ IOUT
(2)
Package Mounting
Solder pad footprint recommendations for the
TPS727xx are available from the Texas Instruments
web site at www.ti.com.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
The recommended land pattern for the DSE package
is shown in Figure 26. Figure 27 shows the
dimensions of the YFF package.
Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
11
TPS727xx
SBVS128C –JUNE 2009–REVISED JANUARY 2011
www.ti.com
(1) Publication IPC-7351 is recommended for alternate designs.
(2) For more information, refer to TI application notes SCBA017 and SLUA271 (Quad Flatpack No-Lead Logic Packages
and QFN/SON PCB Attachment, respectively) for specific thermal information, via requirements, and additional
recommendations for board layout. These documents are available at the Texas Instruments web site
(http://www.ti.com) by searching for the literature number.
(3) Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers
should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for stencil design
considerations.
(4) Customers should contact their board fabrication site for minimum solder mask tolerances between signal pads.
Figure 26. Recommended Land Pattern for DSE Package
12
Submit Documentation Feedback
Copyright © 2009–2011, Texas Instruments Incorporated
TPS727xx
www.ti.com
SBVS128C –JUNE 2009–REVISED JANUARY 2011
(1) Devices in a YFF package can have a dimension that ranges within a specified tolerance. To determine the exact
measurements, contact a local Texas Instruments representative.
Figure 27. YFF Package Dimensions
Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
13
TPS727xx
SBVS128C –JUNE 2009–REVISED JANUARY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April, 2010) to Revision C
Page
•
•
•
Updated YFF front page pin drawing to show pin locations ................................................................................................. 1
Revised Pin Configurations section ...................................................................................................................................... 5
Changed graph title for Figure 7 ........................................................................................................................................... 6
Changes from Revision A (September, 2009) to Revision B
Page
•
•
•
•
•
•
•
•
Changed title of data sheet ................................................................................................................................................... 1
Updated Features list ............................................................................................................................................................ 1
Changed footnote 2 to Absolute Maximum Ratings table .................................................................................................... 2
Revised numerous specifications and parameters in Electrical Characteristics table .......................................................... 3
Revised operating parameters for Figure 5 .......................................................................................................................... 6
Added operating parameters to Figure 7 .............................................................................................................................. 6
Replaced Figure 6 ................................................................................................................................................................ 6
Updated Figure 10 ................................................................................................................................................................ 7
14
Submit Documentation Feedback
Copyright © 2009–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS72710DSER
TPS72710DSET
TPS72711YFFR
TPS72711YFFT
TPS72715DSER
TPS72715DSET
TPS72715YFFR
TPS72715YFFT
TPS727185YFFR
TPS727185YFFT
TPS72718DSER
TPS72718DSET
TPS72718YFFR
TPS72718YFFT
TPS72719DSER
TPS72719DSET
TPS72719YFFR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSE
6
6
4
4
6
6
4
4
4
4
6
6
4
4
6
6
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
UR
UR
QL
QL
GS
GS
GS
GS
RW
RW
GT
GT
GT
GT
CB
CB
AA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
250
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Call TI
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Call TI
3000
250
Green (RoHS
& no Sb/Br)
Call TI
Green (RoHS
& no Sb/Br)
Call TI
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Call TI
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Green (RoHS
& no Sb/Br)
3000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS72719YFFT
TPS72725DSER
TPS72725DSET
TPS72727DSER
TPS72727DSET
TPS727285DSER
TPS727285DSET
TPS72728DSER
TPS72728DSET
TPS72728YFFR
TPS72728YFFT
TPS72730DSER
TPS72730DSET
TPS72730YFFR
TPS72730YFFT
TPS72733DSER
TPS72733DSET
TPS72733YFFR
ACTIVE
DSBGA
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
YFF
4
6
6
6
6
6
6
6
6
4
4
6
6
4
4
6
6
4
250
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
AA
QA
QA
TS
TS
QK
QK
GU
GU
GU
GU
QB
QB
ZZ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Call TI
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Call TI
ZZ
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
QC
QC
ZY
Green (RoHS
& no Sb/Br)
3000
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS72733YFFT
TPS72750YFFR
TPS72750YFFT
ACTIVE
DSBGA
DSBGA
DSBGA
YFF
4
4
4
250
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ZY
CA
CA
ACTIVE
ACTIVE
YFF
YFF
3000
250
Green (RoHS
& no Sb/Br)
-40 to 125
Green (RoHS
& no Sb/Br)
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS72710DSER
TPS72710DSET
TPS72711YFFR
TPS72711YFFT
TPS72715DSER
TPS72715DSET
TPS727185YFFR
TPS727185YFFT
TPS72718DSER
TPS72718DSET
TPS72718YFFR
TPS72718YFFT
TPS72719DSER
TPS72719DSET
TPS72719YFFR
TPS72719YFFT
TPS72725DSER
TPS72725DSET
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
6
6
4
4
6
6
4
4
6
6
4
4
6
6
4
4
6
6
3000
250
179.0
179.0
180.0
180.0
179.0
179.0
180.0
180.0
179.0
179.0
180.0
180.0
179.0
179.0
180.0
180.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.8
1.8
1.8
1.8
1.0
1.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q2
Q2
Q2
Q2
Q1
Q1
Q2
Q2
3000
250
0.89
0.89
1.8
1.26
1.26
1.8
0.69
0.69
1.0
3000
250
1.8
1.8
1.0
3000
250
0.89
0.89
1.8
1.26
1.26
1.8
0.69
0.69
1.0
3000
250
1.8
1.8
1.0
3000
250
0.89
0.89
1.8
1.26
1.26
1.8
0.69
0.69
1.0
3000
250
1.8
1.8
1.0
3000
250
0.89
0.89
1.8
1.26
1.26
1.8
0.69
0.69
1.0
3000
250
1.8
1.8
1.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS72727DSER
TPS72727DSET
TPS727285DSER
TPS727285DSET
TPS72728DSER
TPS72728DSET
TPS72728YFFR
TPS72728YFFT
TPS72730DSER
TPS72730DSET
TPS72730YFFR
TPS72730YFFT
TPS72733DSER
TPS72733DSET
TPS72733YFFR
TPS72733YFFT
TPS72750YFFR
TPS72750YFFT
WSON
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSE
DSE
DSE
DSE
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
YFF
YFF
6
6
6
6
6
6
4
4
6
6
4
4
6
6
4
4
4
4
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
180.0
180.0
179.0
179.0
180.0
180.0
179.0
179.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.8
1.8
1.8
1.8
1.0
1.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q1
Q1
3000
250
1.8
1.8
1.0
1.8
1.8
1.0
3000
250
1.8
1.8
1.0
1.8
1.8
1.0
3000
250
0.89
0.89
1.8
1.26
1.26
1.8
0.69
0.69
1.0
3000
250
1.8
1.8
1.0
3000
250
0.89
0.89
1.8
1.26
1.26
1.8
0.69
0.69
1.0
3000
250
1.8
1.8
1.0
3000
250
0.89
0.89
0.89
0.89
1.26
1.26
1.26
1.26
0.69
0.69
0.69
0.69
3000
250
*All dimensions are nominal
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS72710DSER
TPS72710DSET
TPS72711YFFR
TPS72711YFFT
TPS72715DSER
TPS72715DSET
TPS727185YFFR
TPS727185YFFT
TPS72718DSER
TPS72718DSET
TPS72718YFFR
TPS72718YFFT
TPS72719DSER
TPS72719DSET
TPS72719YFFR
TPS72719YFFT
TPS72725DSER
TPS72725DSET
TPS72727DSER
TPS72727DSET
TPS727285DSER
TPS727285DSET
TPS72728DSER
TPS72728DSET
TPS72728YFFR
TPS72728YFFT
TPS72730DSER
TPS72730DSET
TPS72730YFFR
TPS72730YFFT
TPS72733DSER
TPS72733DSET
TPS72733YFFR
TPS72733YFFT
TPS72750YFFR
TPS72750YFFT
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
DSE
DSE
DSE
DSE
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
DSE
DSE
YFF
YFF
YFF
YFF
6
6
4
4
6
6
4
4
6
6
4
4
6
6
4
4
6
6
6
6
6
6
6
6
4
4
6
6
4
4
6
6
4
4
4
4
3000
250
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
203.0
203.0
182.0
182.0
182.0
182.0
35.0
35.0
17.0
17.0
35.0
35.0
17.0
17.0
35.0
35.0
17.0
17.0
35.0
35.0
17.0
17.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
17.0
17.0
35.0
35.0
17.0
17.0
35.0
35.0
17.0
17.0
17.0
17.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 3
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