TPS73219 [TI]
250mA Low-Dropout Regulator for C2000â¢; 250毫安低压差稳压C2000â ?? ¢
| 型号： | TPS73219 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 250mA Low-Dropout Regulator for C2000⢠|
| 文件： | 总20页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS73219
www.ti.com
SBVS166 –JUNE 2011
250mA Low-Dropout Regulator for C2000™
Check for Samples: TPS73219
1
FEATURES
DESCRIPTION
The TPS73219 family is a low-dropout (LDO) voltage
regulator that offers very good line and load transient
response even without the use of an output capacitor.
The TPS73219 is ideal for driving the C2000 MCUs
fron Texas Instruments. The device offers very low
dropout voltage, thereby reducing power loss.
23
•
Optimal Output Voltage for Core Rail of C2000
Good Line/Load Transient Response for MCUs
250mA LDO Voltage Regulator with Enable
Very Low Dropout Voltage: 40mV (typ) at
250mA
•
•
•
•
•
•
Reverse Current Protection
Stable with or without Output Capacitor
1% Overall Accuracy (Line, Load, and
Temperature)
Available in a 5-Pin SOT23 Package
In combination with a voltage supervisor such as the
TPS3808G19 or TPS3808G01, the TPS73219 can
deliver tight VCORE voltages and generate accurate
power-good signals that meet or exceed power
requirements for the C2000.
•
The TPS73219 is available in a 5-pin SOT23
package.
APPLICATIONS
•
C2000 Core Power Rail Supply
DBV PACKAGE
SOT23
(TOP VIEW)
1
2
3
IN
GND
EN
5
4
OUT
NR/FB
1.8 V
3.3 V
10 kW
TPS3808G01 or
TPS3808G19
10 kW
C2000
TPS73219 or
TPS73534 or
TPS73734
TPS73619
TPS3808G01
EN
OUT
SENSE
SVS
1.8 V
RESET
EN
OUT
SENSE
SVS
3.3 V
RESET
XRS
LDO
1.8 V
LDO
3.3 V
51 kW
15 kW
91 kW
13 kW
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
C2000 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS73219
SBVS166 –JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS732xx yy yz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming; minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
Over operating junction temperature range unless otherwise noted.(1)
PARAMETER
TPS73219
–0.3 to 6.0
UNIT
VIN range
V
V
V
V
VEN range
–0.3 to 6.0
VOUT range
–0.3 to 5.5
VNR, VFB range
–0.3 to 6.0
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
Internally limited
Indefinite
See Thermal Information Table
–55 to +150
–65 to +150
2
°C
°C
kV
V
ESD rating, CDM
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2
Copyright © 2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
THERMAL INFORMATION
TPS73219(3)
DBV
5 PINS
180
THERMAL METRIC(1)(2)
UNITS
θJA
Junction-to-ambient thermal resistance(4)
Junction-to-case (top) thermal resistance(5)
Junction-to-board thermal resistance(6)
θJCtop
θJB
64
35
°C/W
ψJT
Junction-to-top characterization parameter(7)
Junction-to-board characterization parameter(8)
Junction-to-case (bottom) thermal resistance(9)
N/A
ψJB
N/A
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) There is no exposed pad with the DBV package.
(b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2011, Texas Instruments Incorporated
3
TPS73219
SBVS166 –JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.05
–0.5
TYP
MAX UNIT
VIN
Input voltage range
5.5
V
Nominal
TJ = +25°C
+0.5
VOUT
Accuracy
%
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10 mA ≤ IOUT ≤ 250mA
VIN, IOUT, and T
–1.0
±0.5
+1.0
ΔVOUT%/ΔVIN
Line regulation
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 250mA
0.01
0.002
%/V
ΔVOUT%/ΔIOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 250mA
0.0005
Dropout voltage
VDO
IOUT = 250mA
40
150
600
mV
(VIN = VOUT (nom) – 0.1V)
ZO(DO)
ICL
Output impedance in dropout
1.7 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
425
300
0.1
Ω
Output current limit
250
mA
mA
μA
ISC
Short-circuit current
IREV
Reverse leakage current(1) (–IIN
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
10
550
950
IOUT = 10mA (IQ)
IOUT = 250mA
400
650
IGND
GND pin current
μA
µA
dB
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5,
ISHDN
PSRR
Shutdown current (IGND
)
0.02
1
–40°C ≤ TJ ≤ +100°C
f = 100Hz, IOUT = 250 mA
f = 10kHz, IOUT = 250 mA
COUT = 10μF, No CNR
58
37
Power-supply rejection ratio
(ripple rejection)
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10Hz – 100kHz
VN
μVRMS
μs
COUT = 10μF, CNR = 0.01μF
VOUT = 3V, RL = 30Ω
COUT = 1 μF, CNR = 0.01 μF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
EN pin high (enabled)
EN pin low (shutdown)
EN pin current (enabled)
1.7
0
VIN
0.5
0.1
V
V
VEN = 5.5V
0.02
+160
+140
μA
Shutdown
Reset
Temp increasing
Temp decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
+125
(1) Fixed-voltage versions only; refer to Applications section for more information.
4
Copyright © 2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
FUNCTIONAL BLOCK DIAGRAM
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 2. Fixed Voltage Version
Copyright © 2011, Texas Instruments Incorporated
5
TPS73219
SBVS166 –JUNE 2011
www.ti.com
PIN CONFIGURATION
DBV PACKAGE
SOT23
(TOP VIEW)
1
2
3
IN
GND
EN
5
4
OUT
NR/FB
PIN DESCRIPTIONS
SOT23
(DBV)
NAME
IN
PIN NO.
DESCRIPTION
1
2
Input supply
Ground
GND
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN
can be connected to IN if not used.
EN
NR
3
4
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by
the internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set
the output voltage of the device.
FB
4
5
OUT
Output of the Regulator. There are no output capacitor requirements for stability.
6
Copyright © 2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
−
_
40
C
_
+25 C
_
+25
C
_
_
+125
C
+125 C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
0.05
0.10
0.15
0.20
−
_
40
C
−
−
−
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
150
200
250
−
IOUT (mA)
VIN VOUT (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
100
80
60
40
20
0
TPS73225DBV
IOUT = 250mA
TPS73225DBV
_
+125
C
_
+25
C
−
_
40 C
−
−
25
50
0
25
50
75
100
125
0
50
100
150
200
250
_
Temperature ( C)
IOUT (mA)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
_
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ C)
Figure 7.
Figure 8.
Copyright © 2011, Texas Instruments Incorporated
7
TPS73219
SBVS166 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 4V
VIN = 2V
−
−
25
0
50
100
150
200
250
50
0
25
50
75
100
125
_
IOUT (mA)
Temperature ( C)
Figure 9.
Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT (FOLDBACK)
1
500
450
400
350
300
250
200
150
100
50
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
ISC
0.1
TPS73233
0.01
0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−
−
25
50
0
25
50
75
100
125
Output Voltage (V)
_
Temperature ( C)
Figure 11.
Figure 12.
CURRENT LIMIT vs VIN
CURRENT LIMIT vs TEMPERATURE
600
550
500
450
400
350
300
250
600
550
500
450
400
350
300
250
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
_
VIN (V)
Temperature ( C)
Figure 13.
Figure 14.
8
Copyright © 2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN - VOUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
IOUT = 100mA
COUT = Any
IOUT = 1mA
µ
COUT = 1
F
IOUT = 1mA
COUT = 10 F
µ
IO = 100mA
µ
CO = 1 F
IOUT = 1mA
COUT = Any
Frequency = 10kHz
COUT = 10mF
IOUT = 100mA
COUT = 10
µ
F
VOUT = 2.5V
IOUT = Any
VIN = VOUT + 1V
µ
COUT = 0
F
IOUT = 100mA
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
VIN - VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0µF
CNR = 0.01µF
1
1
µ
COUT = 1
F
µ
COUT = 1
F
µ
COUT = 0
F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0
F
µ
COUT = 10
F
IOUT = 150mA
IOUT = 150mA
10 100
0.01
0.01
10
100
1k
10k
100k
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01
F
µ
COUT = 0
F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p 10p 100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 19.
Figure 20.
Copyright © 2011, Texas Instruments Incorporated
9
TPS73219
SBVS166 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
TPS73233
TPS73233
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
µ
µ
µ
VIN = 3.8V
COUT = 0
F
F
F
IOUT = 250mA
50mV/tick
50mV/tick
VOUT
VOUT
VOUT
µ
COUT = 0
F
50mV/div
VOUT
COUT = 1
µ
COUT = 100
F
COUT = 10
50mV/div
1V/div
VOUT
50mV/tick
50mA/tick
dVIN
dt
5.5V
µ
= 0.5V/
s
250mA
4.5V
VIN
10mA
IOUT
µ
µ
10 s/div
10 s/div
Figure 21.
Figure 22.
TPS73233
TPS73233
TURN-ON RESPONSE
TURN-OFF RESPONSE
Ω
RL = 1k
Ω
RL = 20
VOUT
µ
COUT = 0
F
COUT = 10µF
RL = 20Ω
COUT = 1µF
RL = 20Ω
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
Ω
RL = 1k
RL = 20Ω
COUT = 10
µ
COUT = 0
F
µ
F
VOUT
2V
2V
VEN
0V
0V
VEN
µ
100 s/div
µ
100 s/div
Figure 23.
Figure 24.
TPS73233
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
−
−
1
2
0.01
50ms/div
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
Figure 25.
Figure 26.
10
Copyright © 2011, Texas Instruments Incorporated
TPS73219
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SBVS166 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
TPS73201
TPS73201
RMS NOISE VOLTAGE vs CFB
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0
F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 27.
Figure 28.
TPS73201
TPS73201
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
CFB = 10nF
Ω
R1 = 39.2k
µ
COUT = 0
F
µ
COUT = 0
F
VOUT
VOUT
100mV/div
100mV/div
100mV/div
100mV/div
µ
COUT = 10 F
µ
COUT = 10
F
VOUT
VOUT
4.5V
250mA
3.5V
VIN
10mA
IOUT
µ
5
s/div
µ
10 s/div
Figure 29.
Figure 30.
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TPS73219
SBVS166 –JUNE 2011
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APPLICATION INFORMATION
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nΩF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
applications, the sum of capacitor ESR and trace
resistance will meet this requirement.
The TPS73219 belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS73219 ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback
current limit.
OUTPUT NOISE
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS73219 and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Figure 31 shows the basic circuit connections for the
fixed voltage models.
Optional input capacitor.
May improve source
Optional output capacitor.
May improve load transient,
noise, or PSRR.
impedance, noise, or PSRR.
VIN
VOUT
IN
OUT
TPS732xx
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
R2
(1)
EN
GND
NR
Since the value of VREF is 1.2V, this relationship
reduces to:
ON
OFF
Optional bypass
mVRMS
V
capacitor to reduce
output noise.
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
(2)
for the case of no CNR
.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
For best accuracy, make the parallel combination of
R1 and R2 approximately equal to 19kΩ. This 19kΩ,
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR (Figure 20) in the Typical
Characteristics section.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1μF to 1μF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
The TPS73219 uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250μV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
rejection, and ripple rejection.
A
higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
values of IOUT and COUT
.
The TPS73219 does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
12
Copyright © 2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
time after VIN has been removed. This scenario can
result in reverse current flow (if the IN pin is low
impedance) and faster ramp times upon power-up. In
addition, for VIN ramp times slower than a few
milliseconds, the output may overshoot upon
power-up.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the PCB be designed with separate ground planes for
VIN and VOUT, with each ground plane connected only
at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect
directly to the GND pin of the device.
Note that current limit foldback can prevent device
start-up under some conditions. See the Internal
Current Limit section.
INTERNAL CURRENT LIMIT
DROPOUT VOLTAGE
The TPS73219 internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when VOUT drops below 0.5V. See
Figure 12 in the Typical Characteristics section for a
The TPS73219 uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
graph of IOUT vs VOUT
.
For large step changes in load current, the TPS73219
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
insure normal transient response.
Note from Figure 12 that approximately –0.2V of VOUT
results in a current limit of 0mA. Therefore, if OUT is
forced below –0.2V before EN goes high, the device
may not start up. In applications that work with both a
positive and negative voltage supply, the TPS73219
should be enabled first.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
ENABLE PIN AND SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard TTL-CMOS levels. A VEN below 0.5V
(max) turns the regulator off and drops the GND pin
current to approximately 10nA. When EN is used to
shutdown the regulator, all charge is removed from
the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
the TPS73219 can take
a couple of hundred
microseconds to return to the specified regulation
accuracy.
When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
Copyright © 2011, Texas Instruments Incorporated
13
TPS73219
SBVS166 –JUNE 2011
www.ti.com
TRANSIENT RESPONSE
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1μF) from the OUT pin to ground will reduce
undershoot magnitude but increase its duration. In
the adjustable version, the addition of a capacitor,
CFB, from the OUT pin to the FB pin will also improve
the transient response.
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your application. This produces
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
a
The TPS73219 does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if the
load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
The internal protection circuitry of the TPS73219 has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS73219 into thermal
shutdown will degrade device reliability.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
(Fixed voltage version)
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Thermal Information table. Using
heavier copper will increase the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers will also
improve the heat-sink effectiveness.
VOUT
dVńdt +
COUT 80kW ø RLOAD
(4)
REVERSE CURRENT
The NMOS pass element of the TPS73219 provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the EN pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
PD + (VIN * VOUT) IOUT
(5)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80kΩ internal resistor divider to
ground (see Figure 2).
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS73219 are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
14
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS73219DBVR
TPS73219DBVRG4
TPS73219DBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
3000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
TPS73219DBVTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73219DBVR
TPS73219DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
178.0
178.0
9.0
9.0
3.23
3.23
3.17
3.17
1.37
1.37
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73219DBVR
TPS73219DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
180.0
180.0
180.0
180.0
18.0
18.0
Pack Materials-Page 2
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