TPS73625DRB [TI]
Cap-Free, NMOS, 400mA Low-Dropout Regulator with Reverse Current Protection; 无电容， NMOS ， 400毫安低压差稳压器，反向电流保护
| 型号： | TPS73625DRB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Cap-Free, NMOS, 400mA Low-Dropout Regulator with Reverse Current Protection |
| 文件： | 总23页 (文件大小：722K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS736xx
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
Cap-Free, NMOS, 400mA Low-Dropout Regulator
with Reverse Current Protection
FEATURES
DESCRIPTION
•
Stable with No Output Capacitor or Any Value
or Type of Capacitor
The TPS736xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly
constant over all values of output current.
•
•
•
Input Voltage Range of 1.7V to 5.5V
Ultra-Low Dropout Voltage: 75mV typ
Excellent Load Transient Response—with or
without Optional Output Capacitor
•
New NMOS Topology Delivers Low Reverse
Leakage Current
The TPS736xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
ideal for portable applications. The extremely low
output noise (30µVRMS with 0.1µF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
•
•
•
Low Noise: 30µVRMS typ (10Hz to 100kHz)
0.5% Initial Accuracy
1% Overall Accuracy Over Line, Load, and
Temperature
•
•
Less Than 1µA max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
DBV PACKAGE
SOT23
(TOP VIEW)
•
Available in Multiple Output Voltage Versions
–
–
–
Fixed Outputs of 1.20V to 4.3V
Adjustable Output from 1.20V to 5.5V
Custom Outputs Available
OUT
N/C
1
2
3
4
8
7
6
5
IN
1
5
IN
GND
EN
OUT
N/C
N/C
EN
NR/FB
GND
2
NR/FB
3
4
APPLICATIONS
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
DCQ PACKAGE
SOT223
(TOP VIEW)
TAB IS GND
4 5
1
2
3
Optional
Optional
VIN
VOUT
IN
OUT
TPS736xx
GND
IN
GND
EN
OUT NR/FB
EN
NR
Optional
Typical Application Circuit for Fixed Voltage Versions
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
TPS736xx
www.ti.com
SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS736xxyyyz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Additional output voltages from 1.25V to 4.3V in 100mV increments are available on a quick-turn basis using innovative factory
EEPROM programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS736xx
–0.3 to 6.0
–0.3 to 6.0
–0.3 to 5.5
–0.3 to 6.0
Internally limited
Indefinite
UNIT
VIN range
V
V
V
V
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55 to +150
°C
°C
kV
V
–65 to +150
2
ESD rating, CDM
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RθJC
RθJA
POWER RATING POWER RATING POWER RATING
Low-K(2)
High-K(3)
Low-K(2)
DBV
DBV
DCQ
DRB
64°C/W
64°C/W
15°C/W
1.2°C/W
255°C/W
180°C/W
53°C/W
40°C/W
3.9mW/°C
5.6mW/°C
18.9mW/°C
25.0mW/°C
390mW
560mW
1.89W
2.50W
215mW
310mW
1.04W
1.38W
155mW
225mW
0.76W
1.0W
High-K(3)(4)
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3inch x 3inch, 2-layer board with 2-ounce copper traces on top of
the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3inch x 3inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
(4) Based on preliminary thermal simulations.
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
Input voltage range(1)(2)
TEST CONDITIONS
MIN
1.7
TYP
MAX
5.5
UNIT
V
VIN
VFB
Internal reference (TPS73601)
TJ = 25°C
1.198
1.20
1.210
V
Output voltage range
(TPS73601)
VFB
-0.5
–1.0
5.5 – VDO
+0.5
V
VOUT
Nominal
TJ = 25°C
Accuracy(1)
%
over VIN, IOUT
and T
,
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10mA ≤ IOUT ≤ 400mA
±0.5
+1.0
∆VOUT%/∆VIN Line regulation(1)
VO(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 400mA
0.01
0.002
0.0005
%/V
∆VOUT%/∆IOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 400mA
Dropout voltage(3)
VDO
IOUT = 400mA
75
200
mV
(VIN = VOUT(nom)– 0.1V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
3.6V ≤ VIN ≤ 4.2V, 0°C ≤ TJ ≤ 70°C
VOUT = 0V
0.25
650
Ω
400
500
800
800
mA
mA
mA
ISC
Short-circuit current
450
0.1
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT,
IREV
Reverse leakage current(4) (–IIN
)
10
µA
µA
–40°C ≤ TJ ≤ +100°C
IOUT = 10mA (IQ)
IOUT = 400mA
400
800
550
1000
1
IGND
Ground pin current
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5
0.02
µA
µA
FB pin current (TPS73601)
0.1
0.3
f = 100Hz, IOUT = 400mA
f = 10KHz, IOUT = 400mA
COUT = 10µF, No CNR
58
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
37
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10Hz – 100KHz
VN
µVRMS
µs
COUT = 10µF, CNR = 0.01µF
VOUT = 3V, RL = 30Ω COUT = 1µF,
CNR = 0.01µF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
1.7
0
VIN
0.5
0.1
V
V
Enable low (shutdown)
Enable pin current (enabled)
VEN = 5.5V
0.02
160
140
µA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
+125
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in a damaging over-voltage level on the output. To
avoid this situation, disable the device before powering down the VIN
.
(3) VDO is not measured for the TPS73615 (VOUT(nom) = 1.5V) since minimum VIN = 1.7V.
(4) Refer to Applications section for more information.
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4MHz
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
Short
Open
Charge Pump
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R
R
19kΩ for best
1
2
accuracy.
GND
Ω
80k
Ω
8k
R1
R2
Figure 2. Adjustable Voltage Version
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
PIN ASSIGNMENTS
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
DCQ PACKAGE
SOT223
(TOP VIEW)
DBV PACKAGE
SOT23
(TOP VIEW)
OUT
N/C
1
2
3
4
8
7
6
5
IN
TAB IS GND
N/C
N/C
EN
5
4
IN
GND
EN
1
2
3
OUT
NR/FB
GND
NR/FB
1
2
3
4
5
IN
GND
EN
OUT
NR/FB
Terminal Functions
SOT23
(DBV)
SOT223
(DCQ)
3x3 SON
(DRB)
NAME
PIN NO.
PIN NO.
PIN NO.
DESCRIPTION
Input supply
Ground
IN
1
2
3
1
3
5
8
4, Pad
5
GND
EN
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts
the regulator into shutdown mode. Refer to the Shutdown section under
Applications Information for more details. EN can be connected to IN if not used.
NR
4
4
5
4
4
2
3
3
1
Fixed voltage versions only—connecting an external capacitor to this pin bypasses
noise generated by the internal bandgap, reducing output noise to very low levels.
FB
Adjustable voltage version only—this is the input to the control loop error amplifier,
and is used to set the output voltage of the device.
OUT
Output of the Regulator. There are no output capacitor requirements for stability.
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.20
0.15
0.10
0.05
0
0.5
0.4
0.3
0.2
0.1
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
−
_
40 C
_
+25
C
_
+25
C
_
+125 C
_
+125
C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
−
−
−
0.05
0.10
0.15
0.20
−
_
40
C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
150
200
250
300
350 400
−
VIN VOUT (V)
IOUT (mA)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
100
80
60
40
20
0
TPS73625DBV
IOUT = 400mA
TPS73625DBV
_
+125
C
_
+25
C
−
_
40
C
−
−
25
0
50
100
150
200
250
300
350
400
50
0
25
50
75
100
125
_
IOUT (mA)
Temperature ( C)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
VOUT Error (%)
_
Worst Case dVOUT/dT (ppm/ C)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
IOUT = 400mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 3V
VIN = 2V
0
100
200
300
400
−
−
25
50
0
25
50
75
100
125
IOUT (mA)
_
Temperature ( C)
Figure 9.
Figure 10.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
1
800
700
600
500
400
300
200
100
0
VENABLE = 0.5V
VIN = VO + 0.5V
ICL
ISC
0.1
TPS73633
0.5
0.01
−
−
25
50
0
25
50
75
100
125
0
1.0
1.5
2.0
2.5
3.0
3.5
_
Temperature ( C)
VOUT (V)
Figure 11.
CURRENT LIMIT vs VIN
Figure 12.
CURRENT LIMIT vs TEMPERATURE
800
750
700
650
600
550
500
450
400
800
750
700
650
600
550
500
450
400
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
_
VIN (V)
Temperature ( C)
Figure 13.
Figure 14.
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
IOUT = 100mA
COUT = Any
IOUT = 1mA
µ
COUT = 1
F
IOUT = 1mA
COUT = 10 F
µ
IO = 100mA
µ
CO = 1 F
IOUT = 1mA
COUT = Any
IOUT = 100mA
COUT = 10
Frequency = 100kHz
µ
F
µ
COUT = 10
F
IOUT = Any
VOUT = 2.5V
VIN = VOUT + 1V
µ
COUT = 0
F
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
−
VIN VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0µF
CNR = 0.01µF
1
1
µ
COUT = 1
F
µ
COUT = 1
F
µ
COUT = 0
F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0
F
µ
COUT = 10
F
IOUT = 150mA
IOUT = 150mA
10 100
0.01
0.01
10
100
1k
10k
100k
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01 F
µ
COUT = 0 F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73633
LOAD TRANSIENT RESPONSE
TPS73633
LINE TRANSIENT RESPONSE
µ
µ
µ
VIN = 3.8V
COUT = 0
F
F
F
IOUT = 400mA
100mV/tick
50mV/tick
20mV/tick
50mA/tick
VOUT
VOUT
VOUT
IOUT
µ
COUT = 0
F
50mV/div
VOUT
COUT = 1
µ
COUT = 100
F
COUT = 10
50mV/div
1V/div
VOUT
dVIN
dt
5.5V
µ
= 0.5V/
s
400mA
4.5V
VIN
10mA
µ
10 s/div
µ
10 s/div
Figure 21.
Figure 22.
TPS73633
TURN-ON RESPONSE
TPS73633
TURN-OFF RESPONSE
Ω
RL = 1k
RL = 20Ω
COUT = 10µF
VOUT
COUT = 0µF
Ω
RL = 20
Ω
RL = 20
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
µ
COUT = 1
F
Ω
RL = 1k
Ω
RL = 20
COUT = 0µF
µ
COUT = 10
F
VOUT
2V
2V
VEN
0V
0V
VEN
µ
100 s/div
100µs/div
Figure 23.
Figure 24.
TPS73633
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
−
−
1
2
0.01
−
−
25
50ms/div
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise
noted.
TPS73601
RMS NOISE VOLTAGE vs CFB
TPS73601
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0 F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 27.
Figure 28.
TPS73601
TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
CFB = 10nF
Ω
R1 = 39.2k
µ
COUT = 0
F
µ
COUT = 0 F
VOUT
VOUT
100mV/div
100mV/div
200mV/div
200mV/div
µ
COUT = 10 F
VOUT
µ
COUT = 10
F
VOUT
4.5V
400mA
3.5V
VIN
10mA
IOUT
µ
µ
s/div
5
25 s/div
Figure 29.
Figure 30.
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SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
APPLICATION INFORMATION
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
The TPS736xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS736xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and
an adjustable output version. All versions have
thermal and over-current protection, including
foldback current limit.
Input and Output Capacitor Requirements
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This will counteract
reactive input sources and improves transient
response, noise rejection, and ripple rejection. A
higher-value capacitor may be necessary if large,
fast rise-time load transients are anticipated or the
device is located several inches from the power
source.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the
connections for the adjustable output version
(TPS73601).
Optional input capacitor
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
The TPS736xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN – VOUT < 0.5V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
VOUT
VIN
IN
OUT
TPS736xx
EN
GND
NR
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
Output Noise
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS736xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
FB
TPS73601
R1
CFB
EN
GND
R2
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
Optional capacitor
reduces output noise
and improves
(R1 + R2)
R2
(1)
VOUT
=
x 1.204
R2
Since the value of VREF is 1.2V, this relationship
reduces to:
transient response.
mVRMS
V
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
(2)
for the case of no CNR
.
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
For best accuracy, make the parallel combination of
R1 and R2 approximately euqal to 19kΩ. This 19kΩ,
11
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TPS736xx
www.ti.com
SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
For large step changes in load current, the
TPS736xx requires a larger voltage drop from VIN to
VOUT to avoid degraded transient response. The
boundary of this transient dropout region is
approximately twice the dc dropout. Values of
VIN – VOUT above this line insure normal transient
response.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS73601 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB , from the output to the FB
pin will reduce output noise and improve load
transient performance.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the
rate of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
The TPS736xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT
.
the TPS736xx can take
a couple of hundred
The charge pump generates ~250µV of switching
noise at ~4MHz; however, charge-pump noise
contribution is negligible at the output of the regulator
microseconds to return to the specified regulation
accuracy.
for most values of IOUT and COUT
.
Transient Response
Board Layout Recommendation to Improve
PSRR and Noise Performance
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1µF) from the output pin to ground will reduce
undershoot magnitude but increase its duration. In
the adjustable version, the addition of a capacitor,
CFB, from the output to the adjust pin will also
improve the transient response.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the board be designed with separate ground
planes for VIN and VOUT, with each ground plane
connected only at the GND pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the GND pin of
the device.
The TPS736xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
load current quickly drops to zero when a capacitor
is connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
Internal Current Limit
The TPS736xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
VOUT drops below 0.5V. See Figure 11 in the Typical
Characteristics section for a graph of IOUT vs VOUT
.
Shutdown
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. VEN below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown
capability is not required, the Enable pin can be
connected to VIN. When a pull-up resistor is used,
and operation down to 1.8V is required, use pull-up
resistor values below 50kΩ.
(Fixed Voltage Version)
VOUT
dVńdt +
COUT 80kW ø RLOAD
(4)
(Adjustable Voltage Version)
VOUT
(
dVńdt +
)
COUT 80kW ø R1 ) R2 ø RLOAD
(5)
Dropout Voltage
The TPS736xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
12
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TPS736xx
www.ti.com
SBVS038N–SEPTEMBER 2003–REVISED JANUARY 2007
Reverse Current
+35°C above the maximum expected ambient
condition of your application. This produces
a
The NMOS pass element of the TPS736xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass
element, the enable pin must be driven low before
the input voltage is removed. If this is not done, the
pass element may be left on due to stored charge on
the gate.
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
The internal protection circuitry of the TPS736xx has
been designed to protect against overload
conditions. It was not intended to replace proper heat
sinking. Continuously running the TPS736xx into
thermal shutdown will degrade reliability.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current
flowing out of the IN pin due to voltage applied on
the OUT pin. There will be additional current flowing
into the OUT pin due to the 80kΩ internal resistor
divider to ground (see Figure 1 and Figure 2).
Power Dissipation
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low and high K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers will
also improve the heat-sink effectiveness.
For the TPS73601, reverse current may flow when
VFB is more than 1.0V above VIN.
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on
power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
PD + (VIN * VOUT) IOUT
(6)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure
the required output voltage.
Any tendency to activate the thermal protection
circuit indicates excessive power dissipation or an
inadequate heat sink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete
design (including heat sink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
Package Mounting
Solder pad footprint recommendations for the
TPS736xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
13
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
TPS73601DBVR
TPS73601DBVRG4
TPS73601DBVT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
6
6
6
6
8
8
8
8
8
8
8
8
5
5
5
5
6
6
6
6
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-223
SOT-223
SOT-223
SOT-223
SON
DBV
DBV
DBV
DCQ
DCQ
DCQ
DCQ
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DBV
DBV
DBV
DBV
DCQ
DCQ
DCQ
DCQ
DRB
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73601DBVTG4
TPS73601DCQ
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73601DCQG4
TPS73601DCQR
TPS73601DCQRG4
TPS73601DRBR
TPS73601DRBRG4
TPS73601DRBT
TPS73601DRBTG4
TPS736125DRBR
TPS736125DRBRG4
TPS736125DRBT
TPS736125DRBTG4
TPS73615DBVR
TPS73615DBVRG4
TPS73615DBVT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-223
SOT-223
SOT-223
SOT-223
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73615DBVTG4
TPS73615DCQ
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73615DCQG4
TPS73615DCQR
TPS73615DCQRG4
TPS73615DRBR
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
Orderable Device
TPS73615DRBRG4
TPS73615DRBT
TPS73615DRBTG4
TPS73618DBVR
TPS73618DBVRG4
TPS73618DBVT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRB
8
8
8
5
5
5
5
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
DRB
DRB
DBV
DBV
DBV
DBV
DCQ
DCQ
DCQ
DCQ
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-223
SOT-223
SOT-223
SOT-223
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73618DBVTG4
TPS73618DCQ
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73618DCQG4
TPS73618DCQR
TPS73618DCQRG4
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73619DBVR
TPS73619DBVT
TPS73625DBVR
PREVIEW
PREVIEW
ACTIVE
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73625DBVRG4
TPS73625DBVT
TPS73625DBVTG4
TPS73625DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-223
SOT-223
SOT-223
SOT-223
SOT-23
SOT-23
SOT-23
SOT-23
SOT-223
SOT-223
DBV
DBV
DBV
DCQ
DCQ
DCQ
DCQ
DBV
DBV
DBV
DBV
DCQ
DCQ
5
5
5
6
6
6
6
5
5
5
5
6
6
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73625DCQG4
TPS73625DCQR
TPS73625DCQRG4
TPS73630DBVR
TPS73630DBVRG4
TPS73630DBVT
TPS73630DBVTG4
TPS73630DCQ
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73630DCQG4
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TPS73630DCQR
TPS73630DCQRG4
TPS73632DBVR
TPS73632DBVRG4
TPS73632DBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-223
SOT-223
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-223
SOT-223
SOT-223
SOT-223
SON
DCQ
DCQ
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DCQ
DCQ
DCQ
DCQ
DRB
DRB
DRB
DRB
DBV
DBV
DBV
DBV
6
6
5
5
5
5
5
5
5
5
6
6
6
6
8
8
8
8
5
5
5
5
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73632DBVTG4
TPS73633DBVR
TPS73633DBVRG4
TPS73633DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73633DBVTG4
TPS73633DCQ
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DCQG4
TPS73633DCQR
TPS73633DCQRG4
TPS73633DRBR
TPS73633DRBRG4
TPS73633DRBT
TPS73633DRBTG4
TPS73643DBVR
TPS73643DBVRG4
TPS73643DBVT
78 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
SON
250 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
SOT-23
SOT-23
SOT-23
SOT-23
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73643DBVTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 4
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